A CDM ESD risk analysis method, system and electronic device for SOC internal circuit

Abstract

The present invention discloses a CDM ESD risk analysis method, system and electronic device for an internal circuit of a SOC, and relates to the technical field of data processing, including: inputting layout data into a DRC tool and a PERC tool for verification and inspection; generating a first CDM ESD verification result data set based on internal test result data analysis; generating a second CDM ESD verification result data set based on fast and slow path related metal area data and DIO area data analysis around a gate; generating a third CDM ESD verification result data set based on multiple groups of inspection data analysis under different modes; generating CDM ESD risk analysis result data for an internal circuit of a SOC based on the first to third CDM ESD verification result data sets. The present invention performs CDM ESD risk analysis from multiple directions and angles, and improves the comprehensiveness and accuracy of risk analysis, as well as the reliability of chips.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular to a CDM ESD risk analysis method and system for an internal circuit of a SOC and electronic equipment thereof. Background Art

[0002] SoC (System on Chip) is a chip that integrates multiple functional modules, including processor core, storage, communication interface, sensor interface, etc. With the development of technology, the scale and complexity of SoC are increasing, which puts higher requirements on the stability and reliability of chips.

[0003] During the assembly, testing, transportation and storage process, the chip may be charged due to many factors such as friction, contact or electromagnetic induction, and the chip itself stores charge as a plate of a capacitor. The CMD (Charged Device Model) is based on the discharge path to the ground when the charged chip device contacts the ground through the pins, causing the chip device to fail.

[0004] CMD (Charged Device Model) damage is closely related to the development of SoC. In CDM mode, chip failure is mainly divided into two ways: one is the damage of ESD devices related to IO interface or internal gate, MOS or DIO, and the other is the gate damage of logic devices with wiring relationship between different blocks across power regions. This shows that ESD events in CMD mode may cause damage to devices inside the chip, especially devices related to IO interface and internal logic devices. With the increase of SoC scale, the increase of device density on chip, the smaller distance between devices, and the continuous increase of operating frequency and voltage, etc., all these increase the threat of electrostatic discharge (ESD) to chips, and the proportion of CDM damage is becoming more and more serious.

[0005] With the development of SoC, the relationship between CMD damage and chip design and manufacturing is reflected in the continuous improvement of requirements, which requires more comprehensive and effective prevention of potential damage to chips caused by CMD.

[0006] In the CDM ESD (Charged Device Model Electrostatic Discharge) mode, the chip failure analysis method may have the following problems:

[0007] Invisibility: CDM ESD events are usually transient and may occur on a microscopic time scale, making them difficult to observe directly. This makes it difficult to capture the occurrence of CDM ESD events in actual testing, resulting in invisibility in failure analysis.

[0008] Difficult to reproduce: Since CDM ESD events are usually caused by electrostatic discharge, and their occurrence involves a complex charge accumulation and release process, it is difficult to accurately reproduce CDM ESD events in a laboratory environment, which brings difficulties to failure analysis.

[0009] Circuit damage: CDM ESD events may cause instantaneous damage to the chip's internal circuits, leading to circuit failure. However, due to the transient nature of CDM ESD events, circuit damage may occur instantly, making it difficult to analyze damaged circuits using traditional methods.

[0010] Influence of multiple factors: The occurrence of CDM ESD events is affected by multiple factors, including chip structure, material properties, external environment, etc. The complexity of these factors makes it difficult to accurately determine the specific cause of CDM ESD events in failure analysis.

[0011] Limited testing methods: Currently, the testing methods for CDM ESD are relatively limited. Although there are some special CDM ESD testing methods, there are still certain limitations in actual testing, which will affect the accuracy and reliability of failure analysis.

[0012] It can be seen that more attention should be paid to CMD protection measures during chip design and manufacturing, including strengthening the protection of IO interfaces, improving the ESD tolerance of devices, and optimizing layout and wiring design. At the same time, internal cross-power region CDM protection has become more important to reduce the risk of CMD damage. Therefore, in order to improve the stability and reliability of the chip, it is urgent to propose a CDM ESD risk analysis method for SoC internal circuits. Summary of the invention

[0013] The purpose of the present invention is to provide a CDM ESD risk analysis method, system and electronic equipment for the internal circuit of SoC, through a multi-faceted and multi-angle CDM ESD risk analysis method based on DRC verification process and PERC verification process combined with empirical statistics of CDM ESD internal test results of some SoC chips, metal areas related to fast and slow paths, DIO areas of gates, etc., as well as multiple groups of different inspections in different modes, so as to effectively reduce the risk of CDM ESD damage and improve the stability and reliability of the chip.

[0014] The purpose of the present invention is achieved by the following technical solutions:

[0015] In a first aspect, the present invention provides a CDM ESD risk analysis method for a SoC internal circuit, comprising the following steps:

[0016] S1. Obtain layout data and input the layout data into the drc tool and the perc tool for verification and inspection;

[0017] S2. Based on the internal test result data analysis, generate a first CDM ESD verification result data set;

[0018] S3, based on the analysis of the metal area data related to the fast and slow paths and the DIO area data around the gate, generate a second CDM ESD verification result data set;

[0019] S4, generating a third CDM ESD verification result data set based on analysis of multiple groups of inspection data under different modes;

[0020] S5. Generate CDM ESD risk analysis result data of the internal circuit of the SOC according to the first CDM ESD verification result data set, the second CDM ESD verification result data set and the third CDM ESD verification result data set.

[0021] Preferably, based on the internal test result data analysis, generating a first CDM ESD verification result data set specifically includes the following steps:

[0022] Obtain the CDM ESD internal test result data of the SoC chip, quantify the internal test result data, and obtain empirical statistical analysis results;

[0023] Formulate the first check rules for the drc tool and the perc tool based on the empirical statistical analysis results;

[0024] Input the layout data into the DRC tool and the PERC tool for verification and check to generate the first CDM ESD verification result data set.

[0025] Preferably, the obtaining of the CDM ESD internal test result data of the SoC chip and quantifying the internal test result data comprises:

[0026] Collect CDM ESD internal test result data under different processes, including ESD event occurrence, trigger voltage and waveform characteristics under different processes;

[0027] The data under different processes are quantitatively analyzed to obtain numerical expressions of parameters, including ESD event frequency, tolerance voltage, waveform characteristics and tolerance current.

[0028] Preferably, the second CDM ESD verification result data set is generated based on the analysis of the metal area data related to the fast and slow paths and the DIO area data around the gate, specifically including:

[0029] Get the metal area data related to the fast and slow paths of the SoC chip and the DIO area data around the gate;

[0030] Quantify the metal area data related to fast and slow paths and the DIO area data around the gate to obtain quantitative parameters, perform CDM ESD risk impact analysis on the quantitative parameters, and obtain the area distribution rule analysis results;

[0031] Formulate the second inspection rules of drc tool and perc tool according to the analysis results of area distribution rules;

[0032] Input the layout data into the DRC tool and the PERC tool for verification and check to generate the second CDM ESD verification result data set.

[0033] Preferably, the quantization of the metal area data related to the fast and slow paths and the dio area data around the gate to obtain the quantization parameters includes:

[0034] Quantify the metal area data related to fast and slow paths and the DIO area data around the gate, and obtain the numerical expression of the quantified data, including metal layer area, metal line width, metal line spacing, transistor area, capacitance value, resistance value and connection length, DIO unit area and DIO unit quantity;

[0035] The metal layer area includes the fast path metal layer area and the slow path metal layer area, the capacitance value includes the capacitance to ground, and the DIO unit area includes the actual area of ​​each DIO unit and the total area of ​​each DIO unit.

[0036] Preferably, the analysis of multiple groups of inspection data under different modes to generate a third CDM ESD verification result data set includes:

[0037] Determine different working modes and obtain the characteristics of the SOC chip in different working modes;

[0038] Based on the characteristics of SOC chips in different working modes, multiple sets of different CDM ESD inspection rules for drc tools and perc tools are formulated as the third inspection rules;

[0039] Based on the third inspection rule, the layout data is input into the DRC tool and the PERC tool for verification inspection to generate a third CDM ESD verification result data set.

[0040] Preferably, the different working modes include a normal working mode, a low power consumption mode and a standby mode;

[0041] The characteristics of SOC chips in different working modes include metal area, circuit layout, signal transmission path and circuit switching process.

[0042] Preferably, the method further comprises step S6, formulating and implementing corresponding risk prevention measures according to the CDM ESD risk analysis result data of the internal circuit of the SOC; step S6 specifically comprises:

[0043] CDM ESD risk level classification is carried out according to the CDM ESD risk analysis result data of the internal circuit of the soc;

[0044] Formulate corresponding risk prevention measures according to the CDM ESD risk level;

[0045] Implement appropriate risk prevention measures.

[0046] Preferably, after implementing the corresponding risk prevention measures, it also includes recording the prevention effect, optimizing the inspection rules of the drc tool and the perc tool according to the prevention effect, repeating steps S1-S5 based on the optimized inspection rules, and updating the risk prevention measures in step S6.

[0047] In a second aspect, the present invention provides a CDM ESD risk analysis system for a SoC internal circuit, which is applied to a CDM ESD risk analysis method for a SoC internal circuit as described above, and the system comprises:

[0048] A data acquisition module configured to acquire data related to CDM ESD risk analysis of the internal circuit of the SoC, including layout data, internal test result data, metal area data related to fast and slow paths and DIO area data around the gate, and multiple sets of inspection data in different modes;

[0049] A data processing module, configured to process and analyze the data collected by the data collection module;

[0050] A data verification module is configured to input the data processed and analyzed by the data processing module into a DRC tool and a PERC tool for CDM ESD risk verification;

[0051] A data optimization module configured to optimize data related to the cdmesd risk analysis of the internal circuit of the SoC based on the verification result output by the data verification module;

[0052] The risk prevention management module is configured to formulate and manage the CDM ESD risk prevention strategy of the internal circuit of the SoC according to the optimized data.

[0053] Compared with the prior art, the present invention has the following beneficial effects:

[0054] The present invention generates CDM ESD risk analysis result data of the internal circuit of the SoC by analyzing the CDM ESD internal test result data of the SoC chip, the metal area data related to the fast and slow paths, the DIO area data around the gate and multiple groups of inspection data under different modes, and performs CDM ESD risk analysis from multiple directions and angles, which not only improves the comprehensiveness and accuracy of the risk analysis, but also effectively reduces the risk of CDM ESD damage, and further improves the stability and reliability of the chip.

[0055] The present invention formulates verification rules for drc and perc tools, so that the verification results obtained by the drc and perc tools can make the analysis of CDM ESD more accurate and improve the efficiency of risk analysis.

[0056] At the same time, the present invention also optimizes the verification and inspection rules after implementing the risk prevention measures, repeats the verification and inspection, and synchronously updates the risk prevention measures, thereby improving the comprehensiveness and accuracy of the risk analysis and further improving the stability and reliability of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0058] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0059] Figure 1 The present invention provides a flow chart of a CDM ESD risk analysis method for an internal circuit of a SOC;

[0060] Figure 2 A schematic diagram of the process of step S2 provided in this embodiment;

[0061] Figure 3 A schematic diagram of the process of step S3 provided in this embodiment;

[0062] Figure 4 A schematic diagram of the process of step S4 provided in this embodiment;

[0063] Figure 5 A schematic diagram of the process of step S6 provided in this embodiment;

[0064] Figure 6A schematic structural diagram of a CDM ESD risk analysis system for an internal circuit of a SOC is provided for this embodiment;

[0065] Figure 7 A schematic diagram of the structure of an electronic device provided in this embodiment. DETAILED DESCRIPTION

[0066] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0067] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0068] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0069] In view of the problems existing in the chip failure analysis method under the CDM ESD mode, the present invention provides a CDM ESD risk analysis method, system and electronic equipment for the internal circuit of a SOC, which can more comprehensively and accurately analyze the chip failure caused by CDM ESD and reduce the impact of CDM ESD on chip reliability.

[0070] In the embodiment of the present invention, the design rule check (DRC) is an important step in the circuit board design process, which ensures that the design of the circuit board complies with the preset specific manufacturing process requirements. DRC ensures that the designed layout complies with the design rules through a series of checks. These rules usually include layout, device spacing, metal line width, electrical specifications, etc. The DRC tool can help designers to timely discover and solve possible manufacturing risks during the layout design stage, ensure that the design meets the requirements of process manufacturing, and improve the reliability and manufacturing success rate of ICs.

[0071] In the embodiment of the present invention, PERC (Power Electronics Rule Checking) is a tool for verifying the design of power electronic circuits, and is used to check whether the design of power electronic circuits meets the requirements of rules set in specific electrical safety, EMI (electromagnetic interference), power efficiency, etc. These rules may include voltage and current ranges, electromagnetic compatibility requirements, heat dissipation design, etc. The PERC tool can help designers to promptly discover and solve problems that may exist in the design of power electronic circuits during the design stage, and improve the reliability and stability of the design.

[0072] The present invention provides a CDM ESD risk analysis method, system and electronic device for the internal circuit of a SOC. By analyzing the CDM ESD internal test result data of the SoC chip, the metal area data related to the fast and slow paths, the DIO area data around the gate and multiple groups of inspection data under different modes, the CDM ESD risk analysis result data of the internal circuit of the SOC is generated, and the CDM ESD risk analysis is performed from multiple directions and angles, which not only improves the comprehensiveness and accuracy of the risk analysis, but also effectively reduces the risk of CDM ESD damage, and further improves the stability and reliability of the chip. At the same time, the present invention also repeats the verification process and the analysis of the internal test results after implementing the risk prevention strategy, and optimizes the verification process and the risk prevention strategy to reduce the risk of CMD damage and improve the stability and reliability of the chip. The above technical scheme of the present invention will be elaborated in detail below.

[0073] Embodiment 1:

[0074] like Figure 1 As shown, the present invention provides a CDM ESD risk analysis method for an internal circuit of a SOC, comprising the following steps:

[0075] S1. Obtain layout data and input the layout data into the drc tool and the perc tool for verification and inspection;

[0076] S2. Based on the internal test result data analysis, generate a first CDM ESD verification result data set;

[0077] S3, based on the analysis of the metal area data related to the fast and slow paths and the DIO area data around the gate, generate a second CDM ESD verification result data set;

[0078] S4, generating a third CDM ESD verification result data set based on analysis of multiple groups of inspection data under different modes;

[0079] S5. Generate CDM ESD risk analysis result data of the internal circuit of the SOC according to the first CDM ESD verification result data set, the second CDM ESD verification result data set and the third CDM ESD verification result data set.

[0080] Among them, for step S1

[0081] Layout data refers to the layout of the internal circuit of the SoC to be tested for CDM ESD risk. Layout data includes:

[0082] Layout and wiring information: used to describe the layout and interconnected wiring information of each functional module in the chip, including the position and connection relationship of transistors, circuit elements, metal wires and insulation layers.

[0083] Physical characteristic information: used to describe the physical characteristics of each component in the chip, such as the size of the transistor, the width and spacing of the metal wires, and the thickness of the insulating layer.

[0084] Physical constraint information: used to describe the physical constraints in chip design, such as chip size, boundaries, and protection areas.

[0085] Process rule information: used to describe the process rules that need to be met in chip design, including transistor layout rules, metal line routing rules, insulation layer regulations, etc.

[0086] The layout data is input into the DRC tool and the PERC tool for verification and inspection. The purpose is to perform CDM ESD risk analysis in the layout data through the DRC tool and the PERC tool, two commonly used inspection tools in chip design, to obtain accurate and comprehensive verification results.

[0087] Among them, for step S2

[0088] like Figure 2 As shown, based on the internal test result data analysis, a first CDM ESD verification result data set is generated, which specifically includes the following steps:

[0089] S201, obtaining CDM ESD internal test result data of the SoC chip, quantifying the internal test result data, and obtaining empirical statistical analysis results;

[0090] S202, formulating the first inspection rule of the drc tool and the perc tool according to the empirical statistical analysis results;

[0091] S203: Input the layout data into the DRC tool and the PERC tool for verification and check, and generate a first CDM ESD verification result data set.

[0092] In step S201, the obtaining of CDM ESD internal test result data of the SoC chip and quantifying the internal test result data include:

[0093] Collect CDM ESD internal test result data under different processes, including the occurrence of ESD events, trigger voltage and waveform characteristics under different processes; CDM ESD tests can be performed through special test equipment and professional test laboratories to obtain internal test result data; you can also obtain information and experience summary about CDM ESD internal test result data by consulting relevant technical literature, industry reports and academic papers.

[0094] The data under different processes are quantitatively analyzed to obtain numerical expressions of parameters, including ESD event frequency, tolerance voltage, waveform characteristics and tolerance current.

[0095] Tolerance voltage (TLP) refers to the maximum voltage that a chip can withstand when it is subjected to a CDM ESD pulse. The test results will show the tolerance voltage value of the chip under different conditions, such as normal operating temperature, high temperature, low temperature, etc. This value can help evaluate the chip's resistance to ESD.

[0096] Waveform characteristics include waveform response, which refers to the voltage waveform and current waveform of the chip when it is subjected to a CDM ESD pulse. By analyzing the waveform response, we can understand the chip's response speed, amplitude, and duration when an ESD event occurs, thereby evaluating its resistance to ESD.

[0097] The tolerance current (It curve) refers to the maximum current that the chip can withstand when it is subjected to a CDM ESD pulse. The test results will show the tolerance current value of the chip under different conditions, as well as the curve of the current change over time. These data can help evaluate the current tolerance of the chip in an ESD event.

[0098] In step S202, based on the analysis results of ESD event frequency, tolerance voltage, waveform characteristics and tolerance current in the empirical statistical analysis results, the internal test requirements of the SoC chip in the CDM ESD mode are obtained, and based on the internal test requirements, the first inspection rules of the drc tool and the perc tool are formulated.

[0099] In step S203, the layout data to be evaluated for CMD ESD risk is input into the DRC tool and the PERC tool for which the inspection rules have been established for verification. The DRC tool and the PERC tool will output the corresponding verification result report, i.e., the first CDM ESD verification result data set. Through the preliminary inspection of the DRC tool and the PERC tool, some basic design rules and electrical characteristics in the layout data are verified to ensure that the layout design meets the process requirements and electrical specifications. At the same time, the verification result report will also list the relevant data that does not meet the design requirements and the preliminary inspection data of the CDM ESD risk.

[0100] In the embodiment of the present invention, a DRC tool and a PERC tool are used to perform a preliminary check on the layout data based on the internal test result data to obtain a first CDM ESD verification result data set, thereby improving the accuracy of CDM ESD risk analysis.

[0101] Among them, for step S3

[0102] like Figure 3 As shown, the second CDM ESD verification result data set is generated based on the analysis of the metal area data related to the fast and slow paths and the DIO area data around the gate, which specifically includes the following steps:

[0103] S301, obtaining metal area data related to fast and slow paths of the SoC chip and dio area data around the gate;

[0104] S302, quantify the metal area data related to the fast and slow paths and the DIO area data around the gate to obtain quantization parameters, perform CDM ESD risk impact analysis on the quantization parameters, and obtain area distribution rule analysis results;

[0105] S303, formulating the second inspection rule of the drc tool and the perc tool according to the area distribution rule analysis result;

[0106] S304: Input the layout data into the DRC tool and the PERC tool for verification and check, and generate a second CDM ESD verification result data set.

[0107] In step S302, the metal area data related to the fast and slow paths and the dio area data around the gate are quantized to obtain quantization parameters, which specifically include:

[0108] Quantify the metal area data related to fast and slow paths and the DIO area data around the gate, and obtain the numerical expression of the quantized data, including parameters such as metal layer area, metal line width, metal line spacing, transistor area, capacitance value, resistance value and connection length, DIO unit area and DIO unit quantity;

[0109] The metal layer area includes the fast path metal layer area and the slow path metal layer area, the capacitance value includes the capacitance to ground, and the DIO unit area includes the actual area of ​​each DIO unit and the total area of ​​each DIO unit.

[0110] Among them, for step S4

[0111] like Figure 4 As shown, the analysis of multiple groups of inspection data under different modes to generate a third CDM ESD verification result data set includes the following steps:

[0112] S401, determine different working modes, and obtain characteristics of the SOC chip in different working modes; the different working modes include normal working mode, low power mode and standby mode, and the characteristics of the SOC chip in different working modes include metal area, circuit layout, signal transmission path and circuit switching process.

[0113] S402, based on the characteristics of the SOC chip in different working modes, formulate multiple groups of different CDM ESD inspection rules of the drc tool and the perc tool as the third inspection rule; multiple groups of different CDM ESD inspection rules are formulated according to the characteristics in different working modes, and the characteristics in different working modes also include the aforementioned metal layer area, ground capacitance and dio distribution around the gate, but according to different working modes, its characteristics are different. The following examples are given, but the present invention is not limited to this:

[0114] The inspection rules in normal working mode include: Check the metal area of ​​the main working modules inside the chip to ensure that the metal area does not exceed the CDM ESD standard requirements. Calculate the capacitance between the main working modules inside the chip and the ground to ensure that the capacitance to the ground does not cause CDM ESD risks in normal working mode.

[0115] The inspection rules in low power mode include: Checking the metal area of ​​the circuit that is active in low power mode to ensure that the metal area does not exceed the CDM ESD standard requirements. Evaluating the impact of signal transmission characteristics in low power mode on CDM ESD risk, such as whether there is CDM ESD risk caused by the signal transmission path.

[0116] Inspection rules in standby mode include: Checking the metal area of ​​circuits that are still active in standby mode to ensure that the metal area does not exceed the CDM ESD standard requirements. Evaluating the impact of circuit switching and wake-up processes in standby mode on CDM ESD risks, such as whether there is a CDM ESD risk during the switching process.

[0117] S403: Based on the third inspection rule, input the layout data into the DRC tool and the PERC tool for verification inspection to generate a third CDM ESD verification result data set.

[0118] According to the analysis of the verification and inspection results, the CDM ESD risks in different working modes are evaluated and analyzed. If potential risks or problems are found, corresponding optimization measures can be taken, such as redesigning the metal layer layout, optimizing the signal transmission path, or adjusting the circuit switching process.

[0119] The present invention combines different mode settings to form multiple groups of different inspections similar to ant (antenna), so as to comprehensively evaluate and reduce CDM ESD risks.

[0120] Among them, for step S5

[0121] CDM ESD risk analysis result data of the internal circuit of the SOC is generated according to the first CDM ESD verification result data set, the second CDM ESD verification result data set and the third CDM ESD verification result data set.

[0122] In this step, the first, second and third CDM ESD verification result data sets can be integrated together, including the CDM ESD test results, ESD protection circuit performance data, chip layout information, etc. in each data set. Then the integrated data is cleaned and preprocessed, including removing outliers, filling missing data, unifying data formats, etc., to ensure data quality and consistency. Then, the integrated and processed data is analyzed by statistical analysis methods, including descriptive statistics, correlation analysis, frequency distribution analysis, etc., to understand the differences and consistency between different data sets, thereby generating CDM ESD risk analysis result data for the internal circuit of the SOC.

[0123] The present invention generates CDM ESD risk analysis result data of the internal circuit of the SoC by analyzing the CDM ESD internal test result data of the SoC chip, the metal area data related to the fast and slow paths, the DIO area data around the gate and multiple groups of inspection data under different modes, and performs CDM ESD risk analysis from multiple directions and angles, which not only improves the comprehensiveness and accuracy of the risk analysis, but also effectively reduces the risk of CDM ESD damage, and further improves the stability and reliability of the chip.

[0124] Embodiment 2

[0125] This embodiment provides a CDM ESD risk analysis method for an internal circuit of a SoC, which is different from the first embodiment in that step S5 further includes step S6, formulating and implementing corresponding risk prevention measures according to the CDM ESD risk analysis result data of the internal circuit of the SoC; Figure 5 As shown, step S6 specifically includes:

[0126] S601. CDM ESD risk levels are classified according to the CDM ESD risk analysis result data of the internal circuit of the SOC; wherein the CDM ESD risk levels include four levels: high risk, medium risk, low risk and no risk, and the above risk levels are defined according to the CDM ESD risk.

[0127] High risk means that CDM ESD events have occurred or are occurring in multiple directions, and have obviously caused failures in the internal circuits of the SOC. Immediate measures must be taken to handle the events. Medium risk means that CDM ESD events have occurred in local internal circuits of the SOC, causing local failures in the internal circuits of the SOC. Event handling is required for the failed area, and continuous attention must be paid to the CDM ESD risk analysis result data of the internal circuits of the SOC. Low risk means that no CDM ESD events have occurred in the internal circuits of the SOC, but the risk analysis result data show that there is a potential CDM ESD risk. Continuous monitoring of the CDM ESD risk analysis result data of the internal circuits of the SOC is required. No risk means that no CDM ESD events have been found.

[0128] S602. Develop corresponding risk prevention measures according to the CDM ESD risk level;

[0129] Once the CDM ESD risk level is high risk, medium risk or low risk, corresponding risk prevention measures need to be taken, including but not limited to: introducing electrostatic discharge protection devices in chip design, reasonable PCB design and layout, and adding DIO in the gate segment of the CDM risk path.

[0130] Adding DIO to the gate segment of the CDM risk path can be achieved by introducing appropriate protection circuits in the chip design. These protection circuits are designed to prevent CDM events from causing damage or interference to the digital input / output section. For example, a common practice is to add electrostatic discharge protection devices, such as TVS (Transient Voltage Suppression) diodes or ESD (Electrostatic Discharge) protection diodes, to the input / output ports of the chip. These protection devices can quickly turn on and absorb the energy brought by electrostatic discharge, thereby protecting the DIO-related circuits from damage. In addition, the protection of DIO can be enhanced through reasonable PCB (Printed Circuit Board) layout and grounding design. For example, the use of appropriate grounding design can reduce the impact of electrostatic discharge on the DIO line, while reasonable wiring and shielding design can reduce the impact of external interference on DIO.

[0131] Among them, reasonable PCB design and layout include but are not limited to: reducing the RC of the routing between blocks across the power supply area, that is, the reasonable layout and design of the ground capacitance; increasing the gate area of ​​the routing connection between blocks across the power supply area, etc.

[0132] S603. Implement appropriate risk prevention measures.

[0133] As a preferred embodiment of the present invention, after implementing corresponding risk prevention measures, it also includes

[0134] S604, record the prevention effect, optimize the inspection rules of the DRC tool and the PERC tool according to the prevention effect, repeat the CDM ESD risk analysis process and update the risk prevention measures based on the optimized inspection rules. Among them, the CDM ESD risk analysis process is steps S1-S5 in Example 1, and the updating of risk prevention measures refers to updating the risk prevention measures in step S6. The specific process of optimizing the inspection rules of the DRC tool and the PERC tool can adopt the common methods in the field, and the present invention will not be repeated here.

[0135] The present invention formulates verification rules for drc and perc tools, so that the verification results obtained by drc and perc tools can make the analysis of CDM ESD more accurate, and at the same time improve the efficiency of risk analysis. The present invention also optimizes the verification inspection rules after implementing risk prevention measures, repeats the verification inspection, and synchronously updates the risk prevention measures, thereby improving the comprehensiveness and accuracy of risk analysis and further improving the stability and reliability of the chip.

[0136] Embodiment 3

[0137] like Figure 6 As shown, the present invention provides a CDM ESD risk analysis system for a SoC internal circuit, which is applied to a CDM ESD risk analysis method for a SoC internal circuit as in Embodiment 1 and Embodiment 2, and the system includes:

[0138] A data acquisition module configured to acquire data related to CDM ESD risk analysis of the internal circuit of the SoC, including layout data, internal test result data, metal area data related to fast and slow paths and DIO area data around the gate, and multiple sets of inspection data in different modes;

[0139] A data processing module, configured to process and analyze the data collected by the data collection module;

[0140] A data verification module is configured to input the data processed and analyzed by the data processing module into a DRC tool and a PERC tool for CDM ESD risk verification;

[0141] A data optimization module configured to optimize data related to the cdmesd risk analysis of the internal circuit of the SoC based on the verification result output by the data verification module;

[0142] The risk prevention management module is configured to formulate and manage the CDM ESD risk prevention strategy of the internal circuit of the SoC according to the optimized data.

[0143] Embodiment 4

[0144] like Figure 7 As shown, the present invention also provides an electronic device 2, including a processor 21 and a memory 22, the memory 22 is used to store computer program code, the computer program code includes computer instructions, when the processor 21 executes the computer instructions, the electronic device executes a CDM ESD risk analysis method for an internal circuit of a SoC of the above embodiment.

[0145] The electronic device 2 also includes an input device 24 and an output device 23. The processor 21, the memory 22, the input device 24 and the output device 23 are coupled via a connector, and the connector includes various interfaces, transmission lines or buses, etc., which are not limited in the embodiments of the present invention. It should be understood that in various embodiments of the present invention, coupling refers to mutual connection in a specific manner, including direct connection or indirect connection through other devices, for example, through various interfaces, transmission lines, buses, etc.

[0146] The processor 21 may be one or more graphics processing units (GPUs). When the processor 21 is a GPU, the GPU may be a single-core GPU or a multi-core GPU. Optionally, the processor 21 may be a processor group consisting of multiple GPUs, and the multiple processors are coupled to each other via one or more buses. Optionally, the processor may also be other types of processors, etc., which are not limited in the embodiments of the present invention.

[0147] The memory 22 can be used to store computer program instructions and various computer program codes including program codes for executing the scheme of the present invention. Optionally, the memory includes but is not limited to random access memory (RAM), read-only memory (ROM), erasable programmable read only memory (EPROM), or portable read only memory (CD-ROM), which is used for related instructions and data.

[0148] The input device 24 is used to input data and / or signals, and the output device 23 is used to output data and / or signals. The output device 23 and the input device 24 can be independent devices or an integrated device.

[0149] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A CDM ESD risk analysis method for a SoC internal circuit, characterized in that: The following steps are involved: S1. Obtain layout data and input the layout data into the drc tool and the perc tool for verification and inspection; S2. Based on the internal test result data analysis, a first CDM ESD verification result data set is generated, which specifically includes the following steps: Obtain the CDM ESD internal test result data of the SoC chip, quantify the internal test result data, and obtain empirical statistical analysis results; Formulate the first check rules for the drc tool and the perc tool based on the empirical statistical analysis results; Input the layout data into the DRC tool and the PERC tool for verification and check, and generate the first CDM ESD verification result data set; S3. Based on the analysis of the metal area data related to the fast and slow paths and the DIO area data around the gate, generate the second cdmesd verification result data set, specifically including: Get the metal area data related to the fast and slow paths of the SoC chip and the DIO area data around the gate; Quantify the metal area data related to fast and slow paths and the DIO area data around the gate to obtain quantitative parameters, perform CDM ESD risk impact analysis on the quantitative parameters, and obtain the area distribution rule analysis results; Formulate the second inspection rules of drc tool and perc tool according to the analysis results of area distribution rules; Input the layout data into the DRC tool and the PERC tool for verification and check, and generate the second CDM ESD verification result data set; S4. Based on the analysis of multiple groups of inspection data under different modes, a third CDM ESD verification result data set is generated, including: Determine different working modes and obtain the characteristics of the SOC chip in different working modes; Based on the characteristics of SOC chips in different working modes, multiple groups of different CDMESD inspection rules for drc tools and perc tools are formulated as the third inspection rules; Based on the third inspection rule, the layout data is input into the DRC tool and the PERC tool for verification inspection to generate a third CDMSD verification result data set; S5. Generate CDM ESD risk analysis result data of the internal circuit of the SOC according to the first CDM ESD verification result data set, the second CDM ESD verification result data set and the third CDM ESD verification result data set.

2. The CDM ESD risk analysis method for a SoC internal circuit according to claim 1, characterized in that: The obtaining of the CDM ESD internal test result data of the SoC chip and quantifying the internal test result data comprises: Collect CDM ESD internal test result data under different processes, including ESD event occurrence, trigger voltage and waveform characteristics under different processes; The data under different processes are quantitatively analyzed to obtain numerical expressions of parameters, including ESD event frequency, tolerance voltage, waveform characteristics and tolerance current.

3. The CDM ESD risk analysis method for a SoC internal circuit according to claim 1, characterized in that: The quantized fast and slow path related metal area data and the dio area data around the gate are used to obtain the quantized parameters, including: Quantify the metal area data related to fast and slow paths and the DIO area data around the gate, and obtain the numerical expression of the quantified data, including metal layer area, metal line width, metal line spacing, transistor area, capacitance value, resistance value and connection length, DIO unit area and DIO unit quantity; The metal layer area includes the fast path metal layer area and the slow path metal layer area, the capacitance value includes the capacitance to ground, and the DIO unit area includes the actual area of ​​each DIO unit and the total area of ​​each DIO unit.

4. The CDM ESD risk analysis method for a SoC internal circuit according to claim 1, characterized in that: The different working modes include normal working mode, low power consumption mode and standby mode; The characteristics of SOC chips in different working modes include metal area, circuit layout, signal transmission path and circuit switching process.

5. The CDM ESD risk analysis method for a SoC internal circuit according to claim 1, characterized in that: The method further includes step S6, formulating and implementing corresponding risk prevention measures according to the CDM ESD risk analysis result data of the internal circuit of the SOC; step S6 specifically includes: CDM ESD risk level classification is carried out according to the CDM ESD risk analysis result data of the internal circuit of the SoC; Formulate corresponding risk prevention measures according to the CDM ESD risk level; Implement appropriate risk prevention measures.

6. The CDM ESD risk analysis method for a SoC internal circuit according to claim 5, characterized in that: After implementing the corresponding risk prevention measures, it also includes recording the prevention effect, optimizing the inspection rules of the drc tool and the perc tool according to the prevention effect, repeating steps S1-S5 based on the optimized inspection rules, and updating the risk prevention measures in step S6.

7. A CDM ESD risk analysis system for a SoC internal circuit, applied to a CDM ESD risk analysis method for a SoC internal circuit as claimed in any one of claims 1 to 6, characterized in that: The system comprises: A data acquisition module configured to acquire data related to CDM ESD risk analysis of the internal circuit of the SoC, including layout data, internal test result data, metal area data related to fast and slow paths and DIO area data around the gate, and multiple sets of inspection data in different modes; A data processing module, configured to process and analyze the data collected by the data collection module; A data verification module is configured to input the data processed and analyzed by the data processing module into a DRC tool and a PERC tool for CDM ESD risk verification; a data optimization module configured to optimize data related to CDM ESD risk analysis of an internal circuit of the SoC based on a verification result output by the data verification module; The risk prevention management module is configured to formulate and manage the CDM ESD risk prevention strategy of the internal circuit of the SoC according to the optimized data.

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