SiC MOSFET parallel current sharing and oscillation suppression circuit and method

Abstract

The present invention discloses a SiC MOSFET parallel current sharing and oscillation suppression circuit and method, wherein the circuit comprises a DC power supply, a stray inductance, a SiC MOSFET tube Q M , a coupling coil and a SiC MOSFET parallel module; the SiC MOSFET parallel module includes a plurality of branches, each branch includes a first coupling inductor, a second coupling inductor and a SiC MOSFET tube Q connected in series in sequence i , the first coupling inductor of the first branch is negatively coupled with the second coupling inductor of the last branch, the first coupling inductor of the ith branch is negatively coupled with the second coupling inductor of the i-1th branch, and the second coupling inductor of the ith branch is negatively coupled with the first coupling inductor of the i+1th branch. The present invention solves the problem of uneven current of parallel SiC MOSFET tubes and the problem of switch oscillation.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronic devices, and in particular relates to a circuit and method for realizing parallel current sharing and oscillation suppression of SiC MOSFETs by utilizing coupled inductors. Background Art

[0002] Wide bandgap semiconductor power devices represented by silicon carbide (SiC) MOSFET have injected strong vitality into the development of power electronics technology. Compared with traditional silicon-based devices, SiC MOSFET has gradually replaced silicon-based devices due to its advantages such as high-frequency switching, high-temperature operation and low loss, and has been widely used in electric traction, photovoltaic power generation, smart grid and other fields. Due to the high-frequency characteristics of SiC MOSFET devices, small junction capacitance, low gate charge, fast switching speed, and extremely large voltage and current change rates during the switching process, parasitic inductance is very likely to produce voltage overshoot and oscillation under extremely large current change rates di / dt. At the same time, considering cost-effectiveness and manufacturability, multiple SiC MOSFET devices are usually connected in parallel to increase current capability. Current imbalance between SiC MOSFETs is a problem worthy of attention because it affects reliability. Summary of the invention

[0003] The object of the present invention is to provide a SiC MOSFET parallel current sharing and oscillation suppression circuit and method to solve the current imbalance problem on each branch of the parallel SiC MOSFET.

[0004] The present invention solves the above technical problems through the following technical solutions: a SiC MOSFET parallel current sharing and oscillation suppression circuit, comprising a DC power supply, a stray inductor, a SiC MOSFET tube Q connected in sequence M , a coupling coil and a SiC MOSFET parallel module; the SiC MOSFET parallel module includes a plurality of parallel branches, each branch includes a first coupling inductor, a second coupling inductor and a SiC MOSFET tube Q connected in series in sequence i , and the first coupling inductor of the first branch is negatively coupled with the second coupling inductor of the last branch, the first coupling inductor of the i-th branch is negatively coupled with the second coupling inductor of the i-1-th branch, and the second coupling inductor of the i-th branch is negatively coupled with the first coupling inductor of the i+1-th branch, i=2,3,…,n-1, n represents the number of branches;

[0005] The inductance values ​​of the first coupled inductor and the second coupled inductor in each branch are determined according to the current difference between the corresponding branches, so as to achieve current balance between the branches in the SiC MOSFET parallel module.

[0006] Furthermore, the coils of the two negatively coupled coupling inductors are wound on the same magnetic core, and the current directions of the two coupling inductors are opposite.

[0007] Furthermore, the coupled inductor is made by winding a PCB conductor around a magnetic core embedded in the PCB.

[0008] Furthermore, the coupling coil includes a primary side inductor, a secondary side inductor and a secondary side loop resistor, and the primary side inductor is connected in series to the SiC MOSFET tube Q M Between the SiC MOSFET parallel modules; the secondary side inductor and the secondary side loop resistor are connected in series to form a secondary side loop.

[0009] Furthermore, the calculation formula of the inductance value of the primary side inductor, the secondary side inductor, the first coupled inductor or the second coupled inductor is:

[0010] ;

[0011] Where, L represents the inductance value of the corresponding inductor, μ r represents the magnetic permeability of the magnetic material corresponding to the inductor, μ0 represents the magnetic permeability of the air, h represents the height of the magnetic core corresponding to the inductor, r2 represents the inner ring radius or diameter of the magnetic core corresponding to the inductor, r1 represents the outer ring radius or diameter of the magnetic core corresponding to the inductor, N t Indicates the number of coil turns corresponding to the inductance.

[0012] Based on the same concept, the present invention also provides a method for realizing parallel current sharing of SiC MOSFET by using coupled inductors, wherein a first coupled inductor and a second coupled inductor are added to each branch of the SiC MOSFET parallel module, the first end of the second coupled inductor is connected to the first coupled inductor, the second end of the second coupled inductor is connected to the drain of the corresponding SiC MOSFET tube, and the first coupled inductor of the first branch is negatively coupled with the second coupled inductor of the last branch, the first coupled inductor of the i-th branch is negatively coupled with the second coupled inductor of the i-1-th branch, and the second coupled inductor of the i-th branch is negatively coupled with the first coupled inductor of the i+1-th branch, i=2, 3, ..., n-1, and n represents the number of branches; the method comprises:

[0013] Determine the current difference ratio according to engineering practice requirements;

[0014] Determining the current difference between each branch in the SiC MOSFET parallel module according to the current difference ratio;

[0015] According to the current difference between each branch in the SiC MOSFET parallel module, the inductance values ​​of the first coupled inductor and the second coupled inductor in the corresponding branch are determined to achieve current balancing between each branch in the SiC MOSFET parallel module.

[0016] Furthermore, the calculation formula of the current difference ratio is:

[0017] △i d =(γ×I L ) / n;

[0018] Among them, △i d represents the current difference between the branches, γ represents the current difference ratio, I L represents the load current, and n represents the number of branches in the SiC MOSFET parallel module.

[0019] Furthermore, the relationship between the current difference between the branches and the inductance values ​​of the first coupled inductor and the second coupled inductor in the corresponding branch is:

[0020] ;

[0021] ;

[0022] Among them, △i d1i Indicates the current difference between the i-th branch and the first branch, △L d1i The drain parasitic inductance of the SiC MOSFET tube Q1 in the first branch and the drain parasitic inductance of the SiC MOSFET tube Q i The difference between the drain parasitic inductance, △L s1i The source parasitic inductance of the SiC MOSFET tube Q1 in the first branch and the source parasitic inductance of the SiC MOSFET tube Q in the i-th branch are shown in Figure 2. i The difference between the source parasitic inductance, I L represents the load current, t r Indicates the rise time of the load current, △R on1i The on-resistance of the SiC MOSFET tube Q1 in the first branch and the on-resistance of the SiC MOSFET tube Q i The difference between the on-resistance, L d1 represents the drain parasitic inductance of the SiC MOSFET tube Q1 in the first branch, L s1 represents the source parasitic inductance of the SiC MOSFET tube Q1 in the first branch, L mib represents the second coupled inductance of the i-th branch, L mit represents the first coupled inductance of the i-th branch, M 1irepresents the mutual inductance between the first branch and the i-th coupled inductor, s represents the differential operator, R oni represents the SiC MOSFET tube Q of the i-th branch i On-resistance; △i di-1,i represents the current difference between the i-th branch and the i-1-th branch, △L di-1,i represents the SiC MOSFET tube Q of the i-1th branch i-1 The drain parasitic inductance of the i-th branch SiC MOSFET tube Q i The difference between the drain parasitic inductance, △L si-1,i represents the SiC MOSFET tube Q of the i-1th branch i-1 The source parasitic inductance of the i-th branch SiC MOSFET tube Q i The difference between the source parasitic inductance, △R oni-1,i represents the SiC MOSFET tube Q of the i-1th branch i-1 The on-resistance of the SiC MOSFET tube Q of the i-th branch i The difference between the on-resistance, L di-1 represents the SiC MOSFET tube Q of the i-1th branch i-1 The drain parasitic inductance, L si-1 Represents the SiCMOSFET tube Q of the i-1th branch i-1 The source parasitic inductance, M i-1,i Represents the mutual inductance between the i-1th branch and the i-th coupled inductor.

[0023] Beneficial Effects

[0024] Compared with the prior art, the advantages of the present invention are:

[0025] The present invention adds a first coupling inductor and a second coupling inductor to each branch of the SiC MOSFET parallel module, so that the first coupling inductor and the second coupling inductor of each branch realize negative coupling with one of the coupling inductors of two branches adjacent to the branch, and then designs the first coupling inductor and the second coupling inductor in each branch according to the current difference between the branches, so that the conduction current distribution of the SiC MOSFET tubes in each parallel branch is balanced; at the same time, the present invention achieves a balanced conduction current distribution between the SiC MOSFET parallel module and the SiC MOSFET tube Q M A coupling coil is added between the two circuits to utilize the damping effect of the secondary circuit to suppress the switching oscillation of the SiC MOSFET device caused by stray inductance. At the same time, the parallel current balancing and oscillation suppression of the SiC MOSFET are achieved, which helps to give full play to the high switching speed advantage of the SiC power device and improve the reliability of the SiC MOSFET. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solution of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only one embodiment of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 1 is a schematic diagram of a SiC MOSFET parallel current sharing and oscillation suppression circuit in an embodiment of the present invention;

[0028] Figure 2 is a schematic diagram of a SiC MOSFET parallel module in an embodiment of the present invention;

[0029] Figure 3 is a diagram showing the relationship between the coupled inductor and the current difference between the branches in the embodiment of the present invention; wherein, L m represents the sum of the first coupled inductance and the second coupled inductance of the branch, and f represents the switching frequency;

[0030] Figure 4 Schematic diagram of the winding method of two negatively coupled inductor coils in an embodiment of the present invention; wherein i1 and i2 are the current directions of the two coils;

[0031] Figure 5 is a current simulation diagram of each branch when no coupling inductor is added in the embodiment of the present invention;

[0032] Figure 6 It is a current simulation diagram of each branch when the first coupled inductor and the second coupled inductor are added in the embodiment of the present invention. DETAILED DESCRIPTION

[0033] The following is a clear and complete description of the technical solutions in the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] The technical solution of the present application is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0035] Example 1

[0036] like Figure 1 and Figure 2As shown, a SiC MOSFET parallel current sharing and oscillation suppression circuit provided by an embodiment of the present invention includes a DC power supply V dc , stray inductance L loop 、SiC MOSFET tube Q M , coupling coil and SiC MOSFET parallel module; DC power supply V dc The positive electrode passes through the stray inductance L loop Compared with SiC MOSFET tube Q M The drain connection of SiC MOSFET tube Q M The source of is connected to the first end of the primary side inductor L1 of the coupling coil, the second end of the primary side inductor L1 is connected to one end of the SiC MOSFET parallel module, and the other end of the SiC MOSFET parallel module is connected to the DC power supply V dc The SiC MOSFET parallel module includes multiple branches connected in parallel, each branch includes a first coupled inductor, a second coupled inductor and a SiC MOSFET tube Q connected in series in sequence. i , and the first coupling inductor of the first branch is negatively coupled with the second coupling inductor of the last branch, the first coupling inductor of the i-th branch is negatively coupled with the second coupling inductor of the i-1-th branch, and the second coupling inductor of the i-th branch is negatively coupled with the first coupling inductor of the i+1-th branch, i = 2, 3, ..., n-1, n represents the number of branches. The SiC MOSFET tube Q1 of the first branch is driven by the drive signal V G1 Drive, R G1 is the gate resistance of SiC MOSFET tube Q1.

[0037] In order to achieve current balancing between branches in the SiC MOSFET parallel module, the present invention adds a first coupling inductor and a second coupling inductor to each branch in the SiC MOSFET parallel module, and the first coupling inductor and the second coupling inductor of each branch realize negative coupling with one of the coupling inductors of the two branches adjacent to the branch. Taking the SiC MOSFET parallel module including three branches in parallel as an example, Figure 1 As shown, the first branch in the SiC MOSFET parallel module includes the first coupled inductor L connected in series. m1t , the second coupled inductor L m1b and SiC MOSFET tube Q1; the second branch in the SiC MOSFET parallel module includes a first coupled inductor L connected in series in sequence m2t , the second coupled inductor L m2b and SiC MOSFET tube Q2; the third branch in the SiC MOSFET parallel module includes the first coupled inductor L connected in series in sequence m3t , the second coupled inductor L m3bAnd SiC MOSFET tube Q3. The first coupled inductor L of the first branch m1t The second coupling inductor L of the last branch (i.e. the third branch) m3b To achieve negative coupling, the mutual inductance is M 31 ; The first coupled inductor L of the second branch m2t The second coupling inductor L of the first branch m1b To achieve negative coupling, the mutual inductance is M 12 , the second coupled inductor L of the second branch m2b The first coupling inductor L of the third branch m3t To achieve negative coupling, the mutual inductance is M 23 .

[0038] In this embodiment, the SiC MOSFET tube Q M SiC MOSFET tube Q4, that is, SiC MOSFET tube Q M The subscript M is equal to n+1, where n is the number of branches of the SiC MOSFET parallel module.

[0039] The SiC MOSFET parallel module and the SiC MOSFET tube Q4 form a half-bridge structure, wherein the SiC MOSFET tube Q4 is the upper bridge arm of the half-bridge structure, and the SiC MOSFET parallel module is the lower bridge arm of the half-bridge structure. In another embodiment of the present invention, the circuit includes a DC power supply V connected in sequence dc , stray inductance L loop , SiC MOSFET parallel module, coupling coil and SiC MOSFET tube Q4, that is, the SiC MOSFET parallel module is the upper bridge arm of the half-bridge structure, and the SiC MOSFET tube Q4 is the lower bridge arm of the half-bridge structure. When the SiC MOSFET tube Q4 is the upper bridge arm of the half-bridge structure and the SiC MOSFET parallel module is the lower bridge arm of the half-bridge structure, the circuit has better current carrying capacity.

[0040] The principle of adding the first coupled inductor and the second coupled inductor to each branch in the SiC MOSFET parallel module to achieve current balancing is as follows:

[0041] (1)

[0042] Among them, L d1 represents the drain parasitic inductance of the first branch SiC MOSFET tube Q1, L s1 represents the source parasitic inductance of the first branch SiCMOSFET tube Q1, i d1 represents the drain current of the first branch, i d1 / dt represents the rate of change of drain current of the first branch, id2 represents the drain current of the second branch, i d2 / dt represents the rate of change of drain current in the second branch, i d3 represents the drain current of the third branch, i d3 / dt represents the rate of change of the drain current of the third branch, R on1 represents the on-resistance of the first branch SiCMOSFET tube Q1; L d2 represents the drain parasitic inductance of the second branch SiC MOSFET tube Q2, L s2 represents the source parasitic inductance of the second branch SiC MOSFET tube Q2, R on2 represents the on-resistance of the second branch SiC MOSFET tube Q2; L d3 represents the drain parasitic inductance of the third branch SiC MOSFET tube Q3, L s3 represents the source parasitic inductance of the third branch SiC MOSFET tube Q3, R on3 represents the on-resistance of the third branch SiC MOSFET tube Q3; L di represents the SiC MOSFET tube Q of the i-th branch i The drain parasitic inductance, L si represents the SiC MOSFET tube Q of the i-th branch i The source parasitic inductance, i di represents the drain current of the ith branch, L mit and L mib denote the first coupled inductance and the second coupled inductance of the i-th branch, respectively, M i-1,i represents the mutual inductance between the i-1th branch and the i-th coupled inductor, M i,i+1 represents the mutual inductance between the i-th branch and the i+1-th coupled inductor, R oni represents the SiC MOSFET tube Q of the i-th branch i The on-resistance.

[0043] because

[0044] (2)

[0045] (3)

[0046] (4)

[0047] (5)

[0048] (6)

[0049] Among them, △Ld12 It represents the difference between the drain parasitic inductance of the SiC MOSFET tube Q1 in the first branch and the drain parasitic inductance of the SiC MOSFET tube Q2 in the second branch, △L d13 It represents the difference between the drain parasitic inductance of the SiC MOSFET tube Q1 in the first branch and the drain parasitic inductance of the SiC MOSFET tube Q3 in the third branch, △L d1i The drain parasitic inductance of the SiC MOSFET tube Q1 in the first branch and the drain parasitic inductance of the SiC MOSFET tube Q i The difference between the drain parasitic inductance of s12 Indicates the difference between the source parasitic inductance of the SiC MOSFET tube Q1 in the first branch and the source parasitic inductance of the SiC MOSFET tube Q2 in the second branch, △L s13 It represents the difference between the source parasitic inductance of the SiC MOSFET tube Q1 in the first branch and the source parasitic inductance of the SiC MOSFET tube Q3 in the third branch, △L s1i The source parasitic inductance of the SiC MOSFET tube Q1 in the first branch and the source parasitic inductance of the SiC MOSFET tube Q i The difference between the source parasitic inductance of on12 The difference between the on-resistance of the SiC MOSFET Q1 in the first branch and the on-resistance of the SiC MOSFET Q2 in the second branch, △R on13 The difference between the on-resistance of the SiC MOSFET tube Q1 in the first branch and the on-resistance of the SiC MOSFET tube Q3 in the third branch, △R on1i The on-resistance of the SiC MOSFET tube Q1 in the first branch and the on-resistance of the SiC MOSFET tube Q i The difference between the on-resistance of d12 Indicates the current difference between the second branch and the first branch, △i d13 Indicates the current difference between the third branch and the first branch, △i d1i represents the current difference between the ith branch and the first branch; L mib represents the second coupled inductance of the i-th branch, L mit represents the first coupled inductance of the i-th branch.

[0050] According to formula (1) to formula (6), we can get:

[0051] (7)

[0052] (8)

[0053] According to formula (7) and formula (8), we can get:

[0054] (9)

[0055] (10)

[0056] because , where t r Indicates the load current I L The rise time of

[0057] (11)

[0058] (12)

[0059] (13)

[0060] According to formula (11) to formula (13), the current difference between each branch is negatively correlated with the first coupled inductor and the second coupled inductor in the corresponding branch. Therefore, the unbalanced on-current can be limited by designing the first coupled inductor and the second coupled inductor of each branch.

[0061] Under the condition of known circuit parameters and parasitic parameters of SiC MOSFET tube, the current difference ratio between the two branches of the SiC MOSFET parallel module is determined according to engineering practice requirements. In this embodiment, the current difference ratio γ is set to 0.01-0.05. Then, the current difference between the branches in the SiC MOSFET parallel module is determined according to the current difference ratio γ. The specific formula is:

[0062] △i di-1,i =(γ×I L ) / n (14)

[0063] Among them, △i di-1,i represents the current difference between the i-th branch and the i-1-th branch, γ represents the current difference ratio, I L represents the load current, and n represents the number of branches in the SiC MOSFET parallel module. In this embodiment, n is 3.

[0064] Based on formula (12) and formula (13), the parameter range of the inductance value of the first coupled inductor and the second coupled inductor of each branch can be determined according to the current difference between each branch, such as Figure 3 shown.

[0065] In a specific embodiment of the present invention, the coils of the two coupled inductors with negative coupling are wound on the same magnetic core, and the current directions of the two coupled inductors are opposite, such as Figure 4 As shown. Exemplarily, the first coupled inductor L of the first branch m1t The second coupling inductor L of the third branch m3b The coils are wound on the same magnetic core and the current directions of the coils are opposite. The first coupling inductor L of the second branch m2t The second coupling inductor L of the first branch m1b The coils are wound on the same magnetic core and the current directions of the coils are opposite. The second coupling inductor L of the second branch m2b The first coupling inductor L of the third branch m3t The coils are wound on the same magnetic core and the current directions of the coils are opposite.

[0066] In a specific embodiment of the present invention, the magnetic core of the coupled inductor (i.e., the first coupled inductor and the second coupled inductor) is embedded in a PCB (Printed Circuit Board), and the coupled inductor is made by winding a PCB wire around the magnetic core embedded in the PCB.

[0067] The specific process of embedding coupled inductors in PCB is as follows: first, the PCB is divided into 1mm thick upper and lower plates, and a groove process is used to dig out annular grooves with the same size as the core but a depth of 0.5 mm on the back of the upper and lower plates; second, in order to make the thickness of the core meet the design requirements, the core is ground to reduce the thickness of the core to 1mm; finally, the prepared NiZn ferrite core is embedded in the annular groove of the PCB; then the upper and lower plates are pressed into one plate through the PCB lamination process, and the through holes of the upper and lower plates are connected with solder, and the resistor R2 is soldered to the pad of the PCB. After the embedded coupled inductor is constructed, the high-frequency characteristics of the entire circuit can meet the requirements of the switching frequency and oscillation frequency of SiC MOSFET, and the parameters of the designed coil are measured by the ENA network analyzer.

[0068] In order to eliminate the stray inductance L of the power circuit loop As well as the negative effects of increasing the coupling inductance, namely switching oscillation, the SiC MOSFET tube Q M A coupling coil is added between the SiC MOSFET parallel module. The coupling coil includes a primary side inductor L1, a secondary side inductor L2 and a secondary side loop resistor R2. The primary side inductor L1 is connected in series with the SiC MOSFET tube Q M Between the modules connected in parallel with the SiC MOSFET; the secondary side inductor L2 and the secondary side loop resistor R2 are connected in series to form a secondary side loop. The coupling effect is used to increase the damping of the power loop, thereby suppressing the switching oscillation.

[0069] In a specific embodiment of the present invention, the calculation formula of the inductance value of the primary side inductor L1, the secondary side inductor L2, the first coupled inductor or the second coupled inductor is:

[0070] (15)

[0071] Where, L represents the inductance value of the corresponding inductor, μ r represents the magnetic permeability of the magnetic material corresponding to the inductor, μ0 represents the magnetic permeability of the air, h represents the height of the magnetic core corresponding to the inductor, r2 represents the inner ring radius or diameter of the magnetic core corresponding to the inductor, r1 represents the outer ring radius or diameter of the magnetic core corresponding to the inductor, N t Indicates the number of coil turns corresponding to the inductance.

[0072] Exemplarily, the inductance calculation formula of the primary side inductor L1 is: , where L1 represents the inductance of the primary side inductor L1, μ r represents the magnetic permeability of the magnetic material of the primary inductor L1, μ0 represents the air permeability, h represents the core height of the primary inductor L1, r2 represents the inner ring radius or diameter of the core of the primary inductor L1, r1 represents the outer ring radius or diameter of the core of the primary inductor L1, N t Indicates the number of turns of the primary inductor L1.

[0073] In a specific embodiment of the present invention, the DC power supply V dc The two ends of the capacitor are connected in parallel with a DC capacitor C bus and parasitic resistance R esr The series branch of SiC MOSFET tube Q M The two ends of the load inductor L are connected in parallel load .

[0074] Figure 5 and Figure 6 The simulation comparison of the branch currents without and with coupling inductance is shown. Figure 5 and Figure 6 It can be seen that the coupled inductor in the branch and the coupled coil in the power loop can not only balance the current unevenness of the parallel SiC MOSFET tubes, but also suppress the switching oscillation.

[0075] Example 2

[0076] The embodiment of the present invention also provides a method for realizing current sharing of SiC MOSFETs in parallel by using coupled inductors, such as Figure 2As shown, a first coupling inductor and a second coupling inductor are added to each branch of the SiC MOSFET parallel module, a first end of the second coupling inductor is connected to the first coupling inductor, a second end of the second coupling inductor is connected to the drain of the corresponding SiC MOSFET tube, and the first coupling inductor of the first branch is negatively coupled with the second coupling inductor of the last branch, the first coupling inductor of the i-th branch is negatively coupled with the second coupling inductor of the i-1-th branch, and the second coupling inductor of the i-th branch is negatively coupled with the first coupling inductor of the i+1-th branch, i=2, 3, ..., n-1, and n represents the number of branches.

[0077] The method comprises the following steps:

[0078] Step S1: determining the current difference ratio according to engineering practice requirements;

[0079] Step S2: determining the current difference between each branch in the SiC MOSFET parallel module according to the current difference ratio, as shown in formula (14);

[0080] Step S3: Determine the inductance values ​​of the first coupled inductor and the second coupled inductor in the corresponding branch according to the current difference between the branches in the SiC MOSFET parallel module (as shown in formula (12) and formula (13)), so as to achieve current balance between the branches in the SiC MOSFET parallel module.

[0081] The size of the magnetic core can be designed according to the inductance values ​​of the first coupled inductor and the second coupled inductor and formula (15).

[0082] For example, the current difference ratio γ is set to 0.01-0.05, n is 3, and the load current I L If the current difference is 40A, then the current difference △i is calculated according to formula (14): di-1,i =0.2A~1A; the current difference △i di-1,i =0.2A~1A Substitute into formula (13), then select the first coupling inductor L of the i-th branch mit and the second coupling inductor L mib is 850nH.

[0083] What is disclosed above is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or modifications within the technical scope disclosed in the present invention, which should be covered within the protection scope of the present invention.

Claims

1. A SiC MOSFET parallel current sharing and oscillation suppression circuit, comprising a DC power supply, a stray inductor, a SiC MOSFET tube Q connected in sequence M , a coupling coil and a SiC MOSFET parallel module; characterized in that, The SiC MOSFET parallel module includes a plurality of branches connected in parallel, each branch including a first coupled inductor, a second coupled inductor and a SiC MOSFET tube Q connected in series in sequence. i , and the first coupling inductor of the first branch is negatively coupled with the second coupling inductor of the last branch, the first coupling inductor of the i-th branch is negatively coupled with the second coupling inductor of the i-1-th branch, and the second coupling inductor of the i-th branch is negatively coupled with the first coupling inductor of the i+1-th branch, i=2,3,…,n-1, n represents the number of branches; The inductance values ​​of the first coupled inductor and the second coupled inductor in each branch are determined according to the current difference between the corresponding branches, so as to achieve current balancing between the branches in the SiC MOSFET parallel module; The relationship between the current difference between each branch and the inductance value of the first coupled inductor and the second coupled inductor in the corresponding branch is: ； ； Among them, △i d1i Indicates the current difference between the i-th branch and the first branch, △L d1i The drain parasitic inductance of the SiC MOSFET tube Q1 in the first branch and the drain parasitic inductance of the SiC MOSFET tube Q i The difference between the drain parasitic inductance, △L s1i The source parasitic inductance of the SiC MOSFET tube Q1 in the first branch and the source parasitic inductance of the SiC MOSFET tube Q in the i-th branch are shown in Figure 2. i The difference between the source parasitic inductance, I L represents the load current, t r Indicates the rise time of the load current, △R on1i The on-resistance of the SiC MOSFET tube Q1 in the first branch and the on-resistance of the SiC MOSFET tube Q i The difference between the on-resistance, L d1 represents the drain parasitic inductance of the SiC MOSFET tube Q1 in the first branch, L s1 represents the source parasitic inductance of the SiC MOSFET tube Q1 in the first branch, L mib represents the second coupled inductance of the i-th branch, L mit represents the first coupled inductance of the i-th branch, M 1i represents the mutual inductance between the first branch and the i-th coupled inductor, s represents the differential operator, R oni represents the SiC MOSFET tube Q of the i-th branch i On-resistance; △i di-1,i represents the current difference between the i-th branch and the i-1-th branch, △L di-1,i represents the SiC MOSFET tube Q of the i-1th branch i-1 The drain parasitic inductance of the i-th branch SiC MOSFET tube Q i The difference between the drain parasitic inductance, △L si-1,i represents the SiC MOSFET tube Q of the i-1th branch i-1 The source parasitic inductance of the i-th branch SiC MOSFET tube Q i The difference between the source parasitic inductance, △R oni-1,i represents the SiC MOSFET tube Q of the i-1th branch i-1 The on-resistance of the SiC MOSFET tube Q of the i-th branch i The difference between the on-resistance, L di-1 represents the SiC MOSFET tube Q of the i-1th branch i-1 The drain parasitic inductance, L si-1 Represents the SiCMOSFET tube Q of the i-1th branch i-1 The source parasitic inductance, M i-1,i Represents the mutual inductance between the i-1th branch and the i-th coupled inductor.

2. The SiC MOSFET parallel current sharing and oscillation suppression circuit according to claim 1, characterized in that: The coils of the two coupled inductors of the negative coupling are wound on the same magnetic core, and the current directions of the two coupled inductors are opposite.

3. The SiC MOSFET parallel current sharing and oscillation suppression circuit according to claim 2, characterized in that: The coupled inductor is made by winding a PCB conductor around a magnetic core embedded in the PCB.

4. The SiC MOSFET parallel current sharing and oscillation suppression circuit according to any one of claims 1 to 3, characterized in that: The coupling coil includes a primary side inductor, a secondary side inductor and a secondary side loop resistor, and the primary side inductor is connected in series to the SiC MOSFET tube Q M Between the SiC MOSFET parallel modules; the secondary side inductor and the secondary side loop resistor are connected in series to form a secondary side loop.

5. The SiC MOSFET parallel current sharing and oscillation suppression circuit according to claim 4, characterized in that: The calculation formula of the inductance value of the primary side inductor, the secondary side inductor, the first coupled inductor or the second coupled inductor is: ； Where, L represents the inductance value of the corresponding inductor, μ r represents the magnetic permeability of the magnetic material corresponding to the inductor, μ0 represents the magnetic permeability of the air, h represents the height of the magnetic core corresponding to the inductor, r2 represents the inner ring radius or diameter of the magnetic core corresponding to the inductor, r1 represents the outer ring radius or diameter of the magnetic core corresponding to the inductor, N t Indicates the number of coil turns corresponding to the inductance.

6. A method for realizing current sharing of SiC MOSFETs in parallel by using coupled inductors, characterized in that: A first coupling inductor and a second coupling inductor are added to each branch of the SiC MOSFET parallel module, the first end of the second coupling inductor is connected to the first coupling inductor, the second end of the second coupling inductor is connected to the drain of the corresponding SiC MOSFET tube, and the first coupling inductor of the first branch is negatively coupled with the second coupling inductor of the last branch, the first coupling inductor of the i-th branch is negatively coupled with the second coupling inductor of the i-1-th branch, and the second coupling inductor of the i-th branch is negatively coupled with the first coupling inductor of the i+1-th branch, i=2, 3, ..., n-1, and n represents the number of branches; the method comprises: Determine the current difference ratio according to engineering practice requirements; Determining the current difference between each branch in the SiC MOSFET parallel module according to the current difference ratio; Determine the inductance values ​​of the first coupled inductor and the second coupled inductor in the corresponding branch according to the current difference between the branches in the SiC MOSFET parallel module, so as to achieve current balancing between the branches in the SiC MOSFET parallel module; The relationship between the current difference between each branch and the inductance value of the first coupled inductor and the second coupled inductor in the corresponding branch is: ； ； Among them, △i d1i Indicates the current difference between the i-th branch and the first branch, △L d1i The drain parasitic inductance of the SiC MOSFET tube Q1 in the first branch and the drain parasitic inductance of the SiC MOSFET tube Q i The difference between the drain parasitic inductance, △L s1i The source parasitic inductance of the SiC MOSFET tube Q1 in the first branch and the source parasitic inductance of the SiC MOSFET tube Q in the i-th branch are shown in Figure 2. i The difference between the source parasitic inductance, I L represents the load current, t r Indicates the rise time of the load current, △R on1i The on-resistance of the SiC MOSFET tube Q1 in the first branch and the on-resistance of the SiC MOSFET tube Q i The difference between the on-resistance, L d1 represents the drain parasitic inductance of the SiC MOSFET tube Q1 in the first branch, L s1 represents the source parasitic inductance of the SiC MOSFET tube Q1 in the first branch, L mib represents the second coupled inductance of the i-th branch, L mit represents the first coupled inductance of the i-th branch, M 1i represents the mutual inductance between the first branch and the i-th coupled inductor, s represents the differential operator, R oni represents the SiC MOSFET tube Q of the i-th branch i On-resistance; △i di-1,i represents the current difference between the i-th branch and the i-1-th branch, △L di-1,i represents the SiC MOSFET tube Q of the i-1th branch i-1 The drain parasitic inductance of the i-th branch SiC MOSFET tube Q i The difference between the drain parasitic inductance, △L si-1,i represents the SiC MOSFET tube Q of the i-1th branch i-1 The source parasitic inductance of the i-th branch SiC MOSFET tube Q i The difference between the source parasitic inductance, △R oni-1,i represents the SiC MOSFET tube Q of the i-1th branch i-1 The on-resistance of the SiC MOSFET tube Q of the i-th branch i The difference between the on-resistance, L di-1 represents the SiC MOSFET tube Q of the i-1th branch i-1 The drain parasitic inductance, L si-1 Represents the SiCMOSFET tube Q of the i-1th branch i-1 The source parasitic inductance, M i-1,i Represents the mutual inductance between the i-1th branch and the i-th coupled inductor.

7. The method according to claim 6, characterized in that The calculation formula of the current difference ratio is: △i d =(γ×I L ) / n; Among them, △i d represents the current difference between the branches, γ represents the current difference ratio, I L represents the load current, and n represents the number of branches in the SiC MOSFET parallel module.

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