Method and computing device for extracting chip power consumption evaluation waveform

Abstract

The present invention provides a method and computing device for extracting chip power consumption evaluation waveforms. A power consumption detection component is designed by detecting the effective flipping of a module interface. The method includes: loading an integrated power consumption detection component in a simulation environment, wherein the power consumption detection component is implemented based on the effective flipping judgment information of the module interface of the chip; running the simulation environment to simulate power consumption scenarios, and obtaining a predetermined signal flipping rate threshold of the module interface at a power consumption evaluation waveform time point through the power consumption detection component; storing the predetermined signal flipping rate threshold as a configuration item in a corresponding test case for power consumption simulation; and automatically extracting the power consumption evaluation waveform of the test case in subsequent simulations according to the predetermined signal flipping rate threshold. The technical solution according to the present invention can realize automatic acquisition of power consumption waveforms and improve power consumption evaluation efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of chip development, and in particular to a method for extracting chip power consumption evaluation waveforms, a computer program product and a computing device. Background Art

[0002] With the development of science and technology, the demand for digitalization and automation is increasing. Chips, as the basis of related technologies, are being widely used. As chip performance continues to increase, chip power consumption is also increasing. In order to meet various special power consumption requirements, it has become a reasonable demand to evaluate the power consumption of chips. Generally speaking, there are several ways to evaluate the power consumption of chips, including actual measurement after the chip is produced, and after generating the netlist file, using the netlist for electronic design automation (EDA) simulation, calculating the relevant device parameters through tools, and obtaining the power consumption of the chip. For current chip design, chips are usually composed of multiple parts and are large in scale. Unified netlist simulation requires a lot of resources and may be difficult to carry out, which adds difficulty to the work of power consumption evaluation.

[0003] As the scale of chips increases, the difficulty of chip design is also increasing. Functions, power consumption and area need to be traded off. Therefore, the earlier the power consumption evaluation results are obtained, the easier it is to modify. Therefore, new requirements are put forward for the evaluation of chip power consumption, and the need for power consumption simulation is also put forward at different stages of EDA pre-simulation. In addition, for chip power simulation, since the main information of the power consumption simulation waveform is the same, it does not require a long simulation waveform. Usually, only a waveform of tens of microseconds can be used for power consumption evaluation. However, in actual simulation scenarios, the actual waveform of EDA simulation is usually large and needs to be intercepted. The work of finding the right waveform moment is very time-consuming, and the logical relationship of the pipeline signal needs to be given by the design colleagues of the corresponding module before it can be determined. Since there is a certain randomness in the simulation, the power consumption waveform period extracted each time may no longer be applicable after the next code modification, and the time point needs to be found again, which is very time-consuming. In the early and middle stages of chip development, there may be more modifications, which brings more consumption to power consumption simulation. Not only that, since the scene of power consumption simulation and the selection of waveform period are constructed by designers, human errors or omissions may occur, resulting in inaccurate power consumption evaluation. For example, the maximum power consumption scenario constructed is not actually the maximum power consumption scenario, which causes the chip to exceed the power consumption standard in the actual maximum power consumption scenario. When the power consumption comparison is performed after the actual test to confirm, the chip has already been taped out, and it is too costly to make changes.

[0004] Existing chip power consumption testing technology does not have the ability to automatically select the time points of the power consumption waveform, and needs to be done manually. In addition, the extracted time point information cannot be reused and needs to be reconfirmed each time, which is very inefficient. When different modules of the chip are delivered by different teams, the confirmation work is even more time-consuming.

[0005] After manually extracting the power consumption waveform time points, power consumption evaluation is performed, and then the design is adjusted. After the adjustment, the power consumption waveform time points are found again. This process is repeated and requires cooperation from multiple departments, which is time-consuming and labor-intensive.

[0006] Therefore, a technical solution is needed to automatically obtain power consumption waveforms and improve the efficiency of power consumption evaluation. Summary of the invention

[0007] The present invention aims to provide a method, a computer program product and a computing device for extracting a chip power consumption evaluation waveform, which can realize automatic acquisition of the power consumption waveform and improve the power consumption evaluation efficiency.

[0008] According to one aspect of the present invention, a method for extracting a chip power consumption evaluation waveform is provided, the method comprising:

[0009] Loading an integrated power consumption detection component in a simulation environment, wherein the power consumption detection component is implemented based on effective flip judgment information of a module interface of the chip;

[0010] Running the simulation environment to perform power consumption scenario simulation, and obtaining a predetermined signal flip rate threshold of the module interface at a power consumption evaluation waveform time point through the power consumption detection component;

[0011] Storing the predetermined signal toggle rate threshold as a configuration item in a corresponding test case for power consumption simulation;

[0012] According to the predetermined signal toggle rate threshold, the power consumption evaluation waveform of the test case is automatically extracted in subsequent simulation.

[0013] According to some embodiments, the method further comprises:

[0014] In response to iterative updates of the design, the power consumption scenario simulation is performed directly on the iteratively updated register transfer level code using a test case recorded with the predetermined signal toggle rate threshold.

[0015] According to some embodiments, automatically extracting a power consumption evaluation waveform of a test case in a subsequent simulation according to the predetermined signal toggle rate threshold includes:

[0016] When the effective flip judgment information is met, start monitoring the predetermined signal flip rate;

[0017] When the predetermined signal flip rate is greater than the predetermined signal flip rate threshold and is maintained for a first predetermined time, recording the corresponding time point as a starting point and triggering waveform storage;

[0018] The second predetermined time is delayed and the end time is recorded, triggering the stopping of waveform storage, thereby obtaining the power consumption evaluation waveform.

[0019] According to some embodiments, the method further comprises:

[0020] By performing use case regression on different power consumption scenarios, detecting the predetermined signal flip rate under different power consumption scenarios, and determining whether the predetermined signal flip rate meets expectations;

[0021] If the detected predetermined signal toggle rate is greater than the predetermined signal toggle rate threshold, a waveform inspection is triggered to check whether the power consumption scenario meets expectations.

[0022] According to some embodiments, the valid flip judgment information includes:

[0023] A combination of chip data signals and function signals; and / or

[0024] A combination of chip configuration register values; and / or

[0025] Chip control signal sequence.

[0026] According to some embodiments, the power consumption detection component is configured as:

[0027] Setting a trigger condition for a valid scene according to the valid flip judgment information;

[0028] When a trigger condition that satisfies the effective scenario occurs, the effective flip rate of the predetermined signal on the module interface is counted.

[0029] According to some embodiments, the power consumption detection component is integrated into the top layer of the simulation environment through a virtual interface, and a macro path is used to indicate an absolute path at the module level.

[0030] According to some embodiments, the power consumption detection component is integrated into the top level of the simulation environment via a function.

[0031] According to another aspect of the present invention, a computer program product is provided, characterized in that it comprises: a computer program, and when the computer program is executed by a processor, it implements any of the methods described above.

[0032] According to another aspect of the present invention, there is provided a computing device, comprising:

[0033] Processor; and

[0034] A memory storing a computer program, which, when executed by the processor, enables the processor to execute any of the methods described above.

[0035] According to another aspect of the present invention, there is provided a non-transitory computer-readable storage medium having computer-readable instructions stored thereon, and when the instructions are executed by a processor, the processor is caused to execute any of the above methods.

[0036] According to an embodiment of the present invention, by adding the power consumption detection component tool in the power consumption scenario simulation, a predetermined signal toggle rate threshold of the power consumption assessment waveform time period is obtained, and the power consumption assessment waveform of subsequent test cases is automatically extracted according to the predetermined signal toggle rate threshold, thereby realizing automated waveform extraction, improving power consumption assessment efficiency, reducing labor costs and time costs in the power consumption testing process, and improving design and development efficiency.

[0037] According to some embodiments, the design scheme of the present invention achieves equivalent power consumption statistics for all verification and regression scenarios by adding the power consumption detection component tool when verifying and regressing different scenarios. It can compare special power consumption scenarios such as maximum and minimum, and compare them with the power consumption scenarios given by the designer to confirm whether they are the corresponding special power consumption scenarios.

[0038] It is to be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for describing the embodiments are briefly introduced below.

[0040] Figure 1 A flow chart of a method for extracting a chip power consumption evaluation waveform according to an example embodiment is shown.

[0041] Figure 2 A schematic diagram of a method for extracting a chip power consumption evaluation waveform according to an example embodiment is shown.

[0042] Figure 3 A schematic diagram of an application of a method for extracting a chip power consumption evaluation waveform according to an example embodiment is shown.

[0043] Figure 4 A block diagram of a computing device is shown according to an exemplary embodiment. DETAILED DESCRIPTION

[0044] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present invention will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.

[0045] In addition, the described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present invention. However, those skilled in the art will appreciate that the technical solution of the present invention can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring various aspects of the present invention.

[0046] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0047] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0048] It should be understood that although the terms first, second, third, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another component. Therefore, the first component discussed below can be referred to as the second component without departing from the teachings of the present inventive concept. As used herein, the term "and / or" includes any one of the associated listed items and all combinations of one or more.

[0049] The user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the present invention are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0050] Those skilled in the art will appreciate that the drawings are merely schematic diagrams of example embodiments, and the modules or processes in the drawings are not necessarily necessary for implementing the present invention, and therefore cannot be used to limit the protection scope of the present invention.

[0051] With the development of chip technology and the demand for chip capabilities in real life and scenarios, the functions and design scale of chips are gradually expanding, and the functions are becoming more complex. Therefore, the evaluation of chip power consumption is more detailed, pre-emptive and automated. Power consumption waveform analysis is developing towards higher accuracy, faster speed and more comprehensive coverage.

[0052] Therefore, automated power consumption assessment methods have also become one of the research hotspots. The power consumption waveform is a graphical representation of the power consumption changes of an electronic device or circuit over a period of time. By analyzing the power consumption waveform, engineers can identify high-power operation modes and optimize these modes to improve the overall energy efficiency of the system. The power consumption waveform helps to understand the heat distribution of the device during operation, which is very important for designing cooling solutions. Abnormal power consumption waveforms may indicate problems at the hardware or software level, helping technicians to quickly locate the source of the fault. Through an in-depth understanding and analysis of the power consumption waveform, designers and engineers can better cope with the energy efficiency challenges faced by various electronic devices, while also improving the reliability and market competitiveness of products.

[0053] To this end, the present invention proposes a method, a computer program product, and a computing device for extracting chip power consumption evaluation waveforms, which can realize automatic acquisition of power consumption waveforms. According to an embodiment, by adding the power consumption detection component tool in the power consumption scenario simulation, and automatically extracting the power consumption evaluation waveform of subsequent test cases according to the predetermined signal flip rate threshold, automated waveform extraction is achieved, the power consumption evaluation efficiency is improved, the labor cost and time cost in the power consumption test process are reduced, and the design and development efficiency is improved. When verifying and regressing different scenarios, the power consumption detection component tool is added to realize the equivalent statistics of power consumption for all verification and regression scenarios, and the maximum, minimum, and other special power consumption scenarios can be compared, and compared with the power consumption scenarios given by the designer to confirm whether it is the corresponding special power consumption scenario.

[0054] Before describing the embodiments of the present invention, some terms or concepts involved in the embodiments of the present invention are explained.

[0055] Signal flip: When a digital signal changes from 0 to 1, or from 1 to 0, it is called flip. For digital circuits, power consumption includes dynamic power consumption and static power consumption. Dynamic power consumption occurs when the MOS tube is turned on, that is, when it flips. Therefore, by counting the flip rate, it is equivalent to judging the power consumption.

[0056] Interface valid flip: For a chip module, the flip of the interface signal does not mean that the chip is working. For example, there is a set of interface signals of vld and data. The chip only accepts data when the vld signal is high. Therefore, even if the data interface is flipping, but vld is always low, the actual chip will not work. At this time, the interface is invalidly flipped. There are many ways to confirm the effective flip of the interface, including the combination judgment of the interface signal / function signal, the combination judgment of the configuration register value, the control signal sequence judgment, etc.

[0057] Virtual interface: The virtual interface here does not refer to the actual module interface, but the SystemVerilog interface file constructed as needed. The signals inside the module are encapsulated into an interface and instantiated as a virtual type to facilitate verification calls and connections between different components.

[0058] Interface is a Verilog component, but it can be instantiated into two forms: interface and virtualinterface. The ordinary interface form can only be connected to the physical RTL component, such as module, using assign or .a (b) connection; in the virtual interface form, it can be connected and transferred arbitrarily.

[0059] Exemplary embodiments of the present invention are described below with reference to the accompanying drawings.

[0060] Figure 1 A flow chart of a method for extracting a chip power consumption evaluation waveform according to an example embodiment is shown.

[0061] See also Figure 1 According to an example embodiment, a method for extracting a chip power consumption evaluation waveform includes:

[0062] In S101, an integrated power consumption detection component is loaded in a simulation environment, wherein the power consumption detection component is implemented based on effective flip judgment information of a module interface of the chip.

[0063] According to some embodiments, an integrated power consumption detection component is loaded in a simulation environment, and the power consumption detection component is written by collating the effective flip judgment information of the interface and writing the power consumption detection component according to the effective flip judgment information. The effective flip judgment information of the interface is confirmed by the designer, which may be the encoding state of the control signal input by the interface, or the combination result of the configuration information input by the interface, which is determined by the specific module function and implementation, such as sig_a=1, sig_b=1. Afterwards, the power consumption detection component is written according to the effective flip judgment information, which may be a virtual interface or function mode.

[0064] According to some embodiments, the power consumption detection component can be implemented by writing a function in the interface, or by passing the interface to components of other classes and writing a judgment function in the class; different methods can be selected to write the power consumption detection component according to the environment encapsulation and complexity.

[0065] According to some embodiments, the power consumption detection component is integrated into the existing simulation environment as a submodule to ensure that it can work in conjunction with other modules. The simulation environment is configured so that it can load the power consumption detection component and run correctly. This may involve modifying simulation scripts or configuration files. After the power consumption detection component is integrated into the simulation environment, it is also necessary to test the power consumption detection component separately to ensure that it can correctly monitor signal flips and record relevant data. The power consumption detection component is tested together with other simulation modules to ensure that the interaction between them is as expected. Some basic test scenarios are run through simulation to verify whether the power consumption detection component can collect data correctly.

[0066] In S103, the simulation environment is run to perform power consumption scenario simulation, and a predetermined signal flip rate threshold of the module interface at a power consumption evaluation waveform time point is obtained through the power consumption detection component.

[0067] According to some embodiments, first, ensure that the power consumption detection component has been correctly integrated into the simulation environment, and set the simulation time length, sampling interval and other parameters so as to capture sufficiently detailed power consumption waveform data. Prepare a series of test cases according to the power consumption scenarios that need to be evaluated. These test cases should cover various possible operating states and workloads. Start the simulation environment and begin executing the test cases. The power consumption detection component will monitor the specified predetermined signal and record the signal flip rate of each predetermined signal. During the simulation process, the power consumption detection component will collect information such as the timestamp of the signal flip, the state before and after the flip, etc.

[0068] According to some embodiments, the data collected during the simulation process is exported, and based on the collected data, the signal flip rate in each time period is calculated. The flip rate can be obtained by dividing the number of flips by the length of time. According to the calculated flip rate data, determine which flip rates are critical. For example, a group of 16-bit data signals are detected, and the current signal value and the signal value of the previous clock cycle are compared once in each clock cycle. The number of bits of the signal value change is recorded and divided by 16 to obtain the flip rate of the data signal. For example, the first beat is 16'h0000, the second beat is 16'hFFFF, the third beat is 16'h000F, and the fourth beat is 16'h000F. Then the flip rate from the first beat to the second beat is 16 / 16=100%, the flip rate from the second beat to the third beat is 12 / 16=75%, and the flip rate from the third beat to the fourth beat is 0 / 16=0%. The total average flip rate is (100%+75%+0%) / 3=58.3%. Find out the statistical characteristics of the flip rate, such as the mean and standard deviation, and set the threshold value based on these characteristics. And according to the analysis results, set the threshold value of the predetermined signal flip rate for subsequent power consumption evaluation waveform extraction.

[0069] According to some embodiments, when setting the threshold, multiple factors need to be considered, including but not limited to power consumption sensitivity, design goals, expected workload, etc. The rationality of the set thresholds is verified through multiple simulation experiments to ensure that they can accurately reflect the power consumption changes. The thresholds are adjusted according to the verification results until satisfactory accuracy is achieved.

[0070] According to some embodiments, the key state signal refers to a control signal or state indication signal for a specific functional purpose to determine the working scenario; the key data signal is used to input / output functional information and is the main source of flip power consumption. This type of signal is mainly used for power consumption calculation here.

[0071] In S105, the predetermined signal toggle rate threshold is stored as a configuration item in a corresponding test case for power consumption simulation.

[0072] According to some embodiments, the predetermined signal toggle rate threshold is recorded as a configuration item in the corresponding test case for power consumption simulation. During the simulation process, the toggle rate data of the predetermined signal is collected, the predetermined signal is monitored using a toggle rate detection component, and the toggle rate under different power consumption scenarios is recorded. The collected data is analyzed to determine the toggle rate threshold under various power consumption scenarios. A configuration file or a database table is created to record the toggle rate threshold under different power consumption scenarios. The configuration file should clearly indicate the identifier of each scenario, the predetermined signal, and the corresponding toggle rate threshold.

[0073] In S107, according to the predetermined signal toggle rate threshold, the power consumption evaluation waveform of the test case is automatically extracted in a subsequent simulation.

[0074] According to some embodiments, ensure that the power consumption detection component has been integrated into the simulation environment, configure the predetermined signal flip rate threshold, execute the test case, and run the simulation environment. During the simulation process, the power consumption detection component continuously monitors the state of the predetermined signal. When it is detected that the signal flip rate exceeds the preset predetermined signal flip rate threshold, it is identified as a valid flip. According to the recorded valid flip information, the power consumption evaluation waveform is automatically intercepted, and the moment of waveform interception is marked.

[0075] According to some embodiments, if the signal of the register transfer level code (RTL code) itself is monitored, the possible signal can be regarded as: Test_top.dut_top.module_a.module_b.sig_a. If the RTL code level changes, the component content needs to be modified synchronously. And when the environment is encapsulated in uvm_pkg, the hierarchical signal of RTL cannot be directly referenced. Through virtual interface control, the signal seen by the environment is interface_a.sig_a. As for the actual connection relationship with RTL, it can be modified in the outer layer, and the monitoring component itself does not need to be changed; even if pkg encapsulation is performed, the interface can be passed to the internal component of pkg in a variety of ways, including cfg_db and direct assignment.

[0076] Figure 2 A schematic diagram of a method for extracting a chip power consumption evaluation waveform according to an example embodiment is shown.

[0077] See also Figure 2 According to a schematic diagram of a method for extracting a chip power consumption evaluation waveform according to an example embodiment, as shown in the figure, in response to the iterative update of the design, the register transfer level code (RTL) after the iterative update directly uses the test case with the predetermined signal flip rate threshold recorded to simulate the power consumption scenario. When the code needs to be re-simulated after the iterative update, the test case with the power consumption flip threshold recorded is directly used, and the power detection component is used for simulation, so that the power consumption scenario can be automatically confirmed to be triggered according to the predetermined signal, and the waveform interception time point can be automatically obtained according to the interface flip rate.

[0078] According to some embodiments, generally speaking, in actual chip design, the RTL code may be modified later, and may be modified multiple times, so it may be necessary to re-capture the waveform to evaluate power consumption. At this time, the power detection component described in the present invention automatically extracts the power consumption waveform, which improves the test and development efficiency, saves the flow process of debugging by different departments, greatly saves the actual power consumption test evaluation time, and improves the design and development efficiency.

[0079] According to some embodiments, according to the predetermined signal flip rate threshold, the power consumption evaluation waveform of the test case is automatically extracted in the subsequent simulation, including: starting to monitor the predetermined signal flip rate after the effective flip judgment information is met; when the predetermined signal flip rate is greater than the predetermined signal flip rate threshold and maintains the first predetermined time, recording the corresponding time point as the starting point, and triggering waveform storage; delaying the second predetermined time and recording the end time, triggering the stop of waveform storage, so as to obtain the power consumption evaluation waveform. During the simulation process, the flip rate of the predetermined signal is monitored in real time. Specifically, when the effective flip judgment information is met, the flip situation of the predetermined signal is monitored. If the flip rate of the predetermined signal exceeds the preset flip rate threshold, and this state lasts for a predetermined period of time (the first predetermined time), the corresponding time point is recorded as the starting point, and the waveform storage is triggered. When the starting point is reached, the waveform data required for power consumption evaluation is recorded. After a predetermined delay (the second predetermined time), the end time is recorded, and the waveform storage is stopped.

[0080] Figure 3 A schematic diagram of an application of a method for extracting a chip power consumption evaluation waveform according to an example embodiment is shown.

[0081] See also Figure 3 According to an example embodiment, the method further includes: detecting the predetermined signal flip rate in different power consumption scenarios by performing use case regression on different power consumption scenarios, and determining whether the predetermined signal flip rate meets expectations. The flip rate of the power consumption scenario can be detected by writing assertions or other methods, and performing use case regression to confirm whether the assertion meets expectations. For example, if a certain threshold in a certain scenario is considered to be the maximum power consumption scenario, this can be used as an assertion for detection.

[0082] According to some embodiments, if the detected predetermined signal toggle rate is greater than the predetermined signal toggle rate threshold, a waveform review is triggered to check whether the power consumption scenario meets expectations. If other use cases appear or the effective toggle rate of the interface at a time point is greater than the original scenario, a waveform review is triggered to confirm the validity of the scenario and the correctness of the analyzed maximum power consumption scenario. If an unexpected result occurs, it is necessary to check the waveform and configuration first to confirm whether it is a valid scenario. For example, if some configurations cause abnormal chip functions, the power consumption and toggle rate at this time should not be considered as normal power consumption evaluation scenarios.

[0083] According to some embodiments, the effective flip judgment information includes: a combination of chip data signals and function signals; and / or a combination of chip configuration register values; and / or a chip control signal sequence. In order to organize the effective flip judgment information of the interface, we need to collect the encoding state of the control signal input by the interface and the combination result of the configuration information, and use it as the effective flip judgment information. And record the effective flip conditions and use them as the basis for the subsequent flip rate detection component.

[0084] According to some embodiments, the power consumption detection component is configured to: set the trigger condition of the effective scene according to the effective flip judgment information; when the trigger condition of the effective scene is met, count the effective flip rate of the predetermined signal on the module interface. According to the defined effective flip condition, write the logic of the power consumption detection component. The functions of the power consumption detection component include: monitoring the state of the predetermined signal and judging whether the effective flip condition is met; when the trigger condition is met, count the flip rate of the predetermined signal on the interface.

[0085] According to some embodiments, the power consumption detection component is integrated into the top level of the simulation environment through a virtual interface, and a macro path is used to indicate an absolute path at the module level. The power consumption detection component is integrated into the top level of the simulation environment through a function. The power consumption detection component can be implemented in the form of a virtual interface or function, for example, using an interface or function in Verilog to encapsulate the flip rate detection logic.

[0086] Use macro definitions to specify the absolute path of the module hierarchy, and use virtual interfaces to connect multiple components so that when the bottom module is referenced in the top module, the module location can be found correctly. This ensures that the reference consistency is maintained even when the project structure changes.

[0087] According to some embodiments, the simulation environment is run to simulate power consumption scenarios and obtain the effective flip rate threshold of the power consumption time period, including: running the simulation environment to simulate power consumption scenarios, finding waveform time points for power consumption evaluation, and recording the predetermined signal flip rate threshold at the time points. The power consumption detection component is enabled in the simulation environment, and the test case for the specific power consumption scenario is run. The designer examines the generated waveform to find the appropriate waveform time point for power consumption evaluation. The predetermined signal flip rate threshold at these time points is recorded, and it is recorded as a configuration item in the corresponding power consumption simulation case.

[0088] Take the actual application evaluation case as an example: for a tensor operation module, matrix multiplication and scalar multiplication can be realized. Among them, the power consumption of matrix multiplication is much greater than that of scalar multiplication. Therefore, matrix multiplication is judged to be the maximum power consumption scenario from the functional point of view. The designer confirmed according to the design code that when the register configuration matrix_en=1, the module will run matrix multiplication, and the two data input by the interface have two vld signals respectively, and the data is sampled only when vld is valid. Multiplication can be performed only when both data are valid. The internal multiplication of the tensor operation module is composed of a multi-stage adder, as well as various selection components and timing components, which is relatively complex. In addition to the designer himself, it is difficult for others to determine when it should be intercepted as a power-consuming waveform. According to the effective flip judgment information obtained by the above analysis of the design, the judgment condition of the effective scenario is set as: matrix_en==1, vld0==1, vld1==1. And construct the virtual interface signal: valid_sig_flip = the working clock of the block. matrix_en&vld0&vld1&clk. Among them, clk is the working clock of the module. Afterwards, the verification personnel integrate the virtual interface into the top level of the verification environment, and use the macro path to indicate the absolute path of the module level to achieve fast matching with RTL.

[0089] According to the scenario analysis, continuous data input is the maximum power consumption scenario. Verify the continuous excitation input data, and perform simulation with vld being 1 for each beat. Set valid_sig_flip==1 as the trigger condition. For 200 consecutive clock cycles, valid_sig_flip is 1, and start to judge the interface data signal flip rate. Assuming that empirical data shows that the average data flip rate is 50%, when the average data flip rate is greater than 45% for 200 consecutive cycles, start recording the power consumption waveform. The recording time is 2 microseconds. If the average data flip rate is less than 40% for 200 consecutive cycles, or valid_sig_flip is 0, stop recording the waveform and wait for the trigger again.

[0090] After the simulation is completed, the designer confirms whether the power consumption waveform meets expectations. If it does, the power consumption use case and judgment component are archived and can be used directly to complete the extraction of the power consumption waveform. For different simulations, the configuration and code may be different, and the time period of the waveform capture may be different, but the effective time period can be automatically selected without manual repeated extraction.

[0091] If code changes or modifications occur during the subsequent design process, for example, the internal adder is changed into a multiplier. If the adder signal was originally used as the power consumption judgment condition, the condition no longer exists at this time, and the predetermined signal flip rate threshold needs to be re-extracted. Since the module interface is relatively fixed, the original power consumption component can still be used. If the condition is extracted from the RTL code, after being converted to a netlist, the internal signal name and structure of the module will be completely different, but the interface signal will not change, so the component is still available.

[0092] In the above example of the tensor operation module, due to the limitation of the module's computing power, it is impossible to process continuously input data. There is an input data fifo with a depth of 24 that can cache data, and then each average data requires 2 beats for multiplication operation, so the maximum interface flip rate is 50%. Since not every data is processed in 2 beats, coupled with the cache function of the fifo, the data flow has certain fluctuations and cannot be accurately controlled. Therefore, adjust the power consumption detection component, and similarly set valid_sig_flip==1 as the trigger condition. For 200 consecutive clock cycles, the average flip rate of valid_sig_flip is greater than 40%, and the data flip rate is judged, and the power consumption waveform is recorded. The recording time is 2 microseconds. After the simulation is completed, the design colleague confirms whether the waveform segment is correct. Use the corresponding waveform to evaluate the power consumption, and make corrections to the evaluation results to obtain more accurate power consumption evaluation results.

[0093] The power consumption detection component and the 40% flip rate threshold were used as conditions for use case regression. It was found that when the matrix was multiplied by the vector, due to the small amount of data, the module only needed 1 beat to complete the calculation, and the flip rate was higher than the matrix multiplication by the matrix. The maximum power consumption waveform was extracted for the scenario of matrix multiplication by vector, and the final power consumption was greater than the matrix multiplication by matrix. Therefore, for the current module, the maximum power consumption scenario should be matrix multiplication by vector, and the power consumption evaluation results need to be updated. As in the above example, it was originally believed that matrix*matrix was the maximum power consumption scenario, but after actual testing, it was found that in some cases vector*matrix would be a scenario with higher power consumption. At this point, the maximum flip rate after simulation of each use case can be recorded. After the regression is completed, the name of the verification use case with the largest flip rate can be extracted through the script. If it is not the expected use case, an error will be reported.

[0094] According to some embodiments, the design scheme of the present invention can be applied to the design of computer program products, so that when the computer program is executed by a processor, the method described in any of the above items is implemented, so that during the design process of a chip or other hardware circuit, power consumption waveforms can be automatically acquired, efficient power evaluation and feedback can be achieved, and the design process can be accelerated.

[0095] According to some embodiments, the design scheme of the present invention designs a power consumption detection tool through effective flip detection of the module interface, and adds it to the verification simulation environment, so as to automatically monitor the flip ratio of the module in the simulation device. The designer manually checks and confirms the corresponding power consumption scenario waveform segment to confirm the effective flip rate of the module in the power consumption scenario. By setting the effective flip rate as a threshold to the power consumption detection tool, the waveform time point of the power consumption scenario can be automatically marked in the subsequent simulation, and the automatic waveform period selection can be completed.

[0096] According to some embodiments, the design scheme of the present invention achieves equivalent power consumption statistics for all verification and regression scenarios by adding the power consumption detection component tool when verifying and regressing different scenarios. It can compare special power consumption scenarios such as maximum and minimum, and compare them with the power consumption scenarios given by the designer to confirm whether they are the corresponding special power consumption scenarios.

[0097] According to some embodiments, the design scheme of the present invention reduces the coupling of the module RTL code by effectively flipping the module interface instead of detecting the internal functional signals of the module. Because the number of external interface signals of the module is less than that of internal signals, and the changes are relatively less, this increases the versatility and stability of the component and reduces the difficulty of implementation.

[0098] According to some embodiments, the design of the present invention confirms whether the interface is effectively flipped by comparing the overall signal flip rate of the monitored interface flip and the actual power consumption analysis, and can optimize the power consumption design of the coordination of the front and rear multi-level modules.

[0099] Figure 4 A block diagram of a computing device according to an example embodiment of the invention is shown.

[0100] like Figure 4 As shown, computing device 30 includes processor 12 and memory 14. Computing device 30 may also include bus 22, network interface 16, and I / O interface 18. Processor 12, memory 14, network interface 16, and I / O interface 18 may communicate with each other via bus 22.

[0101] The processor 12 may include one or more general-purpose CPUs (Central Processing Units, processors), microprocessors, or application-specific integrated circuits, etc., for executing relevant program instructions. According to some embodiments, the computing device 30 may also include a high-performance graphics card (GPU) 20 for accelerating the processor 12.

[0102] The memory 14 may include a machine system readable medium in the form of a volatile memory, such as a random access memory (RAM), a read-only memory (ROM) and / or a cache memory. The memory 14 is used to store one or more programs including instructions and data. The processor 12 may read the instructions stored in the memory 14 to execute the above-mentioned method according to the embodiment of the present invention.

[0103] The computing device 30 may also communicate with one or more networks via the network interface 16. The network interface 16 may be a wireless network interface.

[0104] The bus 22 may include an address bus, a data bus, a control bus, etc. The bus 22 provides a path for exchanging information between components.

[0105] It should be noted that, in the specific implementation process, the computing device 30 may also include other components necessary for normal operation. In addition, those skilled in the art may understand that the above device may only include components necessary for implementing the embodiments of this specification, and need not include all components shown in the figure.

[0106] The present invention also provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of the above method when the program is executed by a processor. The computer-readable storage medium may include, but is not limited to, any type of disk, including a floppy disk, an optical disk, a DVD, a CD-ROM, a micro drive, and a magneto-optical disk, a ROM, a RAM, an EPROM, an EEPROM, a DRAM, a VRAM, a flash memory device, a magnetic card or an optical card, a nanosystem (including a molecular memory IC), a network storage device, a cloud storage device, or any type of medium or device suitable for storing instructions and / or data.

[0107] An embodiment of the present invention also provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to execute part or all of the steps of any method recorded in the above method embodiments.

[0108] Those skilled in the art can clearly understand that the technical solution of the present invention can be implemented with the help of software and / or hardware. "Unit" and "module" in this specification refer to software and / or hardware that can independently complete or cooperate with other components to complete specific functions, where the hardware can be, for example, a field programmable gate array, an integrated circuit, etc.

[0109] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should know that the present invention is not limited by the described action sequence, because according to the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

[0110] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0111] In the several embodiments provided by the present invention, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some service interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0112] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0113] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0114] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a memory and includes several instructions for a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of the methods of various embodiments of the present invention.

[0115] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0116] The exemplary embodiments of the present invention are specifically shown and described above. It should be understood that the present invention is not limited to the detailed structures, configurations or implementations described herein; on the contrary, the present invention is intended to cover various modifications and equivalent configurations included in the spirit and scope of the appended clauses.

Claims

1. A method for extracting chip power consumption evaluation waveform, characterized in that: The method comprises: Loading an integrated power consumption detection component in a simulation environment, wherein the power consumption detection component is implemented based on effective flip judgment information of a module interface of the chip, and the power consumption detection component detects effective flip of a predetermined signal on the module interface to replace detection of a functional signal inside the module; Run the simulation environment to perform power consumption scenario simulation, and obtain the predetermined signal flip rate threshold of the module interface at the power consumption evaluation waveform time point through the power consumption detection component: export the data collected during the simulation process, calculate the signal flip rate in each time period based on the collected data, and set the predetermined signal flip rate threshold according to the signal flip rate in each time period; Storing the predetermined signal toggle rate threshold as a configuration item in a corresponding test case for power consumption simulation; According to the predetermined signal toggle rate threshold, the power consumption evaluation waveform of the test case is automatically extracted in subsequent simulation.

2. The method according to claim 1, characterized in that Also includes: In response to iterative updates of the design, the power consumption scenario simulation is performed directly on the iteratively updated register transfer level code using a test case recorded with the predetermined signal toggle rate threshold.

3. The method according to claim 1, characterized in that According to the predetermined signal flip rate threshold, the power consumption evaluation waveform of the test case is automatically extracted in the subsequent simulation, including: When the effective flip judgment information is met, start monitoring the predetermined signal flip rate; When the predetermined signal flip rate is greater than the predetermined signal flip rate threshold and is maintained for a first predetermined time, recording the corresponding time point as a starting point and triggering waveform storage; The second predetermined time is delayed and the end time is recorded, triggering the stopping of waveform storage, thereby obtaining the power consumption evaluation waveform.

4. The method according to claim 1, characterized in that: The method further comprises: By performing use case regression on different power consumption scenarios, detecting the predetermined signal flip rate under different power consumption scenarios, and determining whether the predetermined signal flip rate meets expectations; If the detected predetermined signal toggle rate is greater than the predetermined signal toggle rate threshold, a waveform inspection is triggered to check whether the power consumption scenario meets expectations.

5. The method according to claim 1, characterized in that: The effective flip judgment information includes: A combination of chip data signals and function signals; and / or A combination of chip configuration register values; and / or Chip control signal sequence.

6. The method according to claim 1, characterized in that The power consumption detection component is configured as follows: Setting a trigger condition for a valid scene according to the valid flip judgment information; When a trigger condition that satisfies the effective scenario occurs, the effective flip rate of the predetermined signal on the module interface is counted.

7. The method according to claim 1, characterized in that The power consumption detection component is integrated into the top layer of the simulation environment through a virtual interface, and a macro path is used to indicate an absolute path at the module level.

8. The method according to claim 1, characterized in that: The power consumption detection component is integrated into the top layer of the simulation environment through a function.

9. A computer program product, characterized in that include: A computer program, wherein when the computer program is executed by a processor, the method according to any one of claims 1 to 8 is implemented.

10. A computing device, characterized in that include: processor; as well as A memory storing a computer program, which, when executed by the processor, enables the processor to perform the method according to any one of claims 1 to 8.

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