A digital isolator with improved common-mode transient immunity

Abstract

The present application discloses a digital isolator with improved common-mode transient immunity, which relates to the field of integrated circuit isolation technology, and includes a pair of transceiver chips, wherein each transceiver chip has the same structure, and the transceiver chip includes a transmitting module and a receiving module; a digital control module is used to control one of the pair of transceiver chips to be in a transmitting mode, while the other is in a receiving mode. Connecting two identical transceiver modules together can realize multi-channel signal transmission in any direction. In addition, an envelope detection module, a CMTI enhancement module, and a noise elimination module are also disclosed, which are used to improve the common-mode transient immunity of the digital isolator and solve the problem that the transmission signal is easily affected by noise due to large attenuation.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit isolation, and more specifically, to a digital isolator with improved common-mode transient immunity. Background Art

[0002] When two circuits in different voltage domains transmit signals, there may be crosstalk of DC common mode level or interference of abnormal AC level between the systems, resulting in data damage or damage to peripheral circuits. Digital isolators can isolate noise and interference when two circuits communicate with each other, thereby ensuring normal signal interaction. It can provide electrical isolation of up to several thousand volts between two circuits, thereby improving the reliability of the chip. The main indicators of digital isolators are common mode transient immunity (CMTI), which is used to measure the ability of the isolator to withstand rapid changes in ground potential, that is, the ability of the signal not to be disturbed and produce bit errors when the common mode voltage changes rapidly. When a high-voltage pulse shock occurs, the maximum signal slope that can be tolerated is CMTI, which is expressed in kV / us or V / ns. The input common mode range of traditional digital isolators is limited, and can only support common mode transient interference of 50 to 100 kV / us. When a large common mode transient interference occurs, the digital isolator will still face the risk of communication failure. In addition, the transmitting circuit TX and the receiving circuit RX of the traditional digital isolator cannot be multiplexed, especially in the case of multiple channels and different transmission directions. Each product needs to be redesigned, which increases the design and manufacturing costs.

[0003] For example, a Chinese patent application with publication number CN114448415A discloses a digital isolator, including a pair of transceiver circuits and a control circuit, each transceiver circuit includes a transmitting circuit, a receiving circuit and a DC isolation circuit, the DC isolation circuits are connected, and each receiving circuit includes a pair of feedback voltage divider circuits and a differential comparison circuit; when the control circuit controls one transceiver circuit to operate in a transmitting mode and the other transceiver circuit to operate in a receiving mode, the transmitting circuit of the transceiver circuit operating in the transmitting mode receives a square wave signal to generate a corresponding pair of differential square wave signals; after the connected DC isolation circuit receives the pair of differential square wave signals, a pair of differential coupling signals is generated; the transceiver circuit operating in the receiving mode outputs the square wave signal by using the pair of feedback voltage divider circuits and differential comparison circuits. The above technical solution cannot achieve transmission correctness under large transient common mode interference.

[0004] For example, the Chinese patent with the authorization announcement number CN115549670B discloses a digital isolator, including: a signal transmitting circuit, a signal receiving circuit and an isolation circuit coupled between the signal transmitting circuit and the signal receiving circuit, wherein the isolation circuit includes: a first isolation module, which is configured to convert the received input modulated signal into a differential signal; a second isolation module, which is configured to provide an output modulated signal in response to receiving the differential signal, wherein the first isolation module and the second isolation module adopt a mutually symmetrical structure, and the fully differential structure and the fully symmetrical structure improve the anti-interference ability of the circuit, and can support common-mode transient interference greater than 200kV / us. The above technical solution cannot realize the multiplexing of TX and RX in multiple channels and different transmission directions. Summary of the invention

[0005] In view of the above, the present application provides a digital isolator with improved common-mode transient immunity, which includes a pair of identical transceiver modules, each of which operates in one of a transmitting mode or a receiving mode. Connecting two identical transceiver modules together can realize multi-channel signal transmission in any direction. An envelope detection circuit, a CMTI enhancement circuit and a noise elimination circuit are proposed to improve the common-mode transient immunity of the isolator and solve the problem that the transmission signal is easily affected by noise due to large attenuation.

[0006] The present application proposes a digital isolator with improved common-mode transient immunity, comprising:

[0007] A pair of transceiver chips, wherein each of the transceiver chips has the same structure and comprises a transmitting module and a receiving module;

[0008] A digital control module, used to control one of the pair of transceiver chips to be in a transmission mode and the other to be in a reception mode;

[0009] A differential driving module, located in the first voltage domain, for converting the digital signal input to the transceiver chip into a fully differential signal, and transmitting the signal to the sending module in the same voltage domain;

[0010] The sending module is used to perform OOK modulation on the fully differential signal using the clock signal generated by the oscillator to generate a high-frequency fully differential signal; and transmit the high-frequency fully differential signal to the receiving module located in the second voltage domain through the isolation capacitor module;

[0011] The isolation capacitor module comprises: a pair of isolation circuits, wherein each of the isolation circuits has the same structure, and the pair of isolation circuits are used to process two complementary differential signals of the high-frequency fully differential signal;

[0012] The receiving module is used to receive the high-frequency fully differential signal and demodulate and restore it to a digital signal input to the transceiver chip;

[0013] As an optional implementation, the receiving module includes: a CMTI enhancement module;

[0014] The digital control module is further used to: detect the high-frequency fully differential signal output by the isolation capacitor module, and in response to detecting that the common-mode transient voltage in the high-frequency fully differential signal is greater than the target transient voltage, enable and control the CMTI enhancement module to compensate the high-frequency fully differential signal;

[0015] As an optional implementation, the CMTI enhancement module includes: first to fourth resistors, first to fifth capacitors, first to seventh NMOS transistors, and first to fifth PMOS transistors;

[0016] The first end and the third end of the first NMOS tube are connected to one end of the first resistor and the second end of the second PMOS tube, and the other end of the first resistor is connected to the first power supply and the first end of the third NMOS tube; the second end of the first PMOS tube is connected to the second end of the first NMOS tube, the third end of the fourth NMOS tube, the third end of the fourth PMOS tube, the third end of the seventh NMOS tube, and the third end of the fifth PMOS tube; the third end and the first end of the first PMOS tube are connected to one end of the second resistor and the second end of the second NMOS tube; the other end of the second resistor is grounded and connected to the second ends of the first to fifth capacitors and the first ends of the third to fifth PMOS tubes;

[0017] The third end of the second PMOS tube is used to input the first enable signal ENB1; the first end of the second PMOS tube is connected to the first end of the first capacitor, the first end of the third capacitor, and the third end of the third NMOS tube; the third end of the second NMOS tube is used to input the second enable signal EN2, and the first end of the second NMOS tube is connected to the first end of the second capacitor and the third end of the third PMOS tube;

[0018] The second end of the third NMOS tube is connected to the second end of the third PMOS tube, the first end of the fourth capacitor, the first end of the fifth capacitor, one end of the third resistor, and one end of the fourth resistor;

[0019] The other end of the third resistor is connected to the second end of the fourth NMOS transistor and the second end of the fourth PMOS transistor, and is output as a first port; the other end of the fourth resistor is connected to the second end of the seventh NMOS transistor and the second end of the fifth PMOS transistor, and is output as a second port;

[0020] The third ends of the fifth NMOS tube and the sixth NMOS tube are used to input a third enable signal EN3; the first end of the fifth NMOS tube is connected to the second power supply and is connected to the first end of the sixth NMOS tube; the second end of the fifth NMOS tube is connected to the first end of the fourth NMOS tube;

[0021] The second end of the sixth NMOS tube is connected to the first end of the seventh NMOS tube;

[0022] In response to detecting that the common mode transient voltage in the high frequency fully differential signal is greater than the target transient voltage, enabling and controlling the CMTI enhancement module to compensate the high frequency fully differential signal includes:

[0023] The CMTI enhancement module is turned on through the first to third enable signals, so that the CMTI enhancement module compensates for the high-frequency fully differential signal.

[0024] As an optional implementation, the isolation circuit includes a clamping structure and an isolation capacitor;

[0025] The clamping structure includes: a pair of Zener diodes with opposite polarities and a first-order RC high-pass filter;

[0026] The positive and negative electrodes of the pair of Zener diodes with opposite polarities are connected to each other in reverse, wherein the positive electrode of one Zener diode is connected to the high-frequency fully differential signal transmission line and the negative electrode is grounded, and the negative electrode of the other Zener diode is connected to the high-frequency fully differential signal transmission line and the positive electrode is grounded;

[0027] The capacitor in the first-order RC high-pass filter is connected in series to the high-frequency fully differential signal transmission line, and the first end of the capacitor is connected to the sending module; the second end of the capacitor is connected to the positive electrode of the one Zener diode, the negative electrode of the other Zener diode, and one end of the resistor, and is used to output one of the two complementary differential signals;

[0028] The other end of the resistor in the first-order RC high-pass filter is grounded and connected to the cathode of the one Zener diode and the anode of another Zener diode.

[0029] As an optional implementation, the receiving module is further used to amplify the high-frequency fully differential signal after attenuation by the isolation capacitor module, and demodulate and restore it to a digital signal input to the transceiver chip.

[0030] As an optional implementation, the receiving module includes: a pre-amplifier module;

[0031] The pre-amplifier module includes: seventh to tenth resistors, eighth to eleventh capacitors, sixth to ninth PMOS transistors, and eighth to fifteenth NMOS transistors;

[0032] Wherein, the second end of the eighth capacitor is connected to the power supply, and is connected to the second end of the sixth PMOS tube, the second end of the seventh PMOS tube, and the second end of the ninth capacitor; the first end of the eighth capacitor is connected to the third end of the sixth PMOS tube and one end of the seventh resistor; the other end of the seventh resistor is connected to the first end of the sixth PMOS tube, the first end of the eighth NMOS tube, and the third end of the thirteenth NMOS tube;

[0033] The third end of the eighth NMOS tube is connected to the clamp structure and the CMTI enhancement module, and is connected to the second end of the sixth capacitor in the clamp structure; the second end of the eighth NMOS tube is connected to the second end of the ninth NMOS tube, the first end of the tenth NMOS tube, and the first end of the fourteenth NMOS tube; the third end of the fourteenth NMOS tube is connected to the first gain control signal; the second end of the tenth NMOS tube is grounded, and is connected to the second end of the fourteenth NMOS tube, the second end of the eleventh NMOS tube, and the second end of the fifteenth NMOS tube; the third end of the tenth NMOS tube is connected to the first bias voltage;

[0034] The first end of the seventh PMOS tube is connected to the first end of the ninth NMOS tube, one end of the eighth resistor, and the third end of the twelfth NMOS tube; the third end of the seventh PMOS tube is connected to the first end of the ninth capacitor and the other end of the eighth resistor; the third end of the ninth NMOS tube is connected to the clamp structure and the CMTI enhancement module, and is connected to the second end of the seventh capacitor in the clamp structure;

[0035] The second end of the tenth capacitor is connected to the power supply, and is connected to the second end of the eighth PMOS tube, the second end of the ninth PMOS tube, and the second end of the eleventh capacitor; the first end of the tenth capacitor is connected to one end of the ninth resistor and the third end of the eighth PMOS tube; the other end of the ninth resistor is connected to the first end of the eighth PMOS tube and the first end of the twelfth NMOS tube, and outputs a signal VN;

[0036] The second end of the twelfth NMOS tube is connected to the second end of the thirteenth NMOS tube, the first end of the eleventh NMOS tube, and the first end of the fifteenth NMOS tube; the third end of the eleventh NMOS tube is connected to the second bias voltage;

[0037] The first end of the ninth PMOS tube is connected to the first end of the thirteenth NMOS tube and one end of the tenth resistor and outputs a signal VP;

[0038] The first end of the eleventh capacitor is connected to the third end of the ninth PMOS and the other end of the tenth resistor; the third end of the fifteenth NMOS is connected to the first gain control signal;

[0039] The first gain control signal is provided by the digital control module and is used to control the gain of the amplifier in the pre-amplifier module.

[0040] As an optional implementation, the receiving module includes: an envelope detection module;

[0041] The envelope detection module is used to detect the amplitude of the signal and convert the high-frequency fully differential signal into a low-frequency fully differential signal by comparing the threshold voltage;

[0042] The envelope detection module comprises: a dual-end input and dual-end output inductive load operational amplifier and two current sources, which are used to synchronize the offset of the threshold voltage and the high-frequency fully differential signal when the temperature changes, and perform temperature compensation.

[0043] As an optional implementation, the receiving module includes: a decoding module;

[0044] The decoding module is connected to the envelope detection module and is used to convert the low-frequency fully differential signal into a digital signal through a Schmitt trigger;

[0045] The decoding module includes: a low-pass filter, which is used to receive the low-frequency full differential signal from the envelope detection module and filter out high-frequency noise in the low-frequency full differential signal;

[0046] Two cascaded resistor-loaded operational amplifiers, coupled to the low-pass filter, for converting the low-frequency fully differential signal into a single-ended output signal;

[0047] a comparator coupled to the output of the resistive load operational amplifier, wherein a first input terminal receives the single-ended output signal, a second input terminal receives a threshold voltage signal, and the comparator generates an output signal according to a comparison result between the single-ended output signal and the threshold voltage signal;

[0048] A Schmitt trigger is coupled to the output end of the comparator and is used to restore the output signal to a digital signal.

[0049] As an optional implementation, the receiving module includes: a noise elimination module;

[0050] The noise elimination module receives the digital signal output by the decoding module, and in response to detecting that the common mode transient pulse in the digital signal is greater than the first target threshold, performs signal latching through a latch enable signal;

[0051] The noise elimination module includes: a NOT gate, four buffers, two OR gates and an SR latch;

[0052] The digital signal output by the decoding module and the signal obtained by inverting the digital signal through an inverter are respectively logically ORed with the latch enable signal to serve as the two outputs of the SR latch; in response to detecting that the common mode transient pulse in the digital signal is greater than the first target threshold, the latch enable signal is set to 1, and the SR latch latches the signal.

[0053] Compared with the prior art, the beneficial effects of the present application are as follows: the traditional digital isolator demodulation method is to compare the demodulated signal with the threshold before output, but the drift of the signal and the threshold caused by the process and temperature may cause bit errors. The present application proposes a new envelope detection circuit to ensure that the drift direction of the signal and the threshold with temperature is the same.

[0054] The CMTI of traditional digital isolators is low and their tolerance to transient common-mode levels is weak. This application improves the CMTI of the circuit through the clamping structure in the isolation capacitor module, the envelope detection module in the receiving decoding module, and the CMTI enhancement module. When a high dV / dt transient voltage arrives, the CMTI enhancement module can discharge the transient voltage through the capacitor, prevent a large voltage drop on the resistor, and prevent the bias voltage from being affected by the transient signal, thereby enhancing the circuit's ability to withstand transient interference. At the same time, the bias circuit is in an off state when there is no common-mode transient signal, does not consume power, and does not interfere with other parts of the circuit. This design ensures the stability and reliability of signal transmission and significantly improves the product's anti-interference performance.

[0055] In addition, the digital control module detects transient fluctuations in the differential input signal and outputs an enable signal to control the activation of the CMTI enhancement module. This active control method enables the CMTI enhancement module to respond quickly when needed, improving the circuit's ability to resist transient interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 This is the functional block diagram of the digital isolator;

[0057] Figure 2 It is a structural schematic diagram of the isolation capacitor;

[0058] Figure 3 It is a structural diagram of the modulation and transmission module;

[0059] Figure 4 It is a structural diagram of a receiving and decoding module;

[0060] Figure 5 This is a schematic diagram of the principle of the CMTI enhancement module;

[0061] Figure 6 It is the principle schematic diagram of the pre-amplifier module;

[0062] Figure 7 This is a schematic diagram of the principle of envelope detection;

[0063] Figure 8 This is a schematic diagram of the principle of the decoding module;

[0064] Fig. 9 This is a schematic diagram of the principle of the noise elimination module;

[0065] Fig.10 The schematic diagram of the circuit for each key node;

[0066] Fig.11 Schematic diagram of the waveform of each key node. DETAILED DESCRIPTION

[0067] The technical solution of the present application will be described clearly and completely below in conjunction with the drawings of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present application.

[0068] For example, certain words are used in the specification and claims to refer to specific components. Those skilled in the art should understand that hardware manufacturers may use different terms to refer to the same component. This specification and claims do not use differences in names as a way to distinguish components, but use differences in the functions of components as the criteria for distinction. For example, "including" mentioned throughout the specification and claims is an open term, so it should be interpreted as "including but not limited to". In addition, the word "connection" here includes any direct and indirect connection means. Therefore, if the text describes that a first device is connected to a second device, it means that the first device can be directly connected to the second device, or indirectly connected to the second device through other devices or connection means. The subsequent description of the specification is a preferred embodiment of the present application, but the description is for the purpose of illustrating the general principles of the present application and is not used to limit the scope of the present application. The scope of protection of the present application shall be determined by the attached claims.

[0069] In addition, words such as "first", "second", and "third" used in this application are used to modify elements in the claims, and are not used to indicate a priority order, a prior relationship, or that one element precedes another element, or a time sequence when performing method steps. They are only used to distinguish elements with the same name.

[0070] See also Figure 1 , Figure 1 1 is a functional block diagram of the digital isolator 100 of the present application. The digital isolator 100 of the present application includes two identical chips: chip 110a and chip 110b. Each chip is provided with a transmitting module (Transmitter, TX) and a receiving module (Receiver, RX) for realizing bidirectional transmission of signals.

[0071] The sending module 111a and the sending module 112b respectively located on the chip 110a and the chip 110b are used to send signals; the receiving module 112a and the receiving module 111b respectively located on the chip 110a and the chip 110b are used to receive signals; the isolation and transmission of signals between the chip 110a and the chip 110b are realized through a plurality of isolation capacitors 130. The isolation capacitor module 120 is connected between the sending module and the receiving module to ensure that the signal is effectively isolated during the transmission process.

[0072] In a specific implementation, the digital driving signal generated by the digital control module can be used to drive one of the transmitting and receiving modules on each chip to work, while the other module on another chip works. Different digital driving signals can realize signal transmission in different directions.

[0073] Exemplarily, when a signal needs to be transmitted from chip 110a to chip 110b, the sending module 111a of chip 110a starts to send data based on the digital driving signal generated by the digital control module for driving the sending module 111a. The data is transmitted to the receiving module 111b of chip 110b through the isolation capacitor module 120 to complete the signal transmission.

[0074] Exemplarily, when a signal needs to be transmitted from chip 110b to chip 110a, the transmitting module 112b of chip 110b starts transmitting data based on the digital driving signal generated by the digital control module. The data is transmitted to the receiving module 112a of chip 110a through the isolation capacitor module 120. The receiving module 112a of chip 110a demodulates the received data and transmits it to other modules inside or outside the chip 110a.

[0075] In the embodiment of the present disclosure, the differential driving module is located in the first voltage domain, and is used to convert the digital signal input to the transceiver chip into a fully differential signal, and transmit it to the sending module in the same voltage domain.

[0076] The differential drive module is connected to the transmitting module 111a in the chip 110a. It should be noted that, as described above, there are two identical chips in the present application, which means that there is also a differential drive module connected to the transmitting module 112b in the chip 110b. The implementation method and principle of a single chip will be specifically described below. It can be understood that since the digital isolator 100 includes two identical chips, the description of the principle, structure, and function of a certain chip is also applicable to the other.

[0077] In the embodiment of the present disclosure, the sending module 111a is connected to the isolation capacitor module 120, and the isolation capacitor module 120 is connected to the receiving module 111b. The signal input to the digital isolator 100 is converted into a full differential signal through the differential drive module and transmitted to the sending module 111a. The sending module 111a modulates the full differential signal to a high frequency, transmits it to the isolation capacitor module 120, and transmits it to the receiving module 111b through the isolation capacitor module 120. The receiving module 111b is used to receive, demodulate and transmit differential mode signals, suppress common mode signals, amplify differential mode signals, and restore signals through a decoding circuit.

[0078] It can be understood that the role of the differential driving module here is to realize the conversion of the signal input to the digital isolator 100. Therefore, setting the same differential driving module for the two chips included in the digital isolator 100 of the present application is not the only implementation method. In some cases, a unique differential driving module can also be set for converting the input signal and transmitting the converted full differential signal to the sending module of any one of the two chips.

[0079] By adopting a fully differential circuit, better common-mode interference resistance can be achieved, and the common-mode noise of the signal received by the receiving end can be almost completely offset, with a better CMTI effect, which is suitable for long-distance transmission.

[0080] In the embodiment of the present disclosure, the isolation capacitor module 120 includes: a pair of isolation circuits, wherein each isolation circuit has the same structure, and the pair of isolation circuits are used to process two complementary differential signals of the high-frequency fully differential signal.

[0081] like Figure 2 As shown, Figure 2 Schematic diagram of an isolation capacitor module, the isolation capacitor module 120 is composed of a clamping structure and an isolation capacitor 130. The clamping structure includes two identical circuits, one of which is connected to the end of the sending module and the other is connected to the front end of the receiving module, and the two circuits are separated by the isolation capacitor 130. The functions of the two clamping structures are completely consistent, and the specific implementation method will be described in detail below.

[0082] In the embodiment of the present disclosure, the sending module is used to perform OOK (On-Off Keying) modulation on the fully differential signal using the clock signal generated by the oscillator to generate a high-frequency fully differential signal; and transmit the high-frequency fully differential signal to the receiving module located in the second voltage domain through the isolation capacitor module 120;

[0083] Among them, OOK modulation (On-Off Keying) is a digital modulation method, which is a special form of amplitude shift keying (ASK). In OOK modulation, the presence or absence of a carrier is used to represent the 1 and 0 of binary data, so it is a binary amplitude shift keying (2ASK).

[0084] like Figure 3 shown. Figure 3 Schematic diagram of the structure of the sending module. In a specific implementation, the sending module 111a includes: an inverter, two AND gates, and two buffers. The input signal A first performs a logic operation with the clock signal CLK generated by the internal crystal oscillator of the chip. The clock signal passes through the inverter to generate a clock signal with an opposite phase, which is logically operated with the input signal A through the AND gate to generate two differential signals. The upper AND gate receives the input signal A and the inverted clock signal and outputs a differential signal; the lower AND gate receives the input signal A and the original clock signal and outputs another differential signal.

[0085] The two differential signals are processed by buffers respectively. The buffers are used to stabilize the signals and provide sufficient driving capability to ensure that the signals can be effectively transmitted to the subsequent circuits. The buffered signals are transmitted to the clamp structure through the input port VIP and the input port VIN respectively.

[0086] The clamping structure includes two Zener diodes with opposite polarities and a resistor to form an RC high-pass filter for clamping and filtering. The upper clamping structure processes the positive differential signal. The Zener diode included is turned on when the signal voltage exceeds the predetermined value to protect the circuit, and the high-pass filter formed by the resistor and capacitor filters out low-frequency noise. The lower clamping structure processes the negative differential signal and has the same function as the upper structure. The high-frequency stable signal after clamping and filtering is output from the VOP and VON ports respectively.

[0087] In this way, through differential signal transmission, the anti-interference ability is improved and the signal integrity is guaranteed.

[0088] Exemplarily, the isolation capacitor 130 may use silicon dioxide as a signal insulating dielectric, and silicon dioxide has a high dielectric strength compared to other dielectrics.

[0089] In this way, the two differential signals after the above processing are transmitted to the receiving module 111b through the isolation capacitor module 120, completing the signal modulation and transmission process. Through this design, the sending module can effectively modulate the input signal to a high frequency and perform reliable signal transmission through the isolation capacitor 130, ensuring the isolation of the system and the reliability of data transmission.

[0090] like Figure 4 As shown, Figure 4 The figure is a schematic diagram of the structure of the receiving module. The receiving module includes: a clamping structure module, a CMTI enhancement module, a pre-amplifier module, an envelope detection module, a decoding module and a noise elimination module, wherein the specific principle of the clamping structure has been described above. The CMTI enhancement module includes: resistors, capacitors and MOS tubes; the pre-amplifier module includes: two five-tube operational amplifiers; the envelope detection module includes: an operational amplifier and a comparator; the decoding module includes a buffer and a Schmitt trigger; the noise elimination module includes a buffer, an OR gate and an SR latch.

[0091] After the differential signal attenuated by the isolation capacitor 130 is input into the receiving module, it first passes through the clamping structure. As described above, the clamping structure module includes a first-order RC circuit and a voltage-stabilizing diode, which filters out low-frequency signals and possible transient interference levels for the two branches of the differential signal.

[0092] When a large dV / dt voltage arrives, the CMTI enhancement module can improve the circuit's ability to withstand transient voltages and improve CMTI by discharging the voltage through capacitors.

[0093] After passing through the clamping structure module, the signal enters the pre-amplifier module. The pre-amplifier circuit is set at the front end of the envelope detection module as a pre-processing before the envelope detection. It adopts multi-stage amplification and designs the load as inductive, so as to further provide good gain for the carrier signal. By adjusting the signal, the number of tail tubes turned on can be changed, thereby controlling the tail current of the amplifier and changing the gain of the amplifier module.

[0094] After pre-amplification, the signal reaches the envelope detection module. The envelope detection module extracts the amplitude envelope of the signal and outputs it as a low-frequency signal by detecting the amplitude of the signal and comparing it with the threshold voltage. This module uses inductive impedance to make the threshold voltage and signal shift in the same direction when the temperature and process change to reduce the bit error rate.

[0095] After that, the signal enters the decoding module and is decoded and restored to a digital signal. The low-pass filter passes the low-frequency signal and filters out the high-frequency noise. Then the differential signal of the double-ended input is outputted single-ended through two cascaded resistor load op amps. Compared with the current mirror, the resistor load can better stabilize the output common-mode level. The comparator uses one of the signals as the threshold voltage for judgment and the other as the compared signal. The output signal is restored to a digital signal by the Schmitt trigger.

[0096] Finally, the signal enters the noise elimination module, which can decide whether to latch the output to eliminate noise based on the noise enable signal detected by the external circuit.

[0097] See also Figure 5-Figure 9 , each sub-module in the receiving module will be explained in detail.

[0098] like Figure 5 , which is a schematic diagram of the principle of the CMTI enhancement module. The CMTI enhancement module includes: first to fourth resistors (R1 to R4), first to fifth capacitors (C1 to C5), first to seventh NMOS transistors (NM1 to NM7), and first to fifth PMOS transistors (PM1 to PM5);

[0099] The first end and the third end of the first NMOS tube are connected to one end of the first resistor and the second end of the second PMOS tube, and the other end of the first resistor is connected to the first power supply and the first end of the third NMOS tube; the second end of the first PMOS tube is connected to the second end of the first NMOS tube, the third end of the fourth NMOS tube, the third end of the fourth PMOS tube, the third end of the seventh NMOS tube, and the third end of the fifth PMOS tube; the third end and the first end of the first PMOS tube are connected to one end of the second resistor and the second end of the second NMOS tube; the other end of the second resistor is grounded and connected to the second ends of the first to fifth capacitors and the first ends of the third to fifth PMOS tubes;

[0100] The third end of the second PMOS tube is used to input the first enable signal ENB1; the first end of the second PMOS tube is connected to the first end of the first capacitor, the first end of the third capacitor, and the third end of the third NMOS tube; the third end of the second NMOS tube is used to input the second enable signal EN2, and the first end of the second NMOS tube is connected to the first end of the second capacitor and the third end of the third PMOS tube;

[0101] The second end of the third NMOS tube is connected to the second end of the third PMOS tube, the first end of the fourth capacitor, the first end of the fifth capacitor, one end of the third resistor, and one end of the fourth resistor;

[0102] The other end of the third resistor is connected to the second end of the fourth NMOS transistor and the second end of the fourth PMOS transistor, and is output as the first port vo; the other end of the fourth resistor is connected to the second end of the seventh NMOS transistor and the second end of the fifth PMOS transistor, and is output as the second port vo1;

[0103] The third ends of the fifth NMOS tube and the sixth NMOS tube are used to input a third enable signal EN3; the first end of the fifth NMOS tube is connected to the second power supply and is connected to the first end of the sixth NMOS tube; the second end of the fifth NMOS tube is connected to the first end of the fourth NMOS tube;

[0104] The second end of the sixth NMOS tube is connected to the first end of the seventh NMOS tube.

[0105] In the specific implementation, R1, NM1, PM1 and R2 in the CMTI enhancement module form a voltage divider circuit, which can generate a bias voltage and provide it to the subsequent circuit. PM2, NM2, NM5 and NM6 act as switches to control the conduction of the circuit. Capacitors C1, C2 and C3 act as ground loops. NM4 and PM4 and NM7 and PM5 form two bias circuits that are less affected by voltage and process.

[0106] The bias circuits (NM4, PM4, NM7, PM5) are off when there is no common-mode transient signal. Since these circuits have NMOS on the top and PMOS on the bottom, they will not turn on under normal conditions, so when there is no common-mode transient signal, the bias circuit will not consume power and will not interfere with other parts of the circuit.

[0107] When a large transient signal arrives, capacitors C4 and C5 will discharge current to ground, preventing a large voltage drop across resistors R3 and R4. This mechanism ensures that the bias voltage of the circuit is not affected by transient signals, thereby further improving CMTI.

[0108] In a specific implementation, the enable signals ENB1 , EN2 , and EN3 in the CMTI enhancement module may be provided by a digital control module.

[0109] For example, the digital control module includes: a low dropout regulator (LDO) module, which generates a 1.8V power supply through the LDO module. By comparing the output of the LDO module and the output of the bandgap reference generated by the 5V power supply, the transient fluctuations of the two power domains can be compared, and the values ​​of the enable signals ENB1, EN2, and EN3 are given to activate the CMTI module.

[0110] It is understandable that the present application only relates to the TX and RX channels and does not limit the specific LDO module.

[0111] In addition, the modules in the digital control module for detecting transient fluctuations in the differential input signal and outputting an enable signal to activate the CMTI enhancement module to provide compensation are not limited to the LDO module, for example, some overvoltage protection circuits, capacitance detection circuits, and adaptive power supply monitoring circuits.

[0112] As an optional implementation, the pre-amplifier module includes seventh to tenth resistors (R7 to R10), eighth to eleventh capacitors (C8 to C11), sixth to ninth PMOS transistors (PM6 to PM9), and eighth to fifteenth NMOS transistors (NM8 to NM15);

[0113] Wherein, the second end of the eighth capacitor is connected to the power supply, and is connected to the second end of the sixth PMOS tube, the second end of the seventh PMOS tube, and the second end of the ninth capacitor; the first end of the eighth capacitor is connected to the third end of the sixth PMOS tube and one end of the seventh resistor; the other end of the seventh resistor is connected to the first end of the sixth PMOS tube, the first end of the eighth NMOS tube, and the third end of the thirteenth NMOS tube;

[0114] The third end of the eighth NMOS tube is connected to the clamp structure and the CMTI enhancement module, and is connected to the second end of the sixth capacitor in the clamp structure; the second end of the eighth NMOS tube is connected to the second end of the ninth NMOS tube, the first end of the tenth NMOS tube, and the first end of the fourteenth NMOS tube; the third end of the fourteenth NMOS tube is connected to the control voltage; the second end of the tenth NMOS tube is grounded, and is connected to the second end of the fourteenth NMOS tube, the second end of the eleventh NMOS tube, and the second end of the fifteenth NMOS tube; the third end of the tenth NMOS tube is connected to the first bias voltage;

[0115] The first end of the seventh PMOS tube is connected to the first end of the ninth NMOS tube, one end of the eighth resistor, and the third end of the twelfth NMOS tube; the third end of the seventh PMOS tube is connected to the first end of the ninth capacitor and the other end of the eighth resistor; the third end of the ninth NMOS tube is connected to the clamp structure and the CMTI enhancement module, and is connected to the second end of the seventh capacitor in the clamp structure;

[0116] The second end of the tenth capacitor is connected to the power supply, and is connected to the second end of the eighth PMOS tube, the second end of the ninth PMOS tube, and the second end of the eleventh capacitor; the first end of the tenth capacitor is connected to one end of the ninth resistor and the third end of the eighth PMOS tube; the other end of the ninth resistor is connected to the first end of the eighth PMOS tube and the first end of the twelfth NMOS tube, and outputs a signal VN;

[0117] The second end of the twelfth NMOS tube is connected to the second end of the thirteenth NMOS tube, the first end of the eleventh NMOS tube, and the first end of the fifteenth NMOS tube; the third end of the eleventh NMOS tube is connected to the second bias voltage;

[0118] The first end of the ninth PMOS tube is connected to the first end of the thirteenth NMOS tube and one end of the tenth resistor and outputs a signal VP;

[0119] The first end of the eleventh capacitor is connected to the third end of the ninth PMOS and the other end of the tenth resistor; the third end of the fifteenth NMOS is connected to the control voltage;

[0120] In the specific implementation, Figure 6 As shown, Figure 6 The schematic diagram of the pre-amplifier module is shown in Figure 1. The pre-amplifier module receives the clamped high-frequency signal after attenuation by the isolation capacitor module 120. The pre-amplifier consists of two stages of operational amplifiers. The structures of the two stages are exactly the same. The first stage NM8, NM9, PM6, PM7 and NM10, NM14 form a five-tube operational amplifier. The gate terminal of NM14 is connected to the trim1 signal, which can control the number of NM14 tubes that are turned on, thereby changing the tail current to control the gain of the amplifier.

[0121] It is understandable that although Figure 7 NM14 is shown as an NMOS tube, but in fact, this position can be designed as a parallel connection of multiple NMOS tubes as needed, and the conduction of these NMOS tubes is controlled by the trim1 signal to adjust the total conduction current.

[0122] Vbias1 and vbias2 are used to provide bias voltage. C8, R7 and PM6 form an inductive load, which can effectively amplify high-frequency signals.

[0123] It can be understood that the inductive load here refers to the behavior that simulates the inductive characteristics, and after calculation, the total impedance of this part is inductive.

[0124] NM13, NM12, PM8, PM9 and NM11, NM15 as well as R9, R10, C10, C11 form the same second stage operational amplifier, which further improves the high frequency signal gain. The principle of the second stage is the same as that of the first stage, so it will not be described in detail.

[0125] As an optional implementation, the receiving module includes: an envelope detection module;

[0126] The envelope detection module is used to detect the amplitude of the signal and convert the high-frequency fully differential signal into a low-frequency fully differential signal by comparing the threshold voltage;

[0127] The envelope detection module comprises: a dual-end input and dual-end output inductive load operational amplifier and two current sources, which are used to synchronize the offset of the threshold voltage and the high-frequency fully differential signal when the temperature changes, and perform temperature compensation.

[0128] In a specific implementation, the envelope detection module includes: eleventh to fifteenth resistors (R11 to R15), eighth to ninth capacitors (C8 to C9), eleventh and twelfth PMOS transistors (PM11 to PM12), sixteenth to twenty-fifth NMOS transistors (NM16 to NM25);

[0129] like Figure 7 As shown, Figure 7 The schematic diagram of the envelope detection principle. The first stage of the envelope detection module is an operational amplifier with an inductive load. The operational amplifier consists of R11, R12, R13, R14, NM16, NM17, NM18, PM11, PM12, C8 and C9. The trim2 signal fine-tunes the tail current by controlling NM19, further adjusting the gain of the operational amplifier. R11, R13, C8 and PM11 form an inductive impedance, which effectively improves the high-frequency gain of the amplifier. The same is true for R12, R14, C9 and PM12. The circuit uses resistors R11 and R13 with different resistance values ​​to generate differential signals. When PM11, R11, R13 and C8 are set appropriately, one of the differential signals can be used as the threshold voltage for judgment, and the other can be sent to the comparator in the decoding module for comparison with the threshold voltage to output high and low level signals. When the temperature and process drift, VOP and VON will drift in the same direction, thereby ensuring that no bit errors are generated.

[0130] NM20 and NM21, NM22 and NM23 respectively form two sets of envelope detection circuits for demodulating signals, NM24 to NM27 are two current sources, R15 is used to generate a DC voltage difference between VOP and VON, and EN is an enable signal for controlling the magnitude of the current.

[0131] BIAS2 is the bias voltage of the current mirror, so that the current mirror composed of NM24 to NM27 can copy the current given externally.

[0132] The envelope detector module is an electronic circuit or system used to extract the original baseband signal (i.e., the envelope of the signal) from an amplitude modulated (AM) signal. It is widely used in communication systems, especially in radio receivers, to demodulate received AM signals.

[0133] As an optional implementation, the receiving module includes: a decoding module; the decoding module is connected to the envelope detection module, and is used to convert the low-frequency fully differential signal into a digital signal through a Schmitt trigger; the decoding module includes: a low-pass filter, which is used to receive the low-frequency fully differential signal from the envelope detection module and filter out high-frequency noise in the low-frequency fully differential signal; two cascaded resistor-loaded operational amplifiers, coupled to the low-pass filter, and are used to convert the low-frequency fully differential signal into a single-ended output signal; a comparator, which is coupled to the output of the resistor-loaded operational amplifier, wherein the first input terminal receives the single-ended output signal, and the second input terminal receives a threshold voltage signal, and the comparator generates an output signal according to the comparison result between the single-ended output signal and the threshold voltage signal; a Schmitt trigger, which is coupled to the output terminal of the comparator, and is used to restore the output signal to a digital signal.

[0134] In the specific implementation, Figure 8 As shown, Figure 8 The schematic diagram of the decoding module. In the decoding module, BLAS provides bias voltage, and PM13, PM14, PM15, R17, and R18 form a differential amplifier, which can increase gain, suppress temperature drift, and reduce noise. The same applies to PM16, PM17, PM18, R19, and R20. PM19, PM20, PM21, NM26, NM27, NM28, and PM22 form a comparator. PM22 has a larger mutiplier, that is, multiple PMOS tubes are connected in parallel, and NM28 and PM22 are equivalent to open-drain output with a pull-up resistor. The comparator compares the two differential signals and outputs the comparison result through the Schmitt trigger. The output high and low level signals are used as the output of the decoding module.

[0135] As an optional implementation, the receiving module includes: a noise elimination module; the noise elimination module receives the digital signal output by the decoding module, and in response to detecting that the common mode transient pulse in the digital signal is greater than the first target threshold, performs signal latching through a latch enable signal;

[0136] In the specific implementation, Fig. 9 As shown, Fig. 9The schematic diagram of the noise elimination module. The noise elimination module is composed of a digital circuit. The module contains a NOT gate, four buffers, two OR gates and an SR latch. The output VI of the decoding module and VI are respectively ORed with the ENP signal after passing through the inverter and serve as the two inputs of the SR register. When it is detected that the common mode transient pulse in the digital signal output by the decoding module is greater than the first target threshold, the digital control module controls ENP to be set to 1. At this time, SN and RN are both set to 1 (S NOT and R NOT are both set to 1), and the output of the SR latch remains unchanged, thereby eliminating the output burrs. The output VO of the noise elimination module is used as the final output of the receiving module.

[0137] The present disclosure implements, for example, Fig.10 , 11 As shown, Fig.10 The circuit diagram of each key node is shown in Figure 2. Fig.11 Schematic diagrams of waveforms of various key nodes are provided, which illustrate circuit waveforms of several key steps in the modulation and demodulation process of the digital isolator 100 .

[0138] Among them, DIN is the input port of the digital isolator 100, and DOUT is the output port of the digital isolator 100. Signals A and G are single signals, and signals B, C, D, E, and F are differential signals. Fig.11 In order to explain the principle conveniently, only single signals B, C, D, and E are plotted, and signal F is plotted as a differential signal. The input digital signal A is a square wave signal. After passing through the OOK modulator, the high level is modulated into a high-frequency square wave signal B, while the low-level signal remains unchanged. The modulated signal becomes signal C after passing through the capacitor, and the amplitude is greatly attenuated. Before the pre-amplifier module, signal D passes through the capacitor, causing the amplitude to be further reduced, and the common-mode level compensated by the CMTI enhancement module causes the signal to move up. After passing through the pre-amplifier, the amplitude of the high-frequency carrier increases, as shown in signal E.

[0139] The principle of the envelope detection module is to demodulate the envelope of the high-frequency signal as a low-frequency signal. One end of the differential signal vn is used as the transmission signal, and the other end is used as the decision threshold signal vp, as shown in signal F. The decoding module restores the carrier to a digital signal. When vn>vp, it outputs a high level, otherwise it outputs a low level, as shown in signal G.

[0140] Understandably, Fig.11 The units of voltage and time are not indicated because Fig.11 This is only a schematic diagram to explain the principle of modulation and demodulation key waveforms. The scale of the waveform is also for reference only and does not represent the actual amplitude.

[0141] The above description of the embodiments is to facilitate the understanding and application of the present application by those skilled in the art. It is obvious that those familiar with the art can easily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without creative work. Therefore, the present application is not limited to the above embodiments, and improvements and modifications made to the present application by those skilled in the art based on the disclosure of the present application should be within the scope of protection of the present application.

Claims

1. A digital isolator with improved common mode transient immunity, characterized in that: include: A pair of transceiver chips, wherein each of the transceiver chips has the same structure and comprises a transmitting module and a receiving module; A digital control module, used to control one of the pair of transceiver chips to be in a transmission mode and the other to be in a reception mode; A differential driving module, located in the first voltage domain, for converting the digital signal input to the transceiver chip into a fully differential signal, and transmitting the signal to the sending module in the same voltage domain; The sending module is used to perform OOK modulation on the fully differential signal using the clock signal generated by the oscillator to generate a high-frequency fully differential signal; and transmit the high-frequency fully differential signal to the receiving module located in the second voltage domain through the isolation capacitor module; The isolation capacitor module comprises: a pair of isolation circuits, wherein each of the isolation circuits has the same structure, and the pair of isolation circuits are used to process two complementary differential signals of the high-frequency fully differential signal; The receiving module is used to receive the high-frequency fully differential signal and demodulate and restore it to a digital signal input to the transceiver chip; The receiving module includes: a CMTI enhancement module; The digital control module is further used to: detect the high-frequency fully differential signal output by the isolation capacitor module, and in response to detecting that the common-mode transient voltage in the high-frequency fully differential signal is greater than the target transient voltage, enable and control the CMTI enhancement module to compensate the high-frequency fully differential signal; Wherein, the CMTI enhancement module includes: first to fourth resistors, first to fifth capacitors, first to seventh NMOS transistors, and first to fifth PMOS transistors; The first end and the third end of the first NMOS tube are connected to one end of the first resistor and the second end of the second PMOS tube, and the other end of the first resistor is connected to the first power supply and the first end of the third NMOS tube; the second end of the first PMOS tube is connected to the second end of the first NMOS tube, the third end of the fourth NMOS tube, the third end of the fourth PMOS tube, the third end of the seventh NMOS tube, and the third end of the fifth PMOS tube; the third end and the first end of the first PMOS tube are connected to one end of the second resistor and the second end of the second NMOS tube; the other end of the second resistor is grounded and connected to the second ends of the first to fifth capacitors and the first ends of the third to fifth PMOS tubes; The third end of the second PMOS tube is used to input the first enable signal ENB1; the first end of the second PMOS tube is connected to the first end of the first capacitor, the first end of the third capacitor, and the third end of the third NMOS tube; the third end of the second NMOS tube is used to input the second enable signal EN2, and the first end of the second NMOS tube is connected to the first end of the second capacitor and the third end of the third PMOS tube; The second end of the third NMOS tube is connected to the second end of the third PMOS tube, the first end of the fourth capacitor, the first end of the fifth capacitor, one end of the third resistor, and one end of the fourth resistor; The other end of the third resistor is connected to the second end of the fourth NMOS transistor and the second end of the fourth PMOS transistor, and is output as a first port; the other end of the fourth resistor is connected to the second end of the seventh NMOS transistor and the second end of the fifth PMOS transistor, and is output as a second port; The third ends of the fifth NMOS tube and the sixth NMOS tube are used to input a third enable signal EN3; the first end of the fifth NMOS tube is connected to the second power supply and is connected to the first end of the sixth NMOS tube; the second end of the fifth NMOS tube is connected to the first end of the fourth NMOS tube; The second end of the sixth NMOS tube is connected to the first end of the seventh NMOS tube; In response to detecting that the common mode transient voltage in the high frequency fully differential signal is greater than the target transient voltage, enabling and controlling the CMTI enhancement module to compensate the high frequency fully differential signal includes: Turning on the CMTI enhancement module through the first to third enable signals so that the CMTI enhancement module compensates for the high-frequency fully differential signal; The isolation circuit includes a clamping structure and an isolation capacitor; The clamping structure includes: a pair of Zener diodes with opposite polarities and a first-order RC high-pass filter; The positive and negative electrodes of the pair of Zener diodes with opposite polarities are connected to each other in reverse, wherein the positive electrode of one Zener diode is connected to the high-frequency fully differential signal transmission line and the negative electrode is grounded, and the negative electrode of the other Zener diode is connected to the high-frequency fully differential signal transmission line and the positive electrode is grounded; The capacitor in the first-order RC high-pass filter is connected in series to the high-frequency fully differential signal transmission line, and the first end of the capacitor is connected to the sending module; the second end of the capacitor is connected to the positive electrode of the one Zener diode, the negative electrode of the other Zener diode, and one end of the resistor, and is used to output one of the two complementary differential signals; The other end of the resistor in the first-order RC high-pass filter is grounded and connected to the cathode of the one Zener diode and the anode of another Zener diode.

2. The digital isolator according to claim 1, characterized in that: The receiving module is also used to amplify the high-frequency fully differential signal attenuated by the isolation capacitor module, and demodulate and restore it to a digital signal input to the transceiver chip.

3. The digital isolator according to claim 2, characterized in that: The receiving module comprises: a pre-amplifier module; The pre-amplifier module includes: seventh to tenth resistors, eighth to eleventh capacitors, sixth to ninth PMOS transistors, and eighth to fifteenth NMOS transistors; Wherein, the second end of the eighth capacitor is connected to the power supply, and is connected to the second end of the sixth PMOS tube, the second end of the seventh PMOS tube, and the second end of the ninth capacitor; the first end of the eighth capacitor is connected to the third end of the sixth PMOS tube and one end of the seventh resistor; the other end of the seventh resistor is connected to the first end of the sixth PMOS tube, the first end of the eighth NMOS tube, and the third end of the thirteenth NMOS tube; The third end of the eighth NMOS tube is connected to the clamp structure and the CMTI enhancement module, and is connected to the second end of the sixth capacitor in the clamp structure; the second end of the eighth NMOS tube is connected to the second end of the ninth NMOS tube, the first end of the tenth NMOS tube, and the first end of the fourteenth NMOS tube; the third end of the fourteenth NMOS tube is connected to the first gain control signal; the second end of the tenth NMOS tube is grounded, and is connected to the second end of the fourteenth NMOS tube, the second end of the eleventh NMOS tube, and the second end of the fifteenth NMOS tube; the third end of the tenth NMOS tube is connected to the first bias voltage; The first end of the seventh PMOS tube is connected to the first end of the ninth NMOS tube, one end of the eighth resistor, and the third end of the twelfth NMOS tube; the third end of the seventh PMOS tube is connected to the first end of the ninth capacitor and the other end of the eighth resistor; the third end of the ninth NMOS tube is connected to the clamp structure and the CMTI enhancement module, and is connected to the second end of the seventh capacitor in the clamp structure; The second end of the tenth capacitor is connected to the power supply, and is connected to the second end of the eighth PMOS tube, the second end of the ninth PMOS tube, and the second end of the eleventh capacitor; the first end of the tenth capacitor is connected to one end of the ninth resistor and the third end of the eighth PMOS tube; the other end of the ninth resistor is connected to the first end of the eighth PMOS tube and the first end of the twelfth NMOS tube, and outputs a signal VN; The second end of the twelfth NMOS tube is connected to the second end of the thirteenth NMOS tube, the first end of the eleventh NMOS tube, and the first end of the fifteenth NMOS tube; the third end of the eleventh NMOS tube is connected to the second bias voltage; The first end of the ninth PMOS tube is connected to the first end of the thirteenth NMOS tube and one end of the tenth resistor and outputs a signal VP; The first end of the eleventh capacitor is connected to the third end of the ninth PMOS and the other end of the tenth resistor; the third end of the fifteenth NMOS is connected to the first gain control signal; The first gain control signal is provided by the digital control module and is used to control the gain of the amplifier in the pre-amplifier module.

4. The digital isolator according to claim 3, characterized in that: The receiving module includes: an envelope detection module; The envelope detection module is used to detect the amplitude of the signal and convert the high-frequency fully differential signal into a low-frequency fully differential signal by comparing the threshold voltage; The envelope detection module comprises: a dual-end input and dual-end output inductive load operational amplifier and two current sources, which are used to synchronize the offset of the threshold voltage and the high-frequency fully differential signal when the temperature changes, and perform temperature compensation.

5. The digital isolator according to claim 4, characterized in that: The receiving module includes: a decoding module; The decoding module is connected to the envelope detection module and is used to convert the low-frequency fully differential signal into a digital signal through a Schmitt trigger; The decoding module includes: a low-pass filter, which is used to receive the low-frequency full differential signal from the envelope detection module and filter out high-frequency noise in the low-frequency full differential signal; Two cascaded resistor-loaded operational amplifiers, coupled to the low-pass filter, for converting the low-frequency fully differential signal into a single-ended output signal; a comparator coupled to the output of the resistive load operational amplifier, wherein a first input terminal receives the single-ended output signal, a second input terminal receives a threshold voltage signal, and the comparator generates an output signal according to a comparison result between the single-ended output signal and the threshold voltage signal; A Schmitt trigger is coupled to the output end of the comparator and is used to restore the output signal to a digital signal.

6. The digital isolator according to claim 5, characterized in that: The receiving module includes: a noise elimination module; The noise elimination module receives the digital signal output by the decoding module, and in response to detecting that the common mode transient pulse in the digital signal is greater than the first target threshold, performs signal latching through a latch enable signal; The noise elimination module includes: a NOT gate, four buffers, two OR gates and an SR latch; The digital signal output by the decoding module and the signal obtained by inverting the digital signal through an inverter are respectively logically ORed with the latch enable signal to serve as the two outputs of the SR latch; in response to detecting that the common mode transient pulse in the digital signal is greater than the first target threshold, the latch enable signal is set to 1, and the SR latch latches the signal.

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