Data processing method, storage controller, device and storage medium

Abstract

The present application relates to the field of chip technology, and provides a data processing method, storage controller, device and storage medium, the method comprising: obtaining the ith write instruction; i is an integer greater than or equal to 1; identifying the ith write instruction based on configuration parameters, obtaining the ith data to be protected and the ith write address; the configuration parameters indicate the characteristics of multiple storage blocks; the data to be protected corresponds to the storage blocks one by one; the ith data to be protected includes the ith weight data and the ith frame image data; based on the ith write address and the preset offset address, determining the ith target storage address range; the ith target storage address range indicates a part of the first target storage block; the preset offset address is determined based on the configuration parameters; based on the ith target storage address range, writing the ith data to be protected into the first target storage block. The technical solution of the present application can improve the effective bandwidth of DDR, the operating speed and performance of smart terminals.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a data processing method, a storage controller, a device and a storage medium. Background Art

[0002] DDR (Double Data Rate Synchronous Dynamic Random Access Memory) is used to store and process sensor data, image data, algorithm data, etc.

[0003] In smart terminals, weight data and image data are frequently written into DDR. Weight data usually refers to data obtained from sensors, cameras and other devices, which are used for tasks such as target detection, tracking, and recognition after processing and feature extraction. These weight data are frequently written into DDR in smart terminals for subsequent algorithm processing and decision-making. Image data also needs to be written into DDR after collection and preprocessing for use by algorithms such as image processing and deep learning. By writing weight data and image data into DDR, smart terminals can efficiently process and calculate data.

[0004] However, during the current DDR read and write operations, a large amount of invalid data is transmitted, which reduces the effective bandwidth of the DDR and further reduces the operating speed and performance of the smart terminal. Summary of the invention

[0005] The embodiments of the present application provide a data processing method, a storage controller, a device and a storage medium, which can improve the effective bandwidth of DDR, thereby improving the operating speed and performance of the intelligent terminal. The technical solution is as follows:

[0006] According to a first aspect of an embodiment of the present application, a data processing method is provided, the method comprising:

[0007] Get the i-th write instruction; i is an integer greater than or equal to 1;

[0008] Based on the configuration parameters, the i-th write instruction is identified to obtain the i-th data to be protected and the i-th write address; the configuration parameters indicate the characteristics of multiple storage blocks; the multiple storage blocks are part of the memory; the data to be protected corresponds to the storage blocks one by one; the i-th data to be protected includes the i-th weight data and the i-th frame image data; the i-th write address is the first address of the first target storage block; the first target storage block is used to store the i-th data to be protected;

[0009] Based on the i-th write address and the preset offset address, determining the i-th target storage address range; the i-th target storage address range indicates a portion of the first target storage block; the preset offset address is determined based on the configuration parameter;

[0010] Based on the i-th target storage address range, the i-th data to be protected is written into the first target storage block.

[0011] In a possible implementation, the configuration parameters include the number of the storage blocks, the size of the storage blocks, and a preset storage address range of the storage blocks.

[0012] In a possible implementation, determining the i-th target storage address range based on the i-th write address and the preset offset address includes:

[0013] The product of the preset offset address and i is used as the i-th target offset address;

[0014] Based on the i-th target offset address and the i-th write address, the i-th target storage address range is determined; the i-th target storage address range is greater than or equal to the i-th original storage address range, and less than or equal to the preset storage address range of the first target storage block; the i-th original storage address range indicates the size of the i-th data to be protected.

[0015] In a possible implementation, the method further includes:

[0016] The i-th data to be protected is processed based on the configuration parameters to generate the i-th target protection data; the i-th target protection data includes the i-th data to be protected and the i-th flag data; the flag data corresponds to the storage block one by one.

[0017] In a possible implementation, the i-th flag data includes the i-th first flag and the i-th second flag;

[0018] The i-th first flag is set at the head of the image data of the i-th frame; the i-th second flag is set at the tail of the image data of the i-th frame.

[0019] In a possible implementation, the method further includes:

[0020] Acquire a writing process parameter; the writing process parameter indicates that the writing is normal or abnormal;

[0021] If the write process parameter indicates a write abnormality, a first interrupt signal is generated.

[0022] In a possible implementation, the method further includes:

[0023] If the error tolerance time is exceeded and the i+1th target protection data is not obtained, a second interrupt signal is generated; the error tolerance time is greater than the recovery time; the recovery time is the duration between the time point when an error occurs in the i-th target protection data and the time point when writing of the i+1th target protection data begins; the i+1th target protection data is correct data.

[0024] In a possible implementation, the method further includes:

[0025] Get the kth read instruction; k is an integer greater than or equal to 1;

[0026] Identify the kth read instruction based on the configuration parameters, and obtain the kth target storage address range;

[0027] Based on the configuration parameters, determining the kth target offset address;

[0028] Based on the kth target storage address range and the kth target offset address, obtain a kth read address; the kth read address is the first address of the kth target storage address range; the kth read address indicates a second target storage block;

[0029] The kth target protection data is read from the second target storage block based on the kth read address.

[0030] In a possible implementation, the method further includes:

[0031] Parsing the k-th target protection data to obtain the k-th data to be read and the k-th flag data;

[0032] If the k-th flag data is correct, output the k-th data to be read; or

[0033] If the k-th flag data is incorrect, the k-th data to be read is not outputted, and a read error signal is generated.

[0034] In a possible implementation, the method further includes:

[0035] Acquiring a reading process parameter; the reading process parameter indicating a normal reading or an abnormal reading;

[0036] If the reading process parameter indicates a reading abnormality, a third interrupt signal is generated.

[0037] According to a second aspect of an embodiment of the present application, a storage controller is provided, the device comprising:

[0038] An acquisition module, used for acquiring the i-th write instruction; i is an integer greater than or equal to 1;

[0039] A write identification module, used for identifying the i-th write instruction based on configuration parameters, and obtaining the i-th data to be protected and the i-th write address; the configuration parameters indicate the characteristics of multiple storage blocks; the multiple storage blocks are part of the memory; the data to be protected corresponds to the storage blocks one by one; the i-th data to be protected includes the i-th weight data and the i-th frame image data; the i-th write address is the first address of the first target storage block; the first target storage block is used to store the i-th data to be protected;

[0040] an address module, configured to determine an i-th target storage address range based on the i-th write address and a preset offset address; the i-th target storage address range indicates a portion of the first target storage block; the preset offset address is determined based on the configuration parameter;

[0041] A writing module is used to write the i-th data to be protected into the first target storage block based on the i-th target storage address range.

[0042] According to a third aspect of an embodiment of the present application, a computer device is provided, comprising a processor and a memory, wherein the memory is used to store at least one program, and the at least one program is loaded by the processor and executes the data processing method as described above.

[0043] According to a fourth aspect of an embodiment of the present application, a computer-readable storage medium is provided, in which at least one program is stored. The at least one program is loaded and executed by a processor to implement the data processing method as described above.

[0044] In the embodiment of the present application, the embodiment of the present application provides a data processing method, by sequentially storing each frame of image data in a specified location, thereby avoiding the problem of collision and overwriting of image data, thereby protecting the security of image data. In addition, compared with the related art, the embodiment of the present application does not need to embed error checking and correction values ​​in the image data, thereby alleviating the pressure on bandwidth, improving the performance of the advanced driver assistance system, and thus improving the safety of autonomous driving. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 is a schematic diagram of an implementation environment provided according to an embodiment of the present application;

[0047] Figure 2 It is a structural schematic diagram of an advanced driver assistance system chip provided by the related technology;

[0048] Figure 3 It is a structural diagram of a storage controller provided by the related technology;

[0049] Figure 4 It is a structural diagram of an inline error checking and correction safety unit provided by the related art;

[0050] Figure 5 A schematic diagram of a memory controller controlling DDR reading and writing without using an inline error checking and correction safety unit is provided in the related art;

[0051] Figure 6 A schematic diagram of a memory controller controlling DDR reading and writing in the case of using an inline error checking and correction safety unit provided by the related art;

[0052] Figure 7 It is a schematic diagram of the bandwidth ratio occupied by an error checking and correction value provided by the related technology;

[0053] Figure 8 It is a flowchart of a data processing method provided according to an embodiment of the present application;

[0054] Fig. 9 is a flowchart of step 803 provided according to an embodiment of the present application;

[0055] Fig.10 It is a structural diagram of data storage provided by the relevant technology;

[0056] Fig.11 is a structural schematic diagram of a data storage provided according to an embodiment of the present application;

[0057] Fig.12 is a schematic diagram of a data flow between a storage controller and a DDR according to an embodiment of the present application;

[0058] Fig.13is a schematic diagram of an error tolerance protection provided according to an embodiment of the present application;

[0059] Fig.14 is a schematic diagram showing an error in the i-th frame of image data provided according to an embodiment of the present application;

[0060] Fig.15 is a flowchart of another data processing method provided according to an embodiment of the present application;

[0061] Fig.16 is a schematic diagram of a flow chart after step 1505 provided according to an embodiment of the present application;

[0062] Fig.17 is a structural diagram of a storage controller provided according to an embodiment of the present application;

[0063] Fig.18 is a schematic diagram of the structure of a terminal provided in an embodiment of the present application;

[0064] Fig.19 It is a structural diagram of a server provided in an embodiment of the present application. DETAILED DESCRIPTION

[0065] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0066] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0067] In this application, the terms "first", "second", etc. are used to distinguish between identical or similar items with substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is there a limitation on the quantity and execution order. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms.

[0068] These terms are only used to distinguish one element from another element. For example, without departing from the scope of various examples, a first action can be referred to as a second action, and similarly, a second action can also be referred to as a first action. Both the first action and the second action can be actions, and in some cases, can be separate and different actions.

[0069] Here, at least one means one or more than one, for example, at least one action can be one action, two actions, three actions, or any other action that is an integer greater than or equal to one. And multiple means two or more than two, for example, multiple actions can be two actions, three actions, or any other action that is an integer greater than or equal to two.

[0070] Figure 1 It is a schematic diagram of an implementation environment provided according to an embodiment of the present application, and the implementation environment may include a smart terminal 101 and a server 102.

[0071] A storage controller is provided in each of the smart terminals 101, and a DDR is provided outside the smart terminal 101, and the storage controller is used to control the read and write operations of the DDR. The storage controller can also be understood as a DDR controller.

[0072] The smart terminal 101 may be an ADAS (Advanced Driver Assistance Systems) chip, a smart cockpit, a robot, etc. provided with a storage controller.

[0073] The server 102 may be a single server, a server cluster consisting of multiple servers, or a cloud processing center.

[0074] The intelligent terminal 101 is connected to the server 102 via a wired or wireless network.

[0075] In some embodiments, the wireless network or wired network uses standard communication technology and / or protocol. The network is usually the Internet, but it can also be any network, including but not limited to any combination of local area network (LAN), metropolitan area network (MAN), wide area network (WAN), mobile, wired or wireless network, private network or virtual private network. In some embodiments, the data exchanged through the network is represented by technology and / or format including Hyper Text Mark-up Language (HTML), Extensible Markup Language (XML), etc. In addition, conventional encryption technologies such as Secure Socket Layer (SSL), Transport Layer Security (TLS), Virtual Private Network (VPN), Internet Protocol Security (IPsec) can also be used to encrypt all or some links. In other embodiments, customized and / or dedicated data communication technology can also be used to replace or supplement the above data communication technology.

[0076] Figure 2 It is a structural schematic diagram of an advanced driver assistance system chip provided by related technology.

[0077] Among the related technologies, the advanced driver assistance system chip is the foundation and pre-technology of autonomous driving technology, providing the necessary environmental perception and auxiliary control support for the autonomous driving system. Figure 2 As shown, the advanced driver assistance system chip is provided with a SoC (System on Chip), and the SoC is provided with a CPU (Central Processing Unit), an NPU (Neural Processing Unit), a cache, and an input / output interface, etc.

[0078] The ADAS chip also has a memory controller and DDR PHY (Physical Layer). The memory controller is used to manage the read and write operations of the DDR, while the DDR chip is located outside the ADAS chip and is used to store various data. The DDR PHY converts the data sent by the memory controller into a signal that complies with the DDR protocol and sends it to the DDR.

[0079] DDR is used to store and process sensor data, image data, algorithm data, etc. to support various functions and algorithms of advanced driver assistance system chips. DDR includes multiple DDR particles, which represent the smallest storage unit in DDR.

[0080] In the advanced driver assistance system chip, weight data and image data need to be frequently written into DDR. Weight data usually refers to data obtained from sensors, cameras and other devices, which are used for tasks such as target detection, tracking, and recognition after processing and feature extraction. These weight data are frequently written into DDR in the advanced driver assistance system chip for subsequent algorithm processing and decision-making. Image data represents the raw pixel information of image or video data. Image data also needs to be written into DDR after acquisition and preprocessing to facilitate the use of algorithms such as image processing and deep learning.

[0081] By writing weight data and image data into DDR, the advanced driver assistance system chip can efficiently process and calculate data, realize real-time intelligent driving assistance functions, and thus improve driving safety and comfort.

[0082] Figure 3 The present invention is a structural diagram of a storage controller provided by the related technology.

[0083] like Figure 3 As shown in the figure, the storage controller is provided with a core processing unit (core), and the core component is provided with an InlineECC (Inline Error Checking and Correcting) security unit. In addition, the storage controller is also provided with an LBIST (Logic Built-In Self-Test) mechanism, AXI (Advanced eXtensible Interface), APB (Advanced Peripheral Bus), Debug mechanism, and arbitrator, etc.

[0084] Among them, weight data and image data are data related to functional safety. In order to meet the requirements of ISO 2626 (International Organization for Standardization 2626), the functional safety standard for weight data and image data, an inline error checking and correction safety unit is integrated in the storage controller to detect hardware failures of DDR particles that store weight data and image data. When a DDR particle hardware failure occurs, the advanced driver assistance system chip will automatically enter a safe state. For example: the advanced driver assistance system chip restarts. Then, in this case, the driver is required to control the autonomous driving system.

[0085] Figure 4 It is a structural schematic diagram of an inline error checking and correction safety unit provided by the related technology.

[0086] like Figure 4 As shown, the inline error checking and correction security unit includes an error checking and correction encoder, an error checking and correction insertion unit, and an address calculator. The error checking and correction encoder is used to generate an error checking and correction value; the error checking and correction insertion unit is used to insert the error checking and correction value into the corresponding data.

[0087] The inline error checking and correction safety unit can detect and correct bit errors that may occur during data transmission by embedding error checking and correction values ​​in the data transmission path. When reading weight data and image data from DDR or writing to DDR, the inline error checking and correction safety unit will verify the weight data and image data. If an error is found, the storage controller will report the error to the SoC.

[0088] However, due to the consistency issues in reading and writing weight data, image data, and error correction codes, the latency of DDR will increase, especially when weight data and image data are frequently written to DDR.

[0089] Figure 5 The present invention is a schematic diagram of a memory controller controlling DDR reading and writing without using an inline error checking and correction safety unit, as provided by the related art.

[0090] like Figure 5As shown in the figure, without using an inline error checking and correction safety unit, the SoC obtains weight data and image data, and the SoC controls the CPU to configure the register; the storage controller generates a write instruction based on the configuration of the register, and sends the write instruction, weight data, and image data to the DDR; once the DDR completes the data writing, the DDR will send a "Write Data Ready" signal. After receiving this signal, the storage controller will send the next weight data and image data.

[0091] Figure 6 The present invention is a schematic diagram of a memory controller controlling DDR reading and writing when an inline error checking and correction safety unit is used, as provided by the related art.

[0092] like Figure 6 As shown, when using an inline error checking and correction security unit, the SoC obtains weight data and image data, the SoC controls the CPU configuration register, the storage controller generates a write instruction according to the configuration of the register, sends the write instruction, weight data, and image data to the DDR, and calculates the error checking and correction value at the same time and sends the write error checking and correction instruction and the error checking and correction value. Only when the DDR completes the writing of the weight data, image data, and error checking and correction value will it issue the "write data completed" and "write error checking and correction value completed" signals. The storage controller will send the next write instruction, weight data, and image data only after receiving these two signals. Since the waiting time for the "write data completed" and "write error checking and correction value completed" signals is long, it will cause a large delay.

[0093] Therefore, although the inline error checking and correction safety unit ensures the safety of the advanced driver assistance system chip, for the advanced driver assistance system chip, especially in the end-to-end autonomous driving system, when the weight data and image data are frequently written to DDR, the inline error checking and correction safety unit embeds the error checking and correction value in the image data, which will result in a higher bandwidth usage.

[0094] Figure 7 It is a schematic diagram of the ratio of bandwidth occupied by an error checking and correction value provided by the related technology.

[0095] like Figure 7As shown, the bandwidth occupied by the corresponding weight data and image data is 7:1 compared to the error checking and correction value. That is, frequent writing of DDR weight data and image data will greatly increase the bandwidth pressure of DDR, and the effective bandwidth will be reduced by more than 30%. This means that the functional safety of the advanced driver assistance system chip cannot fully enable the inline error checking and correction safety unit to protect the data, because the effective bandwidth of DDR is reduced, which will cause packet loss and even cause some functions of the advanced driver assistance system chip to fail to operate normally, thereby reducing the performance of the advanced driver assistance system chip, affecting the autonomous driving function and safety, and ultimately posing a potential threat to the driver's safety.

[0096] In order to solve the problems existing in the related art, an embodiment of the present application provides a data processing method.

[0097] Figure 8 is a flow chart of a data processing method provided according to an embodiment of the present application, such as Figure 8 As shown, in the embodiment of the present application, the process of writing data to DDR is described by taking the application on an advanced driver assistance system chip with a storage controller as an example. The method includes the following steps:

[0098] In step 801 , the advanced driver assistance system chip obtains the i-th write instruction; i is an integer greater than or equal to 1.

[0099] In some embodiments, before step 801, a portion of storage area needs to be selected from the DDR, and the portion of storage area is used to store data that needs to be protected. The portion of storage area is divided into multiple storage blocks of the same size.

[0100] In one example, the image data to be protected can be determined according to actual needs, that is, any storage block can be designated as the first storage block. The size of the storage area and the size of each storage block can also be determined according to actual needs.

[0101] In one example, the storage addresses included in the partial storage area may be continuous or discontinuous, that is, the first addresses and the last addresses of different storage blocks may be continuous or discontinuous.

[0102] For example, if the size of a DDR is 1G, 300M of it is selected as the storage area, and the 300M storage area is divided into 6 storage blocks of the same size, that is, the size of each storage block is 50M.

[0103] In some embodiments, the configuration parameters include the number of storage blocks, the size of the storage blocks, and a preset storage address range of the storage blocks.

[0104] For example, the preset storage address range of the storage block is 0 to 50M.

[0105] It should be noted that the multiple storage blocks themselves have no order, and the order of use of each storage block can be configured according to actual needs, that is, the corresponding first target storage block is matched for each frame of image data according to actual needs.

[0106] In some embodiments, when the CPU acquires a set of weight data and image data, it configures the register based on the configuration parameters. Optionally, if the weight data and image data are data that need to be protected, the CPU configures a write address for the weight data and image data; the write address indicates any unoccupied storage block. That is, the CPU writes the set of weight data, image data, write address and other information into the register.

[0107] In some embodiments, the advanced driver assistance system chip obtains the write instruction from the register.

[0108] In step 802, the advanced driver assistance system chip identifies the i-th write instruction based on the configuration parameters, and obtains the i-th data to be protected and the i-th write address; the configuration parameters indicate the characteristics of multiple storage blocks; the multiple storage blocks are part of the memory; the data to be protected corresponds to the storage blocks one by one; the i-th data to be protected includes the i-th weight data and the i-th frame image data; the i-th write address is the first address of the first target storage block; the first target storage block is used to store the i-th data to be protected.

[0109] It should be understood that in order to avoid overwriting the i-th frame image data or colliding with the i-th frame image data when writing the i+1-th frame image data into the corresponding target storage block, each storage block is used to store a frame of image data that needs to be protected.

[0110] In some embodiments, the advanced driver assistance system chip identifies the write address in the write instruction, and the write address and the storage block are one-to-one corresponding. That is, after identifying the write address, if the write address indicates any storage block, the data corresponding to the write instruction is the data to be protected. Or if the write address does not fall into any storage block of the storage area, the data corresponding to the write instruction is not the data to be protected.

[0111] In an example, if the data corresponding to the write instruction is not data to be protected, there is no need to execute step 803 and step 804, and the data corresponding to the write instruction and the write address are directly sent to the DDR.

[0112] In some embodiments, the write instruction includes information of the data to be protected, information of the write address, and a data source, wherein the data source includes an NPU or a CPU.

[0113] For example, when the data source is NPU, the data identified based on the write instruction is data that does not need to be protected. Or when the data source is CPU, the data identified based on the write instruction is data that needs to be protected.

[0114] That is to say, in the embodiments of the present application, by identifying the data itself, the write address and the data source, it can be determined whether the data corresponding to the write instruction is data that needs to be protected.

[0115] In some embodiments, the advanced driver assistance system chip stores image data in sequence. Each storage block is used to store one frame of image data. That is, the image data of the i-th frame of image is stored first, and then the image data of the i+1-th frame of image is stored. This avoids the problem of disorder in the process of storing images.

[0116] In step 803, the advanced driver assistance system chip determines the i-th target storage address range based on the i-th write address and the preset offset address; the i-th target storage address range indicates a portion of the first target storage block; the preset offset address is determined based on the configuration parameters.

[0117] Fig. 9 It is a flowchart of step 803 provided according to an embodiment of the present application.

[0118] In some embodiments, the above step 803 may include the following steps 8031 ​​and 8032:

[0119] In step 8031 ​​, the advanced driver assistance system chip uses the product of the preset offset address and i as the i-th target offset address.

[0120] In some embodiments, in the process of storing image data, in order to prevent the i+1th frame image data from overwriting the tth frame image, the target offset address corresponding to the t+1th frame image data is different from that corresponding to the tth frame image data. That is, the first target storage block storing the i-th frame image data is different from the target storage block storing the i+1th frame image.

[0121] In one example, the first storage block is used to store the i-th frame image data, the second storage block is used to store the i+1-th frame image data, and the third storage block is used to store the i+2-th frame image data.

[0122] In some embodiments, depending on the size of the bandwidth, the i-th frame image data may need to be written into the same first target storage block several times. The sub-target offset address corresponding to each portion of data in the i-th frame image data is the same. The sub-write address corresponding to each portion of data in the i-th frame image data is different to avoid data collision or overwriting.

[0123] In one example, the i-th write instruction may include multiple sub-write instructions. Take a portion of data in the i-th frame image data as an example for explanation. The sub-target storage address range of the portion of data can be obtained through the sub-write address and the preset offset address. Among them, the sub-write address is the first address of the portion of data in the first target storage block, and the sub-write address is obtained through the sub-write instruction.

[0124] In an example, the sub-target storage address range of the portion of data may be obtained by the following formula:

[0125] Sub-target storage address range = sub-write address + i × preset offset address.

[0126] For example, the size of each storage block is 50M, the size of the i-th frame image data is 5M, the size of the i-th weight data is 10M, and the preset offset address is 30M.

[0127] For another example, the i-th frame of image data is written into the first target storage block multiple times.

[0128] The first time the first part of data is written, the second time the second part of data is written, and the third time the third part of data is written, and so on.

[0129] Specifically, the sub-target storage address range corresponding to the first portion of data = the sub-write address corresponding to the first portion of data + i×30M.

[0130] The sub-target storage address range corresponding to the second part of the data = the sub-write address corresponding to the second part of the data + i×30M.

[0131] The sub-target storage address range corresponding to the third part of the data = the sub-write address corresponding to the third part of the data + i×30M, etc.

[0132] That is, the sub-write address corresponding to the first part of the data, the sub-write address corresponding to the second part of the data, and the sub-write address corresponding to the third part of the data are different.

[0133] Similarly, the sub-target storage address range corresponding to each part of the data in the i-th frame image data can be obtained.

[0134] Another example: 128 bits of target protection data are written to DDR each time.

[0135] In one example, each portion of the data in the i-th frame of image data is written into the DDR in sequence, for example, from left to right, from top to bottom, etc.

[0136] In step 8032, the advanced driver assistance system chip determines the i-th target storage address range based on the i-th target offset address and the i-th write address; the i-th target storage address range is greater than or equal to the i-th original storage address range, and less than or equal to the preset storage address range of the first target storage block; the i-th original storage address range indicates the size of the i-th data to be protected.

[0137] That is, the embodiment of the present application allows the first target storage block to have remaining storage space after storing the data to be protected, so as to form a buffer space to avoid packet loss or store related feature data in the first target storage block.

[0138] Fig.10 It is a structural diagram of data storage provided by related technologies.

[0139] like Fig.10 As shown, after converting the virtual address of the i-th frame image data into a physical address, it is stored in the physical address. The physical address is any free storage space in the DDR. Such a storage address method that does not specify data is prone to data collision or data overwriting, which reduces the security of stored data.

[0140] Fig.11 It is a structural schematic diagram of data storage provided according to an embodiment of the present application.

[0141] Combine the following Fig.11 The structure of the data storage of the present application is exemplified.

[0142] In some embodiments, by specifying a write address and a target offset address for the data to be protected, the data to be protected is stored in a specified location, thereby avoiding the problem of collision or overwriting of the data to be protected with previously stored data, thereby improving data security, that is, protecting the data to be protected.

[0143] In addition, in the embodiments of the present application, the data to be protected are arranged in sequence according to the specified addresses, that is, the image data is stored frame by frame, which avoids the problem of disorder in the intermediate image data due to the storage of large quantities of image data, that is, the image data is more difficult to be damaged or destroyed.

[0144] In some embodiments, after step 803, the head and tail protection is also performed on the i-th data to be protected; the head and tail protection can be performed on the i-th data to be protected in the following implementation manner.

[0145] The i-th data to be protected is processed based on the configuration parameters to generate the i-th target protection data; the i-th target protection data includes the i-th data to be protected and the i-th flag data; the flag data corresponds to the storage block one by one.

[0146] In one example, the i-th flag data includes the i-th first flag and the i-th second flag; the i-th first flag is set at the head of the i-th frame image data; and the i-th second flag is set at the tail of the i-th frame image data.

[0147] For example, the first mark of the first data to be protected is "001", and the second mark of the first data to be protected is "001".

[0148] The embodiments of the present application enhance the integrity and security of the i-th data to be protected by performing head and tail protection for the i-th data to be protected.

[0149] In step 804 , the advanced driver assistance system chip writes the i th data to be protected into the first target storage block based on the i th target storage address range.

[0150] In some embodiments, since the i-th target offset address and the i-th write address are both virtual addresses, before writing the i-th data to be protected to the specified location in the DDR, it is necessary to convert the i-th target offset address and the i-th write address into the i-th physical address, and then store the i-th data to be protected in the storage location corresponding to the i-th physical address in the DDR, that is, the address mapping is re-performed for the i-th data to be protected, so that the i-th data to be protected is written to the first target storage block.

[0151] In some embodiments, the storage controller sends the i-th data to be protected and the i-th physical address to the DDR through an interface, and the DDR writes the i-th data to be protected into a first target storage block corresponding to the i-th physical address.

[0152] For example, the interface is implemented based on DDR DFI (DDR PHY Interface, DDR physical layer interface).

[0153] Fig.12 It is a schematic diagram of data flow between a storage controller and DDR according to an embodiment of the present application.

[0154] Combine the following Fig.12 The data flow between the memory controller and the DDR is exemplified.

[0155] In some embodiments, once the storage controller sends the ith physical address and the ith data to be protected to the DDR, the DDR completes writing the ith data to be protected, and the DDR will send a "write data complete" signal; the storage controller will send the i+1th physical address and the i+1th protected data. Compared with the inline error checking and correction security unit, the writing of error checking and correction values ​​and the consistency of waiting for data and writing of error checking and correction values ​​are reduced.

[0156] Therefore, in the embodiments of the present application, the data flow between the storage controller and the DDR does not substantially increase the bandwidth pressure, thereby greatly alleviating the bandwidth pressure compared to the inline error checking and correction security unit.

[0157] In some embodiments, during the execution of step 801 to step 802, the writing process is monitored by the following implementation:

[0158] A write process parameter is obtained; the write process parameter indicates that the write is normal or the write is abnormal; if the write process parameter indicates that the write is abnormal, a first interrupt signal is generated.

[0159] For example: normal writing includes no timeout, no illegal jumps, and normal status.

[0160] The write exception includes at least one of a timeout, an illegal jump, and a status exception.

[0161] The first interrupt signal is uploaded to the SoC; the SoC can stop the operation of the advanced driving assistance system chip based on the first interrupt signal.

[0162] Fig.13 It is a schematic diagram of an error tolerance protection provided according to an embodiment of the present application.

[0163] Combine the following Fig.13 The error tolerance protection is exemplified.

[0164] In some embodiments, error tolerance protection may be implemented by:

[0165] If the error tolerance time exceeds and the i+1th target protection data is not obtained, a second interrupt signal is generated; the error tolerance time is greater than the recovery time; the recovery time is the time between the time when an error occurs in the i-th target protection data and the time when writing of the i+1th target protection data begins; the i+1th target protection data is correct data.

[0166] Therefore, since the recovery time is less than the error tolerance time, the second interrupt signal will not be triggered; the advanced driver assistance system chip will perform data processing according to the correct i+1th target protection data within the error tolerance time to ensure the safety of the automatic driving function. Among them, data processing can be understood as the advanced driver assistance system chip obtaining characteristic values ​​according to the correct i+1th target protection data within the error tolerance time.

[0167] In one example, during the process of executing the error tolerance protection, the storage controller diagnoses the correctness of each frame of image data all the time; each diagnosis lasts for a period of time, namely, the diagnosis time.

[0168] Diagnosing the correctness of each frame of image data can be understood as diagnosing whether each frame of image data has a bit flip. If the i-th frame of image data has a bit flip, that is, the i-th frame of image data has an error, a write error signal is generated and reported to the SoC, and the advanced driver assistance system chip determines the data result based on the subsequent frame image data of the i-th frame of image data; that is, the advanced driver assistance system chip ignores the error frame image data when determining the data result.

[0169] Optionally, the SoC accumulates the consecutive number of received write error signals, and if the consecutive number of write error signals reaches a preset number, the SoC may control the advanced driver assistance system chip to stop running.

[0170] For example: the preset quantity is 3, etc.

[0171] Fig.14 is a schematic diagram showing an error in the i-th frame of image data provided according to an embodiment of the present application.

[0172] Combine the following Fig.14 An example description is given of an error in the i-th frame of image data.

[0173] In some embodiments, since the error tolerance time is greater than the recovery time, after an error occurs in the i-th frame of image data in the image data stream, the i+1-th frame of image data begins to be written, and the i+1-th frame of image data is normal, and the i+2-th frame of image data is also normal, that is, there will be no single point failure problem. Since this period of time is less than the error tolerance time, the advanced driver assistance system chip will not stop running.

[0174] It is important to understand that a single point of failure refers to a phenomenon in which there is a critical point or component in a system that, if broken or ineffective, will cause the entire system or a major part of the system to not function properly or to stop functioning.

[0175] Optionally, when the SoC receives three consecutive frames of image data with errors, the advanced driver assistance system chip stops running.

[0176] Optionally, when the SoC receives the second interrupt signal, the advanced driver assistance system chip stops running.

[0177] In some embodiments, the execution of the data processing method can be turned on or off by configuration. The execution of the data processing method will not affect the bus function of the chip. Regardless of whether the execution of the data processing method is turned on or off, the mapping and bandwidth of the bus remain consistent, thereby ensuring that the advanced driver assistance system chip will not be negatively affected during the execution of the data processing method, while ensuring data security.

[0178] It should be understood that the inline error checking and correction security unit embeds ECC values ​​in the image data, resulting in discontinuity of the image data, that is, part of the address corresponds to the image data, and part of the address corresponds to the error checking and correction value, which causes the physical address to be disrupted, so that the bus mapping is inconsistent with the bandwidth. In the embodiment of the present application, the image data is stored continuously, and thus the bus mapping is consistent with the bandwidth.

[0179] The embodiment of the present application stores each frame of image data in a specified location in sequence, thereby avoiding collision and overwriting of image data, thereby protecting the security of image data. In addition, compared with the related art, the embodiment of the present application does not need to embed error checking and correction values ​​in image data, thereby alleviating bandwidth pressure, improving the performance of the advanced driver assistance system, and thus improving the safety of autonomous driving.

[0180] Fig.15 is a flow chart of another data processing method provided according to an embodiment of the present application, such as Fig.15 As shown, in the embodiment of the present application, the process of reading data from DDR is described by taking the application on an advanced driver assistance system chip with a storage controller as an example. The method includes the following steps:

[0181] In step 1501 , the advanced driver assistance system chip obtains the kth read instruction; k is an integer greater than or equal to 1.

[0182] In some embodiments, after storing a preset number of frames of image data, the advanced driver assistance system chip reads the preset number of image data from the DDR for subsequent calculations, thereby providing a driving strategy for the autonomous driving system and ensuring the driver's safety.

[0183] In some embodiments, the advanced driver assistance system chip also reads the image data in sequence, thereby preventing disorder from occurring during the process of reading the image data.

[0184] For example: the kth read instruction corresponds to the kth frame of image data.

[0185] In step 1502 , the advanced driver assistance system chip identifies the kth read instruction based on the configuration parameters and obtains the kth target storage address range.

[0186] In some embodiments, the storage controller can determine whether the kth read instruction indicates image data that needs to be protected based on configuration parameters. Optionally, if the kth read instruction does not indicate image data that needs to be protected, the kth virtual address is directly converted into the kth physical address and then sent to the DDR. Optionally, if the kth read instruction indicates image data that needs to be protected, the kth target storage address range is obtained based on the kth virtual address.

[0187] It should be explained that the storage controller determines whether the k-th image data is image data that needs to be protected through the k-th virtual address.

[0188] In step 1503 , the advanced driver assistance system chip determines the kth target offset address based on the configuration parameters.

[0189] In some embodiments, the storage controller calculates the kth offset address through k and a preset offset address.

[0190] For example: the kth offset address = k × preset offset address.

[0191] In step 1504, the advanced driver assistance system chip obtains the kth read address based on the kth target storage address range and the kth target offset address; the kth read address is the first address of the kth target storage address range; the kth read address indicates the second target storage block.

[0192] In some embodiments, the storage controller uses the difference between the kth target storage address range and the kth target offset address as the kth read address.

[0193] For example: the kth read address = the kth target storage address range - the kth target offset address.

[0194] That is, the kth read address=kth target storage address range-k×preset offset address.

[0195] In step 1505 , the advanced driver assistance system chip reads the kth target protection data from the second target storage block based on the kth read address.

[0196] In some embodiments, since the kth read address is a virtual address, the memory controller converts the kth virtual address into a kth physical address and sends the kth physical address to the DDR.

[0197] The DDR determines a second target storage block based on the kth physical address, and then reads all data stored in the second target storage block.

[0198] Fig.16 It is a flowchart after step 1505 provided according to an embodiment of the present application.

[0199] Combination Fig.16 The process after step 1505 is exemplarily described.

[0200] In some embodiments, after executing step 1505, the following steps are also executed: step 1506 and step 1507a or step 1507b:

[0201] In step 1506 , the advanced driver assistance system chip parses the kth target protection data to obtain the kth data to be read and the kth flag data.

[0202] In step 1507a, if the kth flag data is correct, the kth data to be read is output; or

[0203] In step 1507b, if the kth flag data is incorrect, the kth data to be read is not outputted, and a read error signal is generated.

[0204] In some embodiments, the kth flag data includes a kth first flag and a kth second flag. To ensure the correctness of the data, before the storage controller outputs the kth target protection data to the SoC, the kth target protection data is parsed from the beginning to the end, and the kth first flag is parsed from the beginning of the kth target protection data; and the kth second flag is parsed from the end of the kth target protection data.

[0205] If both the kth first flag and the kth second flag match the second target storage block, the storage controller outputs the kth data to be read. Or if any one of the kth first flag and the kth second flag does not match the second target storage block, the storage controller directly ignores the kth read data, generates a read error signal, and uploads the read error signal to the SoC.

[0206] In one example, the SoC accumulates received error signals, and if a preset number of read error signals are received consecutively, the advanced driver assistance system chip is controlled to stop running.

[0207] For example: the preset number of times is 3, etc.

[0208] In some embodiments, the storage controller monitors the reading process in the following implementation manner during the execution of steps 1501 to 1505:

[0209] A reading process parameter is obtained; the reading process parameter indicates that the reading is normal or abnormal; if the reading process parameter indicates that the reading is abnormal, a third interrupt signal is generated.

[0210] For example: normal reading includes no timeout, no illegal jumps, and normal status.

[0211] The read exception includes at least one of a timeout, an illegal jump, and a status exception.

[0212] The storage controller sends the third interrupt signal to the SoC, and the SoC controls the advanced driver assistance system chip to stop running based on the third interrupt signal.

[0213] In one example, the image data and the corresponding weight data are subsequently calculated based on a preset model. For example, the preset module is a neural network module. The neural network model extracts features from the image data based on the weight data.

[0214] The embodiment of the present application stores each frame of image data in a specified location in sequence, thereby avoiding collision and overwriting of image data, thereby protecting the security of image data. In addition, compared with the related art, the embodiment of the present application does not need to embed error checking and correction values ​​in image data, thereby alleviating bandwidth pressure, improving the performance of the advanced driver assistance system, and thus improving the safety of autonomous driving.

[0215] Fig.17 1 is a schematic diagram of a storage controller 1700 provided according to an embodiment of the present application. The storage controller 1700 includes:

[0216] The acquisition module 1701 is used to acquire the i-th write instruction; i is an integer greater than or equal to 1;

[0217] The write identification module 1702 is used to identify the i-th write instruction based on the configuration parameters, and obtain the i-th data to be protected and the i-th write address; the configuration parameters indicate the characteristics of multiple storage blocks; the multiple storage blocks are part of the memory; the data to be protected corresponds to the storage blocks one by one; the i-th data to be protected includes the i-th weight data and the i-th frame image data; the i-th write address is the first address of the first target storage block; the first target storage block is used to store the i-th data to be protected;

[0218] An address module 1703, configured to determine an i-th target storage address range based on an i-th write address and a preset offset address; the i-th target storage address range indicates a portion of a first target storage block; the preset offset address is determined based on a configuration parameter;

[0219] The writing module 1704 is used to write the i-th data to be protected into the first target storage block based on the i-th target storage address range.

[0220] Among them, the acquisition module 1701, the write identification module 1702, the address module 1703 and the write module 1704 modules, as part of the storage controller, all exist in the form of hardware.

[0221] In some embodiments, the configuration parameters include the number of storage blocks, the size of the storage blocks, and a preset storage address range of the storage blocks.

[0222] The storage controller 1700 further includes a configuration module, and the configuration module is used to generate configuration parameters.

[0223] In some embodiments, the address module 1703 is further configured to:

[0224] The product of the preset offset address and i is used as the i-th target offset address;

[0225] Based on the i-th target offset address and the i-th write address, the i-th target storage address range is determined; the i-th target storage address range is greater than or equal to the i-th original storage address range, and less than or equal to the preset storage address range of the first target storage block; the i-th original storage address range indicates the size of the i-th data to be protected.

[0226] In some embodiments, the storage controller 1700 is further configured to:

[0227] The protection module is used to process the i-th data to be protected based on the configuration parameters to generate the i-th target protection data; the i-th target protection data includes the i-th data to be protected and the i-th flag data; the flag data corresponds to the storage block one by one.

[0228] In some embodiments, the i-th flag data includes the i-th first flag and the i-th second flag;

[0229] The i-th first flag is set at the head of the i-th frame image data; the i-th second flag is set at the tail of the i-th frame image data.

[0230] In some embodiments, the storage controller 1700 is further configured to:

[0231] Get the writing process parameters; the writing process parameters indicate whether the writing is normal or abnormal;

[0232] If the write process parameter indicates a write abnormality, a first interrupt signal is generated.

[0233] In some embodiments, the storage controller 1700 is further configured to:

[0234] If the error tolerance time exceeds and the i+1th target protection data is not obtained, a second interrupt signal is generated; the error tolerance time is greater than the recovery time; the recovery time is the time between the time when an error occurs in the i-th target protection data and the time when writing of the i+1th target protection data begins; the i+1th target protection data is correct data.

[0235] In some embodiments, the storage controller 1700 is further configured to:

[0236] Get the kth read instruction; k is an integer greater than or equal to 1;

[0237] Identify the kth read instruction based on the configuration parameters and obtain the kth target storage address range;

[0238] Based on the configuration parameters, determine the kth target offset address;

[0239] Based on the kth target storage address range and the kth target offset address, a kth read address is obtained; the kth read address is the first address of the kth target storage address range; the kth read address indicates the second target storage block;

[0240] The k-th target protection data is read from the second target storage block based on the k-th read address.

[0241] In some embodiments, the storage controller 1700 is further configured to:

[0242] A parsing module, used for parsing the k-th target protection data to obtain the k-th data to be read and the k-th flag data;

[0243] If the kth flag data is correct, then the kth data to be read is output; or

[0244] If the kth flag data is incorrect, the kth data to be read is not outputted, and a read error signal is generated.

[0245] In some embodiments, the storage controller 1700 is further configured to:

[0246] Get the reading process parameters; the reading process parameters indicate whether the reading is normal or abnormal;

[0247] If the reading process parameter indicates a reading abnormality, a third interrupt signal is generated.

[0248] It should be noted that: when the storage controller provided in the above embodiment executes the corresponding steps, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the storage controller provided in the above embodiment and the data processing method embodiment belong to the same concept, and the specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0249] The embodiment of the present application stores each frame of image data in a specified location in sequence, thereby avoiding collision and overwriting of image data, thereby protecting the security of image data. In addition, compared with the related art, the embodiment of the present application does not need to embed error checking and correction values ​​in image data, thereby alleviating bandwidth pressure, improving the performance of the advanced driver assistance system, and thus improving the safety of autonomous driving.

[0250] An embodiment of the present application further provides a computer device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, and the processor implements the above method when executing the computer program.

[0251] Taking computer equipment as the terminal as an example, Fig.18 This is a schematic diagram of the structure of a terminal provided in an embodiment of the present application, see Fig.18 The terminal 1800 may be a smart phone, a tablet computer, an MP3 player (Moving Picture Experts Group Audio Layer III), an MP4 player (Moving Picture Experts Group Audio Layer IV), a notebook computer, or a desktop computer. The terminal 1800 may also be called a user device, a portable terminal, a laptop terminal, a desktop terminal, or other names.

[0252] Typically, the terminal 1800 includes: a processor 1801 and a memory 1802 .

[0253] The processor 1801 may include one or more processing cores, such as a 4-core processor, a 5-core processor, etc. The processor 1801 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 1801 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 1801 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 1801 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0254] The memory 1802 may include one or more computer-readable storage media, which may be non-transitory. The memory 1802 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 1802 is used to store at least one program code, which is used to be executed by the processor 1801 to implement the process provided by the method embodiment of the present application for the terminal execution in the above method.

[0255] In some embodiments, the terminal 1800 may further optionally include: a peripheral device interface 1803 and at least one peripheral device. The processor 1801, the memory 1802 and the peripheral device interface 1803 may be connected via a bus or a signal line. Each peripheral device may be connected to the peripheral device interface 1803 via a bus, a signal line or a circuit board. Specifically, the peripheral device includes: at least one of a display screen 1804, a camera assembly 1805, an audio circuit 1806 and a power supply 1807.

[0256] The peripheral device interface 1803 may be used to connect at least one peripheral device related to I / O (Input / Output) to the processor 1801 and the memory 1802. In some embodiments, the processor 1801, the memory 1802, and the peripheral device interface 1803 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 1801, the memory 1802, and the peripheral device interface 1803 may be implemented on a separate chip or circuit board, which is not limited in the embodiments of the present application.

[0257] The display screen 1804 is used to display the UI (User Interface). The UI may include graphics, text, icons, videos, and any combination thereof. When the display screen 1804 is a touch display screen, the display screen 1804 also has the ability to collect touch signals on the surface or above the surface of the display screen 1804. The touch signal can be input to the processor 1801 as a control signal for processing. At this time, the display screen 1804 can also be used to provide virtual buttons and / or virtual keyboards, also known as soft buttons and / or soft keyboards. In some embodiments, the display screen 1804 can be one, set on the front panel of the terminal 1800; in other embodiments, the display screen 1804 can be at least two, respectively set on different surfaces of the terminal 1800 or in a folding design; in other embodiments, the display screen 1804 can be a flexible display screen, set on the curved surface or folding surface of the terminal 1800. Even, the display screen 1804 can also be set to a non-rectangular irregular shape, that is, a special-shaped screen. The display screen 1804 can be made of materials such as LCD (Liquid Crystal Display) and OLED (Organic Light-Emitting Diode).

[0258] The camera assembly 1805 is used to capture images or videos. In some embodiments, the camera assembly 1805 includes a front camera and a rear camera. Typically, the front camera is disposed on the front panel of the terminal, and the rear camera is disposed on the back of the terminal. In some embodiments, there are at least two rear cameras, which are any one of a main camera, a depth of field camera, a wide-angle camera, and a telephoto camera, so as to realize the fusion of the main camera and the depth of field camera to realize the background blur function, the fusion of the main camera and the wide-angle camera to realize the panoramic shooting and VR (Virtual Reality) shooting function or other fusion shooting functions. In some embodiments, the camera assembly 1805 may also include a flash. The flash may be a single-color temperature flash or a dual-color temperature flash. A dual-color temperature flash refers to a combination of a warm light flash and a cold light flash, which can be used for light compensation at different color temperatures.

[0259] The audio circuit 1806 may include a microphone and a speaker. The microphone is used to collect sound waves from the user and the environment, and convert the sound waves into electrical signals and input them into the processor 1801 for processing. For the purpose of stereo acquisition or noise reduction, there may be multiple microphones, which are respectively arranged at different parts of the terminal 1800. The microphone may also be an array microphone or an omnidirectional acquisition microphone. The speaker is used to convert the electrical signal from the processor 1801 into sound waves. The speaker may be a traditional film speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, it can not only convert the electrical signal into sound waves audible to humans, but also convert the electrical signal into sound waves inaudible to humans for purposes such as ranging. In some embodiments, the audio circuit 1806 may also include a headphone jack.

[0260] The power supply 1807 is used to power various components in the terminal 1800. The power supply 1807 can be an alternating current, a direct current, a disposable battery, or a rechargeable battery. When the power supply 1807 includes a rechargeable battery, the rechargeable battery can support wired charging or wireless charging. The rechargeable battery can also be used to support fast charging technology.

[0261] Those skilled in the art will understand that Fig.18 The structure shown in the figure does not constitute a limitation on the terminal 1800, and the terminal 1800 may include more or less components than those shown in the figure, or combine some components, or adopt a different component arrangement.

[0262] Take the computer device as a server as an example. Fig.19 This is a structural diagram of a server provided in an embodiment of the present application. The server 1900 may have relatively large differences due to different configurations or performances, and may include one or more processors (Central Processing Units, CPU) 1901 and one or more memories 1902, wherein the one or more memories 1902 store at least one computer program, and the at least one computer program is loaded and executed by the one or more processors 1901 to implement the above data processing method. Of course, the server 1900 may also have components such as a wired or wireless network interface, a keyboard, and an input and output interface for input and output. The server 1900 may also include other components for implementing device functions, which will not be described in detail here.

[0263] The embodiment of the present application also provides a computer-readable storage medium, the computer-readable storage medium includes a stored computer program, wherein when the computer program is running, the device where the computer-readable storage medium is located is controlled to execute the above-mentioned method for generating an image processing model. Optionally, the computer-readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0264] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0265] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A data processing method, characterized in that: include: Get the i-th write instruction; i is an integer greater than or equal to 1; Identifying the i-th write instruction based on configuration parameters to obtain the i-th data to be protected and the i-th write address; the configuration parameters indicate characteristics of multiple storage blocks; A plurality of said storage blocks are part of a memory; The data to be protected corresponds to the storage blocks one by one; the i-th data to be protected includes the i-th weight data and the i-th frame image data; the i-th write address is the first address of the first target storage block; The first target storage block is used to store the i-th data to be protected; the configuration parameters include the number of the storage blocks, the size of the storage blocks and the preset storage address range of the storage blocks; the weight data refers to the data obtained from the sensor and camera device, which is used for target detection, tracking and recognition tasks after processing and feature extraction; The product of the preset offset address and i is used as the i-th target offset address; Determine the i-th target storage address range based on the i-th target offset address and the i-th write address; The i-th target storage address range indicates a portion of the first target storage block; the preset offset address is determined based on the configuration parameter; The i-th target storage address range is greater than or equal to the i-th original storage address range, and less than or equal to the preset storage address range of the first target storage block; The i-th original storage address range indicates the size of the i-th data to be protected; Based on the i-th target storage address range, write the i-th data to be protected into the first target storage block.

2. The method according to claim 1, characterized in that The method further comprises: The i-th data to be protected is processed based on the configuration parameters to generate the i-th target protection data; the i-th target protection data includes the i-th data to be protected and the i-th flag data; the flag data corresponds to the storage block one by one.

3. The method according to claim 2, characterized in that The i-th flag data includes the i-th first flag and the i-th second flag; The i-th first flag is set at the header of the image data of the i-th frame; The i-th second flag is set at the end of the image data of the i-th frame.

4. The method according to claim 1, characterized in that: The method further comprises: Acquire a writing process parameter; the writing process parameter indicates that the writing is normal or abnormal; If the write process parameter indicates a write abnormality, a first interrupt signal is generated.

5. The method according to claim 1, characterized in that The method further comprises: If the error tolerance time is exceeded and the i+1th target protection data is not obtained, a second interrupt signal is generated; the error tolerance time is greater than the recovery time; the recovery time is the duration between the time point when an error occurs in the i-th target protection data and the time point when writing of the i+1th target protection data begins; the i+1th target protection data is correct data.

6. The method according to claim 2, characterized in that The method further comprises: Get the kth read instruction; k is an integer greater than or equal to 1; Identify the kth read instruction based on the configuration parameters, and obtain the kth target storage address range; Based on the configuration parameters, determining the kth target offset address; Based on the kth target storage address range and the kth target offset address, obtain a kth read address; the kth read address is the first address of the kth target storage address range; the kth read address indicates a second target storage block; The kth target protection data is read from the second target storage block based on the kth read address.

7. The method according to claim 6, characterized in that The method further comprises: Parsing the k-th target protection data to obtain the k-th data to be read and the k-th flag data; If the kth flag data is correct, output the kth data to be read; or If the k-th flag data is incorrect, the k-th data to be read is not outputted, and a read error signal is generated.

8. The method according to claim 6, characterized in that The method further comprises: Acquiring a reading process parameter; the reading process parameter indicating a normal reading or an abnormal reading; If the reading process parameter indicates a reading abnormality, a third interrupt signal is generated.

9. A storage controller, characterized in that: include: An acquisition module, used for acquiring the i-th write instruction; i is an integer greater than or equal to 1; A write identification module, used for identifying the i-th write instruction based on configuration parameters to obtain the i-th data to be protected and the i-th write address; the configuration parameters indicate characteristics of multiple storage blocks; A plurality of said storage blocks are part of a memory; The data to be protected corresponds to the storage blocks one by one; the i-th data to be protected includes the i-th weight data and the i-th frame image data; the i-th write address is the first address of the first target storage block; The first target storage block is used to store the i-th data to be protected; the configuration parameters include the number of the storage blocks, the size of the storage blocks and the preset storage address range of the storage blocks; the weight data refers to the data obtained from the sensor and camera device, which is used for target detection, tracking and recognition tasks after processing and feature extraction; An address module, used for taking the product of a preset offset address and i as the i-th target offset address; Determine the i-th target storage address range based on the i-th target offset address and the i-th write address; The i-th target storage address range indicates a portion of the first target storage block; the preset offset address is determined based on the configuration parameter; The i-th target storage address range is greater than or equal to the i-th original storage address range, and less than or equal to the preset storage address range of the first target storage block; The i-th original storage address range indicates the size of the i-th data to be protected; A writing module is used to write the i-th data to be protected into the first target storage block based on the i-th target storage address range.

10. A computer device, characterized in that: The computer device includes a processor and a memory, wherein the memory is used to store at least one program, and the at least one program is loaded by the processor to execute the data processing method according to any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores at least one program, and the at least one program is loaded and executed by the processor to implement the data processing method according to any one of claims 1 to 8.

Images