Hybrid bonding method and hybrid bonding structure

Abstract

The present invention relates to the field of semiconductor technology, and provides a hybrid bonding method and a hybrid bonding structure. The processing methods of the first semiconductor structure and the second semiconductor structure both include: the semiconductor base includes a substrate and a dielectric layer formed on the surface of the substrate, a metal region is formed on the dielectric layer at intervals, and an insulating layer covers the dielectric layer and the metal region; etching on the surface of the insulating layer to form a plurality of bonding pad regions and a blocking groove region; etching through holes in the blocking groove region in the direction of the dielectric layer until the metal region is exposed; depositing a conductive layer, the conductive layer covers the through holes and the blocking groove region, and the surface of the conductive layer is flush with the surface of the bonding pad region; doping the conductive layer with metal impurities; aligning the bonding surfaces of the first semiconductor structure and the second semiconductor structure, and performing annealing treatment to form an oxidized isolation region at the conductive layer, and the oxidized isolation region is formed in the region where the blocking groove region is located.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor processing, and in particular to a hybrid bonding method and a hybrid bonding structure. Background Art

[0002] As the development of ultra-large-scale integrated circuits approaches the physical limit, three-dimensional integrated circuits, which have advantages in both physical size and cost, are an effective way to extend Moore's Law and solve advanced packaging problems. Wafer bonding technology is one of the key technologies for three-dimensional circuit integration, especially hybrid bonding technology, which can realize the internal interconnection of thousands of chips while bonding two wafers, which can greatly improve chip performance and save costs.

[0003] Hybrid Bonding is an advanced integrated circuit packaging technology that replaces traditional bump or solder ball interconnection with direct copper-to-copper connection, and can achieve ultra-fine pitch stacking and packaging in a very small space to achieve the purpose of three-dimensional integration. This technology allows more connection points to be placed in a smaller area, thereby greatly increasing the data communication bandwidth between chips, has the advantages of low resistance and low latency, and helps improve thermal management and reduce heating problems. Based on the above technical advantages, copper hybrid bonding technology is driving the development of next-generation 2.5D and 3D packaging technologies.

[0004] The alignment of bonding holes is a technical problem that needs to be solved by hybrid bonding technology. At present, hybrid bonding technology has the following problems:

[0005] The capacitive coupling of bonding PADs refers to the electrical coupling effect caused by parasitic capacitance between PADs during wafer bonding. This coupling may affect the performance of the circuit, especially in high-frequency applications. The size of the pad (bonding pad area) after wafer bonding affects the size of the parasitic capacitance. A larger pad size can ensure the bonding stability of the wafer, but it will produce excessive parasitic capacitance, which is also not conducive to reducing the size of the semiconductor structure. A smaller pad size will reduce the size of the chip and can also solve the problem of excessive capacitance, but it will also increase the difficulty of the bonding operation. A design solution will be needed to reduce the size of the pad while ensuring the stability of the bonding.

[0006] The wafer bonding process requires annealing. During the annealing process, the pad area will expand and deform. The larger pad area will undergo transitional deformation, resulting in an unstable bonding interface.

[0007] In order to achieve better performance of bonded vias, smaller pads require higher alignment accuracy as the bond trench size and spacing continue to decrease, because even a slight offset may cause bonding failure;

[0008] The through hole is usually filled with copper. When the bonding surfaces are opposite, especially when there is misalignment between the wafer bonding surfaces, copper atoms will diffuse into the bonded wafer. Therefore, a design solution should be provided to avoid the copper in the bonding contact via hole from diffusing into the dielectric layer of the wafer bonding contact surface, thereby reducing the quality of the bonded wafer. Summary of the invention

[0009] The purpose of the present invention is to solve one of the above-mentioned technical problems and to provide an improved hybrid bonding method and hybrid bonding structure, which can reduce the pad size during the bonding process of the wafer semiconductor structure, reduce the inter-wafer capacitance, and improve the convenience of the wafer bonding alignment operation.

[0010] In order to achieve the above object, in some embodiments of the present invention, the following technical solutions are provided:

[0011] A hybrid bonding method comprises the following steps:

[0012] A first semiconductor structure and a second semiconductor structure to be bonded are provided, wherein the processing methods of the first semiconductor structure and the second semiconductor structure both include:

[0013] Providing a semiconductor substrate, the semiconductor substrate comprising a substrate and a dielectric layer formed on a surface of the substrate, wherein metal regions are formed at intervals on the dielectric layer;

[0014] Depositing an insulating layer on the semiconductor substrate, wherein the insulating layer covers the dielectric layer and the metal region;

[0015] Etching on the surface of the insulating layer to form a plurality of bonding pad regions, and a barrier groove region between any adjacent bonding pad regions; when the first semiconductor structure and the second semiconductor structure are bonded, the boundaries of the corresponding barrier groove regions are aligned, and the bonding pad regions are aligned;

[0016] Etching a through hole in the blocking groove region toward the dielectric layer until the metal region is exposed;

[0017] Depositing a conductive layer, wherein the conductive layer covers the through hole and the barrier groove area, and the surface of the conductive layer is flush with the surface of the bonding pad area;

[0018] doping the conductive layer with metal impurities;

[0019] The bonding surfaces of the first semiconductor structure and the second semiconductor structure are aligned, and annealing is performed to form an oxidized isolation region at the conductive layer, wherein the oxidized isolation region is formed in the region where the blocking groove region is located.

[0020] In some embodiments of the present invention, the through hole is formed as a stepped through hole, and the aperture decreases from the barrier groove area to the metal area; the stepped through hole includes a first aperture segment and a second aperture segment, the first aperture segment is close to the surface of the barrier groove area, and the second aperture segment extends along the first aperture segment toward the metal area; the aperture of the first aperture segment is larger than the aperture of the second aperture segment.

[0021] Some embodiments of the present invention further include the following steps: before depositing the conductive layer, a barrier material is deposited on the surface of the through hole to limit the metal impurities from forming an oxidized isolation region within the cross-sectional surface range defined by the through hole.

[0022] In some embodiments of the present invention, the method of depositing a conductive layer includes:

[0023] Depositing a conductive layer until the conductive layer covers the stepped via hole and the entire insulating layer;

[0024] The conductive layer is chemically and mechanically polished until the bonding pad region is exposed and the surface of the conductive layer is flush with the surface of the bonding pad region.

[0025] In some embodiments of the present invention, the conductive layer is made of copper.

[0026] In some embodiments of the present invention, the metal impurities are aluminum, magnesium, or a mixture of aluminum, magnesium and silver.

[0027] Some embodiments of the present invention further provide a hybrid bonding structure, including a first semiconductor structure and a second semiconductor structure; the first semiconductor structure and the second semiconductor structure both include a semiconductor substrate, and the semiconductor substrate includes:

[0028] substrate;

[0029] A dielectric layer is formed on the surface of the substrate, and the dielectric layer includes metal regions arranged at intervals;

[0030] Insulating layer: formed on the surface of the dielectric layer, the insulating layer includes a plurality of bonding pad regions and blocking groove regions, and the blocking groove regions are formed between adjacent bonding pad regions;

[0031] Via: A metal area extending from the surface of the barrier trench area to the surface of the dielectric layer;

[0032] Conductive layer: deposited in the through hole, the conductive layer is doped with metal impurities; the conductive layer covers the through hole and the blocking groove area, and the conductive layer in the blocking groove area forms an oxidized isolation area.

[0033] In some embodiments of the present invention, the through hole includes a first aperture segment and a second aperture segment, the first aperture segment is close to the surface of the blocking groove area, and the second aperture segment extends along the first aperture segment toward the metal area; the aperture of the first aperture segment is larger than the aperture of the second aperture segment;

[0034] When the first semiconductor structure and the second semiconductor structure are bonded, the apertures of the first aperture segments opposite to each other on the two semiconductor structures are equal.

[0035] In some embodiments of the present invention, a barrier material layer is deposited on the surface of the through hole.

[0036] In some embodiments of the present invention, when the first semiconductor structure and the second semiconductor structure are bonded, the apertures of the opposite through holes on the two semiconductor structures are equal, and the apertures of the opposite groups of grooves are equal.

[0037] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0038] The barrier groove area is etched on the dielectric layer. The setting of the barrier groove area can reduce the size of the pad (bonding pad area) during the wafer bonding process. While reducing the pad size, the bonding pad spacing can be increased, but the bonding stability can still be guaranteed, avoiding the direct increase of the bonding pad, resulting in too small a pad spacing, and resulting in capacitive coupling caused by excessive capacitance between pads.

[0039] The blocking groove area is formed into a groove area, and several through holes share one blocking groove area. Multiple through holes share one blocking groove area to form a more stable electrical connection, reduce electrical failures caused by excessive through hole spacing or poor pad contact, enhance the package's resistance to vibration and impact, and improve the reliability of the device.

[0040] By doping metal impurities into the bonding interface and forming an oxide barrier surface in the barrier groove area after annealing, the diffusion of metal ions in the conductive layer into the other dielectric layer caused by alignment errors during the bonding process can be reduced.

[0041] The bonding pad area and the barrier surface area serve as the bonding interface contact area during the bonding process, which increases the contact area of ​​the bonding interface and the bonding alignment margin, thereby avoiding unstable bonding due to insufficient bonding alignment accuracy, and also avoiding directly increasing the bonding pad to make the copper volume too large, which may lead to unstable bonding due to volume expansion during the annealing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0043] Figure 1 Schematic diagram of depositing a dielectric layer on a semiconductor substrate and processing a metal area;

[0044] Figure 2 Schematic diagram of depositing an insulating layer on a semiconductor substrate;

[0045] Figure 3 A schematic diagram of etching the semiconductor substrate insulating layer to form a bonding pad area and a blocking groove area;

[0046] Figure 4 Schematic diagram of etching through holes in the barrier groove area;

[0047] Figure 5 It is a schematic diagram of depositing barrier material in a through hole;

[0048] Figure 6 Schematic diagram of filling the conductive layer into the through hole;

[0049] Figure 7 Schematic diagram of grinding the conductive layer;

[0050] Figure 8 A diagram showing an initial bonding state of the first semiconductor structure and the second semiconductor structure;

[0051] Fig. 9 A schematic diagram of forming a blocking region by bonding and annealing the first semiconductor structure and the second semiconductor structure;

[0052] Fig.10 A diagram showing a bonding misalignment state of a first semiconductor structure and a second semiconductor structure;

[0053] Fig.11 It is a schematic diagram of the structure of the oxidation isolation area and the through-hole area;

[0054] Fig.12 A flow chart of a first embodiment of a hybrid bonding method for a first semiconductor structure and a second semiconductor structure according to the present invention;

[0055] Fig.13 This is a flow chart of a second embodiment of a method for hybrid bonding of a first semiconductor structure and a second semiconductor structure according to the present invention;

[0056] 1- substrate;

[0057] 2- dielectric layer;

[0058] 3-Metallic area;

[0059] 4-insulating layer, 401-bonding pad area, 402-blocking groove area;

[0060] 5-conductive layer;

[0061] 6-through hole, 601-first aperture section, 602-second aperture section;

[0062] 7-oxidation isolation zone;

[0063] 8- Barrier material layer. DETAILED DESCRIPTION

[0064] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0065] Obviously, the drawings described below are only some examples or embodiments of the present application. For ordinary technicians in this field, the present application can also be applied to other similar scenarios based on these drawings without creative work. In addition, it can also be understood that although the efforts made in this development process may be complicated and lengthy, for ordinary technicians in this field related to the content disclosed in this application, some changes in design, manufacturing or production based on the technical content disclosed in this application are just conventional technical means, and should not be understood as insufficient content disclosed in this application.

[0066] The first embodiment of the present invention provides a hybrid bonding method for hybrid bonding between two semiconductor structures. The process of the bonding method is as follows: Fig.12 and Fig.13 , including the following steps.

[0067] First reference Fig.12 .

[0068] A first semiconductor structure and a second semiconductor structure to be bonded are provided. The main structures of the first semiconductor structure and the second semiconductor structure are the same. In this embodiment, the structure of the bonded semiconductor structure is described by taking the structure and processing method of the first semiconductor structure as an example.

[0069] The processing method of the first semiconductor structure includes the following steps.

[0070] refer to Figures 1 to 7, a semiconductor substrate is provided, the semiconductor substrate includes a substrate 1 and a dielectric layer 2 formed on the surface of the substrate 1, and metal regions 3 are formed on the dielectric layer 2 at intervals; wherein the metal regions 3 are block regions formed on the dielectric layer 2 at intervals, and are made of conductive metal material, and can be made by etching a groove region on the dielectric layer 2 and filling it with a metal block, and the surface of the metal region 3 is flush with the surface of the dielectric layer 2. wherein the dielectric layer 2 uses a low dielectric constant material as an interlayer dielectric, which is beneficial to reducing the coupling capacitance between bonded wafers.

[0071] An insulating layer 4 is deposited on the semiconductor substrate, and the insulating layer 4 covers the dielectric layer 2 and the metal region 3 .

[0072] The surface of the insulating layer 4 is etched to form a plurality of bonding pad regions 401 and a blocking groove region 402 between any adjacent bonding pad regions 401; when the first semiconductor structure and the second semiconductor structure are bonded, the boundaries of the corresponding blocking groove regions 402 are aligned, and the bonding pad regions 401 are aligned.

[0073] The surface of the insulating layer 4 is etched to form a blocking groove region 402 at the etched position and a bonding pad region 401 at the unetched position. The bonding pad region 401 serves as a bonding pad during the bonding process between wafers.

[0074] A through hole 6 is etched in the direction of the dielectric layer 2 from the blocking groove area 402 until the metal area 3 is exposed; the diameter of the through hole 6 is smaller than the width of the blocking groove area 402, and after etching the through hole 6, a part of the blocking groove area 402 is still left empty.

[0075] In some embodiments of the present invention, the through hole 6 is formed as a stepped through hole, and the aperture decreases from the blocking groove area 402 to the metal area 3; the stepped through hole includes a first aperture segment 601 and a second aperture segment 602, the first aperture segment 601 is close to the surface of the blocking groove area 402, and the second aperture segment 602 extends along the first aperture segment 601 toward the metal area 3; the aperture of the first aperture segment 601 is larger than the aperture of the second aperture segment 602.

[0076] Based on the above structure, the surface of the blocking groove region 402 , the first aperture segment 601 , and the second aperture segment 602 together form a step structure.

[0077] Conductive layer 5 is deposited, and conductive layer 5 covers through hole 6 and blocking groove area 402, and the surface of conductive layer 5 is flush with the surface of bonding pad area 401; conductive layer 5 is preferably made of copper, and other conductive materials with good conductivity can also be used instead, and metal impurities are doped into conductive layer 5, and the metal impurities are made of aluminum, magnesium, or a mixture of aluminum, magnesium and silver. Conductive layer 5 covers conductive layer 5 filled in through hole 6 and the surface of blocking groove area 402. In some embodiments, metal impurities are filled in the entire conductive layer 5 area, and in some embodiments, metal impurities can also be filled only in the conductive layer 5 area of ​​blocking groove area 402.

[0078] In some embodiments of the present invention, the method of depositing the conductive layer 5 includes:

[0079] Depositing a conductive layer 5 until the conductive layer 5 covers the stepped through hole 6 and the entire insulating layer 4;

[0080] The conductive layer 5 is chemically mechanically polished until the bonding pad area 401 is exposed and the surface of the conductive layer 5 is flush with the surface of the bonding pad area 401 , that is, the conductive layer 5 fills the entire through hole area and the space where the blocking groove area 402 is located.

[0081] The second semiconductor structure is manufactured by the same method as the first semiconductor structure.

[0082] refer to Fig. 9 and Fig.10 , the side surface where the conductive layers of the two semiconductor structures and the bonding pad area 401 are located is the bonding surface, the bonding surfaces of the first semiconductor structure and the second semiconductor structure are aligned, the bonding pad areas 401 of the two wafers are opposite, the blocking groove areas 402 are opposite, and the through holes 6 are opposite. After alignment, annealing treatment is performed, and the annealing conditions are 250°C-350°C, 60min-120min. After annealing treatment, an oxidized isolation area 7 is formed at the conductive layer, and the oxidized isolation area 7 is formed in the area where the blocking groove area 402 is located.

[0083] refer to Fig.11 Since a plurality of through holes 6 share a blocking groove region 402, after the oxide isolation region 7 is formed, the oxide isolation regions 7 of the plurality of through holes are connected, thereby forming a more stable electrical connection.

[0084] refer to Fig.13 and Figure 5Optionally, after the bonding surfaces of the two wafers are facing each other, some embodiments of the present invention further include the following steps: before depositing the conductive layer 5, a barrier material is deposited on the surface of the through hole 6 to form a barrier material layer 8, which is used to limit the metal impurities to form an oxidized isolation region 7 within the cross-sectional surface range defined by the through hole 6. The barrier material can be tantalum, tantalum nitride, titanium or titanium nitride. After depositing the barrier material, the conductive layer 5 is deposited. With this process, after the conductive layer 5 is doped with metal and annealed, an oxidized isolation region will not be formed in the bonding area covered by the through hole 6.

[0085] In a preferred embodiment, the first semiconductor structure and the second semiconductor structure are symmetrical structures, that is, the bonding pad area 401, the barrier groove area 402 and the through hole 6 of the first semiconductor structure and the second semiconductor structure are equal in size. After the bonding surfaces of the two wafers are aligned, the bonding pad areas 401, the barrier groove areas 402 and the through hole 6 of the two semiconductor structures are aligned respectively, and the oxide isolation regions 7 of the two wafers are aligned.

[0086] refer to Fig.10 In the case of wafer bonding misalignment, there may be a problem of misalignment between the bonding pad area 401, the blocking groove area 402 and the through hole 6 between the two wafers. Since the present invention forms an oxide isolation area 7 in the blocking groove area 402, even if the two wafers are misaligned, the oxide isolation area 7 and the bonding pad area 401 are opposite, and the through hole 6 area and the oxide isolation area 7 are opposite, and the copper in the through hole 6 area will not diffuse to the opposite wafer.

[0087] The second embodiment of the present invention further provides a hybrid bonding structure, including a first semiconductor structure and a second semiconductor structure; the first semiconductor structure and the second semiconductor structure are the same, both including a semiconductor substrate, and the semiconductor substrate includes:

[0088] Substrate 1;

[0089] Dielectric layer 2: formed on the surface of substrate 1, dielectric layer 2 includes metal regions 3 arranged at intervals; metal regions 3 may be made of copper;

[0090] Insulating layer 4: formed on the surface of dielectric layer 2, the insulating layer 4 includes a plurality of bonding pad regions 401 and blocking groove regions 402, and the blocking groove regions 402 are formed between adjacent bonding pad regions 401;

[0091] Through hole 6: extending along the surface of the blocking groove area 402 to the metal area 3 on the surface of the dielectric layer 2. The metal area 3 serves as the bottom of the through hole of the semiconductor structure and plays the role of electrical connection between adjacent wafers.

[0092] Conductive layer 5: deposited in through hole 6, the conductive layer 5 is made of copper and doped with metal impurities; the conductive layer 5 in the blocking groove area 402 forms an oxidized isolation area 7. The conductive layer 5 covers the through hole 6 and the blocking groove area 402.

[0093] Among them, the oxide isolation region 7 is formed in the barrier groove area 402, but not in the through hole 6 area. When the two wafers are bonded, the through holes 6 between the wafers are opposite, that is, the copper conductive layers 5 are opposite, thereby realizing the electrical connection between the two wafers. The oxide isolation regions 7 of the barrier groove areas 402 between the wafers are opposite, and the bonding pad areas 401 are opposite. Due to the addition of the barrier groove area 402, the size of the bonding pad area 401 is reduced, and the capacitance between the wafers is reduced. At the same time, the oxide isolation regions 7 between the barrier groove areas 402 are opposite, thereby reducing the risk of copper diffusion between the wafers.

[0094] In some embodiments of the present invention, the through hole 6 is a stepped hole, and the through hole 6 includes a first aperture section 601 and a second aperture section 602. The first aperture section 601 is close to the surface of the barrier groove area 402, and the second aperture section 602 extends along the first aperture section 601 toward the metal area 3. The aperture of the first aperture section 601 is larger than the aperture of the second aperture section 602.

[0095] When the first semiconductor structure and the second semiconductor structure are bonded, the apertures of the first aperture segments opposite to each other on the two semiconductor structures are equal.

[0096] In some embodiments of the present invention, a barrier material layer 8 is deposited on the surface of the through hole 6. During the wafer annealing process, the barrier layer material deposited on the surface of the through hole helps prevent copper from diffusing into the dielectric layer. At the same time, the self-barrier layer can be confined to the dielectric interface to prevent affecting the electrical connection inside the through hole.

[0097] In some embodiments of the present invention, when the first semiconductor structure and the second semiconductor structure are bonded, the apertures of the through holes 6 on the two semiconductor structures that are opposite to each other are equal, and the apertures of the corresponding groups of grooves are equal to each other.

[0098] Based on the technical solution of the present invention, the problems of parasitic capacitance and copper diffusion in the bonding between wafers are solved from the following three aspects:

[0099] 1. Improve the bonding structure so that a plurality of through holes 6 use a blocking groove area 402 as a groove.

[0100] 2. Doping metal impurities (including Al, Mg or Ag) into the conductive layer, and performing annealing after bonding to diffuse the metal impurities to the bonding interface of the barrier groove region 402. The metal impurities can react with the oxide at the interface to form a self-barrier layer containing multi-component oxides.

[0101] 3. First, a dielectric layer is deposited on the semiconductor structure of the wafer, and then a self-barrier layer area and a through hole are made, and then a barrier layer is deposited on the dielectric layer in the through hole area, and then a bonding pad is made to expose the barrier layer interface. After bonding, the self-barrier layer is located at the bonding interface.

[0102] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. It should be pointed out that for those skilled in the art, any modification, equivalent replacement and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the patent application shall be based on the protection scope of the attached claims.

Claims

1. A hybrid bonding method, characterized in that: The following steps are involved: A first semiconductor structure and a second semiconductor structure to be bonded are provided, wherein the processing methods of the first semiconductor structure and the second semiconductor structure both include: Providing a semiconductor substrate, the semiconductor substrate comprising a substrate and a dielectric layer formed on a surface of the substrate, wherein metal regions are formed at intervals on the dielectric layer; Depositing an insulating layer on the semiconductor substrate, wherein the insulating layer covers the dielectric layer and the metal region; Etching on the surface of the insulating layer to form a plurality of bonding pad regions, and a barrier groove region between any adjacent bonding pad regions; when the first semiconductor structure and the second semiconductor structure are bonded, the boundaries of the corresponding barrier groove regions are aligned, and the bonding pad regions are aligned; Etching a through hole in the blocking groove region toward the dielectric layer until the metal region is exposed; Depositing a conductive layer, wherein the conductive layer covers the through hole and the barrier groove area, and the surface of the conductive layer is flush with the surface of the bonding pad area; the conductive layer is made of copper; Doping the conductive layer with metal impurities; the metal impurities are aluminum, magnesium, or a mixture of aluminum, magnesium and silver; The bonding surfaces of the first semiconductor structure and the second semiconductor structure are aligned, and annealing is performed to form an oxidized isolation region at the conductive layer, wherein the oxidized isolation region is formed in the region where the blocking groove region is located.

2. The hybrid bonding method according to claim 1, characterized in that: The through hole is formed as a stepped through hole, and the aperture decreases from the barrier groove area to the metal area; the stepped through hole includes a first aperture segment and a second aperture segment, the first aperture segment is close to the surface of the barrier groove area, and the second aperture segment extends along the first aperture segment toward the metal area; the aperture of the first aperture segment is larger than the aperture of the second aperture segment.

3. The hybrid bonding method according to claim 1 or 2, characterized in that: The method further comprises the following steps: before depositing the conductive layer, depositing a barrier material on the surface of the through hole to limit the metal impurities from forming an oxidized isolation region within the cross-sectional surface range defined by the through hole.

4. The hybrid bonding method according to claim 1, characterized in that: Methods for depositing the conductive layer include: Depositing a conductive layer until the conductive layer covers the stepped via hole and the entire insulating layer; The conductive layer is chemically and mechanically polished until the bonding pad region is exposed and the surface of the conductive layer is flush with the surface of the bonding pad region.

5. A hybrid bonding structure, characterized in that: including a first semiconductor structure and a second semiconductor structure; The first semiconductor structure and the second semiconductor structure both include a semiconductor substrate, and the semiconductor substrate includes: substrate; A dielectric layer is formed on the surface of the substrate, and the dielectric layer includes metal regions arranged at intervals; Insulating layer: formed on the surface of the dielectric layer, the insulating layer includes a plurality of bonding pad regions and blocking groove regions, and the blocking groove regions are formed between adjacent bonding pad regions; Via: A metal area extending from the surface of the barrier trench area to the surface of the dielectric layer; Conductive layer: deposited in the through hole, the conductive layer is doped with metal impurities, the conductive layer is made of copper, and the metal impurities are made of aluminum, magnesium, or a mixture of aluminum, magnesium and silver; the conductive layer covers the through hole and the barrier groove area, and the conductive layer in the barrier groove area forms an oxide isolation area.

6. The hybrid bonding structure according to claim 5, characterized in that: The through hole comprises a first aperture segment and a second aperture segment, wherein the first aperture segment is close to the surface of the blocking groove region, and the second aperture segment extends along the first aperture segment toward the metal region; the aperture of the first aperture segment is larger than the aperture of the second aperture segment; When the first semiconductor structure and the second semiconductor structure are bonded, the apertures of the first aperture segments opposite to each other on the two semiconductor structures are equal.

7. The hybrid bonding structure according to claim 6, characterized in that: A barrier material layer is deposited on the surface of the through hole.

8. The hybrid bonding structure according to claim 6, characterized in that: When the first semiconductor structure and the second semiconductor structure are bonded, the apertures of the through holes on the two semiconductor structures that are opposite to each other are equal, and the apertures of the grooves on the two semiconductor structures that are opposite to each other are equal.

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