Gain-enhanced pseudo-differential amplifier circuit and chip with automatic duty cycle adjustment

Abstract

The present application relates to the field of chip technology, and discloses a gain-enhanced pseudo-differential amplifier circuit with automatic duty cycle adjustment and a chip. The gain-enhanced pseudo-differential amplifier circuit with automatic duty cycle adjustment includes a differential amplifier module and a duty cycle calibration module. The signal input end of the differential amplifier module is used to access a single-ended clock signal, and the in-phase output end and the in-phase output end of the differential amplifier module are used to output a differential clock signal; the duty cycle calibration module is connected to the in-phase output end and the in-phase output end of the differential amplifier module, and is connected to the controlled end of the differential amplifier module to calibrate the duty cycle of the differential clock signal to a preset value, so as to improve the stability of signal transmission between a transmitting end and a receiving end.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a gain-enhanced pseudo-differential amplifier circuit and a chip with automatic duty cycle adjustment. Background Art

[0002] With the development of integrated circuit technology and the increasing bandwidth requirements for data communication, high speed and low power consumption have become the two major mainstream directions of short-distance multi-channel SerDes technology (SERializer / DESerializer for short). In order to reduce power consumption and the number of chip pins, the input and output of traditional short-distance multi-channel SerDes adopt a single-ended structure. The biggest disadvantage of the single-ended structure is that it is sensitive to power supply and ground noise. Traditional single-ended transmission adopts SST structure (direct drive of the inverter), which has a large output signal amplitude and can effectively avoid power supply and ground noise. However, the large signal amplitude increases power consumption and is not suitable for low-power applications. Therefore, low-power SerDes needs to introduce a reference ground transmission mode (using the ground in the chip as the reference level of the signal). In addition, for SerDes with single-ended signal input, low-power applications often use a half-rate structure, which requires the receiver's clock rising and falling edges to be sampled simultaneously, so the traditional SST structure cannot meet the usage requirements. Summary of the invention

[0003] The embodiments of the present application provide a gain-enhanced pseudo-differential amplifier circuit and chip with automatic duty cycle adjustment, which aims to convert a single-ended clock signal into a differential clock signal through a differential amplifier module, and adjust the duty cycle of the differential clock signal through a duty cycle calibration module to improve the stability of signal transmission between a transmitting end and a receiving end.

[0004] An embodiment of the present application provides a gain-enhanced pseudo-differential amplifier circuit with automatic duty cycle adjustment, including a differential amplifier module and a duty cycle calibration module, wherein the signal input end of the differential amplifier module is used to access a single-ended clock signal, and the in-phase output end and the in-phase output end of the differential amplifier module are used to output a differential clock signal; the duty cycle calibration module is connected to the in-phase output end and the in-phase output end of the differential amplifier module, and is connected to the controlled end of the differential amplifier module, so as to calibrate the duty cycle of the differential clock signal to a preset value.

[0005] In some embodiments, the differential amplifier module includes a differential amplifier circuit and a load circuit, the input end of the differential amplifier circuit is connected to the signal input end of the differential amplifier module, the in-phase output end of the differential amplifier circuit is connected to the in-phase output end of the differential amplifier module, the inverting output end of the differential amplifier circuit is connected to the inverting output end of the differential amplifier module, and the controlled end of the differential amplifier circuit is connected to the controlled end of the differential amplifier module; the load circuit is connected to the in-phase output end and the inverting output end of the differential amplifier circuit.

[0006] In some embodiments, the differential amplifier circuit includes a first MOS tube (Metal-Oxide-Semiconductor Field-Effect Transistor, Metal-Oxide Semiconductor Field-Effect Transistor), a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a first resistor and a controlled resistor, the input end of the first MOS tube is connected to a power supply; the input end of the second MOS tube is connected to the power supply; the input end of the third MOS tube is connected to the output end of the first MOS tube; the input end of the fourth MOS tube is connected to the in-phase output end of the differential amplifier circuit, the controlled end of the fourth MOS tube is connected to the controlled end of the third MOS tube, and is connected to the input end of the third MOS tube, the output end of the fourth MOS tube is connected to the input end of the differential amplifier circuit; the input end of the fifth MOS tube is connected to the The output end of the second MOS tube is connected, the output end of the fifth MOS tube is connected to the input end of the differential amplifier circuit; the input end of the sixth MOS tube is connected to the inverting output end of the differential amplifier circuit, the controlled end of the sixth MOS tube is connected to the controlled end of the fifth MOS tube and to the input end of the fifth MOS tube, and the output end of the sixth MOS tube is connected to the output end of the third MOS tube; the first end of the first resistor is connected to the output end of the fourth MOS tube, and the second end of the first resistor is grounded; a controlled resistor, the first end of the controlled resistor is connected to the output end of the sixth MOS tube, the second end of the controlled resistor is grounded, and the controlled end of the controlled resistor is connected to the controlled end of the differential amplifier circuit.

[0007] In some embodiments, the differential amplifier circuit also includes a second resistor and a first capacitor, the first end of the second resistor is connected to the controlled end of the fourth MOSFET, and the second end of the second resistor is connected to the controlled end of the third MOSFET; the differential amplifier circuit also includes a first capacitor, the first plate of the first capacitor is connected to the controlled end of the third MOSFET, and the second plate of the first capacitor is grounded; and / or, the differential amplifier circuit also includes a third resistor and a second capacitor, the first end of the third resistor is connected to the controlled end of the fifth MOSFET, the second end of the third resistor is connected to the controlled end of the sixth MOSFET, the first plate of the second capacitor is connected to the controlled end of the fifth MOSFET, and the second plate of the second capacitor is grounded.

[0008] In some embodiments, the load circuit includes a seventh MOSFET, an eighth MOSFET, a ninth MOSFET and a tenth MOSFET, the input end of the seventh MOSFET is connected to a power supply, and the output end of the seventh MOSFET is connected to a non-inverting output end of the differential amplifier circuit; the input end of the eighth MOSFET is connected to a power supply, the output end of the eighth MOSFET is connected to an inverting output end of the differential amplifier circuit and to a controlled end of the seventh MOSFET, and the controlled end of the eighth MOSFET is connected to the output end of the seventh MOSFET; the input end of the ninth MOSFET is connected to a power supply, the output end of the ninth MOSFET is connected to the output end of the seventh MOSFET, and the controlled end of the ninth MOSFET is connected to the output end of the ninth MOSFET; the input end of the tenth MOSFET is connected to a power supply, the output end of the tenth MOSFET is connected to the output end of the eighth MOSFET, and the controlled end of the tenth MOSFET is connected to the output end of the tenth MOSFET.

[0009] In some of the embodiments, the differential amplifier module further includes a feedback circuit, wherein the non-inverting input terminal of the feedback circuit is connected to the non-inverting output terminal of the differential amplifier circuit; the inverting input terminal of the feedback circuit is connected to the inverting output terminal of the differential amplifier circuit, and the output terminal of the feedback circuit is connected to the controlled terminal of the first MOS tube.

[0010] In some embodiments, the feedback circuit includes a fourth resistor, a fifth resistor, a first inverter, a second inverter, a sixth resistor, a seventh resistor and a first comparator, the first end of the fourth resistor is connected to the non-inverting input end of the feedback circuit; the first end of the fifth resistor is connected to the second end of the fourth resistor, and the second end of the fifth resistor is connected to the inverting input end of the feedback circuit; the input end of the first inverter is connected to the first end of the fourth resistor; the input end of the second inverter is connected to the second end of the fifth resistor; the first end of the sixth resistor is connected to the output end of the first inverter; the first end of the seventh resistor is connected to the second end of the sixth resistor, and the second end of the seventh resistor is connected to the output end of the second inverter; the non-inverting input end of the first comparator is connected to the second end of the sixth resistor, the inverting input end of the first comparator is connected to the second end of the fourth resistor, and the output end of the first comparator is connected to the output end of the feedback circuit.

[0011] In some embodiments, the feedback circuit further includes a third capacitor, a first plate of the third capacitor is connected to the output terminal of the first comparator, and a second plate of the third capacitor is grounded.

[0012] In some embodiments, the differential amplifier module also includes multiple third inverters and multiple fourth inverters, and the multiple third inverters are connected in series between the input end of the first inverter and the in-phase output end of the differential amplifier circuit; the multiple fourth inverters are connected in series between the input end of the second inverter and the inverting output end of the differential amplifier circuit.

[0013] In some of the embodiments, the duty cycle calibration module includes a filter sampling circuit, a comparison circuit and a binary algorithm circuit, the non-phase input terminal of the filter sampling circuit is connected to the non-phase output terminal of the differential amplifier module, and the inverting input terminal of the filter sampling circuit is connected to the inverting output terminal of the differential amplifier module; the non-phase input terminal of the comparison circuit is connected to the non-phase output terminal of the filter sampling circuit, and the inverting input terminal of the comparison circuit is connected to the inverting output terminal of the filter sampling circuit; the input terminal of the binary algorithm circuit is connected to the output terminal of the comparison circuit, and the output terminal of the binary algorithm circuit is connected to the controlled terminal of the differential amplifier module.

[0014] In some embodiments, the filter sampling circuit includes an eighth resistor, a ninth resistor and a fourth capacitor, the first end of the eighth resistor is connected to the in-phase input terminal of the filter sampling circuit, and the second end of the eighth resistor is connected to the in-phase output terminal of the filter sampling circuit; the first end of the ninth resistor is connected to the inverting input terminal of the filter sampling circuit, and the second end of the ninth resistor is connected to the inverting output terminal of the filter sampling circuit; the first plate of the fourth capacitor is connected to the second end of the eighth resistor, and the second plate of the fourth capacitor is connected to the second end of the ninth resistor.

[0015] In some embodiments, the comparison circuit includes a second comparator, a non-inverting input terminal of the second comparator is connected to the non-inverting input terminal of the comparison circuit, an inverting input terminal of the second comparator is connected to the non-inverting input terminal of the comparison circuit, and an output terminal of the second comparator is connected to the output terminal of the comparison circuit.

[0016] In some embodiments, the binary algorithm circuit includes a controller, an initial reset trigger group, a middle reset trigger group, a final reset trigger group, a third inverter, a set trigger group and an AND gate group. The initial reset trigger group, the middle reset trigger group and the final reset trigger group are connected in series between the power access terminal of the binary algorithm circuit and the controller; the initial reset trigger group includes a plurality of initial reset triggers connected in series, the middle reset trigger group includes a plurality of middle reset triggers connected in series, and the final reset trigger group includes a plurality of final reset triggers connected in series; the signal access terminal of the initial reset trigger, the signal access terminal of the middle reset trigger and the signal access terminal of the final reset trigger are all connected to the time control terminal of the controller, and the initial reset trigger group includes a plurality of initial reset triggers connected in series, the middle reset trigger group includes a plurality of middle reset triggers connected in series, and the final reset trigger group includes a plurality of final reset triggers connected in series; the signal access terminal of the initial reset trigger, the signal access terminal of the middle reset trigger and the signal access terminal of the final reset trigger are all connected to the time control terminal of the controller. The reset end of the trigger, the reset end of the middle reset trigger and the reset end of the final reset trigger are all connected to the reset end of the controller; the input end of the third inverter is connected to the input end of the binary algorithm circuit; the set trigger group includes multiple set triggers, the signal access end of the set trigger is connected to the signal output end of the middle reset trigger in a one-to-one correspondence, the power connection end of each set trigger is connected to the output end of the third inverter, and the reset end of each set trigger is connected to the reset end of the controller; the AND gate group includes multiple AND gates, the first input end of the AND gate is connected to the signal output end of the set trigger in a one-to-one correspondence, the second input end of the AND gate is connected to the input end of the middle reset trigger in a one-to-one correspondence, and the output end of the first AND gate is connected to the output end of the binary algorithm circuit.

[0017] An embodiment of the present application also provides a chip, including a substrate and a gain-enhanced pseudo-differential amplifier circuit with automatic duty cycle adjustment, wherein the gain-enhanced pseudo-differential amplifier circuit with automatic duty cycle adjustment is arranged on the substrate.

[0018] Based on the gain-enhanced pseudo-differential amplifier circuit with automatic duty cycle adjustment of the present application, a single-ended clock signal can be converted into a differential clock signal through a differential amplifier module, and the duty cycle of the differential clock signal can be adjusted through a duty cycle calibration module to improve the stability of signal transmission between the transmitter and the receiver, which is of great significance to short-distance, high-speed, low-power multi-channel SerDes systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 This is a schematic diagram of the framework structure of a gain-enhanced pseudo-differential amplifier circuit with automatic duty cycle adjustment in one embodiment of the present application;

[0021] Figure 2 A circuit diagram of a differential amplifier module in one embodiment of the present application;

[0022] Figure 3 This is a schematic diagram of the framework structure of a gain-enhanced pseudo-differential amplifier circuit with automatic duty cycle adjustment in another embodiment of the present application;

[0023] Figure 4 A circuit diagram of a filter sampling circuit and a comparison circuit in one embodiment of the present application;

[0024] Figure 5 A circuit diagram of a binary algorithm circuit in one embodiment of the present application;

[0025] Figure 6 This is a signal waveform diagram of a gain-enhanced pseudo-differential amplifier circuit with automatic duty cycle adjustment in an embodiment of the present application.

[0026] Explanation of the accompanying drawings: 1. Gain-enhanced pseudo-differential amplifier circuit with automatic duty cycle adjustment; 11. Differential amplifier module; 111. Differential amplifier circuit; 112. Load circuit; 113. Feedback circuit; 12. Duty cycle calibration module; 121. Filter sampling circuit; 122. Comparison circuit; 123. Binary algorithm circuit; 1231. Initial reset trigger group; 1232. Middle reset trigger group; 1233. Final reset trigger group; 1234. Set trigger group; 1235. AND gate group; Q1. First MOS tube; Q2. Second MOS tube; Q3. Third MOS tube; Q4. Fourth MOS tube; Q5. Fifth MOS tube; Q6. Sixth MOS tube; Q7. Seventh MOS tube; Q8. Eighth MOS tube; Q9. Ninth MOS tube OS tube; Q10, the tenth MOS tube; RS, the controlled resistor; R1, the first resistor; R2, the second resistor; R3, the third resistor; R4, the fourth resistor; R5, the fifth resistor; R6, the sixth resistor; R7, the seventh resistor; R8, the eighth resistor; R9, the ninth resistor; C1, the first capacitor; C2, the second capacitor; C3, the third capacitor; C4, the fourth capacitor; INV1, the first inverter; INV2, the second inverter; INV3, the third inverter; INV4, the fourth inverter; INV5, the fifth inverter; O1, the first comparator; O2, the second comparator; RDFF1, the initial reset trigger; RDFF2, the middle reset trigger; RDFF3, the final reset trigger; SDFF1, the set trigger; AD1, the AND gate. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0028] An embodiment of the present application provides a chip, which includes at least two sub-chips and a substrate, the two sub-chips are both arranged on the substrate, one of the two sub-chips is a transmitting end (Transmit, TX), and the other of the two sub-chips is a receiving end (Receive, RX).

[0029] Please refer to Figure 1 In order to ensure that the clocks between the transmitting end and the receiving end remain synchronized, the chip also includes a gain-enhanced pseudo-differential amplifier circuit 1 with automatic duty cycle adjustment. The gain-enhanced pseudo-differential amplifier circuit 1 with automatic duty cycle adjustment is arranged on the substrate and connected to the receiving end.

[0030] The duty cycle automatic adjustment gain enhanced pseudo differential amplifier circuit 1 comprises a differential amplifier module 11 and a duty cycle calibration module 12 .

[0031] The signal input end of the differential amplifier module 11 is used to connect the single-ended clock signal, and the in-phase output end and the in-phase output end of the differential amplifier module 11 are used to output the differential clock signal; the duty cycle calibration module 12 is connected to the in-phase output end and the in-phase output end of the differential amplifier module 11, and is connected to the controlled end of the differential amplifier module 11 to calibrate the duty cycle of the differential clock signal to a preset value.

[0032] In the embodiment of the present application, the single-ended clock signal can be converted into a differential clock signal through the differential amplifier module 11, and the duty cycle of the differential clock signal is adjusted through the duty cycle calibration module 12 to improve the stability of signal transmission between the transmitter and the receiver, which is of great significance to the short-distance, high-speed, low-power multi-channel SerDes system. Exemplarily, the preset value can be 40%, 45%, 50%, 55% and 60%. In the present application, the preset value can be preferably 50% so that the accuracy of the rising edge signal and the falling edge signal in the differential clock signal is higher.

[0033] Please refer to Figure 1 and Figure 2In a specific embodiment, the differential amplifier module 11 includes a differential amplifier circuit 111 and a load circuit 112. The input end of the differential amplifier circuit 111 is connected to the signal input end of the differential amplifier module 11, the in-phase output end of the differential amplifier circuit 111 is connected to the in-phase output end of the differential amplifier module 11, the inverting output end of the differential amplifier circuit 111 is connected to the inverting output end of the differential amplifier module 11, and the controlled end of the differential amplifier circuit 111 is connected to the controlled end of the differential amplifier module 11; the load circuit 112 is connected to the in-phase output end and the inverting output end of the differential amplifier circuit 111.

[0034] Specifically, the differential amplifier circuit 111 may include a first MOSFET Q1, a second MOSFET Q2, a third MOSFET Q3, a fourth MOSFET Q4, a fifth MOSFET Q5, a sixth MOSFET Q6, a first resistor R1, and a controlled resistor RS. The input end of the first MOSFET Q1 is connected to a power supply; the input end of the second MOSFET Q2 is connected to a power supply; the input end of the third MOSFET Q3 is connected to the output end of the first MOSFET Q1; the input end of the fourth MOSFET Q4 is connected to the in-phase output end of the differential amplifier circuit 111, the controlled end of the fourth MOSFET Q4 is connected to the controlled end of the third MOSFET Q3, and is connected to the input end of the third MOSFET Q3; the output end of the fourth MOSFET Q4 is connected to the input end of the differential amplifier circuit 111; the fifth MOSFET Q5 ... The input end of the transistor Q5 is connected to the output end of the second MOSFET Q2, and the output end of the fifth MOSFET Q5 is connected to the input end of the differential amplifier circuit 111; the input end of the sixth MOSFET Q6 is connected to the inverting output end of the differential amplifier circuit 111, the controlled end of the sixth MOSFET Q6 is connected to the controlled end of the fifth MOSFET Q5 and to the input end of the fifth MOSFET Q5, and the output end of the sixth MOSFET Q6 is connected to the output end of the third MOSFET Q3; the first end of the first resistor R1 is connected to the output end of the fourth MOSFET Q4, and the second end of the first resistor R1 is grounded; the first end of the controlled resistor RS is connected to the output end of the sixth MOSFET Q6, the second end of the controlled resistor RS is grounded, and the controlled end of the controlled resistor RS is connected to the controlled end of the differential amplifier circuit 111.

[0035] The load circuit 112 may include a seventh MOSFET Q7, an eighth MOSFET Q8, a ninth MOSFET Q9, and a tenth MOSFET Q10. The input end of the seventh MOSFET Q7 is connected to the power supply, and the output end of the seventh MOSFET Q7 is connected to the in-phase output end of the differential amplifier circuit 111. The input end of the eighth MOSFET Q8 is connected to the power supply, and the output end of the eighth MOSFET Q8 is connected to the inverting output end of the differential amplifier circuit 111 and to the controlled end of the seventh MOSFET Q7. The controlled end of the eighth MOSFET Q8 is connected to the inverting output end of the differential amplifier circuit 111. The controlling end is connected to the output end of the seventh MOSFET Q7; the input end of the ninth MOSFET Q9 is connected to the power supply, the output end of the ninth MOSFET Q9 is connected to the output end of the seventh MOSFET Q7, and the controlled end of the ninth MOSFET Q9 is connected to the output end of the ninth MOSFET Q9; the input end of the tenth MOSFET Q10 is connected to the power supply, the output end of the tenth MOSFET Q10 is connected to the output end of the eighth MOSFET Q8, and the controlled end of the tenth MOSFET Q10 is connected to the output end of the tenth MOSFET Q10.

[0036] Please refer to Figure 1 and Figure 2 , wherein the fourth MOSFET Q4, the seventh MOSFET Q7 and the ninth MOSFET Q9 can form a common-gate amplifier circuit, and the second MOSFET Q2, the fifth MOSFET Q5, the sixth MOSFET Q6, the eighth MOSFET Q8, the tenth MOSFET Q10 and the controlled resistor RS can form a two-stage amplifier circuit, wherein the two-stage amplifier circuit includes a first-stage amplifier circuit composed of the second MOSFET Q2 and the fifth MOSFET Q5, that is, a common-gate amplifier circuit, and also includes a second-stage amplifier circuit composed of the sixth MOSFET Q6, the eighth MOSFET Q8, the tenth MOSFET Q10 and the controlled resistor RS, that is, a common-source amplifier circuit.

[0037] Please refer to Figure 1 and Figure 2 It can be understood that the common-gate amplifier circuit composed of the fourth MOSFET Q4, the seventh MOSFET Q7 and the ninth MOSFET Q9 is a unidirectional amplifier circuit; the two-stage amplifier circuit composed of the second MOSFET Q2, the fifth MOSFET Q5, the sixth MOSFET Q6, the eighth MOSFET Q8, the tenth MOSFET Q10 and the controlled resistor RS is a reverse amplifier circuit, so that the differential amplifier circuit 111 can convert the single-ended clock signal into a differential clock signal, thereby meeting the use requirements of the SerDes chip.

[0038] Please refer to Figure 1 and Figure 2Further, in order to stabilize the voltage of the controlled end of the third MOSFET Q3 and the controlled end of the fifth MOSFET Q5, the differential amplifier circuit 111 further includes a second resistor R2 and a first capacitor C1, the first end of the second resistor R2 is connected to the controlled end of the fourth MOSFET Q4, and the second end of the second resistor R2 is connected to the controlled end of the third MOSFET Q3; the first plate of the first capacitor C1 is connected to the controlled end of the third MOSFET Q3, and the second plate of the first capacitor C1 is grounded. The second resistor R2 and the first capacitor C1 form a low-pass filter circuit to filter out high-frequency noise signals entering the controlled end of the third MOSFET Q3, so that the gate voltage of the third MOSFET Q3 can be stabilized, and the switching accuracy of the third MOSFET Q3 can be improved.

[0039] Please refer to Figure 1 and Figure 2 In another embodiment, the differential amplifier circuit 111 may further include a third resistor R3 and a second capacitor C2, wherein a first end of the third resistor R3 is connected to the controlled end of the fifth MOSFET Q5, and a second end of the third resistor R3 is connected to the controlled end of the sixth MOSFET Q6; a first electrode plate of the second capacitor C2 is connected to the controlled end of the fifth MOSFET Q5, and a second electrode plate of the second capacitor C2 is grounded. The third resistor R3 and the second capacitor C2 form a low-pass filter circuit to filter out high-frequency noise signals entering the controlled end of the fifth MOSFET Q5, thereby stabilizing the voltage of the controlled end of the fifth MOSFET Q5, and further improving the switching accuracy of the fifth MOSFET Q5.

[0040] In the embodiment of the present application, when the signal of the duty cycle calibration module 12 changes, the resistance value of the controlled resistor RS will change, thereby changing the static level signal at the input end of the sixth MOS tube Q6, thereby changing the duty cycle of the differential clock signal output by the differential amplifier circuit 111, so as to improve the stability of signal transmission between the transmitting end and the receiving end.

[0041] It can be understood that the load circuit 112 composed of the seventh MOSFET Q7 , the eighth MOSFET Q8 , the ninth MOSFET Q9 and the tenth MOSFET Q10 is a cross-coupled negative resistance circuit, which can increase the amplification gain of the differential amplifier circuit 111 .

[0042] It is understandable that the first MOS Q1, the second MOS Q2, the third MOS Q3, the fourth MOS Q4, the fifth MOS Q5, the sixth MOS Q6, the seventh MOS Q7, the eighth MOS Q8, the ninth MOS Q9 and the tenth MOS Q10 can also be replaced by a triode (Bipolar Junction Transistor, BJT) and an insulated gate bipolar transistor (Insulate-Gate Bipolar Transistor, IGBT), and the effect of the present application can also be achieved. In the embodiment of the present application, no further details are given on this.

[0043] Please refer to Figure 1 and Figure 2 In one embodiment, the differential amplifier module 11 further includes a feedback circuit 113, wherein the non-inverting input terminal of the feedback circuit 113 is connected to the non-inverting output terminal of the differential amplifier circuit 111; the inverting input terminal of the feedback circuit 113 is connected to the inverting output terminal of the differential amplifier circuit 111, and the output terminal of the feedback circuit 113 is connected to the controlled terminal of the first MOS tube Q1.

[0044] Please refer to Figure 1 and Figure 2 Specifically, the feedback circuit 113 may include a fourth resistor R4, a fifth resistor R5, a first inverter INV1, a second inverter INV2, a sixth resistor R6, a seventh resistor R7 and a first comparator O1, the first end of the fourth resistor R4 is connected to the non-inverting input end of the feedback circuit 113; the first end of the fifth resistor R5 is connected to the second end of the fourth resistor R4, and the second end of the fifth resistor R5 is connected to the inverting input end of the feedback circuit 113; the input end of the first inverter INV1 is connected to the first end of the fourth resistor R4; the input end of the second inverter INV2 is connected to the second end of the fifth resistor R5; the first end of the sixth resistor R6 is connected to the first end of the fourth resistor R4; the input end of the second inverter INV2 is connected to the second end of the fifth resistor R5; the first end of the sixth resistor R6 is connected to the second end of the fifth resistor R5; the first end of the sixth resistor R6 is connected to the first end of the fourth resistor R4; the second end of the fifth resistor R5 is connected to the second end of the sixth resistor R7; the first end of the sixth resistor R6 is connected to the first end of the fourth resistor R4; the first end of the fifth resistor R5 is connected to the second end of the fifth resistor R5; the first end of the sixth resistor R6 is connected to the second end of the fifth resistor R7; the first end of the sixth resistor R6 is connected to the second end of the fifth resistor R7; the first end of the fifth resistor R5 is connected to the second end of the fifth resistor R7; the first end of the sixth resistor R6 is connected to the second end of the fourth resistor R4; the first end of the fifth resistor R5 is connected to the second end of the fifth resistor R7; the first end of the sixth resistor R6 is connected to the second end of the fifth resistor R7; the first end of the fifth resistor R5 is connected to the second end of the fifth resistor R7; the first end of the sixth resistor R6 is connected to the second end of the fourth resistor R The first end of the seventh resistor R7 is connected to the second end of the sixth resistor R6, and the second end of the seventh resistor R7 is connected to the output end of the second inverter INV2; the non-inverting input end of the first comparator O1 is connected to the second end of the sixth resistor R6, and the inverting input end of the first comparator O1 is connected to the second end of the fourth resistor R4, and the output end of the first comparator O1 is connected to the output end of the feedback circuit 113 to output a bias voltage to the controlled ends of the first MOS tube Q1 and the second MOS tube Q2, so as to stabilize the common mode voltage of the differential amplifier circuit 111 and stabilize the output signal of the differential amplifier module 11.

[0045] Please refer to Figure 1 and Figure 2Furthermore, the feedback circuit 113 also includes a third capacitor C3, a first plate of the third capacitor C3 is connected to the output end of the first comparator O1, and a second plate of the third capacitor C3 is grounded, so that the output voltage of the output end of the first comparator O1 is stabilized by the third capacitor C3, thereby stabilizing the output voltage of the feedback circuit 113.

[0046] Please refer to Figure 1 and Figure 2 In one embodiment, the differential amplifier module 11 further includes a plurality of third inverters INV3 and a plurality of fourth inverters INV4, wherein the plurality of third inverters INV3 are connected in series between the input end of the first inverter INV1 and the in-phase output end of the differential amplifier circuit 111; and the plurality of fourth inverters INV4 are connected in series between the input end of the second inverter INV2 and the inverting output end of the differential amplifier circuit 111. By connecting a plurality of third inverters INV3 in series, and increasing the size of the third inverter INV3 step by step, the output driving capability can be effectively enhanced. Similarly, by connecting a plurality of fourth inverters INV4 in series, and increasing the size of the fourth inverter INV4 step by step, the output driving capability can also be effectively enhanced.

[0047] It can be understood that if the subsequent load is larger, the number of the third inverter INV3 and the fourth inverter INV4 required is more; if the number of the third inverter INV3 and the fourth inverter INV4 is less, the overall power consumption of the duty cycle automatic adjustment gain enhanced pseudo differential amplifier circuit 1 is lower. In the embodiment of the present application, there is no specific limitation on the number of the third inverter INV3 and the fourth inverter INV4.

[0048] Please refer to Figure 1 and Figure 3 In one embodiment, the duty cycle calibration module 12 includes a filter sampling circuit 121, a comparison circuit 122 and a binary algorithm circuit 123. The in-phase input terminal of the filter sampling circuit 121 is connected to the in-phase output terminal of the differential amplifier module 11, and the inverting input terminal of the filter sampling circuit 121 is connected to the inverting output terminal of the differential amplifier module 11; the in-phase input terminal of the comparison circuit 122 is connected to the in-phase output terminal of the filter sampling circuit 121, and the inverting input terminal of the comparison circuit 122 is connected to the inverting output terminal of the filter sampling circuit 121; the input terminal of the binary algorithm circuit is connected to the output terminal of the comparison circuit 122, and the output terminal of the binary algorithm circuit is connected to the controlled terminal of the differential amplifier module 11.

[0049] The differential clock signal output by the differential amplifier module 11 is filtered and sampled by the filter sampling circuit 121 and then enters the comparison circuit 122, so that the comparison circuit 122 outputs level signals of 0 and 1. The binary algorithm circuit controls the resistance value of the controlled resistor RS through the level signals of 0 and 1, thereby changing the static level signal at the input end of the sixth MOS tube Q6, thereby changing the duty cycle of the differential clock signal output by the differential amplifier circuit 111, so as to improve the stability of signal transmission between the transmitting end and the receiving end.

[0050] Please refer to Figure 1 , Figure 3 and Figure 4 In one embodiment, the filter sampling circuit 121 includes an eighth resistor R8, a ninth resistor R9 and a fourth capacitor C4, wherein the first end of the eighth resistor R8 is connected to the in-phase input end of the filter sampling circuit 121, and the second end of the eighth resistor R8 is connected to the in-phase output end of the filter sampling circuit 121; the first end of the ninth resistor R9 is connected to the inverting input end of the filter sampling circuit 121, and the second end of the ninth resistor R9 is connected to the inverting output end of the filter sampling circuit 121; the first plate of the fourth capacitor C4 is connected to the second end of the eighth resistor R8, and the second plate of the fourth capacitor C4 is connected to the second end of the ninth resistor R9. By using the low-pass filter circuit of the eighth resistor R8, the ninth resistor R9 and the fourth capacitor C4, the DC component of the differential clock signal can pass through, thereby improving the stability of the differential signal obtained by the comparison circuit 122.

[0051] Please refer to Figure 1 , Figure 3 and Figure 4 In one embodiment, the comparison circuit 122 includes a second comparator O2, a non-inverting input terminal of the second comparator O2 is connected to the non-inverting input terminal of the comparison circuit 122, an inverting input terminal of the second comparator O2 is connected to the non-inverting input terminal of the comparison circuit 122, and an output terminal of the second comparator O2 is connected to the output terminal of the comparison circuit 122. When the voltage at the non-inverting input terminal of the second comparator O2 is greater than the voltage at the inverting input terminal, the output terminal of the second comparator O2 outputs a high level 1; when the voltage at the non-inverting input terminal of the second comparator O2 is less than the voltage at the inverting input terminal, the output terminal of the second comparator O2 outputs a low level 0, so that the binary algorithm circuit controls the resistance value of the controlled resistor RS to change through the level signals of 0 and 1, so that the static level signal at the input terminal of the sixth MOS tube Q6 changes, thereby changing the duty cycle of the differential clock signal output by the differential amplifier circuit 111, so as to improve the stability of signal transmission between the transmitting end and the receiving end.

[0052] Please refer to Figure 1 , Figure 3 and Figure 5In one embodiment, the binary algorithm circuit 123 includes a controller, an initial reset trigger group 1231, a middle reset trigger group 1232, a final reset trigger group 1233, a fifth inverter INV5, a set trigger group 1234, and an AND gate group 1235. The initial reset trigger group 1231, the middle reset trigger group 1232, and the final reset trigger group 1233 are connected in series between the power supply access terminal of the binary algorithm circuit 123 and the controller; the initial reset trigger group 1231 includes a plurality of initial reset triggers RD connected in series. FF1, the middle reset trigger group 1232 includes a plurality of middle reset triggers RDFF2 connected in series, and the final reset trigger group 1233 includes a plurality of final reset triggers RDFF3 connected in series; the signal access terminal CK of the initial reset trigger RDFF1, the signal access terminal CK of the middle reset trigger RDFF2 and the signal access terminal CK of the final reset trigger RDFF3 are all connected to the time control terminal of the controller, the reset terminal RB of the initial reset trigger RDFF1, the reset terminal RB of the middle reset trigger RDFF2 and the reset terminal RB of the final reset trigger RDFF3 are all connected to the reset terminal RB of the controller; the input terminal of the fifth inverter INV5 is connected to the input terminal of the binary algorithm circuit; the set trigger group 1234 includes a plurality of set triggers SDFF1, the plurality of set triggers SDFF1 are arranged in one-to-one correspondence with the plurality of middle reset triggers RDFF2, the signal access terminal CK of the set trigger SDFF1 is connected in one-to-one correspondence with the signal output terminal Q of the middle reset trigger RDFF2, and the power connection terminal D of each set trigger SDFF1 is connected to the output terminal of the fifth inverter INV5 The reset terminal RB of each set trigger SDFF1 is connected to the reset terminal RB of the controller; the AND gate group 1235 includes multiple AND gates AD1, and the multiple AND gates AD1 are arranged in a one-to-one correspondence with the multiple set triggers SDFF1. The first input terminal of the AND gate AD1 is connected in a one-to-one correspondence with the signal output terminal Q of the set trigger SDFF1, the second input terminal of the AND gate AD1 is connected in a one-to-one correspondence with the input terminal of the middle reset trigger RDFF2 corresponding to the set trigger SDFF1, and the output terminal of the AND gate AD1 is connected to the output terminal of the binary algorithm circuit 123.

[0053] Specifically, the initial reset trigger group 1231 can be used to absorb the unstable initial clock signal sent by the controller, so that the subsequent stable clock signal can enter the middle reset trigger group 1232, thereby improving the accuracy of the output signal of the binary algorithm circuit 123. In the embodiment of the present application, there is no specific restriction on the number of the initial reset trigger RDFF1 in the initial reset trigger group 1231 and the number of the middle reset trigger RDFF2 in the middle reset trigger group 1232.

[0054] Please refer to Figure 5, exemplarily, the initial reset trigger group 1231 may include two initial reset triggers RDFF1, the two initial reset triggers RDFF1 are respectively the first reset trigger and the second reset trigger; the middle reset trigger group 1232 may include five middle reset triggers RDFF2, the five middle reset triggers RDFF2 are respectively the third reset trigger, the fourth reset trigger, the fifth reset trigger, the sixth reset trigger and the seventh reset trigger; the final reset trigger group 1233 may include one final reset trigger RDFF3, the final reset trigger RDFF3 is the eighth reset trigger. The set trigger group 1234 may include five set triggers SDFF1, the five set triggers SDFF1 are respectively the first set trigger, the second set trigger, the third set trigger, the fourth set trigger and the fifth set trigger. The AND gate group 1235 may include five AND gates AD1, which are respectively the first AND gate, the second AND gate, the third AND gate, the fourth AND gate and the fifth AND gate. The controlled resistor RS may be a parallel connection of multiple switch resistor arrays.

[0055] Please refer to Figure 5 and Figure 6 Specifically, when the reset terminal of the controller outputs a low-level signal, the signal output terminal Q of each reset trigger is low-level, and the signal output terminal Q of each set trigger SDFF1 is high-level, so that the output terminal of each AND gate AD1 is low-level. At this time, the binary algorithm circuit 123 is in the initial state, and S<4:0>=00000. (Instruction manual attached Figure 6 In the figure, DCN and DCP are output signals of the output end of the filter sampling circuit 121; SIGN is the output signal of the output end of the comparison circuit 122; S<4:0> is the output signal of the output end of the binary algorithm circuit 123; CK_LOW is the output signal of the time control end of the controller; RSTN is the reset signal of the reset end of the controller; CAL_END is the output signal of the signal output end Q of the eighth reset flip-flop)

[0056] When the reset terminal of the controller outputs a high level signal, the binary algorithm circuit 123 is started.

[0057] When the time control end of the controller outputs the first rising edge clock signal, the signal access end CK of the first reset trigger receives the rising edge signal, so that the signal output end Q of the first reset trigger can output a high level. At this time, the output end of each AND gate AD1 is still at a low level, and the blocking of the controlled resistor RS remains in the initial state, so that the first reset trigger can be used to eliminate the unstable first rising edge signal.

[0058] When the time control end of the controller outputs the second rising edge clock signal, the signal output end Q of the first reset trigger remains at a high level, and the signal access end CK of the second reset trigger receives the rising edge signal, so that the signal output end Q of the second reset trigger can output a high level, so that the second input end of the first AND gate AD1 is at a high level, and the signal output end Q of the first set trigger SDFF1 is at a high level, so that the first input end of the first AND gate AD1 is at a high level, so that the output end of the first AND gate AD1 can output a high level, so that the output end of the binary algorithm circuit 123 can output S<4:0>=10000, thereby controlling the action of the corresponding controlled resistor RS.

[0059] When the time control terminal of the controller outputs the third rising edge clock signal, the signal output terminal Q of the first reset trigger and the signal output terminal Q of the second reset trigger both maintain a high level, and the signal access terminal CK of the third reset trigger receives the rising edge signal, so that the signal output terminal Q of the third reset trigger can output a high level, so that the second input terminal of the second AND gate AD1 is a high level;

[0060] If the voltage at the non-inverting input terminal of the second comparator O2 is greater than the voltage at the inverting input terminal at this time, the signal output terminal Q of the second comparator O2 outputs a high level, and the high level is converted to a low level via the fifth inverter INV5, so that the signal output terminal Q of the first set trigger SDFF1 outputs a low level, so that the output terminal of the first AND gate AD1 outputs a low level; and because the signal output terminal Q of the third reset trigger outputs a high level, the signal output terminal Q of the second set trigger SDFF1 remains high, so that the output terminal of the second AND gate AD1 outputs a high level, so that the output terminal of the binary algorithm circuit 123 can output <4:0>=01000, thereby controlling the corresponding controlled resistor RS to increase, so that the duty cycle of the differential clock signal is reduced;

[0061] If the voltage at the non-inverting input terminal of the second comparator O2 is less than the voltage at the inverting input terminal at this time, the output terminal of the second comparator O2 outputs a low level, and the low level is converted to a high level via the fifth inverter INV5, so that the signal output terminal Q of the first set trigger SDFF1 outputs a high level, so that the output terminal of the first AND gate AD1 outputs a high level; and since the signal output terminal Q of the third reset trigger outputs a high level, the signal output terminal Q of the third set trigger SDFF1 remains at a high level, so that the output terminal of the second AND gate AD1 outputs a high level, so that the output terminal of the binary algorithm circuit 123 can output S<4:0>=11000, thereby controlling the corresponding controlled resistance RS to decrease, so that the duty cycle of the differential clock signal increases.

[0062] By analogy, the controller's time control terminal outputs the seventh rising edge clock signal, and after controlling the output signal of the fifth AND gate AD1 to change, the calibration of the duty cycle of the differential clock signal is completed. The controller's time control terminal outputs the eighth rising edge clock signal, which causes the signal output terminal Q of the eighth reset flip-flop to output a high level. After receiving the high level signal, the controller stops outputting the clock signal, thereby reducing the overall power loss of the duty cycle automatic adjustment gain enhanced pseudo differential amplifier circuit 1.

[0063] The same or similar numbers in the drawings of this embodiment correspond to the same or similar parts; in the description of this application, it should be understood that if the terms "up", "down", "left", "right", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the drawings, it is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and cannot be understood as limitations on this application. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0064] The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A gain-enhanced pseudo-differential amplifier circuit with automatic duty cycle adjustment, characterized in that: include: A differential amplifier module, wherein the signal input end of the differential amplifier module is used to access a single-ended clock signal, and the in-phase output end and the inverting output end of the differential amplifier module are used to output a differential clock signal; the differential amplifier module comprises a differential amplifier circuit, a load circuit and a feedback circuit, the input end of the differential amplifier circuit is connected to the signal input end of the differential amplifier module, the in-phase output end of the differential amplifier circuit is connected to the in-phase output end of the differential amplifier module, the inverting output end of the differential amplifier circuit is connected to the inverting output end of the differential amplifier module, and the controlled end of the differential amplifier circuit is connected to the controlled end of the differential amplifier module; The load circuit is connected to the in-phase output terminal and the inverting output terminal of the differential amplifier circuit; the differential amplifier circuit comprises: A first MOS tube, wherein an input end of the first MOS tube is connected to a power source; A second MOS tube, wherein an input end of the second MOS tube is connected to the power supply; a third MOS tube, wherein an input end of the third MOS tube is connected to an output end of the first MOS tube; a fourth MOS tube, wherein the input end of the fourth MOS tube is connected to the in-phase output end of the differential amplifier circuit, the controlled end of the fourth MOS tube is connected to the controlled end of the third MOS tube and is connected to the input end of the third MOS tube, and the output end of the fourth MOS tube is connected to the input end of the differential amplifier circuit; a fifth MOS tube, wherein the input end of the fifth MOS tube is connected to the output end of the second MOS tube, and the output end of the fifth MOS tube is connected to the input end of the differential amplifier circuit; a sixth MOS tube, wherein the input end of the sixth MOS tube is connected to the inverting output end of the differential amplifier circuit, the controlled end of the sixth MOS tube is connected to the controlled end of the fifth MOS tube and is connected to the input end of the fifth MOS tube, and the output end of the sixth MOS tube is connected to the output end of the third MOS tube; A first resistor, wherein a first end of the first resistor is connected to the output end of the fourth MOS tube, and a second end of the first resistor is grounded; A controlled resistor, wherein a first end of the controlled resistor is connected to the output end of the sixth MOS tube, a second end of the controlled resistor is grounded, and a controlled end of the controlled resistor is connected to a controlled end of the differential amplifier circuit; The in-phase input terminal of the feedback circuit is connected to the in-phase output terminal of the differential amplifier circuit; the inverting input terminal of the feedback circuit is connected to the inverting output terminal of the differential amplifier circuit, and the output terminal of the feedback circuit is connected to the controlled terminal of the first MOS tube; A duty cycle calibration module is connected to the in-phase output terminal and the inverting output terminal of the differential amplifier module and to the controlled terminal of the differential amplifier module to calibrate the duty cycle of the differential clock signal to a preset value; the duty cycle calibration module includes: A filter sampling circuit, wherein the in-phase input terminal of the filter sampling circuit is connected to the in-phase output terminal of the differential amplification module, and the inverting input terminal of the filter sampling circuit is connected to the inverting output terminal of the differential amplification module; A comparison circuit, wherein a non-inverting input terminal of the comparison circuit is connected to a non-inverting output terminal of the filter sampling circuit, and an inverting input terminal of the comparison circuit is connected to an inverting output terminal of the filter sampling circuit; A binary algorithm circuit, wherein the input end of the binary algorithm circuit is connected to the output end of the comparison circuit, and the output end of the binary algorithm circuit is connected to the controlled end of the differential amplifier module.

2. The gain-enhanced pseudo-differential amplifier circuit with automatic duty cycle adjustment according to claim 1, characterized in that: The differential amplifier circuit also includes: a second resistor, wherein a first end of the second resistor is connected to the controlled end of the fourth MOS tube, and a second end of the second resistor is connected to the controlled end of the third MOS tube; A first capacitor, wherein a first plate of the first capacitor is connected to the controlled end of the third MOS tube, and a second plate of the first capacitor is grounded; and / or, a third resistor, wherein a first end of the third resistor is connected to the controlled end of the fifth MOS tube, and a second end of the third resistor is connected to the controlled end of the sixth MOS tube; A second capacitor, wherein a first plate of the second capacitor is connected to the controlled end of the fifth MOS tube, and a second plate of the second capacitor is grounded.

3. The gain-enhanced pseudo-differential amplifier circuit with automatic duty cycle adjustment according to claim 1, characterized in that: The load circuit comprises: a seventh MOS tube, wherein an input end of the seventh MOS tube is connected to a power supply, and an output end of the seventh MOS tube is connected to a non-inverting output end of the differential amplifier circuit; an eighth MOS tube, wherein the input end of the eighth MOS tube is connected to the power supply, the output end of the eighth MOS tube is connected to the inverting output end of the differential amplifier circuit and to the controlled end of the seventh MOS tube, and the controlled end of the eighth MOS tube is connected to the output end of the seventh MOS tube; a ninth MOS tube, wherein the input end of the ninth MOS tube is connected to the power supply, the output end of the ninth MOS tube is connected to the output end of the seventh MOS tube, and the controlled end of the ninth MOS tube is connected to the output end of the ninth MOS tube; A tenth MOS tube, wherein the input end of the tenth MOS tube is connected to the power supply, the output end of the tenth MOS tube is connected to the output end of the eighth MOS tube, and the controlled end of the tenth MOS tube is connected to the output end of the tenth MOS tube.

4. The gain-enhanced pseudo-differential amplifier circuit with automatic duty cycle adjustment according to claim 1, characterized in that: The feedback circuit comprises: a fourth resistor, a first end of the fourth resistor being connected to the non-inverting input end of the feedback circuit; a fifth resistor, wherein a first end of the fifth resistor is connected to a second end of the fourth resistor, and a second end of the fifth resistor is connected to an inverting input end of the feedback circuit; A first inverter, wherein an input terminal of the first inverter is connected to a first terminal of the fourth resistor; A second inverter, wherein an input terminal of the second inverter is connected to a second terminal of the fifth resistor; a sixth resistor, a first end of the sixth resistor being connected to the output end of the first inverter; a seventh resistor, wherein a first end of the seventh resistor is connected to a second end of the sixth resistor, and a second end of the seventh resistor is connected to an output end of the second inverter; A first comparator, wherein the non-inverting input terminal of the first comparator is connected to the second end of the sixth resistor, the inverting input terminal of the first comparator is connected to the second end of the fourth resistor, and the output terminal of the first comparator is connected to the output terminal of the feedback circuit.

5. The gain-enhanced pseudo-differential amplifier circuit with automatic duty cycle adjustment as claimed in claim 4, characterized in that: The feedback circuit further includes: A third capacitor, wherein a first plate of the third capacitor is connected to the output end of the first comparator, and a second plate of the third capacitor is grounded.

6. The duty cycle automatic adjustment gain enhanced pseudo differential amplifier circuit as claimed in claim 4, characterized in that: The differential amplifier module also includes: A plurality of third inverters are connected in series between the input end of the first inverter and the in-phase output end of the differential amplifier circuit; A plurality of fourth inverters are connected in series between the input end of the second inverter and the inverting output end of the differential amplifier circuit.

7. The gain-enhanced pseudo-differential amplifier circuit with automatic duty cycle adjustment according to claim 1, characterized in that: The filtering sampling circuit comprises: an eighth resistor, wherein a first end of the eighth resistor is connected to the in-phase input end of the filter sampling circuit, and a second end of the eighth resistor is connected to the in-phase output end of the filter sampling circuit; a ninth resistor, wherein a first end of the ninth resistor is connected to the inverting input end of the filter sampling circuit, and a second end of the ninth resistor is connected to the inverting output end of the filter sampling circuit; A fourth capacitor, wherein a first electrode plate of the fourth capacitor is connected to the second end of the eighth resistor, and a second electrode plate of the fourth capacitor is connected to the second end of the ninth resistor.

8. The duty cycle automatic adjustment gain-enhanced pseudo-differential amplifier circuit according to claim 1, characterized in that: The comparison circuit comprises: A second comparator, wherein the non-inverting input terminal of the second comparator is connected to the non-inverting input terminal of the comparison circuit, the inverting input terminal of the second comparator is connected to the non-inverting input terminal of the comparison circuit, and the output terminal of the second comparator is connected to the output terminal of the comparison circuit.

9. The gain-enhanced pseudo-differential amplifier circuit with automatic duty cycle adjustment according to claim 1, characterized in that: The binary algorithm circuit comprises: Controller; An initial reset trigger group, a middle reset trigger group and a final reset trigger group, wherein the initial reset trigger group, the middle reset trigger group and the final reset trigger group are connected in series between the power supply access terminal of the binary algorithm circuit and the controller; the initial reset trigger group includes a plurality of initial reset triggers connected in series, the middle reset trigger group includes a plurality of middle reset triggers connected in series, and the final reset trigger group includes a plurality of final reset triggers connected in series; The signal access end of the initial reset trigger, the signal access end of the middle reset trigger and the signal access end of the final reset trigger are all connected to the time control end of the controller, and the reset end of the initial reset trigger, the reset end of the middle reset trigger and the reset end of the final reset trigger are all connected to the reset end of the controller; a fifth inverter, wherein an input terminal of the fifth inverter is connected to an input terminal of the binary algorithm circuit; A set trigger group, comprising a plurality of set triggers, wherein the plurality of set triggers are arranged in one-to-one correspondence with the plurality of mid-stage reset triggers, the signal input terminals of the set triggers are connected in one-to-one correspondence with the signal output terminals of the mid-stage reset triggers, the power input terminals of each of the set triggers are connected to the output terminals of the fifth inverter, and the reset terminals of each of the set triggers are connected to the reset terminals of the controller; An AND gate group includes multiple AND gates, and the multiple AND gates are arranged in a one-to-one correspondence with the multiple set triggers. The first input end of the AND gate is connected to the signal output end of the set trigger in a one-to-one correspondence, the second input end of the AND gate is connected to the input end of the mid-stage reset trigger corresponding to the set trigger in a one-to-one correspondence, and the output end of the AND gate is connected to the output end of the binary algorithm circuit.

10. A chip, characterized in that: include: substrate, and The duty cycle automatic adjustment gain-enhanced pseudo-differential amplifier circuit according to any one of claims 1 to 9 is arranged on the substrate.

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