Phase detection device, phase self-calibration method and phased array monolithic integrated circuit

Abstract

The present invention belongs to the technical field of phased array antenna channel calibration, specifically a phase detection device, a phase self-calibration method and a phased array monolithic integrated circuit. The phase detection device includes a first frequency divider, a second frequency divider, a first mixer, a second mixer, an N-bit counter and an N-bit edge trigger, wherein the phase of the second mixer output signal S5 is determined by the phase of the detected input signal S4, and the phase of the signal S5 determines the delay tp of the N-bit edge trigger, and the delay tp determines the output result of the output signal S7 of the N-bit edge trigger, so the output signal S7 of the phase detection device can be used to characterize the relative phase of the detected input signal S4, based on this relative phase, the radio frequency channel can be high-precision phase detection and self-calibration. Compared with the prior art, the device and method of the present invention are simpler and have higher detection accuracy.

Description

Technical Field

[0001] The present invention relates to the technical field of phased array antenna channel calibration, and in particular to a phase detection device, a phase self-calibration method and a phased array monolithic integrated circuit. Background Art

[0002] Phased array antenna is an antenna that changes the shape of the far-field pattern by controlling the feeding phase and amplitude of the array antenna unit. It has the advantages of high gain, adjustable beam pointing, beam shaping, and low side lobe, and is widely used in communication, detection and other fields.

[0003] The basic principle of phased array is to use the superposition and phase change of the radiation waveform of the unit antenna to achieve power synthesis and beam scanning. Phased array systems usually include multiple channels. For example, phased array antennas in applications such as 5G communication systems, radar systems, and satellite communication systems require the integration of dozens of channels at least, and tens of thousands of RF channels at most. Phased array systems also require that the phase shift and amplitude between channels remain consistent, and the phase shift error between channels is as small as possible.

[0004] Usually, each RF channel in a phased array system needs to be composed of multiple circuits such as a variable gain amplifier, a phase shifter, a power amplifier, a low noise amplifier, and an RF switch. Among them, the variable gain amplifier and phase shifter are used to complete high-precision amplitude and phase adjustment of the RF signal, which is the key to the phased array system to achieve beam scanning function.

[0005] When the amplitude and phase of many RF channels in the phased array system deviate, it will lead to problems such as pattern deterioration, pointing deviation, gain reduction, sidelobe rise, and zero depth deterioration. There are many factors that affect the amplitude and phase of the RF channel, including device inconsistency, manufacturing tolerance, assembly error, environmental change, array element mutual coupling, position deviation, and channel failure. Therefore, it is necessary to measure and calibrate the amplitude and phase of the phased array antenna channel. According to the actual test environment, there are two ways to calibrate the phased array antenna: external calibration and self-calibration. The external calibration method includes far-field calibration, mid-field calibration, and near-field calibration, all of which are to sample and calibrate the antenna radiation field through an external calibration unit. The external calibration method has high requirements for the site, environment, equipment, instruments, etc., and the calibration time is long and the cost is high. It is generally only used for the calibration of phased array antennas before leaving the factory, and the correction data obtained by calibration is generally solidified in non-volatile memory. After leaving the factory, due to the influence of factors such as ambient temperature, component aging, and channel failure, the phase and amplitude of the RF channel in the phased array system will produce new errors, and the adaptability of the calibration correction data at the factory will gradually decrease, which will lead to a decline in the performance of the phased array system. At this time, due to limited conditions, it is generally difficult to perform external calibration again, and each RF channel in the phased array system can only be recalibrated through self-calibration. The current mainstream phased array self-calibration methods are antenna coupling calibration method and channel coupling calibration method.

[0006] The antenna coupling calibration method is to add some reference antenna units to the phased array antenna system, form a feedback loop through the coupling between each antenna unit to be calibrated and the reference antenna unit in the phased array system, convert the frequency of the data fed back by the coupling, sample it, and send it to the processor for processing, and compare it with the theoretical value to obtain the calibration data. For example, the phased array calibration method disclosed in the patent documents with publication numbers CN112003654A and CN101904051A is the antenna coupling calibration method. This scheme has major problems in practical application: 1) Due to the limitation of spatial layout, the antenna unit to be calibrated and the reference antenna unit cannot be directly aligned, the coupling degree between antennas is extremely low, and the measurement error is large; 2) The distance and relative position of each antenna unit in the array plane and the reference antenna unit are different, resulting in large differences in the strength and accuracy of the coupling signal between different antennas and the reference antenna, which is not conducive to the implementation of calibration; 3) The hardware complexity of implementing modules such as reference antenna units, feedback loops and digital processing in the phased array system is high, which is not conducive to integration.

[0007] The channel coupling calibration method is to add a calibration channel between the RF channel and the antenna of each unit of the phased array through a coupler to form a feedback loop, and the data fed back by the coupling is frequency-converted and sampled, and then sent to the processor for processing, and the calibration data is obtained after comparison with the theoretical value. For example, the phased array calibration method disclosed in the patent document with publication number CN116827453A is a channel coupling calibration method. The channel coupling calibration method can effectively improve the measurement accuracy, and there is good consistency between channels, but there is also the problem of high hardware complexity and inconvenience for integration.

[0008] By analyzing the implementation methods of existing self-calibration technologies, it is not difficult to find that whether it is the antenna coupling method or the channel coupling method, the difference is only in the signal coupling method, and the detection and calculation of the phase information of the coupled signal all need to be implemented through dedicated signal processing equipment. In the prior art, the amplitude detection of the channel is relatively simple, and it can generally be completed using a simple detector, but the method and device for phase detection are relatively complicated. Generally, the high-frequency RF signal is first converted into a low-frequency signal through superheterodyne down-conversion, and then sampled through an analog-to-digital converter (ADC), and finally the phase information of the signal is obtained through digital signal processing and calculation. This device needs to be composed of at least a frequency synthesizer, a down-conversion mixer, an analog-to-digital converter, a digital signal processor and other modules, and has high complexity and implementation cost when implemented in a phased array system. Summary of the invention

[0009] The purpose of the present invention is to provide a phase detection device, a phase self-calibration method and a phased array monolithic integrated circuit. The phase detection device has a simple structure and realizes high-precision phase detection. In the phase self-calibration method, since the radio frequency channel used has the phase adjustment capability, the phase self-calibration can be performed by obtaining the phase response information. For a multi-channel phased array integrated circuit, the same phase detection device is reused to perform phase detection on multiple channels by switching, which simplifies the circuit structure of the entire integrated circuit and reduces the cost.

[0010] To achieve the above object, the present invention adopts the following technical solution:

[0011] A phase detection device, comprising:

[0012] A first frequency divider, whose frequency division ratio is M, is used to receive a signal S0 provided by a radio frequency input terminal, and divide the input signal S0 to obtain a signal S1, wherein the frequency of the signal S1 is f1=f0 / M, wherein f0 is the frequency of the input signal S0;

[0013] The second frequency divider has a division ratio of 2 N, used to receive the signal S1 provided by the first frequency divider, and divide the signal S1 to obtain the signal S2, the frequency of the signal S2 is f2=f1 / 2 N =f0 / (M*2 N );

[0014] The first mixer operates in up-conversion mode, receives the signal S2 provided by the second frequency divider and the input signal S0 provided by the RF input terminal, and performs up-conversion on the signal S2 and the signal S0 to obtain a signal S3, wherein the frequency of the signal S3 is f3=f0+f2;

[0015] The second mixer works in down-conversion mode, receives the detected signal S4 and the signal S3 provided by the first mixer, and down-converts the detected signal S4 and the signal S3 to obtain a signal S5. The frequency of the detected signal S4 is f0, and it carries the phase information of the RF channel to be detected. The frequency of the signal S5 is f5=f3-f0=f2=f0 / (M*2 N );

[0016] The N-bit counter receives the signal S1 provided by the first frequency divider, and counts the incoming cycles of the signal S1, and generates a signal S6 according to the counting result. The signal S6 is composed of an N-bit parallel signal, and the total number of counts is 2 N , the count range is 0 to 2 N -l;

[0017] The N-bit edge trigger receives the signal S5 provided by the second mixer and the signal S6 provided by the N-bit counter. When the rising edge of the signal S5 is reached, the currently received signal S6 is locked and output as the signal S7, ie, the phase detection result.

[0018] Furthermore, the frequency division ratio M of the first frequency divider is set according to the selected semiconductor process and the input signal frequency, and the frequency division ratio 2 of the second frequency divider is set according to the selected semiconductor process and the input signal frequency. N The parameter value N in is set according to the phase detection resolution requirement.

[0019] A phase self-calibration method comprises the following steps:

[0020] Step 1: Obtain a detected signal S4 output by the RF channel to be calibrated, where the frequency of the detected signal S4 is f0 and carries phase information of the RF channel;

[0021] Step 2: Use the above phase detection device to perform phase self-detection on the detected signal S4 to obtain a phase detection result;

[0022] Step 3: Compare the phase result with the initial phase data to obtain the phase offset of the RF channel to be calibrated;

[0023] Step 4: Calculate new calibration compensation data according to the phase offset, and use the new calibration compensation data to complete the phase self-calibration of the RF channel to be calibrated.

[0024] A phased array monolithic integrated circuit has two states: an operating mode and a phase detection mode, and includes a phase detection device, a power division network, a plurality of radio frequency channels, a memory, and a plurality of first single-pole double-throw switches;

[0025] The power division network is a one-to-many power division network, whose input end is connected to the radio frequency common port, and multiple output ends are connected to the first ends of multiple first single-pole double-throw switches through multiple radio frequency channels;

[0026] The second ends of the plurality of first single-pole double-throw switches are connected to the plurality of antenna ports, and the third ends are all connected to the first input end of the phase detection device;

[0027] The second input end of the phase detection device is connected to the radio frequency common port, and the output end is connected to the digital communication interface via the memory;

[0028] When the working mode is started, the second end of the first single-pole double-throw switch is turned on and the third end of the first single-pole double-throw switch is turned off; when the phase detection mode is started, the second end of the first single-pole double-throw switch is turned off and the third end of the first single-pole double-throw switch is turned on.

[0029] Further, the radio frequency channel includes a second single-pole double-throw switch, a third single-pole double-throw switch, a transmitting radio frequency channel, and a receiving radio frequency channel;

[0030] The first end of the second single-pole double-throw switch is a common end, connected to the first radio frequency signal; the second end is connected to the input end of the transmitting radio frequency channel, and the third end is connected to the output end of the receiving radio frequency channel;

[0031] The first end of the third single-pole double-throw switch is a common end, connected to the second radio frequency signal; the second end is connected to the output end of the transmitting radio frequency channel, and the third end is connected to the input end of the receiving radio frequency end;

[0032] The transmitting RF channel is used to perform phase control, amplitude control or signal amplification on the transmitted RF signal;

[0033] The receiving RF channel is used to perform phase control, amplitude control or signal amplification on the received RF signal.

[0034] Furthermore, the RF channel includes a receiving RF channel or a transmitting RF channel, the receiving RF channel is used to perform phase control, amplitude control or signal amplification on a received RF signal, and the transmitting RF channel is used to perform phase control, amplitude control or signal amplification on a transmitted RF signal.

[0035] Due to the adoption of the above technical solution, the present invention has the following advantages:

[0036] 1) The phase detection device and phase self-calibration method of the present invention generate a reference signal by self-mixing, and can realize down-conversion of the radio frequency signal without an additional reference signal, thereby simplifying the frequency synthesizer module and making the system implementation simpler;

[0037] 2) The phase detection device of the present invention uses a simple counter to sample the phase detection result, and the phase detection result is directly output digitally, which can simplify the digital-to-analog conversion and complex digital signal processing;

[0038] 3) The phase detection device of the present invention is simple in design and highly flexible. It can realize the design of schemes with different phase detection accuracy and different detection frequency by only determining the two parameters "M and N";

[0039] 4) The phase detection device of the present invention has high phase detection accuracy and can easily achieve a phase detection accuracy within 1°;

[0040] 5) The phase detection device and the channel to be detected are integrated in the same integrated circuit to achieve phase self-detection within the integrated circuit and match its characteristics with changes in process, temperature and voltage;

[0041] 6) The phased array monolithic integrated circuit using the phase detection device of the present invention can realize channel-level phase self-detection and phase self-calibration functions without adding additional hardware and circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic block diagram of a phase detection device provided in an embodiment;

[0043] Figure 2 A schematic diagram of the change of input and output signals of an N-bit edge trigger in a phase detection device provided in an embodiment over time;

[0044] Figure 3 A schematic block diagram of a radio frequency channel to be detected provided in an embodiment;

[0045] Figure 4 A schematic block diagram of a phased array monolithic integrated circuit structure provided in an embodiment;

[0046] Figure 5 Phase self-calibration flow chart of phased array monolithic integrated circuit provided in the embodiment:

[0047] Reference numerals:

[0048] 100 is a phase detection device, 110 is a first frequency divider, 111 is a second frequency divider, 120 is a first mixer, 121 is a second mixer, 130 is an N-bit edge trigger, 140 is an N-bit counter, 200 is a radio frequency channel, 201 is a second single-pole double-throw switch, 202 is a third single-pole double-throw switch, 210 is a transmitting radio frequency channel, 211 is a first phase control module, 212 is a first amplitude control module, 213 is a first amplification module, 221 is a second phase control module, 222 is a second amplitude control module, 223 is a second amplification module, 220 is a receiving radio frequency channel, 301 is a power division network, 302 is a memory, and 303 is a first single-pole double-throw switch. DETAILED DESCRIPTION

[0049] like Figure 1 As shown, a phase detection device provided in this embodiment includes a phase detection device 100 and a radio frequency channel 200 to be detected. By integrating the phase detection device 100 and the radio frequency channel 200 to be detected in the same integrated circuit, phase self-detection in the channel-level integrated circuit of a multi-channel phased array system is realized, and its characteristics are matched with changes in process, temperature and voltage. The specific structure is as follows:

[0050] The phase detection device 100 includes a first frequency divider 110, a second frequency divider 111, a first frequency mixer 120, a second frequency mixer 121, an N-bit edge trigger 130, and an N-bit counter 140;

[0051] The input end of the first frequency divider 110 is connected to the RF input end, and the output end is connected to the second frequency divider 111 and the N-bit counter 140 respectively; the frequency division ratio of the first frequency divider 110 is M;

[0052] The output end of the second frequency divider 111 is connected to the first input end of the first mixer 120; the frequency division ratio of the second frequency divider 111 is 2 N ;

[0053] The first mixer 120 operates in an up-conversion mode, wherein the frequency terminal (IF) is connected to the second frequency divider 111 as the first input terminal; the local oscillator terminal (LO) is connected to the radio frequency input terminal as the second input terminal; and the radio frequency terminal (RF) is connected to the first input terminal of the second mixer 121 as the output terminal;

[0054] The second mixer 121 works in the down-conversion mode, with its local oscillator terminal (LO) as the first input terminal; the radio frequency terminal (RF) as the second input terminal connected to the input terminal of the detected signal; the intermediate frequency terminal (IF) as the output terminal, connected to the first input terminal of the N-bit edge trigger 130;

[0055] The second input terminal of the N-bit edge trigger 130 is connected to the N-bit counter 140 , and the output terminal is connected to the outside as a phase detection result output terminal.

[0056] According to the following Figure 1 The working principle of the phase detection device 100 of this embodiment is described below:

[0057] During operation, the RF input signal S0 with a frequency of f0 is input from the RF input terminal, and after the frequency division process of the first frequency divider 110, a signal S1 with a frequency of f1=f0 / M is obtained. The signal S1 is divided into two paths: one of which is transmitted to the N-bit counter 140, and the N-bit counter 140 counts the signal arrival cycle of the signal S1, that is, every time the signal S1 passes a cycle, the output signal S6 is incremented by 1. The signal S6 is composed of N-bit parallel signals, and the total number of countable signals is 2. N , the count range is 0 to 2 N -l.

[0058] The other one is transmitted to the second frequency divider 111, and the frequency obtained by the frequency division processing of the second frequency divider 111 is f2=f1 / 2 N =f0 / (M*2 N ) of the signal S2, the signal S2 is transmitted to the first mixer 120, and is mixed with the RF input signal S0 of frequency f0 to obtain the signal S3, the frequency of the signal S3 is f3=f0+f2=(1+1 / (M*2 N The signal S3 is transmitted to the second mixer 121 as the local oscillator signal, and is mixed down with the detected signal S4 with a frequency of f0 to obtain the signal S5. The frequency of the signal S5 is f5=f3-f0=f2=f0 / (M*2 N Since the signal S5 is obtained by down-converting the detected signal S4, the phase of the signal S5 can directly reflect the phase of the detected signal S4. At the same time, the frequency of the signal S5 is lower than that of the detected signal S4 by (M*2 N ) times, phase detection can be performed very easily.

[0059] The output signal S7 of the N-bit edge trigger 130 is determined by the input signal S5 and the signal S6. Figure 2 The signal S6 is output by the N-bit counter 140, so the signal S6 is repeated from 0 to 2 with T0 as the cycle. N -l, where the repetition period T0=2 N *(1 / f1)=1 / f2, Figure 2 The recurring upward sloping solid line shown in FIG. 1 is the signal S6 .

[0060] The frequency of signal S5 is f2, and the period is also T0. Therefore, in each period of T0, signal S5 has one and only one rising edge. When the rising edge of signal S5 is reached, the N-bit edge trigger 130 will lock the current state of input signal S6 and output it as signal S7. Signal S7 is a set of N-bit parallel signals, and its value reflects the time delay tp of the rising edge of signal S5 reaching the trigger. Figure 2 The tp shown in FIG. 1 is the time when the rising edge of signal S5 is reached. The value of signal S6 corresponding to the tp moment in each T0 cycle is the value of output signal S7, as shown in FIG. Figure 2 As shown in FIG. 1 , the value of the signal S7 does not change over time, so the signal S7 can be stably and accurately delivered to the subsequent circuit.

[0061] Based on the above analysis, it can be seen that the phase of the detected signal S4 determines the phase of the signal S5, the phase of the signal S5 determines the delay tp, and the delay tp determines the output result of the signal S7. Therefore, the output signal S7 of the phase detection device 100 can be used to represent the relative phase of the detected input signal.

[0062] The calculation formula of the phase detection resolution of the phase detection device 100 is as follows:

[0063] Phase detection resolution = 360° / 2 N

[0064] According to the above formula, the phase detection resolution of the phase detection device 100 is determined by the frequency division ratio of the second frequency divider 111, which provides a design freedom and design basis for the specific design of the phase detection device 100, that is, the value of the parameter N can be set according to the requirements of the phase detection resolution. In this embodiment, the parameter N is set to 10, corresponding to a phase detection resolution of 0.35°.

[0065] The frequency division ratio M of the first frequency divider 110 determines the frequency f1 of the signal S1, and f1 is used as the clock frequency of the N-bit counter 140. The maximum clock frequency of the N-bit counter 140 is limited by the selected semiconductor process. Therefore, in the specific design of the phase detection device 100, the frequency division ratio M of the first frequency divider 110 needs to be determined according to the selected semiconductor process and the input signal frequency.

[0066] like Figure 4 As shown, a phased array monolithic integrated circuit provided in this embodiment has two states: an operating mode and a phase detection mode, and includes a phase detection device 100, a power division network 301, a plurality of RF channels 200, a memory 302, and a plurality of first single-pole double-throw switches 303.

[0067] The power division network 301 is a one-to-many power division network, whose input end is connected to the RF common port, and multiple output ends are connected to the first ends of multiple first single-pole double-throw switches 303 through multiple RF channels 200;

[0068] The second ends of the plurality of first single-pole double-throw switches 303 are connected to the plurality of antenna ports, and the third ends are all connected to the first input end of the phase detection device 100;

[0069] The phase detection device 100 adopts Figure 1 The structure shown, its second input end is connected to the radio frequency common port, and the output end is connected to the digital communication interface via the memory 302;

[0070] When the working mode is started, the second end of the first single-pole double-throw switch 303 is turned on and the third end of the first single-pole double-throw switch 303 is turned off; when the phase detection mode is started, the second end of the first single-pole double-throw switch 303 is turned off and the third end of the first single-pole double-throw switch 303 is turned on.

[0071] like Figure 3 As shown, the RF channel 200 of this embodiment includes a second single-pole double-throw switch 201, a third single-pole double-throw switch 202, a transmitting RF channel 210, and a receiving RF channel 220. The first end of the second single-pole double-throw switch 201 is connected to the power division network 301 as a common end, the second end is connected to the input end of the transmitting RF channel 210, and the third end is connected to the output end of the receiving RF channel 220; the output end of the transmitting RF channel 210 is connected to the second end of the third single-pole double-throw switch 202; the first end of the third single-pole double-throw switch 202 is connected as a common end Figure 4 A first end of the first single-pole double-throw switch 303 and a third end of the third single-pole double-throw switch 202 are connected to an input end of the receiving radio frequency channel 220 .

[0072] In this embodiment, the transmitting RF channel 210 is composed of a first phase control module 211, a first amplitude control module 212 and a first amplifying module 213 connected in sequence; the input end of the first phase control module 211 is the input end of the transmitting RF channel 210, connected to the second end of the second single-pole double-throw switch 201; the output end of the first amplifying module 213 is the output end of the transmitting RF channel 210, connected to the second end of the third single-pole double-throw switch 202. The first phase control module 211 is used to complete the phase control of the transmitting RF signal, the first amplitude control module 212 is used to complete the amplitude control of the transmitting RF signal, and the first amplifying module 213 is used to amplify the transmitting RF signal. The relative positions of these three modules can be changed.

[0073] The receiving RF channel 220 is composed of a second phase control module 221, a second amplitude control module 222 and a second amplifying module 223; the output end of the second phase control module 221 is the output end of the receiving RF channel 220, connected to the third end of the second single-pole double-throw switch 201; the input end of the second amplifying module 223 is the input end of the receiving RF channel 220, connected to the third end of the third single-pole double-throw switch 202; the second phase control module 221 is used to complete the phase control of the received RF signal, the second amplitude control module 222 is used to complete the amplitude control of the received RF signal, and the second amplifying module 223 is used to amplify the received RF signal. The relative positions of these three modules can also be changed.

[0074] In practical applications, the transmitting RF channel 210 and the receiving RF channel 220 can share a set of phase control modules and amplitude control modules. In this case, there will be only the first amplification module 213 and the second amplification module 223 between the second single-pole double-throw switch 201 and the third single-pole double-throw switch 202, and the phase control module and amplitude control module shared by the transmitting RF channel 210 and the receiving RF channel 220 will be placed before the common end of the second single-pole double-throw switch 201. The RF channel 200 can also be provided with only the transmitting RF channel 210 or only the receiving RF channel 220 according to needs, and in this case, no single-pole double-throw switch is required in the RF channel 200.

[0075] Figure 5 The shown is based on Figure 4 A flowchart of an implementation scheme for performing channel-level phase self-calibration of a phased array system.

[0076] It can be understood that the phased array antenna has been calibrated for each RF channel by external calibration before leaving the factory, and calibration compensation data has been generated and stored in the memory 302 in the phased array antenna device. After the external calibration, the initial phase information of each channel has been detected and stored in the memory 302 in the phased array antenna device through S501 to S504 in the process. This group of initial phase information detected by the phase detection device 100 proposed in the present invention will be used as reference phase information for the phase-level self-calibration of the phased array antenna channel.

Claims

1. A phase detection device, characterized in that: include: A first frequency divider, whose frequency division ratio is M, is used to receive a signal S0 provided by a radio frequency input terminal, and divide the input signal S0 to obtain a signal S1, wherein the frequency of the signal S1 is f1=f0 / M, wherein f0 is the frequency of the input signal S0; The second frequency divider has a division ratio of 2 N , used to receive the signal S1 provided by the first frequency divider, and divide the signal S1 to obtain the signal S2, the frequency of the signal S2 is f2=f1 / 2 N =f0 / (M*2 N ); The first mixer operates in up-conversion mode, receives the signal S2 provided by the second frequency divider and the input signal S0 provided by the RF input terminal, and performs up-conversion on the signal S2 and the signal S0 to obtain a signal S3, wherein the frequency of the signal S3 is f3=f0+f2; The second mixer works in down-conversion mode, receives the detected signal S4 and the signal S3 provided by the first mixer, and down-converts the signal S4 and the signal S3 to obtain the signal S5. The frequency of the detected signal S4 is f0, and it carries the phase information of the RF channel to be detected. The frequency of the signal S5 is f5=f3-f0=f2=f0 / (M*2 N ); The N-bit counter receives the signal S1 provided by the first frequency divider, and counts the incoming cycles of the signal S1, and generates a signal S6 according to the counting result. The signal S6 is composed of an N-bit parallel signal, and the total number of counts is 2 N , the count range is 0 to 2 N -l; The N-bit edge trigger receives the signal S5 provided by the second mixer and the signal S6 provided by the N-bit counter. When the rising edge of the signal S5 is reached, the currently received signal S6 is locked and output as the signal S7, ie, the phase detection result.

2. A phase detection device according to claim 1, characterized in that: The frequency division ratio M of the first frequency divider is set according to the selected semiconductor process and the input signal frequency, and the frequency division ratio 2 of the second frequency divider is set according to the selected semiconductor process and the input signal frequency. N The parameter value N in is set according to the phase detection resolution requirement.

3. A phase self-calibration method, comprising the following steps: Step 1: obtaining a detected signal S4 output by the radio frequency channel to be calibrated, where the signal S4 carries phase information of the radio frequency channel to be detected; Step 2, using a phase detection device as claimed in claim 1 or 2 to perform phase self-detection on the detected signal S4 to obtain a phase detection result; Step 3: Compare the phase result with the initial phase data to obtain the phase offset of the RF channel to be calibrated; Step 4: Calculate new calibration compensation data according to the phase offset, and use the new calibration compensation data to complete the phase self-calibration of the RF channel to be calibrated.

4. A phased array monolithic integrated circuit having two states: an operating mode and a phase detection mode, comprising a power division network, a plurality of radio frequency channels, a memory, a phase detection device, and a plurality of first single-pole double-throw switches; The power division network is a one-to-many power division network, whose input end is connected to the radio frequency common port, and multiple output ends are connected to the first ends of multiple first single-pole double-throw switches through multiple radio frequency channels; The second ends of the plurality of first single-pole double-throw switches are connected to the plurality of antenna ports, and the third ends are all connected to the first input end of the phase detection device; The phase detection device is a phase detection device according to claim 1 or 2, wherein the second input end is connected to the radio frequency common port, and the output end is connected to the digital communication interface via the memory; When the working mode is started, the second end of the first single-pole double-throw switch is turned on, and the third end of the first single-pole double-throw switch is turned off; When the phase detection mode is started, the second end of the first single-pole double-throw switch is turned off, and the third end of the first single-pole double-throw switch is turned on.

5. The phased array monolithic integrated circuit according to claim 4, characterized in that: The radio frequency channel includes a second single-pole double-throw switch, a third single-pole double-throw switch, a transmitting radio frequency channel, and a receiving radio frequency channel; The first end of the second single-pole double-throw switch is a common end, connected to the first radio frequency signal; the second end is connected to the input end of the transmitting radio frequency channel, and the third end is connected to the output end of the receiving radio frequency channel; The first end of the third single-pole double-throw switch is a common end, connected to the second radio frequency signal; the second end is connected to the output end of the transmitting radio frequency channel, and the third end is connected to the input end of the receiving radio frequency end; The transmitting radio frequency channel can perform phase control, amplitude control or signal amplification on the transmitted radio frequency signal; The receiving radio frequency channel can perform phase control, amplitude control or signal amplification on the received radio frequency signal.

6. The phased array monolithic integrated circuit according to claim 4, characterized in that: The RF channel includes a receiving RF channel or a transmitting RF channel. The receiving RF channel can perform phase control, amplitude control or signal amplification on a received RF signal, and the transmitting RF channel can perform phase control, amplitude control or signal amplification on a transmitted RF signal.

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