A static random access memory circuit yield evaluation method

Abstract

The present invention discloses a static random access memory circuit yield assessment method, which belongs to the technical field of power system state estimation. The method includes: obtaining process variables of the static random access memory circuit; inputting the process variables into a trained sparse additive model for performance prediction, and obtaining the performance prediction result of the static random access memory circuit; calculating the yield of the static random access memory based on the performance prediction result; wherein the training method of the sparse additive model includes: generating training samples at the failure boundary of the static random access memory circuit; training the sparse additive model using the training samples, and solving the optimal coefficient of the sparse additive model based on a preset objective function during the training process; and obtaining the trained sparse additive model based on the optimal coefficient of the sparse additive model. The method can improve the evaluation efficiency and reduce the deviation caused by the different distribution of the training samples and the actual test samples while ensuring the accuracy of the yield assessment.

Description

Technical Field

[0001] The invention relates to a static random access memory circuit yield evaluation method, belonging to the technical field of static random access memory circuit yield evaluation. Background Art

[0002] Static Random-Access Memory (SRAM) is a type of random access memory.

[0003] Reliability analysis of memory usually requires running tens of thousands of Monte Carlo (MC) simulations and then performing statistical analysis on the evaluated performance. However, since memories are composed of millions of unit circuits, they are large in scale and each time performance evaluation requires transistor-level simulation, the overall process is extremely time-consuming.

[0004] Existing models for reducing simulation overhead show high accuracy on small-scale circuits. However, when the circuit scale increases and the input process parameters reach tens of thousands of dimensions, the modeling overhead increases significantly and the accuracy is difficult to guarantee, especially the accuracy near the failure domain.

[0005] In the SRAM yield analysis scenario, the accuracy of the surrogate model near the failure domain is extremely high. In order to ensure the accuracy of the surrogate model near the failure domain, the training samples are often not sampled according to the original distribution of the variable (normal distribution). However, due to the different distributions of the training samples and the actual test samples, the training of the surrogate model coefficients will be biased.

[0006] For yield analysis, it is difficult to collect enough samples near the failure domain through the traditional Monte Carlo sampling method to ensure the accuracy of the surrogate model at the failure boundary. If the uniform sampling method is used, although it is relatively easy to collect samples in the failure domain, the surrogate model coefficients are prone to deviations due to insufficient sample density in the nonlinear region. Summary of the invention

[0007] The object of the present invention is to provide a static random access memory circuit yield assessment method, which can improve the assessment efficiency and reduce the deviation caused by the different distribution of training samples and actual test samples while ensuring the yield assessment accuracy.

[0008] In order to achieve the above object, the present invention provides the following technical solutions:

[0009] In a first aspect, the present invention provides a static random access memory circuit yield evaluation method, comprising:

[0010] Obtaining process variables of a static random access memory circuit;

[0011] Inputting the process variables into a trained sparse additive model to perform performance prediction, and obtaining a performance prediction result of a static random access memory circuit;

[0012] Based on the performance prediction result, calculating the yield of the static random access memory;

[0013] Among them, the sparse additive model is constructed based on a group greedy algorithm and is trained using training samples generated at the failure boundary of a static random access memory circuit. During the training process, based on a preset objective function, the optimal coefficients of the sparse additive model are solved to obtain a trained sparse additive model.

[0014] In combination with the first aspect, further, the process variables include process parameters of each MOS tube constituting the static random access memory circuit; wherein the process parameters include the threshold voltage, electron mobility, turn-off voltage, gate oxide layer thickness, channel length and channel width of the MOS tube.

[0015] In combination with the first aspect, further, generating a training sample at a failure boundary of a static random access memory circuit includes:

[0016] Based on the process variables, an initial sample is generated using a Monte Carlo algorithm, and a sampling function is constructed based on the initial sample;

[0017] Scaling the variance of the sampling function, finding the failure boundary of the static random access memory circuit, searching for failure samples at the failure boundary, and fixing the mean and variance of the sampling function;

[0018] Generate training samples based on the fixed mean and variance of the sampling function.

[0019] In combination with the first aspect, further, the sampling function is:

[0020] ;

[0021] in, Represents the process variable vector The sampling function of Indicates A process variable vector, Indicates based on The generated An initial sample, Indicated by The variance matrix composed of the variance corresponding to each process parameter in is: express The corresponding distribution function is Represents the total number of initial samples.

[0022] In combination with the first aspect, further, constructing a sparse additive model based on a group greedy algorithm includes:

[0023] grouping the process variables based on cells of the static random access memory circuit;

[0024] constructing a sparse additive model based on the grouping of the process variables;

[0025] Wherein, the sparse additive model is:

[0026] ;

[0027] in, Represents a sparse additive model based on the process variable vector The output performance prediction results of the static random access memory circuit are represents the central intercept of the sparse additive model, express No. Groups, express The corresponding basis function set is express The corresponding coefficient vector is express Middle Sub-basis functions, express The corresponding coefficient is express The corresponding intercept, express The total number of groups, express Total number of neutron basis functions.

[0028] In combination with the first aspect, further, the objective function is:

[0029] ;

[0030] in, Represents the set of coefficients to be solved for the sparse additive model The objective function is represents the total number of training samples, represents the performance simulation results of the static random access memory circuit, express The L1 norm penalty term of Represents the preset penalty coefficient.

[0031] In combination with the first aspect, further, the calculation formula of the yield of the static random access memory is:

[0032] ;

[0033] in, Represents the yield of static random access memory, represents the first A process variable vector, express The corresponding indicator function is , Represents a sparse additive model based on The output performance prediction results of the static random access memory circuit are represents the failure threshold of the static random access memory circuit, Represents the total number of process variable vectors input into the sparse additive model.

[0034] In a second aspect, the present invention provides a static random access memory circuit yield evaluation device, comprising:

[0035] A data acquisition module, used for acquiring process variables of a static random access memory circuit;

[0036] A performance prediction module, used for inputting the process variables into a trained sparse additive model to perform performance prediction and obtain a performance prediction result of a static random access memory circuit;

[0037] A yield evaluation module, used for calculating the yield of the static random access memory based on the performance prediction result;

[0038] Among them, the sparse additive model is constructed based on a group greedy algorithm and is trained using training samples generated at the failure boundary of a static random access memory circuit. During the training process, based on a preset objective function, the optimal coefficients of the sparse additive model are solved to obtain a trained sparse additive model.

[0039] In a third aspect, the present invention provides a computer system, comprising:

[0040] Storage medium: used to store computer programs;

[0041] Processor: used to execute the computer program to implement the steps of the static random access memory circuit yield evaluation method described in any one of the first aspects.

[0042] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the static random access memory circuit yield evaluation method described in any one of the first aspects.

[0043] Fifthly, the present invention provides a computer program product, comprising a computer program, which, when executed by a processor, implements the steps of the static random access memory circuit yield evaluation method described in any one of the first aspects.

[0044] Compared with the prior art, the present invention has the following beneficial effects:

[0045] The static random access memory circuit yield evaluation method provided by the present invention constructs a sparse additive model based on a grouped greedy algorithm, and uses training samples generated at the failure boundary of the static random access memory circuit to train the sparse additive model, and shifts the center of the sparse additive model to the failure boundary, which can enhance the accuracy of the sparse additive model at the failure boundary and reduce the modeling overhead; during the training process, based on a preset objective function, the optimal coefficient of the sparse additive model is solved to obtain the trained sparse additive model, and then the process variables of the static random access memory circuit are input into the trained sparse additive model for performance prediction, and the performance prediction result of the static random access memory circuit is obtained, and then the yield of the static random access memory is calculated, which can improve the evaluation efficiency while ensuring the yield evaluation accuracy and reduce the deviation caused by the different distribution of training samples and actual test samples. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 is a flow chart of a static random access memory circuit yield evaluation method provided by an embodiment of the present invention;

[0047] Figure 2 It is a schematic diagram of finding the failure boundary of a static random access memory circuit by using the variance of a scaling sampling function provided by an embodiment of the present invention and searching for failure samples at the failure boundary. DETAILED DESCRIPTION

[0048] The technical solution of the present application is further described in detail below in conjunction with specific implementation methods.

[0049] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limitations on the present application. In the absence of conflict, the embodiments of the present application and the technical features in the embodiments may be combined with each other.

[0050] Embodiment 1:

[0051] Figure 1 This is a flow chart of a static random access memory circuit yield evaluation method provided by this embodiment. This flow chart only shows the logical sequence of the method of this embodiment. Different methods can be used without conflict. Figure 1 The steps shown or described are accomplished in the order shown.

[0052] The static random access memory circuit yield evaluation method provided in this embodiment can be applied to a terminal and can be executed by a static random access memory circuit yield evaluation device, which can be implemented by software and / or hardware, and the device can be integrated in a terminal, for example: any tablet computer or computer device with communication function.

[0053] The most classic method for evaluating the yield of static random access memory circuits is to use Monte Carlo simulation to set the process variable vector ,in, , , …, express 1st, 2nd, ..., process parameters, express The total number of process parameters, let for The joint probability density function of is the performance simulation result of the static random access memory circuit, let is the failure threshold of the static random access memory circuit.

[0054] Introducing indicator functions for:

[0055] ;

[0056] The failure rate of the static random access memory circuit is for:

[0057] ;

[0058] Furthermore, the yield of the static random access memory circuit can be calculated through MC.

[0059] However, since the failure rate of SRAM circuits is generally very low, Monte Carlo simulation requires millions of simulations to capture a failure point. At the same time, since the performance of SRAM circuits needs to be evaluated with the help of transistor-level simulations, such as SPICE simulation, each simulation requires a huge computational overhead. By constructing a substitution model to directly establish the mapping relationship between process parameters and SRAM circuit performance, the SPICE simulation process can be replaced, thereby significantly shortening the time for yield evaluation.

[0060] The yield assessment based on the Monte Carlo algorithm requires extremely high accuracy in determining the failure boundary because it is based on the cumulative indicator function. implemented, and the indicator function Whether it is 0 or 1 depends entirely on the prediction result of the SRAM circuit performance and the size of the failure threshold. At the same time, since there are many process parameters that affect the performance of the SRAM circuit, that is, the input dimension of the model is very high, a large number of training samples are required to ensure the accuracy of the entire area.

[0061] Therefore, this embodiment shifts the modeling center to the failure boundary for modeling, and generates training samples at the failure boundary to enhance the accuracy of the model at the failure boundary.

[0062] See also Figure 1 The static random access memory circuit yield evaluation method of this embodiment specifically includes the following steps:

[0063] Step 1: obtaining process variables of a static random access memory circuit;

[0064] In this embodiment, the process variables include process parameters of each MOS transistor constituting the static random access memory circuit; wherein the process parameters include the threshold voltage, electron mobility, turn-off voltage, gate oxide thickness, channel length and channel width of the MOS transistor. In this application, the MOS transistor refers to a metal-oxide semiconductor field effect transistor.

[0065] Step 2: Input the process variables into the trained sparse additive model for performance prediction to obtain the performance prediction result of the static random access memory circuit;

[0066] In this embodiment, the training method of the sparse additive model specifically includes the following steps:

[0067] Step 1: Generate training samples on the failure boundary of the static random access memory circuit;

[0068] In this embodiment, generating training samples at the failure boundary of the static random access memory circuit specifically includes the following steps:

[0069] Step ①: Based on the process variables, the Monte Carlo algorithm is used to generate the initial samples, and based on the initial samples, the sampling function is constructed;

[0070] In this embodiment, the sampling function is:

[0071] ;

[0072] in, Represents the process variable vector The sampling function of Indicates A process variable vector, Indicates based on The generated An initial sample, Indicated by The variance matrix composed of the variance corresponding to each process parameter in is: express The corresponding distribution function is Represents the total number of initial samples.

[0073] Since each process parameter is independent of each other, Only the diagonal has values, and after the distribution of each process parameter is normalized to a normal distribution with a mean of 0 and a variance of 1, the variance of each process parameter is the same, which is 1.

[0074] Step ②: Scale the variance of the sampling function, find the failure boundary of the static random access memory circuit, search for failure samples at the failure boundary, and fix the mean and variance of the sampling function;

[0075] In this embodiment, Figure 2 As shown, by gradually expanding , continuously increasing the probability of collecting failure samples at the failure boundary. Figure 2 middle, , Indicates The first and second process parameters are the horizontal and vertical coordinates, and the sampling function Variance to zoom in or out.

[0076] Step 3: Generate training samples based on the fixed mean and variance of the sampling function.

[0077] In this embodiment, after searching for failure samples on the failure boundary, the mean and variance of the sampling function are fixed, and based on the fixed mean and variance of the sampling function, a training samples.

[0078] Step 2: Use the training samples to train the sparse additive model, and during the training process, solve the optimal coefficients of the sparse additive model based on the preset objective function;

[0079] In this embodiment, the method for constructing a sparse additive model specifically includes the following steps:

[0080] Step ①: grouping process variables based on each unit of the static random access memory circuit;

[0081] In this embodiment, based on each unit of the static random access memory circuit, the process variable Divide into Group:

[0082] ;

[0083] in, , , …, express 1st, 2nd, ..., groups.

[0084] Step ②: Construct a sparse additive model based on the grouping of process variables.

[0085] In this embodiment, the sparse additive model is:

[0086] ;

[0087] in, Represents a sparse additive model based on the process variable vector The output performance prediction results of the static random access memory circuit are represents the central intercept of the sparse additive model, express No. Groups, express The corresponding basis function set is express The corresponding coefficient vector is express Middle Sub-basis functions, express The corresponding coefficient is express The corresponding intercept, express The total number of groups, express Total number of neutron basis functions.

[0088] In a real circuit scenario, most variables have little effect on a certain performance indicator of the circuit, so the input parameters are sparse. At the same time, it is noted that sparsity is not only reflected between groups, but also within groups. Because in addition to most units that are not in the critical path not affecting the circuit performance, most devices in the units located in the critical path have little effect on the circuit performance. In order to make full use of the sparsity between and within groups, this embodiment performs sparse solution by presetting the objective function.

[0089] In this embodiment, the objective function is:

[0090] ;

[0091] in, Represents the set of coefficients to be solved for the sparse additive model The objective function is , , , …, express 1st, 2nd, ..., Groups , , …, The corresponding coefficient vector is represents the total number of training samples, represents the performance simulation results of the static random access memory circuit, express The L1 norm penalty term can reduce most of the coefficients to 0. Represents the preset penalty term coefficient, which is used to control the degree of coefficient sparsity. .

[0092] The objective function can be solved by existing methods such as gradient descent and minimum angle regression to obtain the optimal coefficients of the sparse additive model.

[0093] Step 3: Based on the optimal coefficients of the sparse additive model, obtain the trained sparse additive model.

[0094] Step 3: Based on the performance prediction results, calculate the yield of the static random access memory.

[0095] In this embodiment, the calculation formula of the yield of the static random access memory is:

[0096] ;

[0097] in, Represents the yield of static random access memory, represents the first A process variable vector, express The corresponding indicator function is , Represents a sparse additive model based on The output performance prediction results of the static random access memory circuit are represents the failure threshold of the static random access memory circuit, Represents the total number of process variable vectors input into the sparse additive model.

[0098] The static random access memory circuit yield assessment method provided in the present embodiment constructs a sparse additive model based on a grouped greedy algorithm, and uses training samples generated at the failure boundary of the static random access memory circuit to train the sparse additive model, and shifts the center of the sparse additive model to the failure boundary, which can enhance the accuracy of the sparse additive model at the failure boundary and reduce the modeling overhead; during the training process, based on a preset objective function, the optimal coefficient of the sparse additive model is solved to obtain the trained sparse additive model, and then the process variables of the static random access memory circuit are input into the trained sparse additive model for performance prediction, and the performance prediction result of the static random access memory circuit is obtained, and then the yield of the static random access memory is calculated, which can improve the evaluation efficiency while ensuring the yield evaluation accuracy and reduce the deviation caused by the different distribution of training samples and actual test samples.

[0099] Embodiment 2:

[0100] This embodiment provides a static random access memory circuit yield assessment device, including:

[0101] A data acquisition module, used for acquiring process variables of a static random access memory circuit;

[0102] A performance prediction module, used for inputting process variables into a trained sparse additive model for performance prediction, and obtaining a performance prediction result of a static random access memory circuit;

[0103] A yield evaluation module, used for calculating the yield of the static random access memory based on the performance prediction result;

[0104] Among them, the training methods of sparse additive models include:

[0105] generating training samples at failure boundaries of static random access memory circuits;

[0106] The sparse additive model is trained using the training samples, and during the training process, the optimal coefficients of the sparse additive model are solved based on a preset objective function;

[0107] Based on the optimal coefficients of the sparse additive model, obtain the trained sparse additive model.

[0108] The static random access memory circuit yield evaluation device provided in the embodiment of the present application can execute the static random access memory circuit yield evaluation method provided in Example 1 of the present application, and has functional modules and beneficial effects corresponding to the execution method.

[0109] Embodiment 3:

[0110] This embodiment provides a computer system, including:

[0111] Storage medium: used to store computer programs;

[0112] Processor: used to execute a computer program to implement the steps of the static random access memory circuit yield evaluation method in embodiment 1.

[0113] Embodiment 4:

[0114] This embodiment provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the static random access memory circuit yield evaluation method in Embodiment 1 are implemented.

[0115] Embodiment 5:

[0116] This embodiment provides a computer program product, including a computer program, which implements the steps of the static random access memory circuit yield evaluation method in Embodiment 1 when executed by a processor.

[0117] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0118] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0119] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0120] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0121] The above are only preferred implementations of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A static random access memory circuit yield evaluation method, characterized in that: include: Obtaining process variables of a static random access memory circuit; Inputting the process variables into a trained sparse additive model to perform performance prediction, and obtaining a performance prediction result of a static random access memory circuit; Based on the performance prediction result, calculating the yield of the static random access memory; The sparse additive model is constructed based on a grouped greedy algorithm and is trained using training samples generated at the failure boundary of a static random access memory circuit. During the training process, the optimal coefficients of the sparse additive model are solved based on a preset objective function to obtain a trained sparse additive model. Building a sparse additive model based on a grouped greedy algorithm includes: grouping the process variables based on cells of the static random access memory circuit; constructing a sparse additive model based on the grouping of the process variables; Wherein, the sparse additive model is: ； in, Represents a sparse additive model based on the process variable vector The output performance prediction results of the static random access memory circuit are represents the central intercept of the sparse additive model, express No. Groups, express The corresponding basis function set is express The corresponding coefficient vector is express Middle Sub-basis functions, express The corresponding coefficient is express The corresponding intercept, express The total number of groups, express Total number of neutron basis functions; The objective function is: ； in, Represents the set of coefficients to be solved for the sparse additive model The objective function is represents the total number of training samples, represents the performance simulation results of the static random access memory circuit, express The L1 norm penalty term of Represents the preset penalty coefficient.

2. The static random access memory circuit yield evaluation method according to claim 1, characterized in that: The process variables include process parameters of each MOS tube constituting a static random access memory circuit; wherein the process parameters include a threshold voltage, electron mobility, a turn-off voltage, a gate oxide layer thickness, a channel length and a channel width of the MOS tube.

3. The static random access memory circuit yield evaluation method according to claim 1, characterized in that: Generating training samples at the failure boundary of a static random access memory circuit includes: Based on the process variables, an initial sample is generated using a Monte Carlo algorithm, and a sampling function is constructed based on the initial sample; Scaling the variance of the sampling function, finding the failure boundary of the static random access memory circuit, searching for failure samples at the failure boundary, and fixing the mean and variance of the sampling function; Generate training samples based on the fixed mean and variance of the sampling function.

4. The static random access memory circuit yield evaluation method according to claim 3, characterized in that: The sampling function is: ； in, Represents the process variable vector The sampling function of Indicates A process variable vector, According to The generated An initial sample, Indicated by The variance matrix composed of the variance corresponding to each process parameter in is: express The corresponding distribution function is Represents the total number of initial samples.

5. The static random access memory circuit yield evaluation method according to claim 1, characterized in that: The calculation formula of the yield of the static random access memory is: ； in, Represents the yield of static random access memory, represents the first A process variable vector, express The corresponding indicator function is , Represents a sparse additive model based on The output performance prediction results of the static random access memory circuit are represents the failure threshold of the static random access memory circuit, Represents the total number of process variable vectors input into the sparse additive model.

6. A static random access memory circuit yield evaluation device, characterized in that: include: A data acquisition module, used for acquiring process variables of a static random access memory circuit; A performance prediction module, used for inputting the process variables into a trained sparse additive model to perform performance prediction and obtain a performance prediction result of a static random access memory circuit; A yield evaluation module, used for calculating the yield of the static random access memory based on the performance prediction result; The sparse additive model is constructed based on a grouped greedy algorithm and is trained using training samples generated at the failure boundary of a static random access memory circuit. During the training process, the optimal coefficients of the sparse additive model are solved based on a preset objective function to obtain a trained sparse additive model. Building a sparse additive model based on a grouped greedy algorithm includes: grouping the process variables based on cells of the static random access memory circuit; constructing a sparse additive model based on the grouping of the process variables; Wherein, the sparse additive model is: ； in, Represents a sparse additive model based on the process variable vector The output performance prediction results of the static random access memory circuit are represents the central intercept of the sparse additive model, express No. Groups, express The corresponding basis function set is express The corresponding coefficient vector is express Middle Sub-basis functions, express The corresponding coefficient is express The corresponding intercept, express The total number of groups, express Total number of neutron basis functions; The objective function is: ； in, Represents the set of coefficients to be solved for the sparse additive model The objective function is represents the total number of training samples, represents the performance simulation results of the static random access memory circuit, express The L1 norm penalty term of Represents the preset penalty coefficient.

7. A computer system, characterized in that: include: Storage medium: used to store computer programs; Processor: used to execute the computer program to implement the steps of the static random access memory circuit yield evaluation method according to any one of claims 1 to 5.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the static random access memory circuit yield evaluation method according to any one of claims 1 to 5 are implemented.

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