Chip heat dissipation packaging structure and preparation method of chip heat dissipation packaging structure

Abstract

The present invention provides a chip heat dissipation packaging structure and a preparation method of the chip heat dissipation packaging structure, which relates to the field of chip packaging technology. The chip heat dissipation packaging structure includes a substrate, a packaged chip, a heat conductive material layer and a first heat dissipation cover, wherein the packaged chip is mounted on the substrate; the heat conductive material layer is arranged on the side of the packaged chip away from the substrate; the first heat dissipation cover is arranged on the substrate and covers the outside of the packaged chip, and the first heat dissipation cover is at least partially located on the side of the heat conductive material layer away from the substrate; wherein a plurality of first heat dissipation bumps are arranged on the side of the first heat dissipation cover close to the substrate, and the plurality of first heat dissipation bumps are all connected to the surface of the side of the packaged chip away from the substrate, and the heat conductive material layer is connected to the first heat dissipation cover. Compared with the prior art, the present invention can greatly increase the heat dissipation area by adding the first heat dissipation bump and combining the design of the heat conductive material layer, without expanding the design size of the first heat dissipation cover, and avoiding the problem of warping of the substrate or chip caused by thermal stress.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a chip heat dissipation packaging structure and a method for preparing the chip heat dissipation packaging structure. Background Art

[0002] With the rapid development of the semiconductor industry, the performance improvement of products using FC-BGA packaging in SIP system-level packaging requires the integration of more chips and passive devices to improve its performance, which requires the improvement of its heat dissipation performance. However, its chips and substrates are easily subject to thermal stress, causing the substrate or chip to warp, resulting in internal line breakage or short circuit, resulting in increased leakage current and poor signal integrity.

[0003] Conventional packaging structures use a first heat sink cover to dissipate heat. However, with the improvement of integrated chips and passive devices, the design size of the first heat sink cover will inevitably increase and the number of substrate wiring layers will increase, resulting in parasitic effects and capacitance effects between substrate wiring layers affecting its performance. Summary of the invention

[0004] The purpose of the present invention includes providing a chip heat dissipation packaging structure and a method for preparing the chip heat dissipation packaging structure, which can greatly improve the heat dissipation effect without expanding the design size of the first heat dissipation cover, thereby avoiding the problem of warping of the substrate or chip caused by thermal stress.

[0005] The embodiments of the present invention can be implemented as follows:

[0006] In a first aspect, the present invention provides a chip heat dissipation packaging structure, comprising:

[0007] substrate;

[0008] A packaged chip, wherein the packaged chip is mounted on the substrate and electrically connected to the substrate;

[0009] A heat-conducting material layer, wherein the heat-conducting material layer is arranged on a side of the packaged chip away from the substrate;

[0010] A first heat dissipation cover, which is disposed on the substrate and covers the outside of the packaged chip, and at least part of the first heat dissipation cover is located on a side of the thermal conductive material layer away from the substrate;

[0011] A plurality of first heat dissipation bumps are arranged on a side of the first heat dissipation cover close to the substrate, the plurality of first heat dissipation bumps are all connected to a surface of the packaged chip facing away from the substrate, and the thermal conductive material layer is connected to the first heat dissipation cover.

[0012] In an optional embodiment, the thermal conductive material layer is laminated in an interval shape on a surface of the packaged chip away from the substrate to form a plurality of interval grooves, a plurality of the first heat dissipation bumps are staggered with the thermal conductive material layer and are accommodated in the plurality of interval grooves one by one, and the thermal conductive material layer is laminated to the surface of the first heat dissipation cover.

[0013] In an optional embodiment, the thermally conductive material layer includes a first thermally conductive layer and a second thermally conductive layer, the first thermally conductive layer is arranged in an interval-like manner on a surface of the packaged chip away from the substrate to form a plurality of interval grooves, the plurality of first heat dissipation bumps are staggered with the first thermally conductive layer and are accommodated in the plurality of interval grooves in a one-to-one correspondence, and the second thermally conductive layer covers the first heat dissipation bumps and is connected to the first thermally conductive layer.

[0014] In an optional embodiment, a receiving groove is provided on a side of the first heat dissipation cover facing away from the substrate, the first heat dissipation bump is provided in the receiving groove, and the second heat conductive layer fills the receiving groove and contacts with a side wall of the receiving groove.

[0015] In an optional embodiment, a second heat dissipation cover is further disposed in the accommodating groove, and the second heat dissipation cover covers a surface of the second heat conductive layer on a side away from the substrate and contacts a side wall of the accommodating groove.

[0016] In an optional embodiment, a plurality of second heat dissipation bumps are disposed in the second heat dissipation cover, the positions of the plurality of second heat dissipation bumps correspond one-to-one to the positions of the plurality of first heat dissipation bumps, and each of the second heat dissipation bumps contacts the second heat conductive layer.

[0017] In an optional embodiment, the first heat dissipation cover is further provided with a conducting groove, the conducting groove is provided on at least two sides of the first heat dissipation bump and is spaced apart from the first heat conducting layer, and the second heat conducting layer extends to fill the conducting groove.

[0018] In an optional implementation, the depth of the conducting groove is less than half of the height of the first heat dissipation bump.

[0019] In an optional embodiment, the packaged chip is flip-chip mounted on the substrate, and a filling glue layer is disposed between the packaged chip and the substrate, and the filling glue layer is spaced apart from the first heat dissipation cover.

[0020] In an optional embodiment, the packaged chip is uprightly arranged on the substrate, a receiving groove is arranged on the first heat dissipation cover, the thermal conductive material layer is filled in the receiving groove and covers the first heat dissipation bump, and the thermal conductive material layer is spaced apart from the packaged chip, and a plurality of the first heat dissipation bumps are fixed to a surface of the packaged chip facing away from the substrate through an adhesive layer, and a first grounding pad is also arranged on a side of the packaged chip facing away from the substrate, and one of the first heat dissipation bumps is connected to the first grounding pad.

[0021] In an optional embodiment, a second heat dissipation cover is further provided on the side of the thermally conductive material layer facing away from the substrate, the second heat dissipation cover is arranged in the accommodating groove, and a second heat dissipation bump is arranged in the second heat dissipation cover, and the second heat dissipation bump is in contact with the thermally conductive material layer.

[0022] In an optional embodiment, the chip heat dissipation packaging structure further includes a circuit board, the substrate is arranged on the circuit board, and the first heat dissipation cover is attached to the circuit board and covers the substrate and the packaged chip.

[0023] In an optional embodiment, a grounding hole is provided at the edge of the substrate, a conductive column is provided in the grounding hole, a second grounding pad is provided on the circuit board, one end of the conductive column is connected to the first heat dissipation cover, and the other end is connected to the second grounding pad.

[0024] In an optional embodiment, the diameter of the grounding hole is larger than the diameter of the conductive column, and the grounding hole is filled with a conductive adhesive layer, and the conductive adhesive layer is coated on the conductive column.

[0025] In an optional embodiment, the first heat dissipation cover is in a step shape, and a gap is formed between an edge of a side of the grounding hole away from the circuit board and the first heat dissipation cover.

[0026] In a second aspect, the present invention provides a method for preparing a chip heat dissipation packaging structure, comprising:

[0027] Mounting a packaged chip on a substrate, wherein the packaged chip is electrically connected to the substrate;

[0028] Mounting a first heat dissipation cover on the substrate, wherein the first heat dissipation cover is arranged outside the packaged chip;

[0029] A thermally conductive material layer is provided on the side of the packaged chip away from the substrate, the first heat dissipation cover is at least partially located on the side of the thermally conductive material layer away from the substrate, and a plurality of first heat dissipation bumps are provided on the side of the first heat dissipation cover close to the substrate, the plurality of first heat dissipation bumps are all connected to the surface of the packaged chip facing away from the substrate, and the thermally conductive material layer is connected to the first heat dissipation cover.

[0030] The chip heat dissipation packaging structure and the method for preparing the chip heat dissipation packaging structure provided by the embodiments of the present invention have the following beneficial effects:

[0031] The chip heat dissipation packaging structure and its preparation method provided by the embodiment of the present invention are as follows: a packaged chip is mounted on a substrate, and a heat conductive material layer is arranged on a side of the packaged chip away from the substrate; a first heat dissipation cover is arranged on the substrate and covers the outside of the packaged chip, and the first heat dissipation cover is at least partially located on a side of the heat conductive material layer away from the substrate, wherein a plurality of first heat dissipation bumps are arranged on a side of the first heat dissipation cover close to the substrate, and the plurality of first heat dissipation bumps are all connected to the surface of the packaged chip, and the heat conductive material layer is connected to the first heat dissipation cover. Compared with the prior art, the present invention can greatly increase the heat dissipation area by adding the first heat dissipation bump and combining the design of the heat conductive material layer, and further improve the heat dissipation effect by using the first heat dissipation bump and the heat conductive material layer, and the first heat dissipation bump is bonded to the surface of the packaged chip, without increasing the area of ​​the metal layer on the back of the packaged chip, and further without increasing the design size of the first heat dissipation cover, thereby avoiding the problem of warping of the substrate or chip caused by thermal stress. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 A schematic diagram of a chip heat dissipation packaging structure provided by a first embodiment of the present invention;

[0034] Figures 2 to 6 A process flow chart of a method for preparing a chip heat dissipation packaging structure provided by the first embodiment of the present invention;

[0035] Figure 7 A schematic diagram of a chip heat dissipation packaging structure provided by a second embodiment of the present invention;

[0036] Figure 8 A schematic diagram of a chip heat dissipation packaging structure provided by a third embodiment of the present invention;

[0037] Fig. 9 for Figure 8 A partial enlarged schematic diagram of middle IX;

[0038] Fig.10 A schematic diagram of a chip heat dissipation packaging structure provided by a fourth embodiment of the present invention;

[0039] Fig.11 A schematic diagram of a chip heat dissipation packaging structure provided by a fifth embodiment of the present invention.

[0040] icon:

[0041] 100-chip heat dissipation packaging structure; 110-substrate; 111-grounding hole; 120-packaged chip; 121-filling glue layer; 122-first grounding pad; 130-thermal conductive material layer; 131-first thermal conductive layer; 132-second thermal conductive layer; 140-first heat dissipation cover; 141-accommodating groove; 142-conducting groove; 150-first heat dissipation bump; 151-fixing glue layer; 160-second heat dissipation cover; 170-second heat dissipation bump; 180-circuit board; 181-second grounding pad; 190-conductive column; 191-conductive glue layer. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0043] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0045] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear to indicate an orientation or position relationship, they are based on the orientation or position relationship shown in the accompanying drawings, or are the orientation or position relationship in which the product of the invention is usually placed when used. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0046] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0047] It should be noted that, in the absence of conflict, the features in the embodiments of the present invention may be combined with each other.

[0048] First embodiment

[0049] See also Figure 1 The embodiment of the present invention provides a chip heat dissipation packaging structure 100, which can greatly improve the heat dissipation effect, and at the same time, it is not necessary to expand the design size of the first heat dissipation cover 140, and avoid the problem of warping of the substrate 110 or the chip caused by thermal stress. At the same time, it can reduce thermal shock overflow and improve the reliability and thermal shock performance of the structure.

[0050] The chip heat dissipation packaging structure 100 provided in this embodiment includes a substrate 110, a packaged chip 120, a thermal conductive material layer 130 and a first heat dissipation cover 140. The packaged chip 120 is mounted on the substrate 110 and electrically connected to the substrate 110; the thermal conductive material layer 130 is arranged on a side of the packaged chip 120 away from the substrate 110; the first heat dissipation cover 140 is arranged on the substrate 110 and covers the outside of the packaged chip 120, and the first heat dissipation cover 140 is at least partially located on a side of the thermal conductive material layer 130 away from the substrate 110; wherein, a plurality of first heat dissipation bumps 150 are arranged on a side of the first heat dissipation cover 140 close to the substrate 110, and the plurality of first heat dissipation bumps 150 are all connected to a side surface of the packaged chip 120 away from the substrate 110, and the thermal conductive material layer 130 is connected to the first heat dissipation cover 140.

[0051] It should be noted that the first heat dissipation cover 140 here can be made of ceramic or metal material, preferably metal material, so that the first heat dissipation cover 140 can achieve electromagnetic shielding function.

[0052] In this embodiment, the thermal conductive material layer 130 includes a first thermal conductive layer 131 and a second thermal conductive layer 132. The first thermal conductive layer 131 is arranged in an interval shape on the surface of the package chip 120 away from the substrate 110, and a plurality of interval grooves are formed. A plurality of first heat dissipation bumps 150 are arranged in a staggered manner with the first thermal conductive layer 131, and are accommodated in a plurality of interval grooves one by one. The second thermal conductive layer 132 covers the first heat dissipation bump 150 and is connected to the first thermal conductive layer 131. Specifically, the first thermal conductive layer 131 adopts nano silver / copper and indium materials. For example, the first thermal conductive layer 131 can select an indium material layer, which has a melting point of 183°C. It adopts an interval distribution, which can reduce the material used and reduce the thermal shock overflow of the material. In addition, the second thermal conductive layer 132 is composed of nano silver / copper, which has a high thermal conductivity and can play a heat dissipation role. In some embodiments, the first thermal conductive layer 131 and the second thermal conductive layer 132 can also realize the conductive function.

[0053] It is worth noting that, in actual preparation, the first heat dissipation cover 140 can be mounted first, and then the first heat conduction layer 131 can be formed in the clearance hole of the first heat dissipation cover 140. Of course, the first heat conduction layer 131 can also be directly formed on the back of the packaged chip 120. The first heat conduction layer 131 is arranged at intervals and can form a plurality of spacing grooves, and the first heat dissipation bump 150 can be integrally arranged at the bottom of the first heat dissipation cover 140. When mounting the first heat dissipation cover 140, the first heat dissipation bump 150 can be precisely aligned so that the plurality of first heat dissipation bumps 150 are exactly correspondingly installed in the plurality of spacing grooves, so that the first heat dissipation bump 150 can achieve thermal contact with the first heat conduction layer 131. A clearance hole can be formed between adjacent first heat dissipation bumps 150, and the clearance hole corresponds to the first heat conduction layer 131, so that the first heat conduction layer 131 can be exposed to the first heat dissipation cover 140.

[0054] In this embodiment, a receiving groove 141 is provided on the side of the first heat dissipation cover 140 facing away from the substrate 110, the first heat dissipation bump 150 is provided in the receiving groove 141, and the second heat conductive layer 132 is filled into the receiving groove 141 and contacts the side wall of the receiving groove 141. Specifically, the first heat dissipation bump 150 is integrally provided in the receiving groove 141, and contacts the surface of the packaged chip 120 after penetrating the bottom wall of the receiving groove 141, and the second heat conductive layer 132 can fill the lower half of the receiving groove 141, thereby filling the area between adjacent first heat dissipation bumps 150, and covering the first heat dissipation bumps 150. Among them, the second thermal conductive layer 132 is in contact with the first thermal conductive layer 131 and the first heat dissipation bump 150 at the same time, so the heat of the first thermal conductive layer 131 and the first heat dissipation bump 150 can be gathered to the second thermal conductive layer 132. By setting the second thermal conductive layer 132, on the one hand, the thermal conductivity and heat dissipation effects can be further improved, and on the other hand, the thermal uniformity can be improved to avoid local excessive temperature and affect the heat dissipation efficiency.

[0055] In this embodiment, a second heat dissipation cover 160 is further disposed in the receiving groove 141. The second heat dissipation cover 160 covers a surface of the second heat conductive layer 132 away from the substrate 110 and contacts the side wall of the receiving groove 141. Specifically, the second heat dissipation cover 160 can be made of ceramics. Using ceramics as the top insulating material can avoid static electricity. At the same time, ceramics can improve heat dissipation performance and thermal shock resistance, and have better reliability.

[0056] In this embodiment, a plurality of second heat dissipation bumps 170 are disposed in the second heat dissipation cover 160, and the positions of the plurality of second heat dissipation bumps 170 correspond one-to-one to the positions of the plurality of first heat dissipation bumps 150, and each second heat dissipation bump 170 is in contact with the second heat conductive layer 132. Specifically, the plurality of second heat dissipation bumps 170 are integrally disposed in the second heat dissipation cover 160 and are disposed to protrude upwards. By disposing the plurality of second heat dissipation bumps 170, the heat dissipation area can be greatly increased, thereby further improving the heat dissipation efficiency and heat dissipation effect.

[0057] Furthermore, in other preferred embodiments of the present invention, the plurality of second heat dissipation bumps 170 may also be arranged in a staggered manner with the plurality of first heat dissipation bumps 150, which can also achieve good heat dissipation and heat distribution effects, and make the overall structural strength higher. At the same time, the plurality of second heat dissipation bumps 170 may also protrude downward and be embedded in the second heat conductive layer 132, thereby enhancing the bonding force between the second heat conductive layer and the second heat dissipation layer 160.

[0058] In actual preparation, the second heat dissipation cover 160 and the second heat dissipation protrusion 170 can be prepared in advance, and directly arranged on the surface of the second heat conductive layer 132 after the second heat conductive layer 132 is prepared. It is worth noting that in this embodiment, the second heat dissipation cover 160 is flush with the first heat dissipation cover 140 around the opening of the accommodating groove 141, and the second heat dissipation protrusion 170 can be arranged protruding from the first heat dissipation cover 140, so that the second heat dissipation cover 160 and the second heat dissipation protrusion 170 can form another first heat dissipation cover 140 structure, thereby forming a double-layer first heat dissipation cover 140 structure to further improve the heat dissipation effect.

[0059] In this embodiment, the packaged chip 120 is flip-chip mounted on the substrate 110, and a filling glue layer 121 is disposed between the packaged chip 120 and the substrate 110, and the filling glue layer 121 is spaced apart from the first heat dissipation cover 140. Specifically, micro-bumps are disposed on the front of the packaged chip 120, and connecting pads are disposed on the substrate 110. The micro-bumps are correspondingly welded to the heat dissipation pads, and the filling glue layer 121 can be filled between the packaged chip 120 and the substrate 110, thereby protecting the welding structure at the bottom.

[0060] It is worth noting that in this embodiment, the edge legs of the first heat dissipation cover 140 can be bonded and fixed on the substrate 110 through the adhesive layer, and the edge legs of the first heat dissipation cover 140 can be electrically contacted with the first grounding pad 122 on the substrate 110. The first heat dissipation cover 140 is combined with the first thermal conductive layer 131 to form an electromagnetic shielding structure to achieve a good electromagnetic shielding function. The middle part of the first heat dissipation cover 140 corresponds to the packaged chip 120, and the inner wall of the first heat dissipation cover 140 is filled with adhesive layers 121, so that a cavity can be formed on the inside, and the packaged chip 120 is completely covered therein.

[0061] See also Figures 2 to 6 The embodiment of the present invention further provides a method for preparing a chip heat dissipation packaging structure 100, which is used to prepare the aforementioned chip heat dissipation packaging structure 100. The preparation method comprises the following steps:

[0062] S1: mounting the packaged chip 120 on the substrate 110 .

[0063] See also Figure 2 Specifically, the packaged chip 120 is electrically connected to the substrate 110. During actual preparation, a substrate 110 can be provided online, and then the packaged chip 120 can be mounted using a flip-chip mounting method, and the micro-bumps of the packaged chip 120 are welded and fixed to the connecting pads on the substrate 110 by reflow soldering, and then a filling glue layer 121 is formed at the bottom of the flip-chip welding structure by a glue dispensing process to play a protective role, and finally the glue layer 151 is fixed by baking.

[0064] S2: mounting a first heat dissipation cover 140 on the substrate 110 , wherein the first heat dissipation cover 140 covers the outside of the packaged chip 120 .

[0065] Specifically, the first heat dissipation cover 140 may be mounted on the substrate 110 , and the preparation of the thermal conductive material layer 130 is completed.

[0066] In actual preparation, the first heat dissipation cover 140 can be mounted on the substrate 110 first, and a clearance hole can be formed between the first heat dissipation bumps 150 in the middle of the first heat dissipation cover 140, such as Figure 3 Then, the first heat conducting layer is deposited or glued in the first heat dissipation cover 140, and the first heat conducting layer 131 is formed in the clearance hole, so that the first heat conducting layer 131 can be exposed outside the first heat dissipation cover 140. Figure 4 After the first heat dissipation cover 140 is mounted, a second heat conductive layer 132 is formed in the receiving groove 141 of the first heat dissipation cover 140 by dispensing, coating or vapor deposition process. The second heat conductive layer 132 can simultaneously cover the first heat conductive layer 131 and the first heat dissipation bump 150 and contact the side wall of the receiving groove 141. Figure 5After the second heat-conducting layer 132 is completed, the pre-prepared second heat dissipation cover 160 can be mounted, the second heat dissipation bumps 170 in the second heat dissipation cover 160 protrude upward, and are fixed by a baking process, such as Figure 6 Finally, solder balls are formed on the back of the substrate 110 using a ball planting process, and then cut into individual products using a cutting process to complete the process.

[0067] In this embodiment, a thermal conductive material layer 130 is provided on the side of the packaged chip 120 away from the substrate 110, the first heat dissipation cover 140 is at least partially located on the side of the thermal conductive material layer 130 away from the substrate 110, and a plurality of first heat dissipation bumps 150 are provided on the side of the first heat dissipation cover 140 close to the substrate 110, the plurality of first heat dissipation bumps 150 are all connected to the side surface of the packaged chip 120 facing away from the substrate 110, and the thermal conductive material layer 130 is connected to the first heat dissipation cover 140.

[0068] In summary, the chip heat dissipation packaging structure 100 and the preparation method thereof provided in this embodiment mount the packaged chip 120 on the substrate 110, and set the thermal conductive material layer 130 on the side of the packaged chip 120 away from the substrate 110, set the first heat dissipation cover 140 on the substrate 110, and cover the outside of the packaged chip 120, and the first heat dissipation cover 140 is at least partially located on the side of the thermal conductive material layer 130 away from the substrate 110, wherein the first heat dissipation cover 140 is provided with a plurality of first heat dissipation bumps 150 on the side close to the substrate 110, and the plurality of first heat dissipation bumps 150 are all connected to the surface of the packaged chip 120, and the thermal conductive material layer 130 is connected to the first heat dissipation cover 140. By adding the first heat dissipation bump 150 and combining the design of the thermal conductive material layer 130, the heat dissipation area can be greatly increased, and the first heat dissipation bump 150 and the thermal conductive material layer 130 can be used to further improve the heat dissipation effect. Moreover, the first heat dissipation bump 150 is bonded to the surface of the packaged chip 120, which can reduce the material of the back gold layer, and there is no need to expand the area of ​​the metal layer on the back of the packaged chip 120, and there is no need to expand the design size of the first heat dissipation cover 140, thereby avoiding the problem of warping of the substrate 110 or the chip caused by thermal stress, and avoiding the problem of chip cracking caused by thermal stress. In addition, by combining the first thermal conductive layer 131 and the second thermal conductive layer 132, the heat dissipation effect can be further improved, and the uniformity of thermal conductivity can be improved. By using the second heat dissipation cover 160 and the second heat dissipation bump 170, the heat dissipation area can be increased, thereby improving the heat dissipation effect and heat dissipation efficiency.

[0069] Second embodiment

[0070] See also Figure 7 This embodiment provides a chip heat dissipation packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brief description, parts not mentioned in this embodiment may refer to the corresponding contents in the first embodiment.

[0071] In this embodiment, the thermal conductive material layer 130 is arranged in a spaced-apart manner on the surface of the packaged chip 120 away from the substrate 110, and a plurality of spacer grooves are formed. A plurality of first heat dissipation bumps 150 are staggered with the thermal conductive material layer 130 and are accommodated in the plurality of spacer grooves one by one. The thermal conductive material layer 130 is in contact with the surface of the first heat dissipation cover 140.

[0072] In this embodiment, the thermal conductive material layer 130 is a single-layer structure and is formed on the back of the packaged chip 120 by coating, dispensing or vapor deposition process, while the first heat dissipation cover 140 is a single-layer structure. The first heat dissipation cover 140 is used to directly dissipate heat, which simplifies the process steps and improves the heat dissipation effect.

[0073] Third embodiment

[0074] See also Figure 8 and Fig. 9 The present embodiment provides a chip heat dissipation packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brief description, parts not mentioned in the present embodiment may refer to the corresponding contents in the first embodiment. The difference from the first embodiment is that the present embodiment adds a conducting groove 142.

[0075] In this embodiment, the first heat dissipation cover 140 is further provided with a conducting groove 142, which is provided on at least two sides of the first heat dissipation bump 150 and is spaced apart from the first heat conductive layer 131, and the second heat conductive layer 132 extends to fill the conducting groove 142. Specifically, the conducting groove 142 is provided adjacent to the first heat dissipation bump 150 and is spaced apart from the clearance hole on the first heat dissipation cover 140. Preferably, the conducting groove 142 may be annular and is arranged around the first heat dissipation bump 150. In actual preparation, the second heat conductive layer 132 will extend to fill the conducting groove 142 under the pressing action of the second heat dissipation cover 160, thereby increasing the contact area between the second heat conductive layer 132 and the first heat dissipation cover 140, and further increasing the bonding force.

[0076] Furthermore, the depth of the conducting groove 142 is less than half of the height of the first heat dissipation protrusion 150 . By designing the depth of the conducting groove 142 , the structural strength of the first heat dissipation cover 140 is not affected.

[0077] The chip heat dissipation packaging structure 100 provided in this embodiment, by adding the conducting groove 142, can, on the one hand, enable the second heat conducting layer 132 to extend and fill into the conducting groove 142 under the pressing action of the second heat dissipation cover 160, thereby expanding the extension area of ​​the second heat conducting layer 132 and further improving the heat dissipation performance between the gaps; on the other hand, it can further improve the bonding force between the second heat conducting layer 132 and the first heat dissipation cover 140, thereby avoiding the occurrence of stratification.

[0078] Fourth embodiment

[0079] See also Fig.10 This embodiment provides a chip heat dissipation packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brief description, parts not mentioned in this embodiment may refer to the corresponding contents in the first embodiment. Different from the first embodiment, this embodiment adds an electrostatic shielding function.

[0080] In this embodiment, the packaged chip 120 is uprightly arranged on the substrate 110, a first heat dissipation cover is provided with a receiving groove 141, a thermal conductive material layer 130 is filled in the receiving groove 141 and covers the first heat dissipation bump 150, and the thermal conductive material layer 130 is spaced apart from the packaged chip 120, and a plurality of first heat dissipation bumps 150 are fixed on a surface of the packaged chip 120 facing away from the substrate 110 through an adhesive layer, and a first grounding pad 122 is also provided on a side of the packaged chip 120 facing away from the substrate 110, one of the first heat dissipation bumps 150 is connected to the first grounding pad 122, and the first heat dissipation bump 150 is electrically contacted with the first grounding pad 122, so as to realize electromagnetic shielding function through the first heat dissipation cover 140 and realize electrostatic discharge. Specifically, the thermal conductive material layer 130 is a single-layer structure and is arranged in advance on the first heat dissipation cover 140 together with the first heat dissipation bump 150. The first heat dissipation bump 150 can protrude downward and engage with the front side of the packaged chip 120, so that the thermal conductive material layer 130 on the first heat dissipation cover 140 and the packaged chip 120 can be spaced apart, thereby leaving sufficient wiring space. At this time, the thermal conductive material layer 130 plays a role in enhancing the heat dissipation effect of the first heat dissipation cover 140.

[0081] It should be noted that in this embodiment, the back side of the packaged chip 120 is fixed to the surface of the substrate 110 by an adhesive layer, and a wire bonding pad is provided on the front side of the packaged chip 120, on which a connecting wire is formed by bonding, and the connecting wire is connected to the connecting pad on the substrate 110, thereby realizing an electrical connection between the packaged chip 120 and the substrate 110.

[0082] In this embodiment, a second heat dissipation cover 160 is further provided on the side of the thermal conductive material layer 130 facing away from the substrate 110 . The second heat dissipation cover 160 is arranged in the accommodating groove 141 , and a second heat dissipation bump 170 is arranged in the second heat dissipation cover 160 . The second heat dissipation bump 170 contacts the thermal conductive material layer 130 .

[0083] In this embodiment, a fixed adhesive layer 151 is provided on one side of each first heat dissipation bump 150 close to the substrate 110, and the fixed adhesive layer 151 is bonded to the surface of the packaged chip 120, thereby fixing the plurality of first heat dissipation bumps 150 on the back side of the packaged chip 120. The fixed adhesive layer 151 may be a thermally conductive or electrically conductive material. Of course, in other preferred embodiments, the first heat dissipation bump 150 may be directly held against the surface of the packaged chip 120 without being fixed by an adhesive layer, thereby improving the heat dissipation performance.

[0084] The chip heat dissipation packaging structure 100 provided in this embodiment has a packaged chip 120 that is a front-mounted chip, and a ground pad is designed on the front side of the packaged chip 120 to connect to one of the first heat dissipation bumps 150, thereby achieving electrostatic discharge and connecting to an external ground circuit.

[0085] It should be noted that, in this embodiment, the first heat dissipation cover 140 may be a metal cover, so as to achieve an electromagnetic shielding function and ensure a good heat dissipation effect.

[0086] Fifth embodiment

[0087] See also Fig.11 This embodiment provides a chip heat dissipation packaging structure 100, whose basic structure and principle and the technical effects produced are the same as those of the fourth embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the fourth embodiment.

[0088] In this embodiment, the chip heat dissipation packaging structure 100 includes a substrate 110, a packaged chip 120, a thermal conductive material layer 130 and a first heat dissipation cover 140. The packaged chip 120 is mounted on the substrate 110 and electrically connected to the substrate 110; the thermal conductive material layer 130 is arranged on the side of the packaged chip 120 away from the substrate 110; the first heat dissipation cover 140 is arranged on the substrate 110 and covers the outside of the packaged chip 120, and the first heat dissipation cover 140 is at least partially located on the side of the thermal conductive material layer 130 away from the substrate 110; wherein, a plurality of first heat dissipation bumps 150 are arranged on the side of the first heat dissipation cover 140 close to the substrate 110, and the plurality of first heat dissipation bumps 150 are all connected to the side surface of the packaged chip 120 away from the substrate 110, and the thermal conductive material layer 130 is connected to the first heat dissipation cover 140. The packaged chip 120 is arranged upright on the substrate 110, and a first heat dissipation cover is provided with a receiving groove 141, a heat conductive material layer 130 is filled and arranged in the receiving groove 141, and covers the first heat dissipation bump 150, and the heat conductive material layer 130 and the packaged chip 120 are arranged at intervals, and a plurality of first heat dissipation bumps 150 are fixed on the surface of the packaged chip 120 on the side away from the substrate 110 through a glue layer, and a first grounding pad 122 is also provided on the side of the packaged chip 120 away from the substrate 110, and one of the first heat dissipation bumps 150 is connected to the first grounding pad 122. A second heat dissipation cover 160 is also provided on the side of the heat conductive material layer 130 away from the substrate 110, and the second heat dissipation cover 160 is arranged in the receiving groove 141, and a second heat dissipation bump 170 is arranged in the second heat dissipation cover 160, and the second heat dissipation bump 170 is in contact with the heat conductive material layer 130.

[0089] Furthermore, the chip heat dissipation packaging structure 100 also includes a circuit board 180, the substrate 110 is arranged on the circuit board 180, and the first heat dissipation cover 140 is attached to the circuit board 180 and covers the outside of the substrate 110 and the packaged chip 120. Specifically, the circuit board 180 can be a PCB board, and the first heat dissipation cover 140 is simultaneously covered outside the substrate 110 and the packaged chip 120, and fixed to the circuit board 180 through a glue layer.

[0090] In this embodiment, a grounding hole 111 is provided at the edge of the substrate 110, a conductive column 190 is provided in the grounding hole 111, a second grounding pad 181 is provided on the circuit board 180, one end of the conductive column 190 is connected to the first heat dissipation cover 140, and the other end is connected to the second grounding pad 181. Specifically, the grounding hole 111 is designed at the edge of the substrate 110, and a grounding wiring layer is also provided in the substrate 110, and the grounding wiring layer can extend to the grounding hole 111, so that grounding is achieved through the conductive column 190 in the grounding hole 111. Among them, the conductive column 190 can be a metal column and penetrates both sides of the substrate 110, and both ends of the conductive column 190 can be fixed by welding.

[0091] In this embodiment, the diameter of the grounding hole 111 is larger than the diameter of the conductive column 190, and the grounding hole 111 is filled with a conductive adhesive layer 191, which covers the conductive column 190. Specifically, the conductive adhesive layer 191 can realize the electrical connection between the ground wiring layer and the conductive column 190, thereby realizing the electrostatic shielding function.

[0092] It should be noted that in this embodiment, the second grounding pad 181 is connected to the conductive column 190 on the first heat dissipation cover 140, so that double-layer electromagnetic shielding is achieved by using the conductive column 190 and the first heat dissipation cover 140. In addition, the conductive column 190 can connect the substrate 110 and the second grounding pad 181 on the circuit board 180, thereby shortening the conductive path, thereby reducing impedance, improving its electromagnetic shielding performance, and reducing the design of the wiring layer and grounding pad on the substrate 110. Furthermore, the conductive column 190 can also improve the heat dissipation performance between the bottom of the substrate 110 and the circuit board 180.

[0093] In this embodiment, the first heat dissipation cover 140 is in a stepped shape, and the gap between the edge of the grounding hole 111 away from the circuit board 180 and the first heat dissipation cover 140 is matched. Specifically, the gap width H1 between the surface of the substrate 110 around the grounding hole 111 and the corresponding first heat dissipation cover 140 can be between 1mm-3mm. Due to the existence of the gap, there is a certain buffer gap between the substrate 110 and the first heat dissipation cover 140, which effectively releases the stress caused by thermal shock, can control the warping of the substrate 110, avoid the first heat dissipation cover 140 falling off due to the warping of the substrate 110, and improve the reliability of welding. In addition, through the buffer gap, the air flow can be improved, and the heat dissipation performance of the substrate 110 is also improved.

[0094] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A chip heat dissipation packaging structure, characterized in that: include: substrate; A packaged chip, wherein the packaged chip is mounted on the substrate and electrically connected to the substrate; A heat-conducting material layer, wherein the heat-conducting material layer is arranged on a side of the packaged chip away from the substrate; A first heat dissipation cover, which is disposed on the substrate and covers the outside of the packaged chip, and at least part of the first heat dissipation cover is located on a side of the thermal conductive material layer away from the substrate; Wherein, a plurality of first heat dissipation bumps are arranged on a side of the first heat dissipation cover close to the substrate, the plurality of first heat dissipation bumps are all connected to a surface of the packaged chip facing away from the substrate, and the thermal conductive material layer is connected to the first heat dissipation cover; The thermally conductive material layer includes a first thermally conductive layer and a second thermally conductive layer, the first thermally conductive layer is arranged in an interval shape on a surface of the packaged chip away from the substrate, and a plurality of interval grooves are formed, a plurality of the first heat dissipation bumps are arranged in an offset manner with the first thermally conductive layer, and are accommodated in the plurality of interval grooves one by one, the second thermally conductive layer covers the first heat dissipation bumps, and is connected to the first thermally conductive layer; a receiving groove is arranged on a side of the first heat dissipation cover away from the substrate, the first heat dissipation bump is arranged in the receiving groove, the second thermally conductive layer fills the receiving groove, and contacts with the side wall of the receiving groove.

2. The chip heat dissipation packaging structure according to claim 1, characterized in that: The thermally conductive material layer is arranged in a spaced-apart manner on a surface of the packaged chip away from the substrate, and a plurality of spacer grooves are formed. The plurality of first heat dissipation bumps are staggered with the thermally conductive material layer and are accommodated in the plurality of spacer grooves one by one. The thermally conductive material layer is in contact with the surface of the first heat dissipation cover.

3. The chip heat dissipation packaging structure according to claim 1, characterized in that: A second heat dissipation cover is also arranged in the accommodating groove. The second heat dissipation cover covers a surface of the second heat conducting layer on a side away from the substrate and contacts with a side wall of the accommodating groove.

4. The chip heat dissipation packaging structure according to claim 3, characterized in that: A plurality of second heat dissipation bumps are disposed in the second heat dissipation cover. The positions of the plurality of second heat dissipation bumps correspond to the positions of the plurality of first heat dissipation bumps one by one, and each of the second heat dissipation bumps contacts the second heat conductive layer.

5. The chip heat dissipation packaging structure according to any one of claims 1 to 4, characterized in that: The first heat dissipation cover is also provided with conducting grooves, which are arranged on at least two sides of the first heat dissipation bump and spaced apart from the first heat conducting layer, and the second heat conducting layer extends to fill the conducting grooves.

6. The chip heat dissipation packaging structure according to claim 5, characterized in that: The depth of the conducting groove is less than half of the height of the first heat dissipation bump.

7. The chip heat dissipation packaging structure according to claim 1, characterized in that: The packaged chip is flip-chip mounted on the substrate, and a filling glue layer is disposed between the packaged chip and the substrate, and the filling glue layer is spaced apart from the first heat dissipation cover.

8. The chip heat dissipation packaging structure according to claim 1, characterized in that: The packaged chip is uprightly arranged on the substrate, and a receiving groove is arranged on the first heat dissipation cover. The thermal conductive material layer is filled in the receiving groove and covers the first heat dissipation bump, and the thermal conductive material layer is spaced apart from the packaged chip. A plurality of the first heat dissipation bumps are fixed to a surface of the packaged chip on a side away from the substrate through an adhesive layer. A first grounding pad is also arranged on a side of the packaged chip away from the substrate, and one of the first heat dissipation bumps is connected to the first grounding pad.

9. The chip heat dissipation packaging structure according to claim 8, characterized in that: A second heat dissipation cover is also provided on the side of the thermal conductive material layer facing away from the substrate. The second heat dissipation cover is arranged in the accommodating groove, and a second heat dissipation bump is arranged in the second heat dissipation cover. The second heat dissipation bump is in contact with the thermal conductive material layer.

10. The chip heat dissipation packaging structure according to claim 8 or 9, characterized in that: The chip heat dissipation packaging structure also includes a circuit board, the substrate is arranged on the circuit board, and the first heat dissipation cover is attached to the circuit board and covers the substrate and the packaged chip.

11. The chip heat dissipation packaging structure according to claim 10, characterized in that: A grounding hole is provided at the edge of the substrate, a conductive column is provided in the grounding hole, a second grounding pad is provided on the circuit board, one end of the conductive column is connected to the first heat dissipation cover, and the other end is connected to the second grounding pad.

12. The chip heat dissipation packaging structure according to claim 11, characterized in that: The diameter of the grounding hole is larger than the diameter of the conductive column, and the grounding hole is filled with a conductive adhesive layer, and the conductive adhesive layer covers the conductive column.

13. The chip heat dissipation packaging structure according to claim 11, characterized in that: The first heat dissipation cover is in a step shape, and a gap is fitted between an edge of a side of the grounding hole away from the circuit board and the first heat dissipation cover.

14. A method for preparing a chip heat dissipation packaging structure, used for preparing the chip heat dissipation packaging structure as claimed in claim 1, characterized in that: include: Mounting a packaged chip on a substrate, wherein the packaged chip is electrically connected to the substrate; Mounting a first heat dissipation cover on the substrate, wherein the first heat dissipation cover is arranged outside the packaged chip; A thermally conductive material layer is provided on the side of the packaged chip away from the substrate, the first heat dissipation cover is at least partially located on the side of the thermally conductive material layer away from the substrate, and a plurality of first heat dissipation bumps are provided on the side of the first heat dissipation cover close to the substrate, the plurality of first heat dissipation bumps are all connected to the surface of the packaged chip facing away from the substrate, and the thermally conductive material layer is connected to the first heat dissipation cover.

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