Clock circuit for test equipment and test equipment

Abstract

A clock circuit and a test device for testing equipment, which obtain the amplitude and frequency of an external clock signal and judge whether the amplitude and frequency of the external clock signal meet a first preset condition based on a reference source of an internal clock signal, and output a corresponding switching control signal to a switching switch according to the judgment result. The switching switch automatically switches and connects the internal clock signal and the external clock signal according to the switching control signal, so that the connected external clock signal or the internal clock signal is a usable clock signal, and there is no need to switch repeatedly due to inappropriateness, which greatly reduces the instability of the system clock caused by repeated switching of internal and external clocks and increases the reliability of the test device.

Description

Technical Field

[0001] The present application relates to the field of testing technology, and in particular to a clock circuit of a testing device and a testing device. Background Art

[0002] With the rapid development of the communication field, the stability of the communication system clock has become increasingly important, especially on measurement equipment such as spectrum analyzers, it is even more important to ensure the clock stability of the entire test equipment. In the collaboration of multiple test equipment, it is often necessary to synchronize the clock and synchronize multiple test equipment to the same clock source. Taking the spectrum analyzer as an example, since the spectrum analyzer requires a very high-quality clock, the tuning frequency range of the voltage-controlled crystal oscillator must be small enough, even less than 1ppm (one millionth). Therefore, the spectrum analyzer has certain frequency deviation requirements for the external input clock signal, and the frequency deviation is required to be small enough to meet the phase-locked loop lock. The phase-locked loop itself also has amplitude requirements for the external input clock signal. If the amplitude is too small, the performance will be reduced or even lost, and if the amplitude is too large, the device may be damaged. Therefore, in the spectrum analyzer, there are certain requirements for the amplitude and frequency of the external input clock signal.

[0003] At present, the internal and external clock switching method in the test equipment is: when the device detects that there is an external clock signal input, the clock channel will switch from the internal clock channel to the external clock channel, and the clock synchronization between different test devices will be completed after waiting for the phase-locked loop to lock. If the amplitude or frequency deviation of the external clock signal is too large, causing the phase-locked loop to be unable to lock, it will automatically switch back to the internal clock signal. Since the switching of the phase-locked loop from the internal clock signal to the external clock signal will cause the clock of the device to lose lock once, and the external clock signal cannot be locked due to factors such as frequency and amplitude, the switching of the phase-locked loop from the external clock signal to the internal clock signal will also cause a loss of lock, which undoubtedly increases the instability between the device interconnections. When the external clock signal cannot be locked and switches back to the internal clock signal, after the subsequent external clock signal is adjusted appropriately, the current device does not have a judgment logic to determine whether it can automatically switch to the external clock signal. At this time, it is often necessary to re-plug the synchronization cable, or manually enter the command or click the button to switch, which undoubtedly increases the workload for the interconnection between large-scale multi-test equipment. Summary of the invention

[0004] In view of the above problems, the present application provides a clock circuit of a test device and a test device, which are described in detail below.

[0005] According to the first aspect, an embodiment provides a clock circuit of a test device, comprising: an internal clock signal generating module, an external clock signal input module, a processing module, a switching switch and a phase-locked loop module;

[0006] The internal clock signal generating module is used to generate an internal clock signal;

[0007] The external clock signal input module is used to receive an external clock signal input from the outside;

[0008] The processing module is used to obtain the amplitude and frequency of the internal clock signal and the external clock signal, determine whether the amplitude and frequency of the external clock signal meet a first preset condition based on a reference source of the internal clock signal, and output a corresponding switching control signal according to the determination result;

[0009] The switch has a first end, a second end and a control end, the first end is used to switch between the internal clock signal generating module and the external clock signal input module, the second end is connected to the phase-locked loop module, and the control end is used to receive the switching control signal, and the switching control signal is used to control the first end to switch between the internal clock signal generating module and the external clock signal input module;

[0010] The phase-locked loop module is used to receive an internal clock signal or an external clock signal output by the second end of the switching switch, use the received clock signal as a reference clock signal, and output a first clock signal synchronized with the reference clock signal based on the reference clock signal, wherein the first clock signal is the clock signal of the test device.

[0011] In one embodiment, it further includes: a first splitter;

[0012] The first splitter is used to split the external clock signal into two signals to obtain a first external clock signal and a second external clock signal, wherein the first external clock signal and the second external clock signal are synchronized with the external clock signal, the first external clock signal is output to the processing module, and the second external clock signal is output to the first end of the switching switch.

[0013] In one embodiment, the first splitter includes: a coupler or a power splitter.

[0014] In one embodiment, the processing module includes: a second splitter, a signal amplitude comparison unit, and a processor;

[0015] The second splitter is used to split the first external clock signal into two signals to obtain a third external clock signal and a fourth external clock signal, and the third external clock signal and the fourth external clock signal are synchronized with the external clock signal;

[0016] The signal amplitude comparison unit is used to extract the amplitude of the third external clock signal, and determine whether the amplitude of the extracted third external clock signal is within the amplitude range of a first preset condition, and if it is determined to be within the amplitude range, output a trigger signal to the processor;

[0017] The processor is used to obtain the internal clock signal and the fourth external clock signal, determine the frequency of the fourth external clock signal based on the frequency of the internal clock signal, and judge whether the frequency of the fourth external clock signal is within the frequency range of the first preset condition to obtain a frequency judgment result;

[0018] The processor is further configured to output a corresponding switching control signal according to the frequency determination result and whether the trigger signal is received.

[0019] In one embodiment, the signal amplitude comparison unit includes: a first detector, a first comparator, a second comparator and an AND gate unit;

[0020] The first detector is used to receive the third external clock signal and output a voltage signal corresponding to the amplitude of the third external clock signal;

[0021] The first comparator is used to compare the voltage signal corresponding to the amplitude of the third external clock signal output by the detector with the first reference voltage signal to obtain a first voltage comparison result;

[0022] The second comparator is used to compare the voltage signal corresponding to the amplitude of the third external clock signal output by the detector with the second reference voltage signal to obtain a second voltage comparison result;

[0023] The AND gate unit is used to receive the first voltage comparison result and the second voltage comparison result, and output a trigger signal when the first voltage comparison result and the second voltage comparison result both meet a second preset condition, where the second preset condition is an amplitude range corresponding to the first preset condition.

[0024] In one embodiment, the signal amplitude comparison unit further includes: a digital-to-analog converter; the digital-to-analog converter is used to generate a first reference voltage signal and a second reference voltage signal.

[0025] In one embodiment, the processing module includes: a second splitter, a signal amplitude detection unit, and a processor;

[0026] The second splitter is used to split the first external clock signal into two signals to obtain a third external clock signal and a fourth external clock signal, and the third external clock signal and the fourth external clock signal are synchronized with the external clock signal;

[0027] The signal amplitude detection unit is used to detect the amplitude of the third external clock signal, and output the detected amplitude of the third external clock signal to the processor;

[0028] The processor is used to obtain the internal clock signal and the fourth external clock signal, determine the frequency of the fourth external clock signal based on the frequency of the internal clock signal, and judge whether the frequency of the fourth external clock signal is within the frequency range of the first preset condition to obtain a frequency judgment result;

[0029] The processor is further configured to obtain the amplitude of the third external clock signal, and determine whether the amplitude of the third external clock signal is within the amplitude range of the first preset condition, to obtain an amplitude determination result;

[0030] The processor is further configured to output a corresponding switching control signal according to the frequency determination result and the amplitude determination result.

[0031] In one embodiment, the signal amplitude detection unit includes: a second detector and a first analog-to-digital converter;

[0032] The second detector is used to receive the third external clock signal and output a voltage signal corresponding to the amplitude of the third external clock signal;

[0033] The analog-to-digital converter is used to convert the voltage signal corresponding to the amplitude of the third external clock signal into a digital signal to obtain the amplitude of the third external clock signal.

[0034] Or, in one embodiment, the signal amplitude detection unit includes: a second analog-to-digital converter, the second analog-to-digital converter is used to perform digital-to-analog conversion on the third external clock signal to obtain the amplitude of the third external clock signal;

[0035] Wherein, the conversion rate of the second analog-to-digital converter is greater than the conversion rate of the first analog-to-digital converter.

[0036] In one embodiment, the processing module also includes: a first driver; the first driver is used to amplify the fourth external clock signal and output the amplified fourth external clock signal to the processor so that the processor can recognize and process the fourth external clock signal.

[0037] In one embodiment, it also includes: a third splitter; the third splitter is used to split the internal clock signal into two signals to obtain a first internal clock signal and a second internal clock signal, the first internal clock signal and the second internal clock signal are synchronized with the internal clock signal, the first internal clock signal is output to the switching switch, the second internal clock signal is output to the processor, and the second internal clock signal is used to provide a clock signal for the processor.

[0038] In one embodiment, it also includes: a second driver; the second driver is used to amplify the voltage of the second internal clock signal, and output the amplified second internal clock signal to the processor, so that the processor can recognize and process the second internal clock signal.

[0039] According to the second aspect, an embodiment provides a testing device, comprising:

[0040] A frequency signal acquisition and processing module is used to acquire and analyze frequency signals;

[0041] A clock circuit, wherein the clock circuit is the clock circuit as described in any one of the above embodiments, and is used to provide a clock signal for the test device.

[0042] According to the clock circuit and test equipment of the test equipment in the above-mentioned embodiment, by obtaining the amplitude and frequency of the internal clock signal and the external clock signal, based on the reference source of the internal clock signal, it is judged whether the amplitude and frequency of the external clock signal meet the first preset condition, and according to the judgment result, the corresponding switching control signal is output to the switching switch, and the switching switch automatically switches the internal clock signal and the external clock signal according to the switching control signal, so that the connected external clock signal or internal clock signal is a usable clock signal, and there is no need to repeatedly switch due to inappropriateness, which greatly reduces the instability of the system clock caused by repeated switching of the internal and external clocks, and increases the reliability of the test equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A schematic diagram of the structure of a clock circuit of a test device according to an embodiment of the present application;

[0044] Figure 2 A schematic diagram of the specific structure of a clock circuit of a test device according to an embodiment;

[0045] Figure 3 A schematic diagram of the specific structure of a signal amplitude comparison unit according to an embodiment;

[0046] Figure 4 is a structural schematic diagram of a processing module of an embodiment;

[0047] Figure 5 A schematic diagram of the structure of a signal amplitude detection unit according to an embodiment;

[0048] Figure 6 A schematic diagram of the structure of a signal amplitude detection unit in another embodiment;

[0049] Figure 7 A schematic diagram of the specific structure of a phase-locked loop module according to an embodiment;

[0050] Figure 8 This is a schematic diagram of the structure of the testing equipment according to an embodiment of the present application. DETAILED DESCRIPTION

[0051] The present application is further described in detail below by specific embodiments in conjunction with the accompanying drawings. Wherein similar elements in different embodiments adopt associated similar element numbers. In the following embodiments, many detailed descriptions are intended to enable the present application to be better understood. However, those skilled in the art can easily recognize that some of the features can be omitted in different situations, or can be replaced by other elements, materials, and methods. In some cases, some operations related to the present application are not shown or described in the specification, in order to avoid the core part of the present application being overwhelmed by too much description, and for those skilled in the art, it is not necessary to describe these related operations in detail, and they can fully understand the related operations based on the description in the specification and the general technical knowledge in the art.

[0052] In addition, the features, operations or characteristics described in the specification can be combined in any appropriate manner to form various implementations. At the same time, the steps or actions in the method description can also be interchanged or adjusted in a manner that is obvious to those skilled in the art. Therefore, the various sequences in the specification and the drawings are only for the purpose of clearly describing a certain embodiment and are not meant to be a required sequence, unless otherwise specified that a certain sequence must be followed.

[0053] The serial numbers assigned to the components herein, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in this application, unless otherwise specified, include direct and indirect connections (couplings).

[0054] Please refer to Figure 1, an embodiment of the present application provides a clock circuit of a test device, which can be a spectrum analyzer, a network analyzer and other devices. The clock circuit is used to provide a system clock for the above-mentioned test device, and its clock circuit includes: an internal clock signal generating module 101, an external clock signal input module 102, a processing module 103, a switching switch 104, a phase-locked loop module 105 and a clock signal output terminal 106. Each module is described in detail below.

[0055] The internal clock signal generating module 101 is used to generate an internal clock signal. In some embodiments, the internal clock signal generating module 101 can be a crystal oscillator capable of generating a clock signal, such as a constant temperature crystal oscillator. After the constant temperature crystal oscillator is calibrated, the frequency of the generated clock signal is very accurate and can be used as a clock reference inside the test device.

[0056] The external clock signal input module 102 is used to receive an external clock signal input from outside, wherein the external clock signal is a clock signal generated by other devices (not the test device), and the other devices may be other test devices connected to the test device, or may be devices independent of the interconnected multiple test devices.

[0057] The input end of the processing module 103 is connected to the output end of the external clock signal input module 102, and the output end of the processing module 103 is connected to the control end of the switching switch 104. The processing module 103 is used to obtain the amplitude and frequency of the internal clock signal and the external clock signal, and based on the reference source of the internal clock signal, determine whether the amplitude and frequency of the external clock signal meet the first preset condition, and output the corresponding switching control signal to the control end of the switching switch 104 according to the judgment result. The first preset condition includes a corresponding amplitude range and frequency range. If the amplitude of the external clock signal is within the amplitude range of the first preset condition, and the frequency of the external clock signal is within the frequency range of the first preset condition, the first preset condition is met, otherwise the first preset condition is not met.

[0058] The switching switch 104 has a first end, a second end and a control end. The first end of the switching switch 104 switches between the internal clock signal generating module 101 and the external clock signal input module 102. The second end of the switching switch 104 is connected to the phase-locked loop module 105. The control end of the switching switch 104 is connected to the output end of the processing module 103. The control end of the switching switch 104 is used to receive a switching control signal output by the processing module 103. The switching control signal is used to control the first end to switch between the internal clock signal generating module and the external clock signal input module.

[0059] In some embodiments, the first end of the switching switch 104 is connected to the internal clock signal generating module 101 in an initial state, that is, in the initial state, the internal clock signal generated by the internal clock signal generating module 101 is output to the phase-locked loop module 105 for phase-locked processing through the switching switch 104; when the external clock signal output by the external clock signal input module 102 is received, and the amplitude and frequency of the received external clock signal meet the first preset condition, the switching control signal output by the processing module 103 controls the switching switch 104 to connect its first end with the external clock signal input module 102, and outputs the external clock signal to the phase-locked loop module 105 for phase-locked processing through the switching switch 104; if the external clock signal output by the external clock signal input module 102 is received, but the amplitude and frequency of the received external clock signal do not meet the first preset condition, the switching switch 104 does not perform the switching action, and remains in the initial state, with the first end of the switching switch 104 connected to the internal clock signal generating module 101.

[0060] The input end of the phase-locked loop module 105 is connected to the second end of the switch 104. The phase-locked loop module 105 is used to receive the internal clock signal or the external clock signal output by the second end of the switch 104, take the received clock signal as the reference clock signal, and output the first clock signal synchronized with the reference clock signal to the clock signal output end 106 according to the reference clock signal. The first clock signal is the clock signal of the test device. The synchronization of the first clock signal and the reference clock signal may be the same frequency, or the frequency of the first clock signal may be N times the frequency of the reference clock signal. The value of N is determined by the frequency divider in the phase-locked loop module 105.

[0061] The clock signal output terminal 106 outputs the first clock signal to each module of the test device to provide a clock signal for the test device.

[0062] Therefore, in the clock circuit of the test equipment of the above-mentioned embodiment of the present application, the processing module 103 obtains the amplitude and frequency of the internal clock signal and the external clock signal, and based on the reference source of the internal clock signal, determines whether the amplitude and frequency of the external clock signal meet the first preset condition, and outputs the corresponding switching control signal to the switching switch 104 according to the judgment result. The switching switch 104 automatically switches the internal clock signal and the external clock signal according to the switching control signal, so that the connected external clock signal or the internal clock signal are both usable clock signals, and there is no need to switch repeatedly due to inappropriateness, which greatly reduces the instability of the system clock caused by repeated switching of the internal and external clocks, and increases the reliability of the test equipment.

[0063] Please refer to Figure 2, an embodiment of a clock circuit of a test device is provided below to describe the above modules in detail.

[0064] In some embodiments, the clock circuit of the test device provided in the embodiment of the present application also includes: a first splitter 107, the input end of the first splitter 107 is connected to the external clock signal input module 102, the first splitter 107 is used to divide the external clock signal received by the external clock signal input module 102 into two signals to obtain a first external clock signal and a second external clock signal, and the first splitter 107 has two output ends, one output end is used to output the first external clock signal to the processing module 103 to provide the processing module 103 with a signal to be tested, and the other output end is used to output the second external clock signal to the first end of the switching switch 104. Among them, the first external clock signal and the second external clock signal are synchronized with the external clock signal, for example, they can be signals with the same frequency, and similar descriptions have been made above, which will not be repeated here. In one embodiment, the first splitter 107 can be a coupler or a power divider, and the amplitudes of the first external clock signal and the second external clock signal can be the same or different.

[0065] In some embodiments, the processing module 103 includes: a second splitter 1031, a signal amplitude comparison unit 1032 and a processor 1033, wherein:

[0066] The input end of the second splitter 1031 is connected to the output end of the first splitter 107 for outputting the first external clock signal. The second splitter 1031 is used to split the first external clock signal into two signals to obtain a third external clock signal and a fourth external clock signal. The second splitter 1031 has two output ends, one output end is used to output the third external clock signal to the signal amplitude comparison unit 1032, and the other output end is used to output the fourth external clock signal to the processor 1033. The third external clock and the fourth external clock signal have the same frequency as the external clock signal. In one embodiment, the second splitter 1031 can be a coupler or a power divider, and the amplitudes of the third external clock signal and the fourth external clock signal can be the same or different.

[0067] The signal amplitude comparison unit 1032 is used to extract the amplitude of the third external clock signal and determine whether the amplitude of the extracted third external clock signal is within the amplitude range of the first preset condition. If it is determined to be within the amplitude range, a trigger signal is output to the processor 1033. The signal amplitude comparison unit 1032 can be implemented in a software method or in a hardware circuit. This embodiment provides an implementation method in a hardware circuit. Please refer to Figure 3, the signal amplitude comparison unit 1032 includes: a first detector 201, a first comparator 202, a second comparator 203, and an AND gate unit 204. The first detector 201 is connected to receive a third external clock signal and outputs a voltage signal corresponding to the amplitude of the third external clock signal. The input terminals of the first comparator 202 and the second comparator 203 are both connected to the output terminal of the first detector 201. The first comparator 202 is used to compare the voltage signal corresponding to the amplitude of the third external clock signal output by the first detector 201 with a first reference voltage signal to obtain a first voltage comparison result. The second comparator 203 is used to compare the voltage signal corresponding to the amplitude of the third external clock signal output by the first detector 201 with a second reference voltage signal to obtain a second voltage comparison result. The AND gate unit 204 is used to receive the first voltage comparison result and the second voltage comparison result, and output a trigger signal when both the first voltage comparison result and the second voltage comparison result meet a second preset condition. In some embodiments, the second preset condition is an amplitude range corresponding to the first preset condition. In one embodiment, assuming that the voltage of the first reference voltage signal is Vref1, representing the upper threshold of the voltage amplitude, the voltage of the second reference voltage signal is Vref2, representing the lower threshold of the voltage amplitude, and the voltage of the voltage signal corresponding to the amplitude of the third external clock signal output by the first detector 201 is V, then the second preset condition is: when the first voltage comparison result is V < Vref1 and the second voltage comparison result is V > Vref2, both the first comparator 202 and the second comparator 203 output a high level, and then trigger the AND gate unit 204 to output a high level, that is, output a trigger signal.

[0068] In other embodiments, the signal amplitude comparison unit 1032 further includes: a digital-to-analog converter 205. The first reference voltage signal and the second reference voltage signal are generated and output by the digital-to-analog converter 205. In one embodiment, the first detector 201, the first comparator 202, the second comparator 203, the AND gate unit, and the digital-to-analog converter 205 can all be implemented by existing chips, or can be implemented by building circuit devices. This embodiment does not limit this.

[0069] It should be noted that the amplitude of the third external clock signal used for comparison in the signal amplitude comparison unit 1032 may have a known multiple attenuation after passing through the first splitter 107 and the second splitter 1031. Therefore, when setting the first reference voltage signal and the second reference voltage signal, it is necessary to consider the attenuation multiple of the amplitude for corresponding setting.

[0070] The processor 1033 is used to obtain the internal clock signal and the fourth external clock signal, and use the frequency of the internal clock signal as a reference source. Based on the reference source, that is, based on the frequency of the internal clock signal, the processor 1033 can count the frequency of the fourth external clock signal to obtain the frequency of the fourth external clock signal, and determine whether the frequency of the fourth external clock signal is within the frequency range of the first preset condition to obtain a frequency judgment result; in addition, the processor 1033 is also used to output a corresponding switching control signal according to the frequency judgment result and whether a trigger signal is received. When the frequency judgment result is that the frequency of the fourth external clock signal is within the frequency range of the first preset condition, and the trigger signal output by the signal amplitude comparison unit 1032 is received, the processor 1033 outputs a switching control signal to control the switching switch 104 to connect its first end to the external clock signal input module 102, otherwise, the switching switch 104 is kept in the initial state, that is, the first end of the switching switch 104 is connected to the internal clock signal generation module 101. In one embodiment, the processor 1033 is a processor of the test device, which can be a CPU or an FPGA.

[0071] In one embodiment, the processing module 103 also includes a first driver 1034, which is connected between an output end of the second splitter 1031 for outputting a fourth external clock signal and the processor 1033; the first driver 1034 is used to amplify the voltage of the fourth external clock signal and output the amplified fourth external clock signal to the processor 1033.

[0072] The amplitude and frequency of the external clock signal are detected by the processing module 103, and a switching control signal is output to the switching switch 104 based on the detection result. The switching switch 104 controls its first end to switch between the internal clock signal generating module 101 and the external clock signal input module 102 based on the switching control signal, so that the switching switch 104 outputs the internal clock signal or the external clock signal to the phase-locked loop module 105.

[0073] Please refer to Figure 4 In some other embodiments, the processing module 103 can determine the amplitude and frequency of the external clock signal in the processor 1033, and the processing module 103 includes: a second splitter 1031, a signal amplitude detection unit 1035 and a processor 1033. The second splitter 1031 splits the first external clock signal output by the first splitter 107 into two signals to obtain a third external clock signal and a fourth external clock signal. The third external clock and the fourth external clock signal are synchronized with the external clock signal, wherein the third external clock and the fourth external clock signal may have the same frequency as the external clock signal.

[0074] The signal amplitude detection unit 1035 is used to detect the amplitude of a third external clock signal output by the second splitter 1031, and output the detected amplitude of the third external clock signal to the processor 1033; the processor 1033 is used to obtain a fourth external clock signal output by the second splitter 1031, determine the frequency of the fourth external clock signal, and determine whether the frequency of the fourth external clock signal is within the frequency range of the first preset condition, and obtain a frequency judgment result.

[0075] The processor 1033 is also used to obtain the amplitude of the third external clock signal output by the signal amplitude detection unit 1035, and determine whether the amplitude of the third external clock signal is within the amplitude range of the first preset condition, and obtain an amplitude judgment result; the processor 1033 is also used to output a corresponding switching control signal according to the above-obtained frequency judgment result and amplitude judgment result. That is, when the frequency judgment result is that the detected frequency is within the frequency range of the first preset condition, and when the amplitude judgment result is that the detected amplitude is within the amplitude range of the first preset condition, the switching control signal output by the processor 1033 is used to control the first end of the switching switch 104 to switch to connect with the external clock signal input module 102; otherwise, the first end of the switching switch 104 is kept connected to the internal clock signal generating module 101 in the initial state.

[0076] Please refer to Figure 5 In some embodiments, the signal amplitude detection unit 1035 includes a second detector 301 and a first analog-to-digital converter 302. The input end of the second detector 301 is connected to an output end of the second splitter 1031, and is used to receive a third external clock signal output by the second splitter 1031, and output a voltage signal corresponding to the amplitude of the third external clock signal; the input end of the first analog-to-digital converter 302 is connected to the output end of the second detector 301, and is used to convert the voltage signal corresponding to the amplitude of the third external clock signal output by the second detector 301 into a digital signal, obtain the amplitude of the third external clock signal, and output the detected amplitude of the third external clock signal to the processor 1033.

[0077] Please refer to Figure 6In some other embodiments, the third external clock signal may be converted into a voltage signal corresponding to its amplitude without the need for the second detector 301, that is, the amplitude of the third external clock signal may be directly detected, and the signal amplitude detection unit 1035 includes: a second analog-to-digital converter 401, the input end of the second analog-to-digital converter 401 is connected to an output end of the second splitter 1031, which is used to receive a third external clock signal output by the second splitter 1031, and directly output the amplitude of the third external clock signal to the processor 1033, wherein the conversion rate of the second analog-to-digital converter 40 is greater than the conversion rate of the first analog-to-digital converter 302, for example, the second analog-to-digital converter 40 adopts a high-speed analog-to-digital converter; the first analog-to-digital converter 302 adopts a low-speed analog-to-digital converter, specifically, the models of the low-speed analog-to-digital converter include AD7170, AD7171 and AD7478, etc., and the models of the high-speed analog-to-digital converter include AD9235, AD9236 and LTC2250, etc.

[0078] The above is a specific description of some embodiments of the processing module 103. It should be noted that the processing module 103 is not limited to the methods listed in the above embodiments, and can also be other structures that can achieve its functions, which will not be described one by one in this embodiment.

[0079] The phase-locked loop module 105 can be a phase-locked loop circuit inside the test equipment, please refer to Figure 7In some embodiments, the phase-locked loop module 105 may include: a phase detector 1051, a loop filter 1052, a voltage-controlled crystal oscillator 1053, a fourth splitter 1054 and a frequency divider 1055, wherein a first input end of the phase detector 1051 is connected to a second end of the switch 104, an output end of the phase detector 1051 is connected to an input end of the loop filter 1052, an output end of the loop filter 1052 is connected to an input end of the voltage-controlled crystal oscillator 1053, an output end of the voltage-controlled crystal oscillator 1053 is connected to an input end of the fourth splitter 1054, an output end of the fourth splitter 1054 is connected to a clock signal output end 106, another output end of the fourth splitter 1054 is connected to an input end of the frequency divider 1055, and an output end of the frequency divider 1055 is connected to a second input end of the phase detector 1051; the phase detector 1051 is used to The phases of the two clock signals input from the first input terminal and the second input terminal are compared, and a voltage signal corresponding to the phase difference is output. The loop filter 1052 is used to perform low-pass filtering on the voltage signal corresponding to the phase difference, and output a DC voltage signal. The voltage-controlled crystal oscillator 1053 is a crystal oscillator with adjustable frequency according to the input voltage. The frequency is adjusted by the DC voltage signal output by the loop filter 1052, and a clock signal of corresponding frequency is output. The fourth splitter 1054 divides the clock signal output by the voltage-controlled crystal oscillator 1053 into two paths, one path is output as the first clock signal to the clock signal output terminal 106, and the other path is output as the feedback signal to the input terminal of the frequency divider 1055. The frequency divider 1055 is used to reduce the frequency of the feedback signal by equal multiples, and the output terminal of the frequency divider 1055 outputs the divided feedback signal to the second input terminal of the phase detector 1051.

[0080] In some embodiments, the clock circuit of the test equipment also includes: a third splitter 108, the output end of the internal clock signal generating module 101 is connected to the input end of the third splitter 108, the third splitter 108 has two output ends, the third splitter 108 is used to divide the internal clock signal into two signals to obtain a first internal clock signal and a second internal clock signal, one output end of the third splitter 108 is used to output the first internal clock signal to the first end of the switching switch 104, and the other output end is used to output the second internal clock signal to the processor 1033 as the clock signal of the processor 1033, and the second internal clock signal needs to be voltage amplified by the second driver 109 before being output to the processor 1033, wherein the first internal clock signal, the second internal clock signal and the internal clock signal have the same frequency.

[0081] In the above embodiment, the first splitter 107, the second splitter 1031, the third splitter 108 and the fourth splitter 1054 may be couplers or power splitters, which is not specifically limited in this embodiment.

[0082] The above are some explanations of the clock circuit of the test device provided in the embodiment of the present application. Through the above clock circuit, when the test device is connected to an external clock signal, the amplitude and frequency of the external clock signal are first detected. If the detection result meets the first preset condition, the external clock signal is switched to the clock reference signal of the test device. If the detection result does not meet the first preset condition, the internal clock signal is maintained as the clock reference signal of the test device. There is no need for repeated switching, which greatly reduces the workload.

[0083] Please refer to Figure 8 The embodiment of the present application also provides a test device, wherein the test device can be a frequency analyzer, a network analyzer or other frequency-related analysis device. The test device includes a frequency signal acquisition and processing module 501 and a clock circuit 502, wherein the frequency signal acquisition and processing module 501 is used to perform frequency detection and processing on the signal to be tested so as to perform relevant frequency analysis on the signal to be tested, and the clock circuit 502 is used to provide a clock signal for the test device. It should be noted that the specific implementation of the clock circuit 502 has been referred to the description of the above embodiment and will not be repeated here.

[0084] The above specific examples are used to illustrate the present application, which is only used to help understand the present application and is not intended to limit the present application. For technicians in the technical field to which the present application belongs, they can also make some simple deductions, deformations or substitutions based on the ideas of the present application.

Claims

1. A clock circuit of a test device, characterized in that: include: An internal clock signal generating module, an external clock signal input module, a processing module, a switching switch, a phase-locked loop module and a first splitter; The internal clock signal generating module is used to generate an internal clock signal; The external clock signal input module is used to receive an external clock signal input from the outside; The first splitter is used to split the external clock signal into two signals to obtain a first external clock signal and a second external clock signal, wherein the first external clock signal and the second external clock signal are synchronized with the external clock signal, the first external clock signal is output to the processing module, and the second external clock signal is output to the first end of the switch; The processing module includes a second splitter; the second splitter is used to split the first external clock signal into two signals to obtain a third external clock signal and a fourth external clock signal, and the third external clock and the fourth external clock signal are synchronized with the external clock signal; The processing module is used to obtain the amplitude and frequency of the internal clock signal, the third external clock signal and the fourth external clock signal, and determine whether the amplitude and frequency of the third external clock signal and the fourth external clock signal meet a first preset condition based on a reference source of the internal clock signal, and output a corresponding switching control signal according to the determination result; The switch has a first end, a second end and a control end, the first end is used to switch between the internal clock signal generating module and the external clock signal input module, the second end is connected to the phase-locked loop module, and the control end is used to receive the switching control signal, and the switching control signal is used to control the first end to switch between the internal clock signal generating module and the external clock signal input module; The phase-locked loop module is used to receive an internal clock signal or an external clock signal output by the second end of the switching switch, use the received clock signal as a reference clock signal, and output a first clock signal synchronized with the reference clock signal based on the reference clock signal, wherein the first clock signal is the clock signal of the test device.

2. The clock circuit of the test equipment as claimed in claim 1, characterized in that: The first splitter includes: a coupler or a power splitter.

3. The clock circuit of the test equipment as claimed in claim 1, characterized in that: The processing module also includes a signal amplitude comparison unit and a processor; The signal amplitude comparison unit is used to extract the amplitude of the third external clock signal, and determine whether the amplitude of the extracted third external clock signal is within the amplitude range of a first preset condition, and if it is determined to be within the amplitude range, output a trigger signal to the processor; The processor is used to obtain the internal clock signal and the fourth external clock signal, determine the frequency of the fourth external clock signal based on the frequency of the internal clock signal, and judge whether the frequency of the fourth external clock signal is within the frequency range of the first preset condition to obtain a frequency judgment result; The processor is further configured to output a corresponding switching control signal according to the frequency determination result and whether the trigger signal is received.

4. The clock circuit of the test equipment as claimed in claim 3, characterized in that: The signal amplitude comparison unit comprises: a first detector, a first comparator, a second comparator and an AND gate unit; The first detector is used to receive the third external clock signal and output a voltage signal corresponding to the amplitude of the third external clock signal; The first comparator is used to compare the voltage signal corresponding to the amplitude of the third external clock signal output by the first detector with the first reference voltage signal to obtain a first voltage comparison result; The second comparator is used to compare the voltage signal corresponding to the amplitude of the third external clock signal output by the detector with the second reference voltage signal to obtain a second voltage comparison result; The AND gate unit is used to receive the first voltage comparison result and the second voltage comparison result, and output a trigger signal when the first voltage comparison result and the second voltage comparison result both meet a second preset condition, where the second preset condition is an amplitude range corresponding to the first preset condition.

5. The clock circuit of the test equipment as claimed in claim 4, characterized in that: The signal amplitude comparison unit further includes: a digital-to-analog converter; the digital-to-analog converter is used to generate a first reference voltage signal and a second reference voltage signal.

6. The clock circuit of the test equipment as claimed in claim 1, characterized in that: The processing module also includes a signal amplitude detection unit and a processor; The signal amplitude detection unit is used to detect the amplitude of the third external clock signal, and output the detected amplitude of the third external clock signal to the processor; The processor is used to obtain the internal clock signal and the fourth external clock signal, determine the frequency of the fourth external clock signal based on the frequency of the internal clock signal, and judge whether the frequency of the fourth external clock signal is within the frequency range of the first preset condition to obtain a frequency judgment result; The processor is further configured to obtain the amplitude of the third external clock signal, and determine whether the amplitude of the third external clock signal is within the amplitude range of the first preset condition, to obtain an amplitude determination result; The processor is further configured to output a corresponding switching control signal according to the frequency determination result and the amplitude determination result.

7. The clock circuit of the test equipment as claimed in claim 6, characterized in that: The signal amplitude detection unit includes: a second detector and a first analog-to-digital converter; The second detector is used to receive the third external clock signal and output a voltage signal corresponding to the amplitude of the third external clock signal; The analog-to-digital converter is used to convert the voltage signal corresponding to the amplitude of the third external clock signal into a digital signal to obtain the amplitude of the third external clock signal; Or, the signal amplitude detection unit includes: a second analog-to-digital converter, the second analog-to-digital converter is used to perform analog-to-digital conversion on the third external clock signal to obtain the amplitude of the third external clock signal; Wherein, the conversion rate of the second analog-to-digital converter is greater than the conversion rate of the first analog-to-digital converter.

8. The clock circuit of the test equipment according to claim 3 or 6, characterized in that: The processing module also includes: a first driver; the first driver is used to amplify the fourth external clock signal and output the amplified fourth external clock signal to the processor, so that the processor can identify and process the fourth external clock signal.

9. The clock circuit of the test equipment according to claim 3 or 6, characterized in that: Also includes: The third splitter; The third splitter is used to divide the internal clock signal into two signals to obtain a first internal clock signal and a second internal clock signal. The first internal clock signal and the second internal clock signal are synchronized with the internal clock signal. The first internal clock signal is output to the switching switch, and the second internal clock signal is output to the processor. The second internal clock signal is used to provide a clock signal for the processor.

10. The clock circuit of the test equipment according to claim 9, characterized in that: Also includes: Second drive; The second driver is used to amplify the second internal clock signal and output the amplified second internal clock signal to the processor, so that the processor can identify and process the second internal clock signal.

11. A testing device, characterized in that: include: A frequency signal acquisition and processing module is used to acquire and analyze frequency signals; A clock circuit, wherein the clock circuit is the clock circuit as claimed in any one of claims 1 to 10, and is used to provide a clock signal for the test device.

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