A PSRAM control device and chip

Abstract

The present invention provides a PSRAM control device and chip, comprising: a plurality of buses for respectively inputting data streams; a plurality of protocol analysis modules, which are equal in number to the buses and connected one-to-one, and are respectively used to perform protocol analysis on the corresponding data streams; an arbitrator, which is connected to each of the protocol analysis modules and is used to determine the priority of the plurality of data streams; a plurality of PSRAM particles; and a PSRAM timing generation module, which is connected to the arbitrator and each of the PSRAM particles and is used to select one of the plurality of PSRAM particles or select at least two of the plurality of PSRAM particles for control based on a control signal and output a corresponding PSRAM timing for the selected PSRAM particle based on the data stream output by the arbitrator.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and in particular to a PSRAM control device and a PSRAM control chip. Background Art

[0002] At present, with the rapid development of Internet of Things (IoT) technology, the requirements for bandwidth performance and low power consumption are getting higher and higher. In all scenarios with image and video processing, such as cameras and monitors, the system's requirements for PSRAM bandwidth are different due to differences in camera resolution. Therefore, it is very important to flexibly control the number of PSRAMs. Usually, the amount of data transmitted in the IoT mode is very small, and single PSRAM is the main market. With the gradual development of artificial intelligence Internet of Things (ALOT), the market for multiple PSRAMs is also gradually growing.

[0003] However, in order to control chip area and tape-out costs, the existing PSRAM controllers mainly control reading and writing of a single particle or multiple particles. At the same time, the bandwidth is fixed after the chip is tape-out, which is not conducive to the flexible application of the chip in the market later.

[0004] Therefore, it is necessary to provide a PSRAM control device and a PSRAM control chip to effectively solve the above problems. Summary of the invention

[0005] The invention provides a PSRAM control device and a PSRAM control chip.

[0006] An embodiment of the present invention provides a PSRAM control method, including:

[0007] Multiple buses for inputting data streams separately;

[0008] A plurality of protocol analysis modules, which are equal in number to the bus and are connected one-to-one, and are used to perform protocol analysis on the corresponding data streams respectively;

[0009] An arbitrator, connected to each of the protocol analysis modules, for determining the priority of the plurality of data flows;

[0010] Multiple PSRAM chips; and

[0011] A PSRAM timing generation module is connected to the arbitrator and each of the PSRAM particles, and is used to select one of the multiple PSRAM particles or select at least two of the multiple PSRAM particles for control based on a control signal and output a corresponding PSRAM timing for the selected PSRAM particle based on the data stream output by the arbitrator.

[0012] Preferably, the PSRAM timing generation module includes:

[0013] A particle selection unit connected to each of the PSRAM particles;

[0014] A clock gating unit connected to each of the PSRAM particles;

[0015] A data selection unit connected to each of the PSRAM particles;

[0016] A bus unit, for receiving a control signal;

[0017] A register unit connected to the bus unit, the particle selection unit, the clock gating unit and the data selection unit, and configured to control the gating of the corresponding PSRAM particle through the particle selection unit based on the control signal, input a clock signal to the corresponding PSRAM particle through the clock gating unit, and select a corresponding data channel through the data selection unit;

[0018] A state machine is connected to the arbiter and the data selection unit, and is used to generate the PSRAM timing output through the data channel based on the data stream output by the arbiter.

[0019] Preferably, the bus unit comprises an APB bus.

[0020] Preferably, the protocol parsing module includes:

[0021] a protocol conversion unit, connected to the corresponding bus, and configured to perform protocol conversion on the data stream; and

[0022] An asynchronous fifo unit is connected to the protocol conversion unit and the arbitrator, and is used for buffering the data stream.

[0023] Preferably, the number of the PSRAM particles is four, and the PSRAM timing generation module selects one, two or four of the multiple PSRAM particles for control based on a control signal.

[0024] Preferably, if the control signal selects one of the PSRAM particles for control, the state machine transmits 16 bits of data through the data channel per clock, and obtains data from the asynchronous fifo unit once every four clocks through the arbitrator;

[0025] If the control signal selects two of the PSRAM particles for control, the state machine transmits 32 bits of data through the data channel per clock, and obtains data from the asynchronous FIFO unit once every two clocks through the arbitrator;

[0026] If the control signal selects four PSRAM particles for control, the state machine transmits 64 bits of data through the data channel per clock, and obtains data from the asynchronous FIFO unit once per clock through the arbitrator.

[0027] Preferably, the bus comprises an AHB bus.

[0028] Preferably, the protocol conversion unit cuts off the lower 2 bits of data when performing protocol conversion on the data stream.

[0029] Furthermore, a PSRAM control chip is provided, comprising: a chip body and a PSRAM control device as described in any one of the above items.

[0030] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0031] The PSRAM control device and chip provided in the embodiment of the present invention are designed to control the chip area and the cost of tape-out, realize adjustable bandwidth, and enable the chip to meet a variety of application scenarios. By directly expanding a single PSRAM control device and modifying the system-related configuration, the data bit width of the final output can support simultaneous access to up to 4 PSRAM particles. A chip can support a small bandwidth while also meeting the demand for a larger bandwidth, thereby reducing energy consumption and saving tape-out costs. At the cost of a smaller area, the scalability of the chip after tape-out is improved. In application scenarios with lower bandwidth requirements, chips running at a lower frequency only need to be connected to one PSRAM particle to achieve the purpose of reducing energy consumption; if the bandwidth requirement increases, two PSRAM particles are directly connected to the chip at normal frequency; for chips that need to be overclocked, four PSRAM particles can be connected to provide maximum bandwidth support without the need for re-tapeout. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are some embodiments of the present invention, not all embodiments. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor.

[0033] Figure 1 A structural block diagram of a PSRAM control device provided by one embodiment of the present invention;

[0034] Figure 2 An interface timing diagram of a PSRAM particle provided by an embodiment of the present invention;

[0035] Figure 3 A structural block diagram of a PSRAM timing generation module provided by one embodiment of the present invention;

[0036] Figure 4 A schematic diagram of the number of input and output data of a state machine provided by an embodiment of the present invention;

[0037] Figure 5 A structural block diagram of a clock gating unit provided for one embodiment of the present application;

[0038] Figure 6 A schematic diagram of address selection when a protocol conversion unit performs protocol conversion on the data stream provided in one embodiment of the present application;

[0039] Figure 7 A schematic diagram of a flow chart of a PSRAM timing generation module reading data is provided in accordance with an embodiment of the present invention. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0042] Based on the problems existing in the prior art, an embodiment of the present invention provides a control device and a chip of a PSRAM.

[0043] Figure 1 A structural block diagram of a PSRAM control device provided by an embodiment of the present invention. Figure 2 An interface timing diagram of a PSRAM particle provided by an embodiment of the present invention. Figure 1 and 2As shown, an embodiment of the present invention provides a PSRAM control device, including: multiple buses 11, for respectively inputting data streams. Multiple protocol analysis modules 12, which are equal in number to the buses 11 and connected one-to-one, for respectively performing protocol analysis on the corresponding data streams. An arbitrator 13, connected to each protocol analysis module 12, for determining the priority of multiple data streams. Multiple PSRAM particles 15; and a PSRAM timing generation module 14, connected to the arbitrator 13 and each PSRAM particle 15, for selecting one of the multiple PSRAM particles 15 based on a control signal or selecting at least two of the multiple PSRAM particles 15 for control and outputting a corresponding PSRAM timing for the selected PSRAM particle 15 based on the data stream output by the arbitrator 13.

[0044] In some embodiments, the number of PSRAM particles 15 is four, and the PSRAM timing generation module 14 selects one, two, or four of the multiple PSRAM particles 15 for control based on the control signal. The bus 11 may include an AHB bus. Correspondingly, the bus may include an AHB1 bus, an AHB2 bus, an AHB3 bus, and an AHB4 bus. Thus, four data streams can be input using four AHB buses respectively. Correspondingly, the number of protocol parsing modules 12 can be four, each connected to a corresponding AHB bus, so as to perform protocol parsing on the corresponding data stream.

[0045] Figure 2 In the chip select signal, CS is the chip select signal of the PSRAM particle. If CS is low, the particle is selected and can initiate a data request. CK is the clock signal, which is the input clock signal of DQ when writing data. RWDS is the data shielding signal when writing data. When RWDS is high, the data is shielded and not written to PSRAM. When RWDS is low, it is written normally. When reading data, RWDS is the clock signal of the data. Trwr (HyperRAM Read-Write Recovery Time) is the recovery time after a read and write. Tacc (HyperRAM Read Initial Access Time) is the read initialization access time.

[0046] In some embodiments, each protocol parsing module 12 includes a protocol conversion unit 121 and an asynchronous fifo unit 122. The protocol conversion unit 121 is connected to the corresponding bus 11 and is used to perform protocol conversion on the data stream. The asynchronous fifo unit 122 is connected to the protocol conversion unit 121 and the arbitrator 13 and is used to perform data buffering on the data stream. The asynchronous fifo unit 122 is a first-in-first-out data buffer.

[0047] In some embodiments, Figure 6As shown, the protocol conversion unit 121 cuts off the lower 2 bits of data when performing protocol conversion on the data stream. Specifically, in system design, the AHB bus is generally a 32-bit address bus, and each bit address of the PSRAM particle 15 corresponds to 8 bits of data. In order to save the bit width of the asynchronous fifo unit 122, the lower 2 bits are cut off during the AHB protocol conversion, and the address increment is kept the same as the PSRAM particle 15. If the number of PSRAM particles 15 is 1, the address increment during the AHB protocol conversion is 1. If the number of PSRAM particles 15 is 2, the address increment during the AHB protocol conversion is 2. If the number of PSRAM particles 15 is 4, the address increment during the AHB protocol conversion is 4.

[0048] In some embodiments, Figure 3 As shown, the PSRAM timing generation module 14 includes a bus unit 141, a register unit 142, a state machine 143, a particle selection unit 144, a clock gating unit 145, and a data selection unit 146. Among them, the particle selection unit 144, the clock gating unit 145, and the data selection unit 146 are respectively connected to the gating interface, the clock interface, and the data interface of each PSRAM particle 15. The bus unit 141 is used to receive a control signal. The register unit 142 is connected to the bus unit 141, the particle selection unit 144, the clock gating unit 145, and the data selection unit 146, and is used to control the gating of the corresponding PSRAM particle 15 through the particle selection unit 144 based on the control signal, input the clock signal to the corresponding PSRAM particle 15 through the clock gating unit 145, and select the corresponding data channel 147 through the data selection unit 146. The state machine 143 is connected to the arbiter 13 and the data selection unit 146, and is used to generate the PSRAM timing output through the data channel 147 based on the data stream output by the arbiter 13.

[0049] In some embodiments, the bus unit 141 includes an APB bus. In this embodiment, a pseudo-static random access memory (PSRAM, pseudo SRAM) controller based on an advanced microcontroller bus (AMBA, Advanced Microcontroller Bus Architecture, including four different bus standards: AHB, ASB, APB, AXI), wherein the interface of the data stream is the AHB bus, and the configured interface is the Advanced Peripheral Bus (APB, Advance Peripheral Bus) bus, supporting a total of 5 AHB data buses, each of which is an asynchronous design, with a built-in asynchronous fifo (first-in, first-out data buffer), and then passes through an arbitrator, and finally sends the data to the PSRAM timing generation module 14 to be converted into a PSRAM protocol output.

[0050] In some embodiments, an actual external c_nemb register is used as the register unit 142, and the register determines the effective number of PSRAM timing signals output to the outside.

[0051] In some embodiments, the PSRAM timing generation module 14 generates the PSRAM interface timing, write data splitting, and read data splicing through a large state machine 143 .

[0052] In some embodiments, the data bit width of the AHB bus is assumed to be 32 bits, and the maximum number of PSRAM particles supported is 4, so the maximum number of data is 32. Since the interface type of the PSRAM timing generation module 14 is DDR mode, it can be obtained that the port bit width of the asynchronous fifo unit 122 needs to be designed to be 64, and the number of read and write times of the asynchronous fifo unit 122 needs to be selected according to the number of configured PSRAM particles 15. Figure 4 As shown, if the control signal selects one PSRAM particle 15 for control, the state machine 143 transmits 16 bits of data through the data channel 147 per clock, and obtains data from the asynchronous fifo unit 122 once every four clocks through the arbiter 13. If the control signal selects two PSRAM particles 15 for control, the state machine 143 transmits 32 bits of data through the data channel 147 per clock, and obtains data from the asynchronous fifo unit 122 once every two clocks through the arbiter 13. If the control signal selects four PSRAM particles 15 for control, the state machine 143 transmits 64 bits of data through the data channel 147 per clock, and obtains data from the asynchronous fifo unit 122 once every clock through the arbiter 13.

[0053] In some embodiments, the PSRAM timing generation module 14 needs to generate the clock signal required by each PSRAM particle 15, so the output clock signal (clk1-clk4) needs to be gated according to the configuration signal of the PSRAM to ensure that the clock is not output excessively under different configurations.

[0054] In some embodiments, Figure 7 As shown, for the output data (DQ) selection design of the data selection unit 146, since the bit width of the asynchronous fifo unit 122 is designed to be 64 bits, the maximum number of particles 4 must also be met during the DQ design, so the bit width of DQ needs to be designed to be 32 bits, and the data is selected to be output at different DQ ports through the configuration of the register unit 142. For example, when there are 15 PSRAM particles, DQ selections are 7~0; when there are 2 PSRAM particles 15, DQ selections are 15~0, and when there are 4 PSRAM particles 15, DQ selections are 31~0.

[0055] When transmitting data, it is necessary to select the data transmitted by the asynchronous fifo unit 122 according to the mod_nemb configuration of the register unit 122. For example, when there is one PSRAM particle 15, the required data is 16 bits, then 4 clocks are required to transmit 64 bits of data, the first clock transmits 63-48 bits, the second clock transmits 47-32 bits, the third clock transmits 31-16 bits, and the fourth clock transmits 15-0 bits; if the required PSRAM particles 15 are 2 pieces, the required data is 32 bits, then 2 clocks are required to transmit 64 bits of data, 63-32 bits are transmitted in the first clock, and 31-0 bits are transmitted in the second clock; if the required number of psram is 4, the required data is 64, and the 64-bit data transmission can be completed in one clock.

[0056] In some embodiments, the process is as follows: the PSRAM timing generation module 14 receives the start control signal wr_cmd ( Figure 3 After the start signal and Wr_en signal in the CAS, the CAS segment data begins to be generated. The CAS segment data consists of 48 bits, and its highest bit bit47 is used to identify whether the command is read or write. Bit46 indicates the data space or register space inside the PSRAM, and bit45 indicates the type of transfer (burst). Bit44~0 is the address space that needs to be accessed.

[0057] After the address is sent, there is a delay (Latency) segment, which determines the control of the internal self-refresh of the PSRAM timing generation module 14. When accessing the PSRAM timing generation module 14, whether to refresh is controlled by the read and write data select (RWDS) of the transmission address segment. This signal is an input signal when transmitting the address. If it is high, the latency needs to be *2, and if it is low, it is not needed.

[0058] In the data generation stage, if the received data stream (cmd) is write data, the data needs to be split and placed in the final data channel 147. If the received data stream is read data, the data read from the PSRAM timing generation module 14 needs to be split and placed in the asynchronous fifo unit 122, and finally returned to the AHB bus.

[0059] The PSRAM control device provided in this application is to control the chip area and the cost of tape-out, realize adjustable bandwidth, and make the chip meet a variety of application scenarios. By directly expanding and modifying the system-related configuration of a single PSRAM control device, the data bit width of the final output can support simultaneous access to up to 4 PSRAM particles 15. A chip can support a small bandwidth while also meeting the demand for a larger bandwidth, saving energy consumption and tape-out costs. At the cost of a smaller area, the scalability of the chip after tape-out is improved. In application scenarios with low bandwidth requirements, chips running at a lower frequency only need to be connected to one PSRAM particle 15 to achieve the purpose of reducing energy consumption; if the bandwidth demand increases, two PSRAM particles 15 are directly connected to the chip at normal frequency; for chips that need to be overclocked, four PSRAM particles 15 can be connected to provide maximum bandwidth support without the need for re-tapeout.

[0060] The present application also provides a PSRAM control chip, comprising: a chip body and a PSRAM control device as in any of the above embodiments.

[0061] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A PSRAM control device, characterized in that: include: Multiple buses for inputting data streams separately; A plurality of protocol analysis modules, which are equal in number to the bus and are connected one-to-one, and are used to perform protocol analysis on the corresponding data streams respectively; An arbitrator, connected to each of the protocol analysis modules, for determining the priority of the plurality of data flows; The protocol analysis module includes: a protocol conversion unit connected to the corresponding bus and used to perform protocol conversion on the data stream; and an asynchronous fifo unit connected to the protocol conversion unit and the arbitrator and used to perform data buffering on the data stream; Four PSRAM chips; and The PSRAM timing generation module is connected to the arbitrator and each of the PSRAM particles, and is used to select one of the multiple PSRAM particles or select at least two of the multiple PSRAM particles for control based on a control signal and output a corresponding PSRAM timing for the selected PSRAM particle based on the data stream output by the arbitrator; the PSRAM timing generation module includes: a particle selection unit connected to each of the PSRAM particles; a clock gating unit connected to each of the PSRAM particles; a data selection unit connected to each of the PSRAM particles; a bus unit for receiving the control signal; a register unit connected to the bus unit The state machine is connected with the arbitrator and the data selection unit, and is used to control the gating of the corresponding PSRAM particle through the particle selection unit based on the control signal, input the clock signal to the corresponding PSRAM particle through the clock gating unit, and select the corresponding data channel through the data selection unit; the state machine is connected with the arbitrator and the data selection unit, and is used to generate the PSRAM timing output through the data channel based on the data stream output by the arbitrator; the PSRAM timing generation module selects one, two or four of the multiple PSRAM particles for control based on the control signal; If the control signal selects one of the PSRAM particles for control, the state machine transmits 16 bits of data through the data channel per clock, and obtains data from the asynchronous FIFO unit once every four clocks through the arbitrator; If the control signal selects two of the PSRAM particles for control, the state machine transmits 32 bits of data through the data channel per clock, and obtains data from the asynchronous FIFO unit once every two clocks through the arbitrator; If the control signal selects four PSRAM particles for control, the state machine transmits 64 bits of data through the data channel per clock, and obtains data from the asynchronous FIFO unit once per clock through the arbitrator.

2. The PSRAM control device according to claim 1, characterized in that: The bus unit includes an APB bus.

3. The PSRAM control device according to claim 1, characterized in that: The bus includes an AHB bus.

4. The PSRAM control device according to claim 3, characterized in that: The protocol conversion unit cuts off the lower 2 bits of data when performing protocol conversion on the data stream.

5. A PSRAM control chip, characterized in that: include: A chip body and a PSRAM control device as claimed in any one of claims 1 to 4.

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