Exponential and normalization circuits, maximum value search circuits, MAC circuits and chips

Abstract

The present invention belongs to the field of integrated circuit technology and specifically relates to an exponential and normalization circuit, a maximum value search circuit, a MAC circuit and chip, and a CIM chip integrated with a floating-point MAC circuit. The maximum value search circuit is composed of multiple comparison units arranged in columns, each of which includes three NMOS transistors N1 to N3, a PMOS transistor P1, an AND gate AND1, an OR gate OR1, and an inverter INV1. The circuit adopts a crossbar structure design, resulting in a simpler circuit and faster recognition speed. The exponential and normalization circuit includes an addition array, a data transmission module, a maximum value search circuit, and an output module. This circuit can sequentially complete multiple steps of the calculation process using a pipeline strategy and process some steps in parallel, shortening the overall task delay, more efficiently processing the exponential normalization task, and reducing the circuit area overhead and power consumption. The present invention solves the problem of the prior art lacking a dedicated circuit for exponential and normalization.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to an exponentiation and normalization circuit, a maximum value search circuit, a floating-point MAC circuit, and a CIM chip integrated with the floating-point MAC circuit. Background Art

[0002] In recent years, the rapid development of deep learning and neural networks has placed higher demands on computing power. The traditional von Neumann architecture, with its separation of processor and memory, faces serious challenges when processing large-scale neural networks. As the size of neural network models continues to expand, the frequent movement of data between the processor and memory has become a major bottleneck in performance and energy consumption. This problem is particularly prominent in deep learning tasks that require processing massive amounts of data. To overcome these limitations, in-memory computing (IMC) technology has attracted widespread attention in the deep learning field. In-memory computing allows computational operations to be performed directly in storage units, eliminating the need to frequently transfer data between the processor and memory. This architecture is of great significance for neural network computing.

[0003] It is worth noting that in the neural network calculation process, floating-point exponent and normalization (Asynchronous Exponent Normalization 15Processing, AENP) is an important process of neural network floating-point calculation. Floating-point exponent and normalization play a key role in ensuring the accuracy of neural network calculations, improving calculation efficiency, enhancing model generalization capabilities, and supporting various optimization technologies.

[0004] In traditional logic circuits with floating-point MAC operations, the highly parallel processes required for floating-point exponentiation and normalization, such as data reading, addition, and maximum value search, are performed sequentially over multiple cycles by different circuit modules. This results in poor performance in terms of both area overhead and power consumption. Therefore, finding an exponentiation and normalization circuit with higher integration and computational efficiency, lower power consumption, and faster speed has become a pressing technical challenge for those skilled in the art. Summary of the Invention

[0005] To address the issues of area overhead, power consumption, and inefficiency in existing circuits when processing exponentiation and normalization tasks in floating-point MAC operations, the present invention provides an exponentiation and normalization circuit, a maximum value search circuit, a floating-point MAC circuit, and a CIM chip integrating the floating-point MAC circuit.

[0006] The technical solutions provided by the present invention are as follows:

[0007] The invention discloses an exponent sum normalization circuit, which is used for summing exponent parts of multiple groups of floating-point operands and floating-point weights in floating-point multiplication and accumulation operations, and outputting the maximum value of each exponential sum obtained by the operation.

[0008] The index and normalization circuit includes: an addition array, a data transmission module, a maximum value search circuit and an output module. The addition array includes a plurality of addition units arranged in columns; the addition unit in each row is used to convert the input operand index IE i Weight index WE i Add and output the corresponding exponent and SUM i .

[0009] The data transmission module consists of multiple stack units arranged in columns; each stack unit is used to receive the exponent and SUM output by the addition unit bit by bit in the order from low to high. i After receiving the data on each bit, it is output in reverse order to the maximum value search circuit.

[0010] The maximum value search circuit is used to calculate the maximum value according to the input of multiple exponential and SUM i Generates a flag signal LOG representing the maximum index contained therein i The maximum value search circuit is composed of multiple comparison units arranged in columns. Each comparison unit contains three NMOS transistors N1 to N3, one PMOS transistor P1, one AND gate AND1, one OR gate OR1, and one inverter INV1. The circuit connection relationship of the maximum value search circuit is as follows:

[0011] In each comparison unit, the source of N1 is grounded; the drain of N1 is connected to the source of N2; the drain of N2 is connected to the source of N3; the drains of N3 and P1 are connected to one of the inputs of AND1 and serve as the output port of the flag signal for the corresponding row. The source of P1 is connected to VDD; the gate of N1 is connected to the enable signal EN; the gate of P1 is connected to the PRE port; the other input of AND1 and the input of INV1 are connected to the output of the stack unit in the corresponding row; and the output of AND1 is connected to one of the outputs of OR1. In the entire maximum value search circuit, the other input of OR1 in the comparison unit of the first row is grounded, and the other input of OR1 in the comparison units of the remaining rows is connected to the output of OR1 in the comparison unit of the previous row; the output of OR1 in the comparison unit of the last row is connected to the gate of N3 in the comparison units of all rows.

[0012] The output module is used to receive the exponents and SUM output by the addition unit. i The flag signal LOG output by the comparison unit iThe index and output corresponding to the flag signal that is still high after multiple rounds of comparison are used as the normalized result SUM.

[0013] As a further improvement of the present invention, each adding unit in the adding array is composed of a serial adder FA and a D flip-flop; the two data input terminals of FA are connected to IE i WE i , the output end of FA is connected to the input end of the stack unit; the carry input end CI of FA is connected to the data output end Q of the D flip-flop, the carry output end CO of FA is connected to the data input port D of the D flip-flop, and the clock signal port of the D flip-flop is connected to the clock signal CLK.

[0014] As a further improvement of the present invention, the maximum number of bits supported by the stack unit in the data transmission module is determined by the exponent output by the addition unit and the sum of i OK. When the exponent output by the addition unit is equal to SUM i When it is N bits, the data transmission module uses an N-bit stack unit.

[0015] As a further improvement of the present invention, an N-bit stack unit is composed of N D flip-flops D1 to Dn, 2n-2 tri-state buffers E1 to E2n-2, and a 2-to-1 selector MUX. The circuit connection relationship is as follows:

[0016] D1 to Dn are forward cascaded through E1 to En-1. The Q end of the previous stage D flip-flop is connected to the input end of the three-state buffer, and the output end of the three-state buffer is connected to the D end of the next stage D flip-flop. The control end of E1 to En-1 is connected to the first enable signal EN1.

[0017] D1~Dn are also reverse cascaded through En~En-2. The D end of the next-stage D flip-flop is connected to the input end of the three-state buffer, and the output end of the three-state buffer is connected to the Q end of the previous-stage D flip-flop; the control end of En~En-2 is connected to the second enable signal EN2.

[0018] The clock signal ports of D1 to Dn-2 are connected to the clock signal CLK; the D terminal of the first-stage D flip-flop is connected to the output terminal of the addition unit, which is used to receive the exponents and SUM output by the addition unit in reverse order. i .

[0019] The data port 0 of the MUX is grounded, the data port 1 is connected to the Q end of the first-stage D flip-flop, the selection end is connected to the OPT signal, and the output end outputs the exponential and SUM arranged in sequence. i .

[0020] As a further improvement of the present invention, the stack unit implements the bit-by-bit inversion and output of the received N-bit data, which includes two stages: data storage and data reading. The process is as follows:

[0021] (1) Data storage stage

[0022] Set EN1 to high level and EN2 to low level; and control the MUX to output the data of data port 0 through the OPT signal.

[0023] N bits of data are input from the D terminal of D1 in order from the lowest bit to the highest bit. After several clock cycles, the N bits of data are stored in order from the lowest bit to the highest bit in Dn to D1. At this stage, the output of the MUX is 0.

[0024] (2) Data readout stage

[0025] Set EN1 to high level and EN2 to low level; and control the MUX to output the data of data port 1 through the OPT signal.

[0026] In the following clock cycles, the data stored in D1 to Dn are outputted in sequence through the output port of the MUX; that is, the MUX outputs N bits of data arranged from high to low, realizing the bit-by-bit reversal of the data input to the D end of D1 during the data storage stage.

[0027] As a further improvement of the present invention, the maximum value search circuit implements a strategy for identifying the maximum value from the sum of the exponentials of each N bit input and generating a corresponding flag signal as follows:

[0028] (1) The respective flag signal lines LOG are connected through the PRE ports in the comparison units of each row. i Precharged to high level.

[0029] (2) Receive the indexes and sums output by the stack cells in each row in order from high to low i .

[0030] (3) The maximum value search circuit receives the index and SUM calculated for each row i When each bit is set, the level state of the mark signal line of each row changes and meets the following rules:

[0031] A. If the SUM entered in each row i If the corresponding bit includes both "1" and "0", the flag signal line of the corresponding row with data "1" maintains the previous level state, and the flag signal line of the corresponding row with data "0" discharges and becomes a low level.

[0032] B. When the flag signal line of any row is at a low level, it will always remain at a low level and will no longer become a high level.

[0033] C. If the SUM entered in each row iIf the corresponding bits of the flag signal lines are all "1" or all "0", the flag signal lines of each row maintain the previous level state.

[0034] (4) After any cycle, if only the flag signal line of one row is high, the exponential sum of the input of this row is the maximum of all exponential sums, which is used as the normalization result;

[0035] or,

[0036] After completing the input of the lowest bit of the index sum of each row, the index sum of the corresponding row whose flag signal line is still at a high level is the maximum value among all the index sums, which is used as the normalization result.

[0037] As a further improvement of the present invention, when the addition array, the data transmission module, and the maximum value search circuit include M rows, the output module used by the exponential and normalization circuits also includes M transmission gates arranged in columns and a cascaded OR gate; the transmission gate TG of each row i The input of SUM i , the control end connects to LOG i The cascaded OR gate uses the non-zero output of each transmission gate as the final normalized result SUM.

[0038] The present invention also includes a maximum value search circuit for identifying the maximum value from a plurality of multi-bit numbers input bit by bit. The maximum value search circuit is composed of multiple comparison units arranged in columns, each of which includes three NMOS transistors N1 to N3, one PMOS transistor P1, an AND gate AND1, an OR gate OR1, and an inverter INV1. In each comparison unit, the source of N1 is grounded; the drain of N1 is connected to the source of N2; the drain of N2 is connected to the source of N3; the drains of N3 and P1 are connected to one input terminal of AND1 and serve as the output port of the flag signal for the corresponding row. The source of P1 is connected to VDD; the gate of N1 is connected to the enable signal EN; the gate of P1 is connected to the PRE port; and the other input terminal of AND1 is connected to the input terminal of INV1 and serves as the input port of each multi-bit number. The output end of AND1 is connected to one of the output ends of OR1; in the entire maximum value search circuit, the other input end of OR1 in the comparison unit of the first row is grounded, and the other input end of OR1 in the comparison unit of the remaining rows is connected to the output end of OR1 in the comparison unit of the previous row; the output end of OR1 in the comparison unit of the last row is connected to the gate of N3 in the comparison units of all rows.

[0039] The present invention also includes a floating-point MAC circuit for implementing multiplication and accumulation operations between multiple groups of floating-point numbers. The MAC circuit uses the aforementioned exponential sum normalization circuit to normalize the exponential sums of each group of floating-point numbers and outputs the maximum value of all calculated exponential sums as the normalization result.

[0040] The present invention also includes a CIM chip having a floating-point MAC operation function. The CIM chip integrates the aforementioned floating-point MAC circuit.

[0041] The technical solution provided by the present invention has the following beneficial effects:

[0042] The present invention provides a new maximum value search circuit with a cross structure. This circuit can quickly identify the maximum value among multiple multi-bit numbers after completing the input. Compared with various existing circuits with the same function, the maximum value search circuit designed by the present invention has a simpler structure, which can greatly reduce area overhead and energy loss, and has a higher recognition rate, allowing more flexible operation scheduling, so it has a wider range of application scenarios.

[0043] Based on the maximum value search circuit, the present invention also designs a circuit specifically designed to implement exponentiation and normalization in floating-point MAC operations. This circuit systematically links the exponent summation, maximum exponent search, and exponent sum normalization tasks within the exponentiation and normalization process, achieving pipelined operation. This allows for rapid exponentiation and normalization in a shorter cycle, reducing computational latency and increasing computational speed. Furthermore, compared to existing circuits with the same functional modules, the present invention's circuit has significantly reduced area overhead and energy consumption. Timing control of the computational process is also simplified. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 This is a circuit diagram of the maximum value search circuit provided in Example 1 of the present invention.

[0045] Figure 2 This is a signal flow diagram for the maximum value search circuit provided in Embodiment 1 of the present invention to realize maximum value recognition of four five-bit binary numbers.

[0046] Figure 3 This is a circuit architecture diagram of the exponential and normalization circuit provided in Example 2 of the present invention.

[0047] Figure 4 4 is a circuit diagram of a stack unit in an exponential and normalization circuit according to embodiment 2 of the present invention.

[0048] Figure 5 This is a circuit diagram of an output module in the exponential and normalization circuit of Example 2 of the present invention. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0050] Example 1

[0051] The present invention also includes a maximum value search circuit for identifying the maximum value from a plurality of multi-bit numbers input bit by bit. The maximum value search circuit is composed of a plurality of comparison units arranged in columns. In practical applications, the multi-bit numbers to be identified are synchronously input bit by bit into the comparison units in different rows of the circuit in order from MSB to LSB. After the multi-bit numbers are input, the circuit outputs a flag signal LOG representing the size of the input data in each row. When the final result of the flag signal LOG for a row is in a high-level state, it indicates that the multi-bit number input to the comparison unit in that row is the maximum value among all the data. When the final result of the flag signal LOG for a row is in a low-level state, it indicates that the multi-bit number input to the comparison unit in that row is not the maximum value among all the input data.

[0052] Specifically, if Figure 1 As shown, each comparison unit in the maximum value search circuit provided by this embodiment includes three NMOS transistors N1-N3, one PMOS transistor P1, an AND gate AND1, an OR gate OR1, and an inverter INV1. In each comparison unit, the source of N1 is grounded; the drain of N1 is connected to the source of N2; the drain of N2 is connected to the source of N3; the drains of N3 and P1 are connected to one input terminal of AND1 and serve as the output port of the flag signal LOG for the corresponding row. The source of P1 is connected to VDD; the gate of N1 is connected to the enable signal EN; the gate of P1 is connected to the PRE port; the other input terminal of AND1 is connected to the input terminal of INV1 and serves as the input port of each multi-bit number. The output terminal of AND1 is connected to one output terminal of OR1.

[0053] In the entire maximum value search circuit, the other input end of OR1 in the comparison unit of the first row is grounded, and the other input end of OR1 in the comparison units of the remaining rows is connected to the output end of OR1 in the comparison unit of the previous row; the output end of OR1 in the comparison unit of the last row is connected to the gate of N3 in the comparison units of all rows.

[0054] In this embodiment, the number of rows of comparison units in the maximum value search circuit corresponds to the maximum number of input data groups supported by the circuit. For example, a maximum value search circuit with N rows of comparison units can search for the maximum value of up to N multi-bit numbers. The circuit does not impose any restrictions on the number of bits of the multi-bit number to be identified; it can search for the maximum value among any number of multi-bit numbers.

[0055] The maximum value search circuit provided in this embodiment implements the following strategy for identifying the maximum value from the sum of the exponentials of each N-bit input and generating the corresponding flag signal:

[0056] (1) The respective flag signal lines LOG are connected through the PRE ports in the comparison units of each row. i Precharged to high level.

[0057] (2) Through the IN gate in each row comparison unit i The port synchronously receives the multi-bit number to be identified in order from high to low.

[0058] (3) When the maximum value search circuit receives each bit of the multi-bit number input from each row, the level state of the flag signal line of each row changes according to the following rules:

[0059] A. If the corresponding bits of the multi-bit numbers input in each row include both "1" and "0", the flag signal line of the corresponding row with data "1" maintains the previous level state, and the flag signal line of the corresponding row with data "0" discharges and becomes a low level.

[0060] B. When the flag signal line of any row is at a low level, it will always remain at a low level and will no longer become a high level.

[0061] C. If the corresponding bits of the multi-bit numbers input in each row are all "1" or all "0", the flag signal lines of each row maintain the previous level state.

[0062] (4) Assuming that the number of bits of the multi-bit numbers input in each row is M, then after at most M cycles, the flag signal output by the comparison unit in each row can reflect the maximum value therein.

[0063] Specifically, after any cycle, if only the flag signal line of one row is high, the exponential sum of the input of that row is the maximum of all exponential sums. Alternatively, after completing the input of the least significant bit of each row's multi-bit data, the exponential sum of the corresponding row whose flag signal line is still high is the maximum of all exponential sums. It should be noted that during each comparison process, the number of comparison units whose flag signal LOG is ultimately still high may be one or more rows. When the characterization signals output by multiple comparison units are all 1, it indicates that the inputs of the corresponding rows are the same and are all the maximum values ​​of all input data.

[0064] The following describes in detail the search process and working principle of the maximum value search circuit provided in this embodiment by taking four 5-bit numbers as an example:

[0065] Assume that the four binary data RAW1 to RAW4 to be compared are 11001, 10011, 11011, and 11001 respectively. Before the data is input to the comparison units of each row, the gate terminal of the PMOS transistor P1 in each comparison unit is set to a high level through the PRE signal line, and then the flag signal line LOG of each row is set to 0. i Precharge to a high level state in advance. Figure 2 It reflects the changes of various signals during the data input process. Then, each 5-bit binary number is input into the comparison unit of each row synchronously according to the principle of inputting the MSB first, then the second lowest bit, and finally the LSB.

[0066] 1. Cycle 1

[0067] Combine Figure 2 As shown in the figure, in the first cycle, the value input to each row is "1111", that is, the input IN of each row is all "1". At this time, the operating state of the MOS transistors in each row is roughly the same. Before the most significant bit of the number enters the comparison unit, the LOG signal line of each row has been precharged to "1". Since the input IN of each bit is also "1", the output of the AND gate is "1". The output of the AND gate is connected to the input of the OR gate, so the output of the OR gate in each row is also "1". The output of the OR gate in each row serves as the CAN signal, so the CAN signal is also "1". Because the CAN signal line is electrically connected to the gate of the NMOS transistor N3 in each comparison unit, N3 in each comparison unit is in the on state.

[0068] During the comparison phase of each cycle, the EN pins in each row are turned on, turning on the NMOS transistors N1 in each row. The input data IN in each row is connected to the NMOS transistors N2 in each row via inverters. Since the input IN in each row is "1" during this cycle, N2 in each row is turned off. Therefore, in each row's comparison unit, N1 and N3 are turned on, but N2 is turned off. Therefore, the LOG signal lines in each row cannot be connected to ground sequentially through N3, N2, and N1. In other words, LOG remains high.

[0069] As can be seen, in this cycle, all row inputs are "1," so the LOG flag signals of RAW1 to RAW4 remain consistent with the previous cycle (i.e., the precharge phase), all at high levels. The changes in the LOG signals during this cycle satisfy Rule C.

[0070] 2. Cycle2

[0071] In the second cycle, the inputs to each row are "1011." At this point, the rows with a "1" comparator input are the same as in the first cycle, meaning the LOG signal line remains at "1." It's worth noting that the OR gates in each row are cascaded and connected to the gates of N3 in each row. Therefore, as long as the OR gate in any row outputs 1, N3 in all rows is turned on. Therefore, N3 in all rows is turned on during this cycle.

[0072] During each cycle, N1 remains on due to the EN control, while the conduction state of N2 in each row is affected only by the value of the input data IN. When IN is "0," the gate of N2 is at a high level after the inverter, turning N2 on. Conversely, when IN is "1," the gate of N2 is at a low level after the inverter, turning N2 off.

[0073] Therefore, in this cycle, N2 in the row corresponding to RAW2, where the second-highest bit is "0," is turned on, while N2 in the other rows is turned off. This ultimately causes the LOG signal line in the row corresponding to RAW2 to form a discharge path through N3, N2, and N1, and to reach a low level. The LOG signal lines in the remaining rows remain high.

[0074] As can be seen, during this cycle, the LOG flag signal of RAW2, whose input is "0," drops to a low level, while the LOG flag signals of RAW1, RAW3, and RAW4, whose inputs are "1," remain at their previous high level. The changes in the LOG signals during this cycle satisfy Rule A.

[0075] 3. Cycle3

[0076] In the third cycle, the data input to each row is "0000," meaning all "0s." At this point, the AND gates in each row output "0," which in turn causes the OR gates to also output "0," ultimately causing the CAN signal line connected to the N3 gate of each row to also output "0." At this point, N3 in each row is cut off, meaning that the LOG signal line in each row cannot form a discharge path with the ground line, and the previous level remains.

[0077] This shows that in this cycle, all row inputs are "0", so the LOG flag signals of RAW1 to RAW4 all maintain the level state of the previous cycle. The change of the LOG signal in this cycle meets Rule C.

[0078] 4. Cycle4

[0079] In the fourth cycle, the data input to each row is "0110". Since the LOG signal line of the row corresponding to RAW3 and the input IN of the current cycle are both "1", the CAN signal is also "1" and N3 of each row is turned on.

[0080] Based on the input data for each row, the gate of N2 in the rows corresponding to RAW1 and RAW4 is high, turning N2 on. The gate of N2 in the rows corresponding to RAW2 and RAW3 is low, turning N2 off. Since N1 in all rows is already on during this cycle, a discharge path is formed for the rows corresponding to RAW1 and RAW4, and the LOG signal lines for these two rows also go low.

[0081] At this point, after four cycles, the signal lines of the corresponding rows of RAW1, RAW2 and RAW4 are all reduced to a low level. Therefore, the data finally input to RAW3, whose LOG signal line is still at a high level, is the maximum value.

[0082] As can be seen, during this cycle, the inputs to RAW1 and RAW4 are "0," and the inputs to RAW2 and RAW3 are "1." Therefore, the LOG signal lines for RAW1 and RAW4 maintain the same level as in the previous cycle, while the LOG signal lines for RAW1 and RAW4 drop to a low level. The changes in the LOG signal during this cycle satisfy rules A and B.

[0083] 5. Cycle5

[0084] In the fifth cycle, the input of each row is "1111", that is, all "1" input. At this time, the input signal IN outputs "0" through the inverter, so the gate voltage of N2 in each row is low, and N2 in all rows is turned off, so no discharge path can be formed, and the flag signal line LOG of each row still maintains the previous level state.

[0085] This shows that in this cycle, the inputs of RAW1 to RAW4 are all "1", and the flag signal lines LOG of RAW1 to RAW4 all maintain the level state of the previous cycle. The change of the LOG signal in this cycle meets rules A and B.

[0086] In summary, while the maximum value search circuit provided by this embodiment is very simple, it can identify the maximum value among all input data in real time after multiple multi-bit inputs are completed, demonstrating extremely strong data search performance. This novel circuit effectively reduces the area overhead and energy consumption of traditional maximum value search circuits, significantly improving maximum value search efficiency and embracing a wide range of applications.

[0087] Example 2

[0088] Utilizing the maximum value search circuit designed in Example 1, this embodiment further provides an exponent sum normalization circuit, which is used to sum the exponential parts of multiple groups of floating-point operands and floating-point weights in floating-point multiplication and addition operations, and output the maximum value of each exponential sum calculated.

[0089] like Figure 3As shown, the index and normalization circuit includes: an addition array, a data transmission module, a maximum value search circuit and an output module. The addition array includes a plurality of addition units arranged in columns; the addition unit in each row is used to convert the input operand index IE i Weight index WE i Add and output the corresponding exponent and SUM i .

[0090] Specifically, each adding unit in the adding array in this embodiment adopts an adder with carry, and is composed of a serial adder FA and a D flip-flop. In each row of the adding unit, the two data input terminals of FA are connected to IE i WE i The output of FA is connected to the input of the stack unit; the carry input CI of FA is connected to the data output Q of the D flip-flop; the carry output CO of FA is connected to the data input D of the D flip-flop; and the clock signal port of the D flip-flop is connected to the clock signal CLK. It is important to emphasize that during the calculation process, the addition units in each row output the calculation results bit by bit, in order from LSB to MSB, to the data transmission module.

[0091] The data transmission module consists of multiple stack units arranged in columns; each stack unit is used to receive the exponent and SUM output by the addition unit in real time in the order from low to high. i After receiving the data on each bit, it is output in reverse order to the maximum value search circuit.

[0092] The maximum number of bits supported by the stack unit in the data transmission module of this embodiment is determined by the exponent output by the addition unit and the sum i OK. When the exponent output by the addition unit is equal to SUM i When it is N bits, the data transmission module uses an N-bit stack unit.

[0093] In detail, such as Figure 4 As shown, the N-bit stack unit consists of N D flip-flops D1 to Dn, 2n-2 tri-state buffers E1 to E2n-2, and a 2-to-1 selector MUX. The circuit connection relationship is as follows:

[0094] D1 to Dn are forward cascaded through E1 to En-1. The Q end of the previous stage D flip-flop is connected to the input end of the three-state buffer, and the output end of the three-state buffer is connected to the D end of the next stage D flip-flop. The control end of E1 to En-1 is connected to the first enable signal EN1.

[0095] D1~Dn are also reverse cascaded through En~En-2. The D end of the next-stage D flip-flop is connected to the input end of the three-state buffer, and the output end of the three-state buffer is connected to the Q end of the previous-stage D flip-flop; the control end of En~En-2 is connected to the second enable signal EN2.

[0096] The clock signal ports of D1 to Dn-2 are connected to the clock signal CLK; the D terminal of the first-stage D flip-flop is connected to the output terminal of the addition unit, which is used to receive the exponents and SUM output by the addition unit in reverse order. i .

[0097] The data port 0 of the MUX is grounded, the data port 1 is connected to the Q end of the first-stage D flip-flop, the selection end is connected to the OPT signal, and the output end outputs the exponential and SUM arranged in sequence. i .

[0098] Specifically, Figure 4 The stack unit shown implements the bit-by-bit inversion and output of the received N-bit data, which includes two stages: data storage and data reading. The process is as follows:

[0099] (1) Data storage stage

[0100] Set EN1 to high level and EN2 to low level; and control the MUX to output the data of data port 0 through the OPT signal.

[0101] N bits of data are input from the D terminal of D1 in order from the lowest bit to the highest bit. After several clock cycles, the N bits of data are stored in order from the lowest bit to the highest bit in Dn to D1. At this stage, the output of the MUX is 0.

[0102] (2) Data readout stage

[0103] Set EN1 to high level and EN2 to low level; and control the MUX to output the data of data port 1 through the OPT signal.

[0104] In the following clock cycles, the data stored in D1 to Dn are output in sequence through the output port of the MUX; that is, the MUX outputs N bits of data arranged from high to low, realizing bit-by-bit reversal of the data input to the D end of D1 during the data storage stage.

[0105] At this point, the transmission unit has bit-reversed the exponents and SUMi calculation results of the addition array, outputting them in LSB-to-MSB order, and outputting the exponents and calculation results in MSB-to-LSB order. The format of the output multi-bit numbers matches the maximum value search circuit's requirement that the input multi-bit data be arranged in MSB-to-LSB order.

[0106] Specifically, the data transmission module in the exponential and normalization circuit of this embodiment matches the addition array with the maximum value search circuit. This allows for the orderly connection of the two major tasks of numerical addition and maximum value search required in the exponential and normalization processes of floating-point MAC operations, thus achieving pipeline operation.

[0107] The maximum value search circuit in this embodiment is used to input multiple indexes and SUM i Generates a flag signal LOG representing the maximum index contained therein i In particular, the maximum value search circuit used in this embodiment is the circuit designed in Example 1. In the maximum value search circuit, one input terminal of the AND gate and the input terminal of the inverter in each row of the comparison unit are directly connected to the output of the stack unit in the corresponding row.

[0108] The characteristics and operating principles of the maximum value search circuit in the exponential sum normalization circuit have been described in detail in Example 1 and will not be repeated in this embodiment. In conjunction with Example 1, it can be seen that after the data transmission module inputs the lowest bit of the exponential sum of each row into the comparison unit of each row, the exponential sum of the corresponding row for which the flag signal line LOG is still high is the maximum among all exponential sums and should be output as the normalization result.

[0109] Finally, the output module is used to receive the exponents and SUM output by the addition unit. i The flag signal LOG output by the comparison unit i The index and output corresponding to the flag signal that is still high after multiple rounds of comparison are used as the normalized result SUM.

[0110] In this embodiment, the circuit scale of the output module is adapted to the scale of the aforementioned addition array, data transmission module and maximum value search circuit. When the addition array, data transmission module and maximum value search circuit include M rows, the output module should also support the calculation of the sum of M groups of SUMs. i and LOG i Output the largest set of indices and SUM.

[0111] like Figure 5 As shown, the output module for normalizing the four groups of indices and results includes four transmission gates arranged in columns and a cascaded OR gate; the transmission gate TG in each row i The input of SUM i , the control end connects to LOG i The cascaded OR gate uses the non-zero outputs of each transmission gate as the final normalized result SUM.

[0112] Combined with the previous content, we can see that after exponential addition, data bit reversal and maximum value search, the SUM of each row output isi The signal flag for the row with the largest value is set to 1, while the signal flags for the remaining rows are all set to 0. Therefore, after passing through the transmission gates, only the transmission gates for the row or rows with the largest values ​​will output the corresponding results. Finally, by cascading OR gates, the maximum value of the identified exponential sum can be obtained based on the above values, which is the normalized result SUM.

[0113] Example 3

[0114] This embodiment provides a floating-point MAC circuit for implementing multiplication and accumulation operations between multiple groups of floating-point numbers. The MAC circuit uses the exponential sum normalization circuit described in Example 2 to normalize the exponential sums of each group of floating-point numbers and outputs the maximum value of all calculated exponential sums as the normalization result.

[0115] Example 4

[0116] This embodiment further provides a CIM chip having a floating-point MAC operation function. The floating-point MAC circuit in Embodiment 3 is integrated into the CIM chip.

[0117] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. An exponential and normalization circuit, characterized in that It is used to add the exponential parts of multiple groups of floating-point operands and floating-point weights in floating-point multiplication and accumulation operations, and output the maximum value of each exponential sum calculated; the exponential sum normalization circuit includes: an addition array, a data transmission module, a maximum value search circuit and an output module; The addition array includes a plurality of addition units arranged in columns; the addition unit in each row is used to convert the input operand index IE i Weight index WE i Add and output the corresponding exponent and SUM i ; The data transmission module is composed of a plurality of stack units arranged in columns; each stack unit is used to receive the exponent and SUM output by the addition unit bit by bit in the order from low to high. i and output the data on each bit in reverse order to the maximum value search circuit after receiving the data on each bit; The maximum value search circuit is used to calculate the maximum value according to the input of multiple exponential and SUM i Generates a flag signal LOG representing the maximum index contained therein i The maximum value search circuit is composed of a plurality of comparison units arranged in columns, each comparison unit including three NMOS transistors N1 to N3, one PMOS transistor P1, one AND gate AND1, one OR gate OR1, and one inverter INV1. In each comparison unit, the source of N1 is grounded; the drain of N1 is connected to the source of N2; the drain of N2 is connected to the source of N3; the drains of N3 and P1 are connected to one of the input terminals of AND1 and serve as the output ports of the corresponding row flag signal; the source of P1 is connected to VDD; and the gate of N1 is connected to the enable signal EN. The gate of P1 is connected to the PRE port; the other input of AND1 and the input of INV1 are connected to the output of the stack unit in the corresponding row; the output of AND1 is connected to one of the outputs of OR1; in the entire maximum value search circuit, the other input of OR1 in the comparison unit in the first row is grounded, and the other input of OR1 in the comparison units in the remaining rows is connected to the output of OR1 in the comparison unit in the previous row; the output of OR1 in the comparison unit in the last row is connected to the gate of N3 in the comparison units in all rows; Output module, which is used to receive the exponents and SUM output by the addition unit i The flag signal LOG output by the comparison unit i The index and output corresponding to the flag signal that is still high after multiple rounds of comparison are used as the normalized result SUM.

2. The exponential and normalization circuit of claim 1 , wherein: Each adding unit in the adding array is composed of a serial adder FA and a D flip-flop; the two data input terminals of FA are connected to IE i WE i , the output end of FA is connected to the input end of the stack unit; the carry input end CI of FA is connected to the data output end Q of the D flip-flop, the carry output end CO of FA is connected to the data input port D of the D flip-flop, and the clock signal port of the D flip-flop is connected to the clock signal CLK.

3. The exponential and normalization circuit of claim 1 , wherein: The maximum number of bits supported by the stack unit in the data transmission module is determined by the exponent and SUM output by the addition unit. i Sure; When the exponent output by the addition unit is summed i When it is N bits, the data transmission module adopts an N-bit stack unit.

4. The exponential and normalization circuit of claim 3, wherein: The N-bit stack unit consists of N D flip-flops D1 to Dn, 2n-2 tri-state buffers E1 to E2n-2, and a 2-to-1 selector MUX. The circuit connections are as follows: D1 to Dn are connected in a forward cascade via E1 to En-1. The Q terminal of the previous D flip-flop is connected to the input terminal of the tri-state buffer, and the output terminal of the tri-state buffer is connected to the D terminal of the next D flip-flop. The control terminals of E1 to En-1 are connected to the first enable signal EN1. D1 to Dn are also reversely cascaded through En to En-2. The D terminal of the subsequent D flip-flop is connected to the input terminal of the tri-state buffer, and the output terminal of the tri-state buffer is connected to the Q terminal of the previous D flip-flop. The control terminals of En to En-2 are connected to the second enable signal EN2. The clock signal ports of D1~Dn-2 are connected to the clock signal CLK; the D end of the first-stage D flip-flop is connected to the output end of the addition unit, which is used to receive the exponents and SUM output by the addition unit in reverse order. i ; The data port 0 of the MUX is grounded, the data port 1 is connected to the Q end of the first-stage D flip-flop, the selection end is connected to the OPT signal, and the output end outputs the exponential and SUM arranged in sequence. i .

5. The exponential and normalization circuit of claim 4, wherein: The stack unit implements the bit-by-bit inversion and output of the received N-bit data, which includes two stages: data storage and data reading. The process is as follows: (1) Data storage stage Set EN1 to high level and EN2 to low level; and control the MUX to output the data of data port 0 through the OPT signal; N bits of data are input from the D end of D1 in order from low to high. After several clock cycles, the N bits of data are stored in Dn to D1 in order from low to high. At this stage, the output of MUX is 0. (2) Data readout stage Set EN1 to high level and EN2 to low level; and control the MUX to output the data of data port 1 through the OPT signal; In the following clock cycles, the data stored in D1 to Dn are outputted in sequence through the output port of the MUX; that is, the MUX outputs N bits of data arranged from high to low, realizing the bit-by-bit reversal of the data input to the D end of D1 during the data storage stage.

6. The exponential and normalization circuit of claim 5, wherein: The maximum value search circuit implements the strategy of identifying the maximum value from the sum of the exponentials of each N bit input and generating the corresponding flag signal as follows: (1) The respective flag signal lines LOG are connected through the PRE ports in the comparison units of each row i Precharge to high level; (2) Receive the indexes and sums output by the stack cells in each row in order from high to low i ; (3) The maximum value search circuit receives the index and SUM calculated for each row i When each bit is set, the level state of the mark signal line of each row changes and meets the following rules: A. If the SUM entered in each row i The corresponding bit of includes both "1" and "0", then the flag signal line of the corresponding row with data "1" maintains the previous level state, and the flag signal line of the corresponding row with data "0" becomes low level; B. Once the flag signal line of any row is switched to low level, it will always remain in low level state and will no longer become high level; C. If the SUM entered in each row i If the corresponding bits of are all "1" or all "0", the flag signal lines of each row maintain the previous level state; (4) After any cycle, if only the flag signal line of one row is high, the exponential sum of the input of this row is the maximum value of all exponential sums, which is used as the normalized result; or, After completing the input of the lowest bit of the index sum of each row, the index sum of the corresponding row whose flag signal line is still at a high level is the maximum value among all the index sums, which is used as the normalization result.

7. The exponential and normalization circuit of claim 1 , wherein: When the addition array, data transmission module, and maximum value search circuit include M rows, the output module used by the exponential and normalization circuit also includes M transmission gates arranged in columns and a cascaded OR gate; the transmission gate TG of each row i The input of SUM i , the control end connects to LOG i ; The cascaded OR gate outputs the non-zero value output by each transmission gate as the final normalized result SUM.

8. A maximum value search circuit, characterized in that: It is used to identify the maximum value from multiple multi-bit numbers input bit by bit. The maximum value search circuit is composed of multiple comparison units arranged in columns. Each comparison unit includes three NMOS transistors N1 to N3, one PMOS transistor P1, one AND gate AND1, one OR gate OR1, and one inverter INV1. In each comparison unit, the source of N1 is grounded; the drain of N1 is connected to the source of N2; the drain of N2 is connected to the source of N3; the drains of N3 and P1 are connected to one input terminal of AND1 and serve as the output port of the flag signal of the corresponding row; the source of P1 is connected to VDD. The gate of N1 is connected to the enable signal EN; the gate of P1 is connected to the PRE port; the other input of AND1 is connected to the input of INV1 and serves as the input port of each multi-bit number; the output of AND1 is connected to one of the outputs of OR1; in the entire maximum value search circuit, the other input of OR1 in the comparison unit of the first row is grounded, and the other input of OR1 in the comparison units of the remaining rows is connected to the output of OR1 in the comparison unit of the previous row; the output of OR1 in the comparison unit of the last row is connected to the gate of N3 in the comparison units of all rows; The maximum value identification strategy of the maximum value search circuit is as follows: (1) The respective flag signal lines LOG are connected through the PRE ports in the comparison units of each row i Precharge to high level; (2) Receive the indexes and sums output by the stack cells in each row in order from high to low i ; (3) The maximum value search circuit receives the index and SUM calculated for each row i When each bit is set, the level state of the mark signal line of each row changes and meets the following rules: A. If the SUM entered in each row i The corresponding bit of includes both "1" and "0", then the flag signal line of the corresponding row with data "1" maintains the previous level state, and the flag signal line of the corresponding row with data "0" becomes low level; B. Once the flag signal line of any row is switched to low level, it will always remain in low level state and will no longer become high level; C. If the SUM entered in each row i If the corresponding bits of are all "1" or all "0", the flag signal lines of each row maintain the previous level state; (4) After any cycle, if only the flag signal line of one row is high, the exponential sum of the input of this row is the maximum value of all exponential sums, which is used as the normalized result; or, After completing the input of the lowest bit of the index sum of each row, the index sum of the corresponding row whose flag signal line is still at a high level is the maximum value among all the index sums, which is used as the normalization result.

9. A floating-point MAC circuit for implementing multiplication and accumulation operations between multiple groups of floating-point numbers, characterized in that: It adopts the exponent sum normalization circuit as described in any one of claims 1 to 7 to normalize the exponent sum of each group of floating-point numbers, and outputs the maximum value of all calculated exponent sums as the normalization result.

10. A CIM chip having a MAC operation function for floating-point numbers, characterized in that: The floating-point MAC circuit according to claim 9 is integrated into the CIM chip.

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