Data transmission method, electronic device and storage medium

Abstract

The present disclosure provides a data transmission method, an electronic device and a storage medium, the method comprising: obtaining a first data amount of data to be transmitted, and converting the first data amount into a corresponding number of binary bytes; dividing the data to be transmitted into a plurality of sub-data packets based on the bits of the binary byte number whose values ​​are 1; generating a first command packet corresponding to the sub-data packet, and sending the first command packet to a second bare chip through a transmission module; after receiving a response message returned by the second bare chip based on the first command packet, determining a third number based on the first number and the second number, and determining the third number of first clock cycles after receiving the response message as the corresponding sub-data packet transmission clock cycle; in a single first clock cycle in the sub-data packet transmission clock cycle, sending the fourth number of bytes in the corresponding sub-data packet to the second bare chip through the transmission module. The present disclosure can improve the flexibility and efficiency of data transmission between bare chips.

Description

Technical Field

[0001] The present disclosure relates to the field of chip technology, and in particular to a data transmission method, an electronic device and a storage medium. Background Art

[0002] Application scenarios such as high-performance computing and artificial intelligence have increasingly higher requirements for chip computing power. The computing power of a chip depends on the number of transistors integrated into the chip, and the existing chip process has reached its physical limit. It is difficult to integrate more transistors per unit area of ​​silicon chips. At the same time, due to the size of the photolithography machine mask, the yield of making larger silicon chips will drop significantly, and it is very difficult to integrate more transistors on a single silicon chip. In the existing technology, the functions of the chip are often split into multiple bare chips, each bare chip is prepared separately, and multiple bare chips are reconstructed into a complete computing system to improve computing power.

[0003] In order to reconstruct multiple bare chips into a complete computing system, it is necessary to accurately transfer data between bare chips, which relies on a certain communication protocol. The communication protocol in the prior art often predefines the number of bytes in each data packet, and then divides the data to be transmitted into multiple data packets containing a fixed number of bytes and transmits each data packet separately. When transmitting each data packet, the sender needs to send an additional notification data packet to notify the receiving end to start transmitting the data packet before starting to transmit the data packet. In this way, an additional notification data packet needs to be sent for each fixed number of bytes transmitted. This method can only divide the data to be transmitted into data packets of fixed size, and the flexibility of the transmission process is low. At the same time, when the number of bytes to be transmitted is large, it needs to be divided into a large number of fixed-size data packets for transmission, and the number of notification data packets to be sent is large, and the transmission efficiency is low. Summary of the invention

[0004] The embodiments of the present disclosure provide a data transmission method, an electronic device and a storage medium, which can reduce the number of data packets used to notify a receiving end when transmitting data between bare chips, improve the flexibility of data transmission between bare chips, and improve the efficiency of data transmission between bare chips.

[0005] According to one aspect of the present disclosure, a data transmission method is provided, which is applied to a first bare chip, wherein the first bare chip includes a transmission module, the transmission module includes a first number of ordered transmission interfaces, and the method includes:

[0006] Acquire a first data amount of data to be transmitted, and convert the first data amount into a corresponding number of binary bytes, wherein the first data amount is used to represent the number of bytes in the data to be transmitted;

[0007] Based on each bit in the number of binary bytes having a value of 1, dividing the data to be transmitted into a plurality of sub-data packets, wherein the number of bytes in a single sub-data packet is determined by taking the number of bits corresponding to the bits in the number of binary bytes having a value of 1 as an exponent of 2;

[0008] Performing a first transmission task on each of the sub-data packets in sequence, the first transmission task comprising: generating a first command packet corresponding to the sub-data packet, and sending the first command packet to the second bare chip through the transmission module, so that the second bare chip returns a response message in response to the first command packet, wherein the first command packet carries a second number, and the second number is used to represent the number of bytes in the sub-data packet; after receiving the response message returned by the second bare chip based on the first command packet, determining a third number based on the first number and the second number, and determining the third number of first clock cycles after receiving the response message as the corresponding sub-data packet transmission clock cycle;

[0009] In a single first clock cycle in the sub-packet transmission clock cycle, a fourth number of bytes in the corresponding sub-packet is sent to the second bare chip through the transmission module, wherein the fourth number of bytes includes an ordered first number of bits, and the ordered first number of bits are respectively transmitted through the ordered first number of transmission interfaces.

[0010] Optionally, generating a first command packet corresponding to the sub-data packet includes:

[0011] Obtain a first command packet template, where the first command packet template includes eight bits;

[0012] Determine an identification code corresponding to the second die, and fill the first three bits of the first command packet template with the identification code;

[0013] The second number is determined based on the number of bytes in the sub-data packet, and the second number is filled into the last five bits of the payload of the first command packet template to obtain the first command packet.

[0014] Optionally, sending the first command packet to the second bare chip through the transmission module includes:

[0015] In response to a first transmission request, a first feature code is generated, and the first feature code is sent to the second die through the transmission module, wherein the first transmission request is a request for the first die to transmit the sub-data packet to the second die, and the first feature code is used to notify the second die to send the first command packet to the second die in at least one subsequent first clock cycle;

[0016] At least one first clock cycle after sending the first feature code, the first command packet is sent to the second bare chip through the transmission module.

[0017] Optionally, after sending the first command packet to the second bare chip through the transmission module, the method further includes:

[0018] Counting a first clock cycle, and stopping counting the first clock cycle after receiving the response information, to obtain a clock cycle count value;

[0019] After receiving the response information returned by the second die based on the first command packet, determining a third number based on the first number and the second number includes:

[0020] In a case where the clock cycle count value is not greater than a first count threshold, determining the third number based on the second number and the first number;

[0021] When the clock cycle count value is greater than the first count threshold value and less than the second count threshold value, a first interrupt packet is generated, and the first interrupt packet is sent to a first central processor corresponding to the first die, so that the first central processor responds to the first interrupt packet and controls the first die to resend the first command packet to the second die after a fifth number of first clock cycles;

[0022] When the count value obtained by counting in the first clock cycle is greater than the second count threshold, a second interrupt packet is generated, and the second interrupt packet is sent to the first central processor corresponding to the first bare chip, so that the first central processor controls the first bare chip to stop sending the sub-data packet to the second bare chip.

[0023] Optionally, the second bare chip returns response information in response to the first command packet, including:

[0024] The second die determines, based on the second number in the first command packet, a first memory space corresponding to the second number, and determines a remaining memory space of the second die;

[0025] In a case where the first memory space is smaller than the remaining memory space, the second die returns the response information to the first die.

[0026] Optionally, in a single first clock cycle in the sub-data packet transmission clock cycle, sending a fourth number of bytes in the corresponding sub-data packet to the second bare chip through the transmission module includes:

[0027] In a first clock cycle of a transmission clock cycle of the sub-data packet, generating a second feature code and sending the second feature code to the second die, wherein the second feature is used to notify the second die that in a subsequent fifth number of clock cycles, the first die sends each byte of the sub-data packet to the second die;

[0028] In a single first clock cycle in the sub-data packet transmission clock cycle, a first number of bits corresponding to a fourth number of bytes are read from a register of the first bare chip, and the first number of bits are sent in parallel to the second bare chip through the first number of transmission interfaces.

[0029] Optionally, the first die is in a first clock domain, the second die is in a second clock domain, the first die includes a first bus transmission module, a first buffer, and a data sending state machine, the first bus transmission module is connected to a data bus of the first die, an input end of the first buffer is connected to the first bus transmission module, an output end of the first buffer is connected to the data sending state machine, the data sending state machine is further connected to the transmission module, the data sending state machine is in a functional clock domain, and sending the corresponding fourth number of bytes in the sub-data packet to the second die through the transmission module includes:

[0030] The first bus transmission module sequentially reads each byte of the sub-data packet from the memory of the first bare chip through the data bus of the first bare chip, writes each read byte into the first buffer at the rising edge of each first clock cycle of the first clock domain, and determines a first reading order according to the order in which each byte is written into the first buffer;

[0031] Through the data sending state machine, at the rising edge of each clock cycle in the functional clock domain, each byte is read from the first buffer in accordance with the first reading order and sent to the transmission module, and the received fourth number of bytes is sent to the second bare chip through the transmission module, so that the second bare chip writes the fourth number of bytes into the memory of the second bare chip at the rising edge of each clock cycle in the second clock domain.

[0032] Optionally, the second die includes a receiving module, the receiving module includes a data receiving state machine, a second buffer and a second bus transmission module, the data receiving state machine is in the functional clock domain, and the second die writes the fourth number of bytes into the memory of the second die at the rising edge of each clock cycle of the second clock domain, including:

[0033] receiving, by the data receiving state machine, a fourth number of bytes sent from the transmission module of the first bare die, and writing the received fourth number of bytes into the second buffer at the rising edge of each clock cycle of the functional clock domain, and determining a second reading order based on the order in which the fourth number of bytes are written into the second buffer;

[0034] At a rising edge of a single second clock cycle in the second clock domain, the second bus transmission module reads the fourth number of bytes from the second buffer in the second reading order and writes the fourth number of bytes to the memory of the second die.

[0035] Optionally, the method further comprises:

[0036] In each of the first clock cycles, generating a valid signal and sending the valid signal to the second bare chip through the transmission module, wherein the valid signal is used to control the working state of the transmission module of the first bare chip and the transmission module of the second bare chip in the corresponding first clock cycle;

[0037] The step of determining a third number of first clock cycles after receiving the response information as a sub-data packet transmission clock cycle comprises:

[0038] In at least one first clock cycle after receiving the response information, the valid signal is switched to a low level signal, and in a sixth number of the first clock cycles, the valid signal is switched to a high level signal;

[0039] Determine a third number of first clock cycles after the valid signal is switched to a high level signal as the sub-data packet transmission clock cycle, and maintain the valid signal as a high level signal during the sub-data packet transmission clock cycle;

[0040] After the sub-data packet transmission clock cycle, the valid signal is switched to a low level signal.

[0041] Optionally, a serial clock signal line is further provided between the first die and the second die, and the method further comprises:

[0042] The first bare die obtains a system clock cycle signal of a multi-chip module, and performs frequency division processing on the system clock cycle signal to obtain a clock cycle signal corresponding to the first clock cycle, wherein the multi-chip module includes the first bare die and the second bare die;

[0043] In each first clock cycle, the clock cycle signal corresponding to the first clock cycle is sent to the second bare die through the serial clock signal line.

[0044] One aspect of the present disclosure also proposes an electronic device, which includes a memory, a processor, a program stored in the memory and executable on the processor, and a data bus for realizing connection and communication between the processor and the memory, wherein the program, when executed by the processor, realizes the data transmission method as described in any one of the above items.

[0045] One aspect of the present disclosure further provides a computer-readable storage medium, wherein the computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the data transmission method as described in any one of the above items.

[0046] The present disclosure proposes a data transmission method, an electronic device and a storage medium, wherein a first data amount used to characterize the number of bytes in the data to be transmitted is converted into a corresponding binary form to obtain a corresponding number of binary bytes, and then the data to be transmitted is divided into a plurality of sub-data packets based on the bits with a value of 1 in each bit of the binary byte number, wherein the number of bytes in a single sub-data packet is determined by taking the number of bits corresponding to the bits with a value of 1 in the binary byte number as an exponent of 2, and the number of bytes in each of the plurality of sub-data packets obtained is an integer power of 2, wherein the number of bytes in the sub-data packet with the largest number of bytes is greater than half of the total number of bytes of the data to be transmitted, and for each sub-data packet, the number of bytes therein is greater than the sum of the number of bytes of all other sub-data packets whose number of bytes is smaller than that of the sub-data packets, so that the data to be transmitted can be flexibly divided according to the number of bytes in the data to be transmitted. The data packet is divided into multiple sub-data packets, and the number of the sub-data packets will not be greater than the number of bits of the binary bytes. When the number of bytes of the data to be transmitted doubles, only one more sub-data packet needs to be divided, which can effectively reduce the number of sub-data packets. At the same time, since the number of bytes of each sub-data packet is an integer power of 2, the exponent of the integer power of 2 can be used as the second number to fill in the corresponding first command packet. After that, when sending each sub-data packet, a first command packet is first sent to the second bare chip to notify the second bare chip of the number of bytes in the sub-data packet that needs to be sent subsequently, and after receiving the response information returned by the second bare chip, the third number is determined based on the first number and the second number, so as to determine each first clock cycle required for transmitting each byte of the data packet to be transmitted. After that, in each first clock cycle, the ordered first number of transmission interfaces respectively send the first number of bits used to constitute the fourth number of bytes to the second bare chip. In the present disclosure, since the first data amount used to characterize the number of bytes in the data to be transmitted is converted into the corresponding number of binary bytes, and the data to be transmitted is divided into multiple sub-data packets based on this, it is possible to flexibly adapt to data to be transmitted of different sizes, divide the data to be transmitted into multiple sub-data packets of different sizes, and ensure that the number of sub-data packets is not greater than the number of bits of the number of binary bytes. Afterwards, before sending each sub-data packet, the exponent when the number of bytes in the sub-data packet is expressed as a positive integer power of 2 is filled into the first command packet as a second number and sent to the second bare chip to notify the second bare chip of the number of bytes of the sub-data packet that needs to be sent subsequently, and after receiving the response information returned by the second bare chip, each byte of the sub-data packet is started to be sent, thereby reducing the number of notification data packets that need to be sent additionally during the transmission process while ensuring that the accuracy of data transmission is not reduced, thereby improving the efficiency of data transmission.

[0047] Other features and advantages of the present disclosure will be described in the following description, and partly become apparent from the description, or understood by practicing the present disclosure. The purpose and other advantages of the present disclosure can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The accompanying drawings are used to provide further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0049] Figure 1 is a system architecture diagram of a data transmission method using an embodiment of the present disclosure;

[0050] Figure 2 is a main flow chart of a data transmission method according to an embodiment of the present disclosure;

[0051] Figure 3 is a schematic diagram of a process of performing data transmission between a first die and a second die based on an embodiment of the present disclosure;

[0052] Figure 4 yes Figure 2 A sub-flow chart of step S203;

[0053] Figure 5 yes Figure 2 A sub-flow chart of step S203;

[0054] Figure 6 yes Figure 2 A sub-flow chart of step S203;

[0055] Figure 7 yes Figure 2 A sub-flow chart of step S204;

[0056] Figure 8 yes Figure 2 A sub-flow chart of step S204;

[0057] Fig. 9 is a partial structural schematic diagram of a first die according to an embodiment of the present disclosure;

[0058] Fig.10 is a schematic diagram of the structure of a receiving module in a second bare chip based on an embodiment of the present disclosure;

[0059] Fig.11 yes Figure 8 A sub-flowchart of step S802;

[0060] Fig.12is a flow chart of an embodiment of counting a first clock cycle based on an embodiment of the present disclosure;

[0061] Fig.13 is a schematic diagram of different situations of receiving response information based on an embodiment of the present disclosure;

[0062] Fig.14 is a flow chart of a first bare chip controlling the working state of a transmission link by sending a valid signal based on an embodiment of the present disclosure;

[0063] Fig.15 is a schematic diagram of a link between a first die and a second die based on an embodiment of the present disclosure;

[0064] Fig.16 This is a schematic diagram of changes in valid signals, data packets and response information under a clock cycle signal based on an embodiment of the present disclosure;

[0065] Fig.17 is a flow chart of a process in which a first die sends a clock signal to a second die to synchronize data transmission based on an embodiment of the present disclosure;

[0066] Fig.18 A system architecture diagram of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0067] In order to make the purpose, technical solution and advantages of the present disclosure more clear, the present disclosure is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present disclosure and are not used to limit the present disclosure.

[0068] Before further describing the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are described. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations:

[0069] Die: refers to the unpackaged semiconductor chip obtained after the wafer is cut and tested. The edge of the die is often designed with pads or small holes for connecting metal wires to the outside through metal wires. Each die contains a large number of transistors and other electronic components to form a complete circuit structure to achieve specific functions. Dies often need to be packaged before they can be used.

[0070] Chiplet: A design method that splits a single system-level chip into multiple independent functional modules, then makes each functional module into a corresponding bare die, and interconnects and packages multiple bare dies that meet specific functions together through die-to-die interconnection technology to form a multi-chip module, using the multi-chip module as a system-level chip.

[0071] With the rapid development of technologies such as high-performance computing and artificial intelligence, the demand for chip computing power is increasing. However, as the chip manufacturing process has approached the physical limit, it is becoming increasingly difficult to integrate more transistors on a single chip to increase chip computing power. In related technologies, a large chip is often divided into multiple dies, and each die is manufactured separately. Then, multiple dies are packaged into a multi-chip module to replace a single large chip, thereby increasing computing power.

[0072] In the related art, in order to make multiple bare chips of a multi-chip module work together to form a complete computing system, it is necessary to have efficient and accurate data transmission between multiple bare chips in the same package. In the related art, bare chips often transmit data to each other based on a certain communication protocol. The related communication protocol often predefines the number of bytes in each data packet, and then divides the data to be transmitted into multiple data packets containing a fixed number of bytes and transmits each data packet separately. When transmitting each data packet, the sender needs to send an additional notification data packet to notify the receiving end to start transmitting the data packet before starting to transmit the data packet. In this way, an additional notification data packet needs to be sent for each fixed number of bytes transmitted. This method can only divide the data to be transmitted into data packets of fixed size, and the flexibility of the transmission process is low. When the number of bytes to be transmitted is large, it needs to be divided into a large number of fixed-size data packets for transmission. The number of notification data packets that need to be sent is large, and the transmission efficiency is low.

[0073] Based on this, the present disclosure provides a data transmission method, an electronic device and a storage medium, which can improve the flexibility of data transmission between bare chips, reduce the number of notification data packets that need to be sent additionally during the transmission process, and improve the efficiency of data transmission.

[0074] Description of the system architecture of the present disclosure embodiment

[0075] Figure 1 The system architecture diagram used in the data transmission method of the embodiment of the present disclosure includes: a first die 110 and a second die 120, wherein the first die includes a transmission module 111, and the transmission module includes a first number of transmission interfaces 112; the first die 110 is a die for sending sub-data packets, and the second die 120 is a die for receiving sub-data packets, and the first die 110 and the second die 120 are both part of the computing system.

[0076] The first bare chip 110 is provided with a unit for controlling the process of the first bare chip sending a sub-data packet to the second bare chip, and is used to generate a first command packet in response to a request of the first bare chip to send a sub-data packet to the second bare chip, and is also used to count the first clock cycle after sending the first command packet until receiving the response information returned by the second bare chip in response to the first command packet, so as to obtain a clock cycle count value, and compare the clock cycle count value with a first counting threshold value, and when the clock cycle count value is less than the first counting threshold value, determine a third number of consecutive first clock cycles as the sub-data packet transmission clock cycle.

[0077] The transmission module 111 is used to transmit the generated first command packet to the second bare chip, and to receive the response information returned by the second bare chip 120 in response to the first command packet. The transmission module 111 is also used to send the fourth number of bytes in the sub-data packet to the second bare chip in each first clock cycle of the sub-data packet transmission clock cycle, wherein each transmission interface 112 sends a single bit in the corresponding fourth number of bytes to the second bare chip in a single first clock cycle.

[0078] Overall implementation of the data transmission method of the disclosed embodiment

[0079] The embodiment of the present disclosure provides a data transmission method, which is applied to a first bare chip. The first bare chip includes a transmission module. Figure 2 , data transmission methods include:

[0080] Step S201, obtaining a first data amount of data to be transmitted, and converting the first data amount into a corresponding number of binary bytes;

[0081] Step S202, dividing the data to be transmitted into a plurality of sub-data packets based on the bits in the binary byte number that are 1, wherein the number of bytes in a single sub-data packet is determined by taking the number of bits corresponding to the bits in the binary byte number that are 1 as an exponent of 2;

[0082] Step S203, sequentially executing a first transmission task for each sub-data packet, the first transmission task comprising: generating a first command packet corresponding to the sub-data packet, and sending the first command packet to the second bare chip through a transmission module, so that the second bare chip returns a response message in response to the first command packet, wherein the first command packet carries a second number, and the second number is used to represent the number of bytes in the sub-data packet; after receiving the response message returned by the second bare chip based on the first command packet, determining a third number based on the first number and the second number, and determining the third number of first clock cycles after receiving the response message as the corresponding sub-data packet transmission clock cycle;

[0083] Step S204, in a single first clock cycle in the sub-packet transmission clock cycle, sending a fourth number of bytes in the corresponding sub-packet to the second bare chip through the transmission module, wherein the fourth number of bytes includes an ordered first number of bits, and the ordered first number of bits are respectively transmitted through the ordered first number of transmission interfaces.

[0084] In step S201, the first data amount is used to characterize the number of bytes in the data to be transmitted, and the binary byte number is data that represents the number of bytes in the data to be transmitted in binary form. Specifically, the first data amount can be determined by detecting the number of bytes in the data to be transmitted, and the binary byte number is obtained by binary conversion based on the first data amount. Exemplarily, the first data amount is 900, that is, the data to be transmitted contains 900 bytes, and the corresponding binary byte number is 1110000100.

[0085] In step S202, after the number of binary bytes is obtained, it can reflect the number of bytes in each sub-packet when each byte of the data to be transmitted is divided into multiple sub-packets. Specifically, the number of bytes in each sub-packet can be expressed as , where n represents the nth bit in the binary byte number, and the lowest bit in the binary byte number is the 0th bit, Indicates the value of the nth bit in the binary byte number. Since the value of each bit in the binary byte number is 0 or 1, based on this, it is only necessary to use the number of bits corresponding to the bits with a value of 1 in the binary byte number as the exponent of 2 to determine the number of bytes in each sub-data packet, thereby dividing the data to be transmitted into corresponding multiple sub-data packets. For example, the first data volume is 900, and the corresponding binary byte number is 1110000100. Among the 0th to 9th bits of the binary byte number, only the 2nd, 7th, 8th, and 9th bits have a value of 1. At this time, the data to be transmitted can be divided into 4 sub-data packets, and the number of bytes in the 4 sub-data packets is respectively , , , , that is, the number of bytes in the 4 sub-packets is 512, 256, 128, and 4 respectively. At this time, the first 512 bytes of the data to be transmitted are divided into the first sub-packet, and the 513th to 768th bytes are divided into the second sub-packet, and so on, the data to be transmitted is divided into the corresponding 4 sub-packets.

[0086] In step S203, the first transmission task is a data transmission task of sending a sub-data packet from the first die to the second die; the first command packet is a command packet used to notify the second die that the first die needs to transmit a sub-data packet of a size corresponding to the second number to the second die, and the length of the first command packet can be 8 bits. The transmission module is a communication link for transmitting data between the first die and the second die. Specifically, the transmission module is composed of a first number of transmission interfaces, and the first number of transmission interfaces can perform data transmission in parallel, wherein the transmission interface can be a high-speed I / O interface, and the high-speed transceiver capability of the high-speed I / O interface is used to enable high-speed data transmission between the first die and the second die. Byte is the unit of data length, that is, byte, and a byte is composed of 8 bits. The response information is a data packet returned by the second die after receiving the first command packet sent by the first die. The response information can be an empty data packet or a data packet filled with a preset characteristic value. The first clock cycle is a clock cycle in the clock domain where the first die is located. It can be understood that the die is essentially an integrated circuit. In the related art, in order to simplify the design process of the die, the die will be operated in a certain clock domain, and the synchronization and stability of the die will be ensured by aligning the various actions of the die with the clock signal. Specifically, a square wave can be generated at a fixed frequency, and one cycle of the square wave can be used as a first clock cycle, or the first clock cycle can be determined based on an external clock signal. The second number is a value used to characterize the number of bytes in the sub-data packet. It can be understood that the first command packet is also a data packet, which represents data through 0 and 1. If the binary form corresponding to the number of bytes in the sub-data packet is directly filled into the first command packet as the second number, the length of the first command packet will be longer. Since the number of bytes in each sub-data packet is an integer power of 2, based on this, the second number can be an exponent after the number of bytes in the sub-data packet is expressed as a power of 2. For example, the number of bytes in a sub-packet is 128, that is, , the corresponding second number is 7, and the corresponding binary form 111 is only needed to be filled into the first command packet to fill the second number of bits. In this way, each time a bit is extended to fill the second number, the number of bytes that can be represented by the first command packet can be greatly increased. For example, when there are only 3 bits in the first command packet to fill the second number, it can represent to bytes, when 5 bits are allocated in the first command packet to fill the second number, it can represent to Only a few bits are needed in the first command packet to represent the number of bytes in the sub-data packet, thereby greatly shortening the length of the first command packet, reducing the time required to transmit the first command packet, and improving the efficiency of data transmission between bare chips.

[0087] It can be understood that since the number of bits used to write the second number in the first command packet is limited, for example, the length of the first command packet is 8 bits, of which only five bits are allocated for writing the second number, in order to enable the first command packet to represent a larger range of byte numbers, in the present disclosure, the second number may also be the exponent of the number of words (word, consisting of 2 bytes), double words (double word, consisting of two words, i.e., four bytes) or quad words (Quad Word, consisting of 4 words, i.e., 8 bytes) constituted by the bytes in the sub-data packet expressed as an integer power of 2.

[0088] In another possible implementation, the second number may be determined by expanding upward to the smallest integer power of 2 based on the number of bytes in the sub-data packet. For example, if the data to be transmitted includes 10k bytes, it is adjusted upward to 16k. At this time, when the second number is represented by the number of quadwords in the sub-data packet, 16k bytes contain 2k quadwords, that is, There are four characters, and at this time, the corresponding second number is 11.

[0089] It is understandable that a number of specific bits are predefined in the first command packet for filling the second number. After the second number is determined, the second number is filled into the corresponding bit in the first command packet. For example, the first command packet is composed of 8 bits, the lower 5 bits are used to represent the second number. When the second number is 11, the corresponding binary form is 01011, then 01011 is filled into the lower 5 bits in the first command packet, that is, bit [4:0] of the first command packet.

[0090] Specifically, when the first die prepares a sub-data packet to be sent to the second die and needs to send the sub-data packet to the second die, the first die can generate a transmission request through a corresponding central processor, and after detecting the transmission request, in response to the transmission request, first detect the length of the sub-data packet, determine the number of bytes in the sub-data packet, thereby determining the corresponding second number, and then fill the second number into the corresponding bit position in the first command packet to obtain the first command packet, and then refer to Figure 3 , sending the first command packet and the corresponding packet header together to the second bare chip.

[0091] It is understandable that if the first chip and the second chip cannot communicate normally, if the first chip sends out each sub-packet, data loss will occur. Based on this, in the present embodiment, after receiving the first command packet sent by the first chip, the second chip will generate corresponding response information based on the first command packet, and send the response information back to the first chip. When the first chip receives the response information returned by the second chip, it indicates that the first chip and the second chip can communicate normally, and the first chip can start to send the corresponding sub-packet to the second chip. At this time, since the second number can reflect the number of bytes in the corresponding sub-packet, and the first number reflects the number of transmission interfaces, that is, the number of bits that can be transmitted in parallel in a single first clock cycle, the number of clock cycles required for the first chip to send all bytes in the sub-packet to the second chip can be determined based on the first number and the second number, that is, the third number is determined. Exemplarily, the second number is 01011, that is, the sub-packet consists of bytes, and the first number is 8, that is, one first clock cycle can transmit 8 bits in parallel, that is, 1 byte. At this time, the corresponding third number is , which will receive the response information after The first clock cycle is determined as the corresponding sub-data packet transmission clock cycle.

[0092] It should be noted that the first die and the second die are relative concepts. When a single die sends a sub-data packet to other die, it is the first die, and when it receives a sub-data packet sent by other die, it is the second die. In addition, executing the corresponding first transmission task for each sub-data packet in sequence means that after sending all bytes of the previous sub-data packet to the second die, the first transmission task is executed for the next sub-data packet.

[0093] In step S204, the fourth number is used to represent the number of bytes that the first bare chip can send to the second bare chip in a single first clock cycle, and the fourth number is determined by the first number, that is, by the number of transmission interfaces in the transmission module. Specifically, in a single first clock cycle, each transmission interface can be used to transmit one bit, and 8 bits constitute one byte. Based on this, the fourth number is the value obtained by dividing the first number by 8. It should be noted that in this embodiment, the number of transmission interfaces included in the transmission module is an integer multiple of 8, that is, the first number is an integer multiple of 8.

[0094] Specifically, after determining the sub-data packet transmission clock cycle, every fourth number of bytes in the sub-data packet are sequentially transmitted in each first clock cycle in the sub-data packet transmission clock cycle. Figure 3, the fourth number is 1. At this time, within a single first clock cycle, the first die sends 1 byte to the second die. At this time, in the first first clock cycle of the sub-data packet transmission clock cycle, byte 1 of the sub-data packet is sent to the second die, and in the second first clock cycle, byte 2 of the sub-data packet is sent to the second die, and so on, until the third number of first clock cycles in the sub-data packet transmission clock cycle is executed, so as to accurately send each byte in the sub-data packet from the first die to the second die in a continuous third number of first clock cycles. At the same time, in each first clock cycle, each bit in the fourth number of bytes of the sub-data packet is respectively allocated to each transmission interface in the transmission module for transmission. Since a single transmission interface is only used to transmit a single bit in a single first clock cycle, and each bit is essentially a high-level or low-level signal, by allocating the ordered first number of bits constituting the fourth number of bytes to the ordered first number of transmission interfaces for transmission, a single transmission interface only transmits one bit in a single first clock cycle. In this way, the anti-interference of each transmission interface during signal transmission can be improved, and the accuracy of each bit transmitted by the transmission interface during transmission can be ensured. At the same time, the transmission efficiency of the sub-data packet can be improved by parallel transmission of multiple transmission interfaces. After receiving the bits transmitted through each transmission interface, the second bare chip can also reassemble each bit into corresponding bytes according to the order of the transmission interface to ensure the accuracy of the sub-data packet transmission process.

[0095] In the embodiment disclosed in step S201 to step S204, the transmission interface is used as a transmission module between the first bare chip and the second bare chip. The first data amount used to characterize the number of bytes in the data to be transmitted is converted into the corresponding number of binary bytes, and the data to be transmitted is divided into a plurality of sub-data packets based on this. In this way, the data to be transmitted of different sizes can be flexibly adapted, and the data to be transmitted is divided into a plurality of sub-data packets of different sizes, ensuring that the number of sub-data packets is not greater than the number of bits of the number of binary bytes. Afterwards, before sending each sub-data packet, the exponent when the number of bytes in the sub-data packet is expressed as a positive integer power of 2 is filled into the first command packet as a second number and sent to the second bare chip to notify the second bare chip of the number of bytes of the sub-data packet to be sent subsequently, and after receiving the response information returned by the second bare chip, each byte of the sub-data packet is started to be sent, thereby reducing the number of notification data packets that need to be sent additionally during the transmission process while ensuring that the accuracy of data transmission is not reduced, thereby improving the efficiency of data transmission.

[0096] Steps S201 to S204 in the data transmission method of the present disclosure are described as a whole. Since step S201 and step S202 have been described in detail above, step S203 and step S204 are described in detail below.

[0097] Detailed description of step S203

[0098] In step S203, a first command packet is generated and sent to the second bare chip through the transmission module, so that the second bare chip returns a response message in response to the first command packet, wherein the first command packet carries a second number, and the second number is used to represent the number of bytes in the sub-data packet.

[0099] In one embodiment, referring to Figure 4 In step S203, a first command packet is generated, including:

[0100] Step S401, obtaining a first command packet template, the first command packet template including eight bits;

[0101] Step S402, determining an identification code corresponding to the second die, and filling the identification code into the first three bits of the first command packet template;

[0102] Step S403, determine the first power corresponding to the sub-packet based on the number of bytes in the sub-packet, and determine the second number corresponding to the sub-packet based on the binary form of the exponent of the first power, and fill the second number into the last five bits of the payload of the first command packet template to obtain the first command packet, wherein the first power is an integer power of 2 corresponding to the number of bytes in the sub-packet.

[0103] In step S401, the first command packet template is a template of a data packet. In the present disclosure, the first command packet template may include 8 bits, wherein the upper three bits of the first command packet template are used to fill in the identification code of the second bare chip for receiving the sub-data packet, that is, receiving the first command packet, and the lower five bits are used to fill in the second number.

[0104] In step S402, the feature code is a set of numbers used as the identification of the second die. It can be understood that in a multi-chip module formed by interconnecting the dies, the number of dies is often more than two, and each die needs to be connected to multiple other dies respectively to achieve multi-die interconnection. In the related art, the number of dies in a multi-chip module generally does not exceed 8. Based on this, in the present disclosure, corresponding identification codes are pre-assigned to the multiple dies connected to the first die. For example, the multi-chip module is composed of 8 dies including the first die, which are respectively recorded as die A, die B, ..., die H, and the corresponding identification codes are 000, 001, 010, 011, 100, 101, 110, 111. At this time, die A needs to send a sub-data packet to die B, that is, die A is used as the first die, and die B is used as the second die. At this time, die A needs to send a first command packet to die B, that is, fill the identification code 010 corresponding to die B into the first three bits of the first command packet template. In this way, when sending the first command packet, the corresponding identification code is obtained by detecting the first three bits of the first command packet, and then the mapping relationship between each identification code and the die is found to determine the second die to be sent to and allocate the first command packet to the corresponding transmission module for transmission.

[0105] In step S403, the first power is a power index when the number of bytes, double words or quad words in the sub-data packet is represented by an integer power of 2. Specifically, the number of bytes in the sub-data packet is detected, and the corresponding first power can be determined based on the number of bytes, and the binary form corresponding to the exponent of the first power is used as the second number. Exemplarily, in the present disclosure, the second number is an exponent when the number of quad words in the sub-data packet is represented by an integer power of 2. For example, the sub-data packet contains 128 bytes, that is, 16 quad words, and 16 can be represented as At this time, the corresponding second number is 4. After conversion into binary, the result is 00100. At this time, 00100 is filled into the last five bits of the first command packet template to obtain the first command packet.

[0106] For example, when the first die needs to send a sub-data packet consisting of 128 bytes to the die with the identification code of 010, the corresponding first command packet can be represented as 01000100.

[0107] In the embodiment disclosed in steps S401 to S403, the identification code of the bare chip required to receive the sub-data packet is obtained, the identification code is filled into the first three bits of the first command packet template, and the number of bytes in the sub-data packet is detected, and the corresponding second number is calculated and filled into the last five bits of the first command packet template, so as to obtain the first command packet. In this way, when sending the first command packet, the corresponding second bare chip is determined by detecting the first three bits of the first command packet and the first command packet is sent through the corresponding transmission module to send the first command packet to the second bare chip, so that the second bare chip determines the number of bytes in the sub-data packet that needs to be received by detecting the last five bits in the first command packet.

[0108] In one embodiment, referring to Figure 5 In step S203, sending the first command packet to the second bare chip through the transmission module includes:

[0109] Step S501, in response to a first transmission request, generating a first feature code, and sending the first feature code to a second bare chip through a transmission module;

[0110] Step S502: at least one first clock cycle after sending the first feature code, sending the first command packet to the second bare chip through the transmission module.

[0111] In step S501, the first transmission request is a request for the first die to transmit a sub-data packet to the second die; the first feature code is used to notify the second die that the first die sends a first command packet to the second die in at least one subsequent first clock cycle. It can be understood that the data packet from the first die to the second die includes at least two types of first command packets and sub-data packets, and the second die needs to perform different processing corresponding to different types of data packets. For example, when the type of the received data packet is the first command packet, the second die needs to return a response message to the first die, and when the type of the received data packet is the sub-data packet, it is necessary to store each received byte locally in the second die. Based on this, before sending different types of data packets, the first die needs to send a specific feature code to the second die, so that the second die determines the type of the data packet received from the first die later and performs corresponding processing. Based on this, in this embodiment, when it is detected that the first die needs to send a first transmission request of a sub-data packet to the second die, the first feature code is generated first, so that the second die determines that the type of the data packet sent by the first die in at least one subsequent first clock cycle is the first command packet. Exemplarily, the first feature code may be a preconfigured set of specific digital combinations, for example, the first feature code may be 0xFA, which may be expressed as 11111010 in binary. The first feature code is then filled into each bit of a data packet, and is distributed to each transmission interface of the transmission module, and sent to the second die, so that the second die determines that the type of the data packet sent by the first die in at least one subsequent first clock cycle is a first command packet, and in response to the first command packet, returns a response message to the first die.

[0112] In step S502, after the first feature code is sent to the second bare chip, a first command packet is sent to the second bare chip in at least one first clock cycle thereafter. It is understandable that after the first feature code is sent so that the second bare chip determines that the type of the data packet subsequently sent by the first bare chip is the first command packet, the first command packet is continuously sent to the second bare chip in each first clock cycle before receiving the response information returned by the second bare chip, so as to avoid the second bare chip failing to receive the first command packet due to link fluctuation. Specifically, the first command packet may be sent to the second bare chip starting from the first clock cycle next to the first clock cycle in which the first feature code is sent until the response information returned by the second bare chip is received.

[0113] In the embodiment disclosed in step S501 to step S502, before sending the first command packet, the first feature code corresponding to the first command packet is sent to the second bare chip, so that the second bare chip determines that the type of the data packet sent by the first bare chip in at least one subsequent first clock cycle is the first command packet based on the received first feature code. Afterwards, the first bare chip sends the first command packet to the second bare chip in at least one first clock cycle after sending the first feature code, so that the second bare chip returns response information based on the first command packet sent by the first bare chip.

[0114] In step S203, after receiving the first command packet sent by the first die, the second die needs to return a response message to the first die. In one embodiment, refer to Figure 6 In step S203, the second bare chip returns a response message in response to the first command packet, including:

[0115] Step S601, the second die determines a first memory space corresponding to the second number based on the second number in the first command packet, and determines a remaining memory space of the second die;

[0116] Step S602: When the first memory space is smaller than the remaining memory space, the second die returns a response message to the first die.

[0117] In step S601, the first memory space refers to the memory space required to be occupied by the number of bytes of the sub-data packet determined based on the second number; the remaining memory space refers to the remaining space in the local memory space of the second die where no data is stored. It is understandable that the memory space of the second die is limited. When the remaining memory space of the second die is insufficient to store the sub-data packet, if the first die transmits the sub-data packet to the second die, it will cause memory overflow and lose part of the data. Based on this, after receiving the first command packet, the second die needs to detect the last five bits in the first command packet to obtain the second number, and determine the number of bytes of the sub-data packet based on the second number, thereby determining the size of the memory space required to be occupied by the sub-data packet, i.e., the first memory space, and at the same time detect the remaining amount of the local memory space of the second die. Specifically, in this embodiment, the second number is used to represent the number of four words in the sub-data packet. Based on this, in this embodiment, the second number is converted from binary to decimal, and the conversion result is used as the exponent of 2 to determine the number of four words in the sub-data packet. A four-word contains 8 bytes, so the number of bytes in the sub-data packet can be determined, thereby determining the size of the memory space occupied by the sub-data packet. Exemplarily, the first command packet is 01000100, and the last five bits are detected to obtain 00100, which is converted to decimal to be 4, representing the sub-data packet. Four words, that is, 128 bytes, and the corresponding first memory space is 128 bytes.

[0118] In step S602, it can be understood that when the first memory space is smaller than the remaining memory space, it means that the remaining memory space of the second die is sufficient to store the sub-data packet sent by the first die. At this time, the second die returns a response message to the first die, notifying the first die that the sub-data packet can be sent to the second die. On the contrary, when the first memory space is larger than the remaining memory space of the second die, it means that the remaining memory of the second die is insufficient to store the sub-data packet sent by the first die. At this time, the second die does not return a response message to the first die, so as to avoid the first die from transmitting the sub-data packet to the second die, thereby avoiding the loss of part of the data in the sub-data packet due to insufficient remaining memory space of the second die.

[0119] In the embodiment disclosed in steps S601 to S602, after receiving the first command packet, the second bare chip first detects the second number in the first command packet, and determines the size of the memory space required to store the number of bytes represented by the second number, obtains the first memory space, and simultaneously detects the size of the remaining memory space locally of the second bare chip. Thereafter, the sizes of the first memory space and the remaining memory space are compared. When the first memory space is smaller than the remaining memory space, it indicates that the remaining memory of the second bare chip is sufficient to store the sub-data packet. At this time, the second bare chip returns a response message to the first bare chip, thereby ensuring the integrity of the sub-data packet after being transmitted to the second bare chip, and avoiding the loss of part of the data in the sub-data packet due to insufficient memory space of the second bare chip.

[0120] Detailed description of step S204

[0121] In one embodiment, referring to Figure 7 In step S204, in a single first clock cycle in the sub-data packet transmission clock cycle, the first bare chip sends a fourth number of bytes to the second bare chip through the transmission module, including:

[0122] Step S701, in the first clock cycle of the sub-data packet transmission clock cycle, generating a second feature code and sending the second feature code to the second bare chip;

[0123] Step S702 , in a single first clock cycle in a sub-data packet transmission clock cycle, read a first number of bits corresponding to a fourth number of bytes from a register of the first bare chip, and send the first number of bits in parallel to the second bare chip through a first number of transmission interfaces.

[0124] In step S701, the second feature code is used to notify the second die that in the subsequent fifth number of clock cycles, the first die sends each byte of the sub-data packet to the second die, where the fifth number is the third number minus 1. Specifically, the second feature code may be pre-configured. For example, the second feature code may be 0x5F, which is 01011111 after conversion to binary. Specifically, since the first die can send different types of data packets such as the first command packet and the sub-data packet to the second die, the second die needs to take different processing methods after receiving different types of data packets. Before sending the sub-data packet, the first die needs to first notify the second die that the type of the data packet to be sent subsequently is a sub-data packet. Based on this, in this embodiment, by first sending the second feature code to the second die in the first first clock cycle in the sub-data packet transmission clock cycle, the second die determines that the type of the data packet subsequently received from the first die is a sub-data packet, and stores the received sub-data packet in the memory space of the second die.

[0125] In step S702, in each first clock cycle of the fifth number of first clock cycles after sending the second feature code, the fourth number of bytes of the sub-data packet are read in sequence from the register of the first bare chip, and then the first number of bits constituting the fourth number of bytes are allocated to the first number of transmission interfaces of the transmission module and transmitted in parallel to the second bare chip. After that, the second bare chip writes each received byte in sequence into the memory space for storage until the fifth number of first clock cycles are executed, and the second bare chip can receive the complete sub-data packet.

[0126] In this embodiment, the second die is notified of the number of bytes in the sub-data packet that needs to be transmitted later in the first command packet, and then the second die is enabled to determine that the first die starts to transmit each byte in the sub-data packet through the second feature code, and then the bytes in the sub-data packet are transmitted to the second die, thereby ensuring the accuracy of the transmission process of the sub-data packet. In addition, because the first command packet and the second feature code are used to make the second die sense the first first clock cycle and the number of required first clock cycles of the transmission sub-data packet before transmitting each byte of the sub-data packet, in the process of transmitting each byte, after sending each byte, the first die does not need to wait to receive an additional response from the second die and start transmitting the next byte after receiving the response. The process of the first die sending each byte of the sub-data packet is continuous, so that the transmission delay of each clock cycle can overlap with the transmission process of the next clock cycle, so that the data transmission process is no longer sensitive to the delay caused by the transmission path itself, and the data transmission efficiency between the die is ensured.

[0127] In step S701 to step S702, before transmitting the sub-data packet, a second feature code is generated and sent to the second bare chip, so that the second bare chip determines that the data packet sent by the first bare chip in the subsequent multiple first clock cycles is a sub-data packet, and in each first clock cycle of the fifth number of first clock cycles, the fourth number of bytes are sequentially read from the register of the first bare chip, and the first number of bits constituting the fourth number of bytes are allocated to the first number of transmission interfaces of the transmission module, and transmitted to the second bare chip in parallel. By first sending a first command packet to notify the second bare chip of the number of bytes included in the sub-data packet, and then using the second feature code to enable the second bare chip to determine that the data packet sent by the first bare chip in the subsequent multiple first clock cycles is a sub-data packet, the accuracy of the transmission process is ensured, and at the same time, the first bare chip can continuously send each byte in the sub-data packet to the second bare chip, so that the data transmission process is no longer sensitive to the delay caused by the transmission path itself, and the data transmission efficiency between the bare chips is ensured.

[0128] In one embodiment, the first die and the second die operate in different clock domains. In this case, the transmission of a data packet from the first die to the second die involves data transmission across clock domains. If data is directly transmitted across clock domains, a metastable state may occur, resulting in errors in the data transmission process. Based on this, in one embodiment, referring to Figure 8 , the first die is in the first clock domain, and the second die is in the second clock domain. In step S204, the first die sends a fourth number of bytes to the second die through the transmission module, including:

[0129] Step S801: the first bus transmission module sequentially reads each byte of the sub-data packet from the memory of the first bare chip through the data bus of the first bare chip, writes each read byte into the first buffer at the rising edge of each first clock cycle of the first clock domain, and determines a first reading order according to the order in which each byte is written into the first buffer;

[0130] Step S802, through the data sending state machine, at the rising edge of each clock cycle in the functional clock domain, each byte is read from the first buffer in accordance with the first reading order and sent to the transmission module, and the received fourth number of bytes is sent to the second bare chip through the transmission module, so that the second bare chip writes the fourth number of bytes into the memory of the second bare chip at the rising edge of each clock cycle in the second clock domain.

[0131] Specifically, refer to Fig. 9The first bare chip includes a first bus transmission module, a first buffer and a data sending state machine. The first bus transmission module is connected to the data bus of the first bare chip, the input end of the first buffer is connected to the first bus transmission module, the output end of the first buffer is connected to the data sending state machine, the data sending state machine is also connected to the transmission module, and the data sending state machine is in the functional clock domain.

[0132] In step S801, the first bus transmission module is a module connected to the data bus inside the first bare chip. The first bus transmission module can call the data bus of the first bare chip, read each byte of the sub-data packet from the memory of the first bare chip, and write the read bytes into the first buffer in sequence for caching at the rising edge of each first clock cycle of the first clock domain in which the first bare chip works. By reading data from the memory of the first bare chip at the rising edge of each first clock cycle, it can be ensured that each byte can be read under a certain clock signal, thereby avoiding the occurrence of a metastable state when reading each byte from the memory space of the first bare chip.

[0133] In addition, since the bit width supported by the data bus of the first die is often greater than the bit width supported by the transmission module, for example, the bit width of the data bus inside the first die can reach 64 bits, while the transmission module often only supports 8 bits or 16 bits. In a single clock cycle, 64 bits of data in the memory of the first die can be read through the data bus, while the transmission module can only transmit 8 bits or 16 bits in a single clock cycle. In this way, each byte of the sub-data packet can be read from the memory space of the first die by calling the data bus and written into the first buffer for caching. Subsequently, the corresponding bytes can be directly read from the first buffer and sent to the second die through the transmission module, without calling the data bus of the first die to access the memory space of the first die when sending the corresponding bytes, thereby reducing the time required for data transmission and improving transmission efficiency.

[0134] It is understandable that after writing each byte of the sub-data packet into the first buffer, each byte needs to be sent to the second bare chip in an accurate order. Based on this, it is necessary to record the order in which each byte is written into the first buffer as the first reading order, so that each byte can be read from the first buffer in the first reading order and sent to the second bare chip through the transmission module, so as to maintain the accuracy of the transmission order of each byte, thereby ensuring the accuracy of the transmission process of the sub-data packet. Specifically, the first buffer can be a first-in first-out (FIFO) cache, and the rising edge of each first clock cycle can be detected by edge detection counting, so that each byte of the sub-data packet can be read from the memory of the first bare chip through the data bus at the rising edge of each first clock cycle, and each byte is stored in the first buffer. At this time, the first buffer will record the writing order of each byte. When reading bytes from the first buffer later, they will be read in the order in which each byte is written into the first buffer, that is, the byte written into the first buffer first will be read first.

[0135] In step S802, the data transmission state machine is in the functional clock domain, which is another clock domain independent of the first clock domain in which the first die works and the second clock domain in which the second die works. Specifically, the first buffer acts as a transition buffer, and its write data interface works in the first clock domain, so as to write each byte read from the memory of the first die into the first buffer at each rising edge of the first clock cycle; the read data interface of the first buffer works in the functional clock domain, and the data transmission state machine reads the corresponding fourth number of bytes from the first buffer at the rising edge of each clock cycle of the functional clock domain, and distributes the first number of bits constituting the fourth number of bytes to the first number of transmission interfaces for transmission, so that the sub-data packet crosses from the first clock domain where the first die is located to the transition functional clock domain, so as to subsequently transition from the functional clock domain to the second clock domain where the second die is located, so that the sub-data packet can maintain accuracy during the transmission process across clock domains.

[0136] Specifically, since the first buffer is a first-in-first-out cache, when the data sending state machine reads data from the first buffer, it will read the bytes first written into the first buffer and transmit them to the transmission module, thereby forming a first-in-first-out method, ensuring the accuracy of the transmission order of each byte of the sub-data packet, so that each byte of the sub-data packet can be accurately transmitted to the second bare chip.

[0137] After the fourth number of bytes are sent to the second bare chip through the transmission module, the second bare chip, as a receiving end, can be provided with a second buffer, so that each received byte is written into the second buffer, and the written bytes are read from the second buffer at the rising edge of each clock cycle in the second clock domain, so that each byte is converted from the functional clock domain to the second clock domain, thereby realizing the transmission of each byte of the sub-data packet across clock domains.

[0138] In the embodiment disclosed in step S801 to step S802, at the rising edge of each first clock cycle, the data bus of the first bare chip is called through the first bus transmission module, each byte of the sub-data packet is read from the memory of the first bare chip, and written into the first buffer, and then the data packet sending state machine reads the fourth number of bytes from the first buffer in sequence and transmits them to each transmission interface at the rising edge of each clock cycle of the functional clock domain in the order when each byte is written into the first buffer, and transmits them to each transmission interface, by making the write data interface and the read data interface of the first buffer work in different clock domains respectively, so that each byte can be transferred from the first clock domain to the functional clock domain during the transmission process. Afterwards, when the second bare chip receives each byte, it transfers from the functional clock domain to the second clock domain where the second bare chip is located, thereby realizing data transmission across clock domains, and avoiding the occurrence of metastable conditions during the cross-clock domain transmission process, thereby ensuring the accuracy of the data transmission process.

[0139] In one embodiment, referring to Fig.10 The second bare chip includes a receiving module, the receiving module includes a data receiving state machine, a second buffer and a second bus transmission module, referring to Fig.11 , the second die writes a fourth number of bytes into the memory of the second die at the rising edge of each clock cycle of the second clock domain, including:

[0140] Step S1101, receiving a fourth number of bytes sent from a transmission module of a first bare chip through a data receiving state machine, and writing the received fourth number of bytes into a second buffer at a rising edge of each clock cycle of a functional clock domain, and determining a second reading order based on an order in which the fourth number of bytes are written into the second buffer;

[0141] Step S1102 , at a rising edge of a single second clock cycle in a second clock domain, the second bus transmission module reads a fourth number of bytes from the second buffer in a second reading order, and writes the fourth number of bytes into the memory of the second die.

[0142] In step S1101, the second die includes a receiving module, which is a unit for receiving data packets sent by the first die through the transmission module. Specifically, the receiving module may include multiple receiving interfaces, which are connected to the transmission interface of the first die, so as to receive each byte sent by the first die and transmit it to the data receiving state machine. Fig.10 The data receiving state machine and the data sending state machine in the first bare chip are in the same functional clock domain. After receiving each byte sent by the first bare chip, the data receiving state machine will write each received byte into the second buffer of the receiving module at the rising edge of each clock cycle of the functional clock domain. Similar to the first buffer, the second buffer is also a first-in-first-out cache. The second buffer will record the order in which each byte is written into the second buffer as the second reading order.

[0143] In step S1102, similar to the first buffer, the second buffer acts as an intermediate buffer, the write data interface of the second buffer operates in the functional clock domain, and the read data interface operates in the second clock domain of the second die. The second bus transmission module can read each byte of the received sub-data packet from the second buffer at the rising edge of each clock cycle of the second clock domain, and at the same time call the data bus of the second die to write each byte read from the second buffer into the memory space of the second die, thereby completing the storage of each byte of the sub-data packet.

[0144] In the embodiment disclosed in step S1101 to step S1102, by setting a receiving module including a data receiving state machine, a second buffer and a second bus transmission module on the second die, since the data receiving state machine and the data sending state machine of the first die are in the same clock domain, each byte can be maintained in the same clock domain when being transmitted from the first die to the second die through the transmission module, thereby ensuring that no metastable state occurs during the transmission process. After the second die receives each byte sent by the first die, the data receiving state machine writes each received byte into the second buffer in sequence at the rising edge of each clock cycle in the functional clock domain, and then the second bus transmission module reads each written byte from the second buffer at the rising edge of each clock cycle in the second clock domain, and calls the data bus of the second die to write the bytes read from the second buffer into the memory of the second die, thereby realizing cross-clock domain data transmission from the functional clock domain to the second clock domain, and ensuring the accuracy of the data transmission process.

[0145] Embodiment of counting the first clock cycle after sending the first command packet

[0146] In one embodiment, referring to Fig.12In step S203, after the first command packet is sent to the second bare chip through the transmission module, the method further includes:

[0147] Step S1201, counting a first clock cycle, and stopping counting the first clock cycle after receiving a response message, to obtain a clock cycle count value;

[0148] In step S203, after receiving the response information returned by the second bare chip based on the first command packet, determining the third number based on the first number and the second number includes:

[0149] Step S1202, when the clock cycle count value is not greater than the first count threshold, determining a third number based on the second number and the first number;

[0150] Step S1203, when the clock cycle count value is greater than the first count threshold value and not greater than the second count threshold value, generating a first interrupt packet, and sending the first interrupt packet to a first central processor corresponding to the first die, so that the first central processor responds to the first interrupt packet and controls the first die to resend the first command packet to the second die after the fifth number of first clock cycles;

[0151] Step S1204, when the count value obtained by counting in the first clock cycle is greater than the second count threshold, a second interrupt packet is generated and sent to the first central processor corresponding to the first die, so that the first central processor controls the first die to stop sending sub-data packets to the second die.

[0152] In step S1201 , the clock cycle count value is the number of first clock cycles from when the first die sends the first command packet to when the second die receives response information returned based on the first command packet.

[0153] It can be understood that after the first bare chip sends the first command packet, referring to Figure 3 After receiving the first command packet sent by the first die, the second die will generate corresponding response information and send it to the first die. In the first die, by counting the first clock cycle until the response information returned by the second die in response to the first command packet is received, the first clock cycle is stopped, thereby determining the number of first clock cycles required to send the first command packet to the second die and receive the response information returned by the second die, and obtaining the clock cycle count value. In this way, since the duration of each first clock cycle is fixed, counting the first clock cycle can determine the total duration required for the first die to send the first command packet to the second die and for the second die to return the response information to the first die after receiving the first command packet.

[0154] Specifically, each first clock cycle includes a rising edge and a falling edge, and the first clock cycle can be counted by writing data to a register of the first bare chip. After the first bare chip sends the first command packet to the second bare chip, the value stored in the register is initialized, and then the value in the register is updated at the rising edge of each first clock cycle, that is, each time a rising edge is detected, the value in the register is increased by 1, so that the first clock cycle is counted until the response information returned by the second bare chip is received, and the value in the register is stopped to obtain the clock cycle count value. In this way, the value in the register is updated at each rising edge of the first clock cycle, so that the action of the first bare chip is aligned with the clock signal of the first clock cycle, so as to ensure the synchronization and stability of the bare chips.

[0155] In step S1202, the first counting threshold is a preset value, and the first counting threshold can be stored in a designated threshold register of the first bare chip. Specifically, the first counting threshold can be determined according to the size of the first command packet, the size of the response information, and the number of transmission interfaces. Exemplarily, the first command packet is composed of M bits, the response information is composed of N bits, and the number of transmission interfaces of the transmission module is 8. Since a single transmission interface only transmits one bit in a single first clock cycle when transmitting the sub-data packet later, in order to ensure the consistency of the delay, when determining the first counting threshold, it is also set to transmit only a single bit in the first command packet or the response information in a single first clock cycle by a single transmission interface. At this time, the first bare chip is All bits of the first command packet can be sent through the transmission interface in the first clock cycle. Similarly, the second bare chip All bits of the response information can be sent in the first clock cycle. At this time, the first counting threshold can be + +X, where X is an integer not less than 0 and represents the allowed delay caused by the transmission module itself. Represents the ceiling function.

[0156] The threshold register may be a 16-bit register, and the first counting threshold fills the lower 8 bits in the threshold register, i.e., reg(0x16)[7:0]; when the clock cycle count value is less than the first counting threshold, it indicates that the transmission module between the first die and the second die is relatively idle, and the delay of data transmission between the first die and the second die is low, and the sub-data packet can be sent from the first die to the second die through the transmission module. At this time, the third number is determined based on the first number and the second number, the first number is the number of transmission interfaces of the transmission module, and in a single first clock cycle, a single transmission interface can transmit one bit, and at this time, the third number represents the number of first clock cycles required to transmit the number of bytes represented by the second number to the second die through the first number of transmission interfaces, that is, the number of first clock cycles required to transmit the sub-data packet from the first die to the second die. Exemplarily, the first number is 8, at this time, in a single first clock cycle, the first die can transmit 8 bits, that is, 1 byte, to the second die, the second number represents the number of four words in the sub-data packet, the second number is 512, then the sub-data packet includes 4k bytes, the third number is 4k, that is, 4k first clock cycles are required to transmit the sub-data packet from the first die to the second die. Thus, by comparing the clock cycle count value with the first count threshold, the time required for the first die to send the first command packet to the second die through the transmission module and the second die to return the response information to the first die through the transmission module is determined, thereby determining the delay caused by the transmission module between the first die and the second die to the data transmission and the reliability of the transmission module. The sub-data packet is transmitted only when and only when the clock cycle count value is less than the first count threshold, that is, the delay caused by the transmission module between the first die and the second die to the data transmission is low and the transmission module is available, thereby ensuring that the sub-data packet can be transmitted between the first die and the second die at high speed and accurately.

[0157] After determining the third number, the third number of consecutive first clock cycles after receiving the response information is used as the sub-data packet transmission clock cycle. Specifically, starting from the next first clock cycle of the first clock cycle of receiving the response information, the third number of consecutive first clock cycles can be determined as the sub-data packet transmission clock cycle. Exemplarily, the third number is 4k, the first clock cycle of receiving the response information is recorded as the first clock cycle clk_1, the next first clock cycle of clk_1 is clk_2, and so on. At this time, clk_2 to clk_4k+1 are used as the sub-data packet transmission clock cycles. Therefore, when the clock cycle count value is less than the first count threshold, that is, when the transmission module between the first bare chip and the second bare chip is reliable and the delay is low, the third number is determined based on the first number and the second number, and the third number of first clock cycles is determined as the sub-data packet transmission clock cycle. In this way, it can be ensured that during the transmission of the sub-data packet, the delay of the transmission module is low. Therefore, by directly using a high-speed I / O interface as a transmission interface between the first bare chip and the second bare chip, and before transmitting the data packet, the first bare chip sends a first command packet to the second bare chip to configure the number of first clock cycles required for the subsequent transmission of the sub-data packet and detect the delay and reliability of the transmission module, the sub-data packet can be transmitted between the first bare chip and the second bare chip with low delay and accurately.

[0158] In one possible implementation, after the first clock cycle of receiving the response information, a single first clock cycle after a certain number of first time cycles is used as the start, and a third number of consecutive first clock cycles are used as the sub-packet transmission clock cycle. In this way, a certain number of first clock cycles may be spaced from receiving the response information to starting to send the sub-packet to perform additional processing. For example, in the certain number of first clock cycles, the first die sends an additional data packet to the second die to notify the second die that the first die will send each byte in the sub-packet in sequence in the subsequent multiple first clock cycles.

[0159] In step S1203, the second counting threshold is a preset value, and it can be understood that the second counting threshold is greater than the first counting threshold. In one embodiment, the second counting threshold can be stored in a threshold register of the first die, and the threshold register refers to a register in the first die allocated to store the first counting threshold and the second counting threshold. Exemplarily, the threshold register can be a 16-bit register, wherein the second counting threshold is stored in the upper 8 bits of the threshold register, recorded as reg(0x16)[15:8], and the first counting threshold is stored in the lower 8 bits of the threshold register, recorded as reg(0x16)[7:0]. When the clock cycle count value is greater than the first count threshold value and not greater than the second count threshold value, it indicates that the second die can receive the first command packet and return the corresponding response information to the first die, and the transmission module is available. However, it takes a long time to send the first command packet to the second die and receive the returned response information from the second die. At this time, the second die itself is in a busy response state and cannot respond to the first command packet in time, or the transmission module is occupied or interfered, resulting in a long delay in transmitting data. At this time, if the sub-data packet is sent to the second die, on the one hand, it may be that the second die is currently processing other tasks and cannot write each byte sent by the first die into the corresponding memory space for storage in time and accurately. On the other hand, it may be that the bytes sent by the first die in multiple first clock cycles are accumulated in the transmission module due to the congestion of the transmission module, resulting in the loss of part of the data in the data packet. Based on this, at this time, the first die does not send the sub-data packet to the second die, generates a first interrupt packet and sends it to the first central processor corresponding to the first die, so that the first central processor determines that the transmission of the sub-data packet to the second die has been interrupted. At the same time, since the response information returned by the second bare chip can be received at this time, that is, the transmission module between the first bare chip and the second bare chip is available, and currently only the second bare chip itself is in a busy response state or the transmission module is congested and cannot return the response information in time, therefore, the first command packet can be re-sent to the second bare chip after an interval of the fifth number of first clock cycles to re-detect the total time required for sending the first command packet to the second bare chip through the transmission module and receiving the response information returned by the second bare chip, so as to determine whether the sub-data packet can be transmitted to the second bare chip.

[0160] In step S1204, after sending the first command packet, the first clock cycle is counted, and the counting result is stored in a corresponding register. When the value stored in the register is greater than the second counting threshold, that is, after the second counting threshold number of first clock cycles, the response information returned by the second bare chip in response to the first command packet is still not received, at this time, it can be considered that the first command packet sent by the first bare chip cannot be transmitted to the second bare chip through the transmission module, and the process of transmitting data between the first bare chip and the second bare chip has timed out. Based on this, a second interrupt packet is generated and sent to the central processor of the first bare chip, so that the first central processor controls the first bare chip to stop sending the sub-data packet to the second bare chip, thereby avoiding the loss of data in the sub-data packet.

[0161] Specifically, refer to Fig.13 In the first clock cycle of sending the first command packet, the clock cycle count value is initialized to 0, and then the first clock cycle is counted. At this time, when the response information returned by the second bare chip is received, the clock cycle count value does not exceed the first count threshold, and the bytes of the sub-data packet can be transmitted in the subsequent multiple first clock cycles; when the response information is received, the clock cycle count value is greater than the first count threshold but not greater than the second count threshold, then after an interval of several first clock cycles, the first command packet is re-sent to the second bare chip; when the clock cycle count value is greater than the second count threshold and the response information returned by the second bare chip is not received, at this time, the transmission task of the sub-data packet is terminated.

[0162] In the embodiment disclosed in step S1201 to step S1202, after sending the first command packet, the clock cycle count value is obtained by counting the first clock cycle to determine the path delay between the first die and the second die. When the clock cycle count value is not greater than the first count threshold, it means that the path delay is low. At this time, the third number is determined based on the first number and the second number, so as to determine the sub-data packet transmission clock cycle, and the sub-data packet transmission is directly started. When the clock cycle count value is greater than the first count threshold and not greater than the second count threshold, it means that the transmission module between the first die and the second die is available, and the delay of transmitting data between the first die and the second die through the transmission module is large. At this time, a first interrupt packet is generated to notify the first central processor corresponding to the first die, so that the first central processor controls the first die to re-send the first command packet to the second die after a certain number of first clock cycles and restarts counting the first clock cycle to determine whether the delay of transmitting data between the first die and the second die is reduced to less than the first count threshold. When the result of counting the first clock cycle is greater than the second counting threshold, it means that within the second counting threshold number of first clock cycles, the first die has not received the response information returned by the second die, which can be regarded as the time required for data transmission between the first die and the second die has timed out, and the transmission module between the first die and the second die is faulty. At this time, a second interrupt packet is generated and sent to the first central processor corresponding to the first die, so that the first central processor controls the first die to stop sending sub-data packets to the second die. Therefore, the sub-data packets are transmitted only when and only when the path delay between the first die and the second die is low, so that the sub-data packets can be transmitted accurately with low delay between the first die and the second die.

[0163] Implementation method for sending valid signals and clock signals in each clock cycle

[0164] In one embodiment, referring to Fig.14 , the data transmission method further includes:

[0165] Step S1401, in each first clock cycle, generating a valid signal and sending the valid signal to the second bare chip through a transmission module;

[0166] Determining a third number of first clock cycles after receiving the response information as a sub-data packet transmission clock cycle includes:

[0167] Step S1402, switching the valid signal to a low level signal in at least one first clock cycle after receiving the response information, and switching the valid signal to a high level signal in a sixth number of first clock cycles;

[0168] Step S1403, determining the third number of first clock cycles after the valid signal is switched to the high level signal as the sub-data packet transmission clock cycle, and maintaining the valid signal as the high level signal during the sub-data packet transmission clock cycle;

[0169] Step S1404: after the sub-data packet transmission clock cycle, the valid signal is switched to a low level signal.

[0170] In step S1401, the valid signal is used to control the working state of the transmission module of the first bare chip and the transmission module of the second bare chip in the corresponding first clock cycle. When the valid signal is a high-level signal, the transmission module is in a working state. At this time, the transmission module is still performing the corresponding data packet transmission task, and the second bare chip can receive data transmitted by the transmission module; when the valid signal is a low-level signal, the transmission module is in a non-working state, which indicates that the transmission module has completed the transmission task of the previous set of data and has not started the next data transmission task. When the second bare chip detects that the valid signal is a low-level signal, it stops receiving data transmitted from the transmission module. By sending a valid signal to control whether the second bare chip receives the data transmitted by the transmission module, based on this, the second bare chip can accurately receive each byte in the sub-packet transmitted by the first bare chip through the transmission module by accurately configuring the value of the valid signal corresponding to each first clock cycle. Specifically, refer to Fig.15 Between the first die and the second die, a valid signal can be synchronously sent to the second die while a data packet is sent using the transmission interface in each first clock cycle.

[0171] In step S1402, refer to Fig.16 , in the first first clock cycle of transmitting the first command packet, the valid signal is set to a high level signal, and the first feature code 0xFA is sent. In the next first clock cycle of sending the first feature code 0xFA, the valid signal is maintained as a high level signal and the first command packet is started to be transmitted. Before receiving the response information returned by the second bare chip, the valid signal is maintained as a high level signal to continuously send the first command packet to the second bare chip. After receiving the response information returned by the second bare chip, in the next first clock cycle after receiving the response information, the valid signal is set to a low level signal to make the second bare chip stop receiving data from the transmission module and determine that the transmission phase of the first command packet has ended. Afterwards, after the sixth number of first clock cycles, it is necessary to start transmitting each byte of the sub-data packet. Therefore, after the sixth number of first clock cycles, the valid signal is switched to a high level to make the second bare chip start receiving data transmitted by the transmission module. For example, refer to Fig.16After receiving the response information and in the next first clock cycle, the valid signal is set to a low level, and the valid signal is maintained as a low level signal within a first clock cycle, and then the valid signal is set to a high level signal to start transmitting each byte of the sub-data packet.

[0172] In step S1403, after the valid signal is switched to a high level signal, it means that the first bare chip starts to transmit each byte in the sub-data packet to the second bare chip. Based on this, the third number of first clock cycles after the valid signal is switched to a high level signal is determined as the sub-data packet transmission clock cycle, and in the sub-data packet transmission clock cycle, the valid signal is maintained at a high level signal to determine that the transmission module performs the transmission task of each byte of the sub-data packet in the corresponding third number of first clock cycles. For example, referring to Fig.16 After the valid signal maintains a low-level signal for a first clock cycle, the valid signal is set to a high-level signal, and in the first first clock cycle after being set to a high-level signal, the first bare chip sends a second feature code 0x5F to the second bare chip, and then maintains the valid signal as a high-level signal to transmit each byte in the sub-data packet.

[0173] In step S1404, after executing the third number of first clock cycles corresponding to the sub-packet transmission clock cycle, it means that the transmission task of each byte of the sub-packet has been completed. At this time, the valid signal is switched to a low level signal to stop the second bare chip from receiving the data transmitted by the transmission module.

[0174] In the embodiment disclosed in steps S1401 to S1404, a valid signal is generated and transmitted to the second bare chip while the first bare chip transmits data to the second bare chip to manage the working state of the transmission module, thereby dividing the different stages of the data transmission process, so that the second bare chip can determine the validity of the data transmitted by the transmission module by detecting the valid signal, thereby accurately completing the transmission process of the sub-data packet.

[0175] In one embodiment, referring to Fig.15 A serial clock signal line for sending a clock cycle signal is also provided between the first die and the second die, referring to Fig.17 , the data transmission method further includes:

[0176] Step S1701, the first bare chip obtains a system clock cycle signal of the multi-chip module, and performs frequency division processing on the system clock cycle signal to obtain a clock cycle signal corresponding to a first clock cycle;

[0177] Step S1702: In each first clock cycle, a clock cycle signal corresponding to the first clock cycle is sent to the second bare die through a serial clock signal line.

[0178] In step S1701, the multi-chip module is a system-level chip composed of multiple bare chips, and the multi-chip module includes a first bare chip and a second bare chip; the system clock cycle signal refers to the clock cycle signal corresponding to the multi-chip module. Specifically, the system clock cycle signal is generated by a crystal oscillator with a fixed frequency. Exemplarily, the frequency of the crystal oscillator is 50Mhz, then at this time, every 20ns is a system clock cycle. In this embodiment, the system clock cycle signal is processed by dividing the frequency, specifically, the system clock cycle signal is processed by an even number of frequency division, for example, a two-division process, a four-division process, etc. Exemplarily, a two-division circuit composed of a D flip-flop is provided in the first bare chip, referring to Fig.15 , the system clock cycle signal is used as the input of the two-frequency division circuit in the first bare chip, so as to perform two-frequency division processing on the system clock cycle signal. By performing frequency division processing on the system clock cycle signal, a clock cycle signal corresponding to the first clock cycle is obtained, referring to Fig.16 After the system clock cycle signal is divided by two, the frequency of the obtained first clock cycle is half of the system clock cycle signal, and the length of a single first clock cycle is twice the length of the system clock cycle. By reducing the frequency of the clock cycle signal through frequency division processing, and making the first bare chip work in the clock domain composed of the first clock cycle obtained after the frequency division processing, the dynamic power consumption of the bare chip can be reduced and the stability of signal processing can be improved, thereby simplifying the design of the first bare chip and reducing the complexity of the bare chip design.

[0179] In step S1702, in each first clock cycle, when the first bare chip sends the fourth number of bytes in the corresponding first command packet or sub-data packet to the second bare chip, the first bare chip sends the clock cycle signal of the first clock cycle to the second bare chip through the serial clock signal line, thereby providing the second bare chip with a reference time cycle signal for sampling the data sent by the first bare chip, so that the second bare chip can sample each bit transmitted by the transmission interface based on the rising edge of the clock cycle signal transmitted by the serial clock signal line, thereby synchronizing the data transmission between the first bare chip and the second bare chip, so that the second bare chip can correctly receive the data sent by the first bare chip.

[0180] In the embodiment disclosed in step S1701 to step S1702, the clock cycle signal corresponding to the first clock cycle is obtained by dividing the system clock cycle signal, thereby reducing the frequency of the clock cycle of the first die, reducing the operating power consumption of the first die and improving the stability of the signal processed by the first die, thereby simplifying the requirements of the first die on the hardware design, reducing the design difficulty of the first die, and simplifying the design process of the first die. At the same time, in each first clock cycle, while transmitting data through the transmission module, the first die sends the clock cycle signal corresponding to the first clock cycle to the second die through the serial clock signal line, so that the second die can sample each bit transmitted by the transmission interface based on the rising edge of the clock cycle signal transmitted by the serial clock signal line, thereby synchronizing the data transmission between the first die and the second die.

[0181] Description of the apparatus and device of the present disclosure

[0182] The present disclosure also provides an electronic device 1800, including:

[0183] at least one processor, and

[0184] a memory communicatively connected to at least one processor; wherein,

[0185] The memory stores instructions, and the instructions are executed by at least one processor so that when the at least one processor executes the instructions, a method as described in any one of the above embodiments of the present application is implemented.

[0186] Combine the following Fig.18 The hardware structure of the electronic device is described in detail. The electronic device includes: a processor 1810 , a memory 1820 , an input / output interface 1830 , a communication interface 1840 and a bus 1850 .

[0187] The processor 1810 may be implemented by a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided by the embodiments of the present disclosure;

[0188] The memory 1820 may be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 1820 may store an operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program codes are stored in the memory 1820, and the processor 1810 calls and executes the data transmission method of the embodiments of this disclosure;

[0189] Input / output interface 1830, used to implement information input and output;

[0190] Communication interface 1840, used to realize communication interaction between the device and other devices, which can be realized through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.); and

[0191] The bus 1850 transmits information between the various components of the device (e.g., the processor 1810, the memory 1820, the input / output interface 1830, and the communication interface 1840);

[0192] The processor 1810 , the memory 1820 , the input / output interface 1830 , and the communication interface 1840 are communicatively connected to each other within the device via a bus 1850 .

[0193] An embodiment of the present application also provides a computer-readable storage medium, which stores one or more programs. The one or more programs can be executed by one or more processors to implement the data transmission method of the above embodiment, which will not be repeated here.

[0194] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present disclosure described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "comprises" and "comprising" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0195] It should be understood that in the present disclosure, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0196] It should be understood that in the description of the embodiments of the present disclosure, the meaning of multiple (or multiple items) is more than two, greater than, less than, exceed, etc. are understood as not including the number, and above, below, within, etc. are understood as including the number.

[0197] In the several embodiments provided in the present disclosure, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0198] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0199] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0200] It should also be understood that the various implementations provided in the embodiments of the present disclosure can be combined arbitrarily to achieve different technical effects.

[0201] The above is a specific description of the implementation methods of the present disclosure, but the present disclosure is not limited to the above implementation methods. Technical personnel familiar with the art can also make various equivalent modifications or substitutions without violating the spirit of the present disclosure. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present disclosure.

Claims

1. A data transmission method, characterized in that: Applied to a first bare chip, the first bare chip includes a transmission module, the transmission module includes a first number of transmission interfaces in order, the method includes: Acquire a first data amount of data to be transmitted, and convert the first data amount into a corresponding number of binary bytes, wherein the first data amount is used to represent the number of bytes in the data to be transmitted; Based on each bit in the number of binary bytes having a value of 1, dividing the data to be transmitted into a plurality of sub-data packets, wherein the number of bytes in a single sub-data packet is determined by taking the number of bits corresponding to the bits in the number of binary bytes having a value of 1 as an exponent of 2; Executing a first transmission task on each of the sub-data packets in sequence, the first transmission task comprising: generating a first command packet corresponding to the sub-data packet, and sending the first command packet to the second bare chip through the transmission module, so that the second bare chip returns a response message in response to the first command packet, wherein the first command packet carries a second number, and the second number is used to represent the number of bytes in the sub-data packet; after receiving the response message returned by the second bare chip based on the first command packet, determining a third number based on the first number and the second number, and determining the third number of first clock cycles after receiving the response message as the corresponding sub-data packet transmission clock cycle, wherein the third number is used to represent the number of clock cycles required to send all bytes in the sub-data packet to the second bare chip; In a single first clock cycle in the sub-packet transmission clock cycle, a fourth number of bytes in the corresponding sub-packet is sent to the second bare chip through the transmission module, wherein the fourth number of bytes includes an ordered first number of bits, and the ordered first number of bits are respectively transmitted through the ordered first number of transmission interfaces.

2. The data transmission method according to claim 1, characterized in that: The generating a first command packet corresponding to the sub-data packet comprises: Obtain a first command packet template, where the first command packet template includes eight bits; Determine an identification code corresponding to the second die, and fill the first three bits of the first command packet template with the identification code; Determine a first power corresponding to the sub-packet based on the number of bytes in the sub-packet, determine a second number corresponding to the sub-packet based on the binary form of the exponent of the first power, and fill the second number into the last five bits of the payload of the first command packet template to obtain the first command packet, wherein the first power is an integer power of 2 corresponding to the number of bytes in the sub-packet.

3. The data transmission method according to claim 1, characterized in that: The sending the first command packet to the second bare chip by the transmission module includes: In response to a first transmission request, a first feature code is generated, and the first feature code is sent to the second die through the transmission module, wherein the first transmission request is a request for the first die to transmit the sub-data packet to the second die, and the first feature code is used to notify the second die to send the first command packet to the second die in at least one subsequent first clock cycle; At least one first clock cycle after sending the first feature code, the first command packet is sent to the second bare chip through the transmission module.

4. The data transmission method according to claim 1, characterized in that: After sending the first command packet to the second bare chip through the transmission module, the method further includes: Counting a first clock cycle, and stopping counting the first clock cycle after receiving the response information, to obtain a clock cycle count value; After receiving the response information returned by the second die based on the first command packet, determining a third number based on the first number and the second number includes: In a case where the clock cycle count value is not greater than a first count threshold, determining the third number based on the second number and the first number; When the clock cycle count value is greater than the first count threshold value and less than the second count threshold value, a first interrupt packet is generated, and the first interrupt packet is sent to a first central processor corresponding to the first die, so that the first central processor responds to the first interrupt packet and controls the first die to resend the first command packet to the second die after a fifth number of first clock cycles; When the count value obtained by counting in the first clock cycle is greater than the second count threshold, a second interrupt packet is generated, and the second interrupt packet is sent to the first central processor corresponding to the first bare chip, so that the first central processor controls the first bare chip to stop sending the sub-data packet to the second bare chip.

5. The data transmission method according to claim 1, characterized in that: The second bare chip returns a response message in response to the first command packet, including: The second die determines, based on the second number in the first command packet, a first memory space corresponding to the second number, and determines a remaining memory space of the second die; In a case where the first memory space is smaller than the remaining memory space, the second die returns the response information to the first die.

6. The data transmission method according to claim 1, characterized in that: The sending of the fourth number of bytes in the corresponding sub-data packet to the second bare chip through the transmission module in a single first clock cycle in the sub-data packet transmission clock cycle includes: In a first clock cycle of a transmission clock cycle of the sub-data packet, generating a second feature code and sending the second feature code to the second die, wherein the second feature is used to notify the second die that in a subsequent fifth number of clock cycles, the first die sends each byte of the sub-data packet to the second die; In a single first clock cycle in the sub-data packet transmission clock cycle, a first number of bits corresponding to a fourth number of bytes are read from a register of the first bare chip, and the first number of bits are sent in parallel to the second bare chip through the first number of transmission interfaces.

7. The data transmission method according to claim 1, characterized in that: The first die is in a first clock domain, the second die is in a second clock domain, the first die includes a first bus transmission module, a first buffer and a data transmission state machine, the first bus transmission module is connected to a data bus of the first die, the input end of the first buffer is connected to the first bus transmission module, the output end of the first buffer is connected to the data transmission state machine, the data transmission state machine is also connected to the transmission module, the data transmission state machine is in a functional clock domain, and the fourth number of bytes in the corresponding sub-data packet is sent to the second die through the transmission module, including: The first bus transmission module sequentially reads each byte of the sub-data packet from the memory of the first bare chip through the data bus of the first bare chip, writes each read byte into the first buffer at the rising edge of each first clock cycle of the first clock domain, and determines a first reading order according to the order in which each byte is written into the first buffer; Through the data sending state machine, at the rising edge of each clock cycle in the functional clock domain, each byte is read from the first buffer in accordance with the first reading order and sent to the transmission module, and the received fourth number of bytes is sent to the second bare chip through the transmission module, so that the second bare chip writes the fourth number of bytes into the memory of the second bare chip at the rising edge of each clock cycle in the second clock domain.

8. The data transmission method according to claim 7, characterized in that: The second die includes a receiving module, the receiving module includes a data receiving state machine, a second buffer and a second bus transmission module, the data receiving state machine is in the functional clock domain, and the second die writes the fourth number of bytes into the memory of the second die at the rising edge of each clock cycle of the second clock domain, including: receiving, by the data receiving state machine, a fourth number of bytes sent from the transmission module of the first bare die, and writing the received fourth number of bytes into the second buffer at the rising edge of each clock cycle of the functional clock domain, and determining a second reading order based on the order in which the fourth number of bytes are written into the second buffer; At a rising edge of a single second clock cycle in the second clock domain, the second bus transmission module reads the fourth number of bytes from the second buffer in the second reading order and writes the fourth number of bytes to the memory of the second die.

9. The data transmission method according to claim 1, characterized in that: The method further comprises: In each of the first clock cycles, generating a valid signal and sending the valid signal to the second bare chip through the transmission module, wherein the valid signal is used to control the working state of the transmission module of the first bare chip and the transmission module of the second bare chip in the corresponding first clock cycle; The step of determining a third number of first clock cycles after receiving the response information as a sub-data packet transmission clock cycle comprises: In at least one first clock cycle after receiving the response information, the valid signal is switched to a low level signal, and in a sixth number of the first clock cycles, the valid signal is switched to a high level signal; Determine a third number of first clock cycles after the valid signal is switched to a high level signal as the sub-data packet transmission clock cycle, and maintain the valid signal as a high level signal during the sub-data packet transmission clock cycle; After the sub-data packet transmission clock cycle, the valid signal is switched to a low level signal.

10. The data transmission method according to claim 1, characterized in that: A serial clock signal line is further provided between the first die and the second die, and the method further comprises: The first bare die obtains a system clock cycle signal of a multi-chip module, and performs frequency division processing on the system clock cycle signal to obtain a clock cycle signal corresponding to the first clock cycle, wherein the multi-chip module includes the first bare die and the second bare die; In each first clock cycle, the clock cycle signal corresponding to the first clock cycle is sent to the second bare die through the serial clock signal line.

11. An electronic device, characterized in that: The electronic device includes a memory, a processor, a program stored in the memory and executable on the processor, and a data bus for realizing connection and communication between the processor and the memory. When the program is executed by the processor, the data transmission method according to any one of claims 1 to 10 is realized.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the data transmission method according to any one of claims 1 to 10.

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