A mixed height cell legalization circuit layout method for chip fence area

Abstract

The present invention discloses a mixed height unit legalization circuit layout method for a chip fence area, comprising the steps of: pre-legalization processing: based on the global layout result, processing the unit violating the legalization of the fence area, and shrinking or expanding the unit violating the legalization of the fence area to fit the fence area; linear complementary solution processing: generating a quadratic programming problem for searching the nearest legal position of the unit, converting it into a linear complementary problem, and using a fast iteration method to solve the linear complementary problem; heuristic calculation considering weight coefficients: placing each placeable unit according to the obtained unit coordinates; refining the layout quality so that the final line length is obtained, and using unit movement, unit exchange and heuristic methods considering weight coefficients to complete this stage. The present invention can avoid missing a better layout position, can handle more complex fence area shapes, obtain accurate results, and save computing resources and time.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a mixed height unit legalization circuit layout method for a chip fence area. Background Art

[0002] In the legalization method in the layout flow of integrated circuits, the latest open source detailed layouter is mainly used to optimize the method of laying out standard cells with a height of more than two rows in fence areas of various shapes. The technology mainly includes the following steps: 1. Pre-legalization and mixed-height standard cell legalization steps, giving priority to standard cell legalization. 2. Quality refinement step using the simplest simulated annealing to reduce displacement.

[0003] However, this method has some technical problems and shortcomings. First, this method may not be able to effectively optimize the placement of standard cells in all cases, because its legal position search for each standard cell is only greedy in the horizontal and vertical directions, which may miss better layout positions. Secondly, this method may require a lot of computing resources and time. In addition, since it only uses the simplest greedy algorithm, it may not be able to handle some more complex fence area shapes, which may limit its use in practical applications. The final simulated annealing is not good enough for quality refinement because the algorithm is too simple. It only performs the most basic optimization unit displacement, and it is not the optimal displacement result. Summary of the invention

[0004] In order to solve the above problems, the present invention proposes a mixed-height unit legalization circuit layout method for the chip fence area, which can avoid missing better layout positions, handle more complex fence area shapes, obtain accurate results, and save computing resources and time.

[0005] To achieve the above object, the technical solution adopted by the present invention is: a mixed height unit legalization circuit layout method for a chip fence area, comprising the steps of:

[0006] S10, pre-legalization processing: based on the global layout result, processing the cells that violate the legalization of the fence area, and shrinking or expanding the cells that violate the legalization of the fence area to fit the fence area;

[0007] S20, linear complementary solution processing: first generate a quadratic programming problem for searching for the nearest legal position of the unit, then convert it into a linear complementary problem, and then use a fast iteration method to solve the linear complementary problem;

[0008] S30, heuristic calculation considering weight coefficients: After solving the linear complementarity problem, each placeable unit is placed according to the obtained unit coordinates; after placement, the layout quality is refined to make the final line length, and this stage is completed using unit movement, unit exchange and heuristic methods considering weight coefficients.

[0009] Furthermore, the pre-legalization process includes the steps of: based on the global layout result, first processing the cells that violate the legalization of the fence area, and fixing the positions of these cells before performing the multi-stage legalization process to keep the quality of the maximum displacement from deteriorating; and shrinking or expanding the cells that violate the legalization of the fence area to fit the fence area.

[0010] Furthermore, in the linear complementary solution processing stage, the steps are included:

[0011] S201, finding for each unit a legal position closest to its initial position that does not violate the design rules;

[0012] S202, finding, for each unit, a legal position closest to its initial position in the global layout; generating a quadratic programming problem for the problem of finding the position closest to it;

[0013] S203, next, the quadratic programming problem is transformed into a linear complementarity problem;

[0014] S204, using a fast iteration method to solve the linear complementarity problem.

[0015] Furthermore, the problem of finding the closest location is generated into a quadratic programming problem, including:

[0016] The objective function and constraints to be minimized are:

[0017] ;

[0018] Where x is the horizontal coordinate of the position to be solved, y is the vertical coordinate of the position to be solved, and x pos y is the initial horizontal coordinate of each cell after global layout and before detailed layout. posis the initial ordinate of each cell after global layout but before detailed layout, die.xUR is the x coordinate of the lower left corner of the search area, die.yUR is the y coordinate of the upper right corner of the search area, wsite is the width of the grid, rowHeight is the height of the grid, grid is a self-divided rectangular grid, grid[k][l] represents a grid in the kth row and lth column, linked_cell indicates whether there is a cell in the grid, NULL is empty, isValid is used to determine whether the grid can effectively place the cell, true is normal placement; if there is no vacant position, set grid.group == cellingroup| UINTMAX, indicating that the cell is placed in the matching group position or the unassigned boundary position; the following k and l are their value limiting conditions, extending from the x and y coordinates of the current cell to the distance, and the length of each extension is the set search step, that is, x step ,y step； x step is the step size of each iteration when searching for the placement position of the unit in the x direction, y step The step size for each iteration when searching for the placement position of the cell in the y direction.

[0019] Furthermore, the quadratic programming problem is transformed into a linear complementarity problem, including:

[0020] Define the matrix Q as a 2x2 identity matrix;

[0021] Define the matrix A as a 2x(2+2*x_step* y_step) matrix, where the first two columns are (-1,0) and (0,-1), and the following columns are (1,0), (0,1),...,(1,0),(0,1);

[0022] Define vector b as a vector of (0,0,die.xUR / wsite-x_step,die.yUR / rowHeight - y_step,...), where the following elements are the relevant information of each grid grid[k][l];

[0023] Define vector c to represent the gradient of the objective function;

[0024] Solving LCP(c, Q, b, A) means solving for vector z and vector ω to satisfy the following conditions:

[0025] ;

[0026] where v is the Lagrange multiplier vector.

[0027] Furthermore, a fast iterative method is used to solve the linear complementarity problem, and the library file elign in C++ is used to quickly solve the matrix, so as to quickly obtain the legal layout position of the required unit.

[0028] Furthermore, the heuristic calculation stage considering the weight coefficients comprises the steps of:

[0029] Calculate the target unit's displacement penalty value;

[0030] Set a penalty threshold. If the target unit displacement penalty value is greater than the penalty threshold, the unit movement and unit exchange will not be executed. If the target unit displacement penalty value is less than the penalty threshold, the unit movement and unit exchange will be executed.

[0031] The weight coefficient is calculated based on the wire length, displacement and overlap loss, where the weight coefficient is initialized to 1.0, and then increases or decreases according to the good or bad results of each iteration, and the movement and exchange of units are accepted or rejected according to the probability function on which the weight coefficient depends; the optimizer gradually adjusts the weight coefficient during the optimization process;

[0032] The layout is iteratively improved by exerting influence between cells and performing cell moves and swaps.

[0033] Furthermore, the operation process of the unit movement includes:

[0034] When the displacement penalty of the target unit is lower than a threshold, the target unit is moved to another position;

[0035] The displacement threshold is proportional to the width of the layout core area and inversely proportional to the number of iterations of the heuristic calculation.

[0036] Furthermore, the unit exchange operation process includes: exchanging units of the same type to minimize the total unit displacement; for units of the same size, both the total displacement and the maximum displacement are reduced.

[0037] The beneficial effects of adopting this technical solution are:

[0038] The present invention aims at layout legalization, and obtains the optimal placement position of each unit by solving the linear complementarity problem. The legalization result reflects the legalization status of the layout and the displacement status of the unit, and a heuristic algorithm considering the weight coefficient is used to further optimize the average displacement and maximum displacement of the unit after legalization. Specifically, the present invention reduces the average displacement and maximum displacement of the legalized unit by solving the linear complementarity problem and a heuristic algorithm considering the weight coefficient, and does not consume too much time. It is an effective and efficient layout legalization optimization method.

[0039] The present invention can generate higher quality legalized layout results. By using the solution of the linear complementary problem to find the legalized position of the cell, and then optimizing the cell displacement by a heuristic algorithm that considers the weight coefficient, it is possible to complete the legalization of the illegal cells and other cells while finding a better result than the greedy algorithm that is most used in the general legalization algorithm, so that some legal cell placement positions with shorter displacements are discovered, achieving efficient legalization of the layout, and improving the efficiency and performance of the circuit design. This design makes the entire process of circuit layout and wiring more efficient and coordinated.

[0040] The present invention converts the quadratic programming problem into a linear complementarity problem and can find more undiscovered and better placement positions than the greedy strategy of the general legalization algorithm, so as to explore better solutions for unit positions and cope with fence areas of different shapes.

[0041] The invention takes into account the heuristic algorithm of coefficient weight, exchanges the units of the same size and the same layout area, uses unit movement to optimize the average displacement and total displacement of the unit, calculates the weight coefficient of the heuristic algorithm to obtain a shorter average displacement and maximum displacement of the unit; the weight coefficient is dynamically changed according to the layout result, so that the layout always moves towards the optimal result and finally converges; in order to reduce the average displacement and maximum displacement of the unit, keep the layout legalization result unchanged, a mixed height unit legalization algorithm is designed for irregular areas and efficient short-time legalization algorithm. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic flow chart of a mixed height unit legalization circuit layout method for a chip fence area according to the present invention;

[0043] Figure 2 Schematic diagram of pre-legalization in an embodiment of the present invention, wherein (a) the illegal unit is located outside the fence area, (b) is reduced to the fence area, (c) the illegal unit is located within the fence area, and (d) is extended to the fence area;

[0044] Figure 3 Schematic diagram of the flow of the heuristic method considering the weight coefficient in an embodiment of the present invention. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is further described below with reference to the accompanying drawings.

[0046] In this embodiment, see Figure 1 As shown, the present invention proposes a mixed height unit legalization circuit layout method for a chip fence area, comprising the steps of:

[0047] S10, pre-legalization processing: based on the global layout result, processing the cells that violate the legalization of the fence area, and shrinking or expanding the cells that violate the legalization of the fence area to fit the fence area;

[0048] S20, linear complementary solution processing: first generate a quadratic programming problem for searching for the nearest legal position of the unit, then convert it into a linear complementary problem, and then use a fast iteration method to solve the linear complementary problem;

[0049] S30, heuristic calculation considering weight coefficients: After solving the linear complementarity problem, each placeable unit is placed according to the obtained unit coordinates; after placement, the layout quality is refined to make the final line length, and this stage is completed using unit movement, unit exchange and heuristic methods considering weight coefficients.

[0050] As an optimization scheme for the above-mentioned embodiment, the pre-legalization processing includes the steps of: based on the global layout results, first processing the cells that violate the legalization of the fence area, and fixing the positions of these cells before performing the multi-stage legalization process to keep the quality of the maximum displacement from deteriorating; and shrinking or expanding the cells that violate the legalization of the fence area to fit the fence area.

[0051] In the pre-legalization stage, Figure 2 A pre-legalization step is described that aims to reduce the maximum displacement of cells that violate the fence region legalization. The fence region is a physical area assigned to cells in a hierarchical design. This step first processes cells that violate the fence region legalization and fixes their positions before going through a multi-stage legalization process to keep the quality of the maximum displacement from deteriorating. Cells that violate the fence region legalization are either shrunk or expanded to fit within the fence region. In the pre-legalization example above, (a) the violating cell is outside the fence region. (b) It is shrunk to fit within the fence region. (c) The violating cell is inside the fence region. (d) It is extended to fit within the fence region.

[0052] As an optimization solution of the above embodiment, in the linear complementary solution processing stage:

[0053] In this stage, in the legalization problem of mixed height cells, a global layout of a chip with n standard cells is given. After obtaining the result of the global layout, legalization is performed.

[0054] Includes steps:

[0055] S201, find for each cell the legal position closest to its initial position that does not violate the design rules; because legalization first requires that there is no overlap between cells and they are aligned with the power rails respectively;

[0056] S202, in order to minimize the interference with the semi-perimeter line length result of the global layout, find a legal position closest to the initial position of the global layout for each unit; generate a quadratic programming problem for the problem of finding the closest position;

[0057] S203, next, the quadratic programming problem is transformed into a linear complementarity problem;

[0058] S204, using a fast iteration method to solve the linear complementarity problem.

[0059] Specifically, the problem of finding the closest location is generated into a quadratic programming problem, including:

[0060] The objective function and constraints to be minimized are:

[0061] ;

[0062] Where x is the horizontal coordinate of the position to be solved, y is the vertical coordinate of the position to be solved, and x pos y is the initial horizontal coordinate of each cell after global layout and before detailed layout. pos is the initial ordinate of each cell after global layout but before detailed layout, die.xUR is the x coordinate of the lower left corner of the search area, die.yUR is the y coordinate of the upper right corner of the search area, wsite is the width of the grid, rowHeight is the height of the grid, grid is a self-divided rectangular grid, grid[k][l] represents a grid in the kth row and lth column, linked_cell indicates whether there is a cell in the grid, NULL is empty, isValid is used to determine whether the grid can effectively place the cell, true is normal placement; if there is no vacant position, set grid.group == cellingroup| UINTMAX, indicating that the cell is placed in the matching group position or the unassigned boundary position; the following k and l are their value limiting conditions, extending from the x and y coordinates of the current cell to the distance, and the length of each extension is the set search step, that is, x step ,y step； x step is the step size of each iteration when searching for the placement position of the unit in the x direction, y step The step size for each iteration when searching for the placement position of the cell in the y direction.

[0063] Convert the quadratic programming problem into a linear complementarity problem, including:

[0064] Define the matrix Q as a 2x2 identity matrix;

[0065] Define the matrix A as a 2x(2+2*x_step* y_step) matrix, where the first two columns are (-1,0) and (0,-1), and the following columns are (1,0), (0,1),...,(1,0),(0,1);

[0066] Define vector b as a vector of (0,0,die.xUR / wsite-x_step,die.yUR / rowHeight - y_step,...), where the following elements are the relevant information of each grid grid[k][l];

[0067] Define vector c to represent the gradient of the objective function;

[0068] Solving LCP(c, Q, b, A) means solving for vector z and vector ω to satisfy the following conditions:

[0069] ;

[0070] In the above questions,

[0071] ;

[0072] Where (x, y) is the position to be solved, v is the Lagrange multiplier vector, die.xUR is the x-coordinate of the lower left corner of the search region, die.yUR is the y-coordinate of the upper right corner of the search region, wsite and rowHeight are the width and height of the grid, is the grid information, and are the steps taken by the algorithm in each iteration when searching for the placement of the unit in the x and y directions, respectively.

[0073] The linear complementarity problem is solved using a fast iterative method, and the matrix is ​​quickly solved using the C++ library file elign, so as to quickly obtain the legal layout position of the required cells.

[0074] As an optimization solution of the above embodiment, Figure 3 As shown, the heuristic calculation stage considering the weight coefficient includes the steps of:

[0075] Calculate the target unit's displacement penalty value;

[0076] Set a penalty threshold. If the target unit displacement penalty value is greater than the penalty threshold, the unit movement and unit exchange will not be executed. If the target unit displacement penalty value is less than the penalty threshold, the unit movement and unit exchange will be executed.

[0077] The weight coefficient is calculated based on the wire length, displacement and overlap loss, where the weight coefficient is initialized to 1.0, and then the coefficient is increased or decreased based on the good or bad results of each iteration, and the movement and exchange of units are accepted or rejected based on the probability function that the weight coefficient depends on; the optimizer gradually adjusts the weight coefficient during the optimization process; this heuristic algorithm can achieve high-quality layout results with lower running time and memory consumption.

[0078] The layout is iteratively improved by exerting influence between cells and performing cell moves and swaps.

[0079] The operation process of the unit movement includes: adjusting by unit movement in order to improve the displacement quality;

[0080] When the displacement penalty of the target unit is lower than a threshold, the target unit is moved to another position;

[0081] This move may increase the cell displacement. However, another cell move may reduce the cell displacement after the previous cell move. The combined effect of these two cell moves is to reduce the total displacement.

[0082] The displacement threshold is proportional to the width of the layout core area and inversely proportional to the number of iterations of the heuristic calculation.

[0083] The operation process of the unit exchange includes: the main purpose of unit exchange is to obtain better line length by exchanging different units; here, the same type of units are exchanged to minimize the total unit displacement; for units of the same size, the total displacement and the maximum displacement are reduced. When the utilization rate is high, this unit exchange is effective because the unit exchange can optimize the displacement quality without changing the layout.

[0084] The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. It should be understood by those skilled in the art that the present invention is not limited to the above embodiments. The above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention to be protected. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. A mixed height unit legalization circuit layout method for a chip fence area, characterized in that: Includes steps: S10, pre-legalization processing: based on the global layout result, processing the cells that violate the legalization of the fence area, and shrinking or expanding the cells that violate the legalization of the fence area to fit the fence area; S20, linear complementary solution processing: first generate a quadratic programming problem for searching for the nearest legal position of the unit, then convert it into a linear complementary problem, and then use a fast iteration method to solve the linear complementary problem; S30, heuristic calculation considering weight coefficients: after solving the linear complementarity problem, each placeable unit is placed according to the obtained unit coordinates; after placement, the layout quality is refined to make the final line length, and this stage is completed using unit movement, unit exchange and heuristic methods considering weight coefficients; In the linear complementary solution processing stage, the steps include: S201, finding for each unit a legal position closest to its initial position that does not violate the design rules; S202, finding, for each unit, a legal position closest to its initial position in the global layout; generating a quadratic programming problem for the problem of finding the position closest to it; S203, next, the quadratic programming problem is transformed into a linear complementarity problem; S204, solving the linear complementarity problem using a fast iteration method; The problem of finding the closest location is generated as a quadratic programming problem, including: The objective function and constraints to be minimized are: ； ； Where x is the horizontal coordinate of the position to be solved, y is the vertical coordinate of the position to be solved, and x pos y is the initial horizontal coordinate of each cell after global layout and before detailed layout. pos is the initial ordinate of each cell after global layout but before detailed layout, die.xUR is the x-coordinate of the lower left corner of the search area, die.yUR is the y-coordinate of the upper right corner of the search area, wsite is the width of the grid, rowHeight is the height of the grid, grid is a self-divided rectangular grid, grid[k][l] represents a grid in the kth row and lth column, linked_ cell indicates whether there is a cell in the grid. NULL is empty, isValid is used to determine whether the grid can effectively place cells, true means normal placement; if there is no position If missing, set grid.group == cellingroup|UINT_ MAX, which means that the cell is placed at the matching group position or the unassigned boundary position; the following k and l are their value limiting conditions, which are the x and y coordinates of the current cell extending far away, and the length of each extension is the set search step, that is, x step ,y step； x step is the step size of each iteration when searching for the placement position of the unit in the x direction, y step The step size for each iteration when searching for the placement position of the unit in the y direction; Convert the quadratic programming problem into a linear complementarity problem, including: Define the matrix Q as a 2x2 identity matrix; Define the matrix A as 2x(2+2*x step * y step ) where the first two columns are (-1,0) and (0,-1) and the following columns are (1,0), (0,1),...,(1,0),(0,1) ; Define vector b as (0,0,die.xUR / wsite-x step ,die.yUR / rowHeight - y step ,...), where the following elements are the relevant information of each grid grid[k][l]; Define vector c to represent the gradient of the objective function; Solving LCP(c, Q, b, A) means solving for vector z and vector ω to satisfy the following conditions: ； where v is the Lagrange multiplier vector.

2. A mixed height unit legalization circuit layout method for a chip fence area according to claim 1, characterized in that: The pre-legalization process includes the following steps: based on the global layout result, firstly processing the cells that violate the legalization of the fence area, and fixing the positions of these cells before performing the multi-stage legalization process to keep the quality of the maximum displacement from deteriorating; and shrinking or expanding the cells that violate the legalization of the fence area to fit the fence area.

3. The mixed height unit legalization circuit layout method for chip fence area according to claim 1, characterized in that: The linear complementarity problem is solved using a fast iterative method, and the matrix is ​​quickly solved using the C++ library file elign, so as to quickly obtain the legal layout position of the required cells.

4. The method for circuit layout of mixed height units in a chip fence area according to claim 1, characterized in that: The stage of heuristic calculation taking into account weight coefficients comprises the steps of: Calculate the target unit's displacement penalty value; Set a penalty threshold. If the target unit displacement penalty value is greater than the penalty threshold, the unit movement and unit exchange will not be executed. If the target unit displacement penalty value is less than the penalty threshold, the unit movement and unit exchange will be executed. The weight coefficient is calculated based on the wire length, displacement and overlap loss, where the weight coefficient is initialized to 1.0, and then increases or decreases according to the good or bad results of each iteration, and the movement and exchange of units are accepted or rejected according to the probability function on which the weight coefficient depends; the optimizer gradually adjusts the weight coefficient during the optimization process; The layout is iteratively improved by exerting influence between cells and performing cell moves and swaps.

5. The mixed height unit legalization circuit layout method for chip fence area according to claim 4, characterized in that: The operation process of the unit movement includes: When the displacement penalty of the target unit is lower than a threshold, the target unit is moved to another position; The displacement threshold is proportional to the width of the layout core area and inversely proportional to the number of iterations of the heuristic calculation.

6. The method for circuit layout of mixed height units legalized for chip fence area according to claim 4, characterized in that: The unit exchange operation process includes: exchanging units of the same type to minimize the total unit displacement; for units of the same size, both the total displacement and the maximum displacement are reduced.

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