3D optoelectronic interconnect packaging structure and preparation method thereof

Abstract

The present invention provides a 3D optoelectronic interconnection packaging structure and a preparation method thereof, which belongs to the field of semiconductor manufacturing technology. A glass composite body combined with a dielectric layer can be used to construct a glass waveguide structure. By forming a through groove exposing the glass waveguide layer and bonding a lateral light-emitting chip in the through groove, the photosensitive area of ​​the lateral light-emitting chip and the glass waveguide layer can construct a light transmission path, and optoelectronic interconnection can be achieved through the interconnection of metal columns, rewiring layers and adapter plates. The present invention can realize optoelectronic interconnection integration, reduce packaging size, reduce power consumption, and improve reliability. It is suitable for high-density integrated packaging and can achieve good optoelectronic transmission.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor manufacturing, and relates to a 3D optoelectronic interconnect packaging structure and a preparation method thereof. Background Art

[0002] 3D interconnect packaging structure is a packaging technology that achieves high-density integration and efficient interconnection by stacking chips in the vertical direction. This technology mainly uses through-silicon via (TSV) adapters, through-glass via (TGV) adapters and micro-bump technology to achieve interconnection between chips.

[0003] A microprocessor is an integrated circuit chip that performs arithmetic and logical operations of a computer and controls other devices and functions. It is a core component of a computer or other electronic device. As the performance of microprocessors continues to increase, the maximum available data communication rate of electronic interconnects used to enable data to flow in and out has become increasingly dominant, that is, the maximum available data communication rate of electronic interconnects limits the overall system performance. Optical interconnects have the advantages of a higher bandwidth-length product (BLP) and can reduce power and save costs. Therefore, integrating electronic interconnects with optical interconnects for optoelectronic interconnects can effectively solve the bottleneck problem of electronic interconnects.

[0004] Therefore, it is necessary to provide a 3D optoelectronic interconnect packaging structure and a preparation method thereof. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a 3D optoelectronic interconnect packaging structure and a preparation method thereof, so as to solve the bottleneck problem of electronic interconnection in the application of the prior art.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a 3D optoelectronic interconnect packaging structure, comprising the following steps:

[0007] Providing a glass composite, the glass composite comprising a stacked glass substrate and a glass waveguide layer, wherein the refractive index of the glass waveguide layer is greater than the refractive index of the glass substrate;

[0008] Patterning the glass waveguide layer to expose a portion of the glass substrate;

[0009] forming a dielectric layer on the exposed glass substrate, wherein the dielectric layer covers the glass waveguide layer and the refractive index of the dielectric layer is smaller than the refractive index of the glass waveguide layer;

[0010] forming a metal column penetrating the dielectric layer and the glass substrate;

[0011] Forming a first redistribution layer on the dielectric layer and forming a second redistribution layer on the glass substrate, wherein the first redistribution layer and the second redistribution layer are both electrically connected to the metal pillar;

[0012] forming a through groove penetrating the first redistribution layer, the dielectric layer, the glass substrate and the second redistribution layer, wherein the glass waveguide layer is exposed on a sidewall of the through groove;

[0013] Providing a composite adapter plate, the composite adapter plate comprising an adapter plate and a third rewiring layer and a fourth rewiring layer located on both sides of the adapter plate, and the adapter plate, the third rewiring layer and the fourth rewiring layer are electrically connected;

[0014] Bonding the composite transfer board to the second rewiring layer and being located above the through groove, wherein the third rewiring layer is electrically connected to the second rewiring layer;

[0015] Providing an electric chip and a side-light emitting chip, and bonding the electric chip to the fourth rewiring layer, and the electric chip is electrically connected to the fourth rewiring layer, and bonding the side-light emitting chip to the through groove, and the side-light emitting chip is electrically connected to the third rewiring layer, and the photosensitive area of ​​the side-light emitting chip is arranged corresponding to the glass waveguide layer;

[0016] A metal bump is formed on the first rewiring layer, and the metal bump is electrically connected to the first rewiring layer.

[0017] Optionally, the glass composite is prepared by a fusion draw lamination method.

[0018] Optionally, the dielectric layer includes a polyimide dielectric layer or a silicon oxide dielectric layer.

[0019] Optionally, a method for punching holes when forming the metal pillars includes a laser punching method or a mechanical drilling method; a method for forming the through-grooves includes a laser punching method or a mechanical drilling method.

[0020] Optionally, the adapter board includes a TSV adapter board or a TGV adapter board.

[0021] Optionally, the method further includes forming a bottom filling layer between the electric chip and the fourth rewiring layer.

[0022] Optionally, the glass composite is of wafer-level size, and further includes a dicing process step after forming the metal bumps.

[0023] The present invention also provides a 3D optoelectronic interconnect packaging structure, the 3D optoelectronic interconnect packaging structure comprising:

[0024] A glass composite, the glass composite comprising a stacked glass substrate and a patterned glass waveguide layer, the glass waveguide layer partially exposing the glass substrate, and the refractive index of the glass waveguide layer is greater than the refractive index of the glass substrate;

[0025] a dielectric layer, the dielectric layer being located on the exposed glass substrate and covering the glass waveguide layer, and the refractive index of the dielectric layer being smaller than the refractive index of the glass waveguide layer;

[0026] a metal column, wherein the metal column penetrates the dielectric layer and the glass substrate;

[0027] A first rewiring layer, wherein the first rewiring layer is located on the dielectric layer and is electrically connected to the metal pillar;

[0028] a second redistribution layer, the second redistribution layer being located on the glass substrate and electrically connected to the metal pillar;

[0029] a through groove, wherein the through groove penetrates the first redistribution layer, the dielectric layer, the glass substrate and the second redistribution layer, and the sidewall of the through groove exposes the glass waveguide layer;

[0030] A composite adapter plate, the composite adapter plate is bonded to the second rewiring layer and is located above the through groove, comprising an adapter plate and a third rewiring layer and a fourth rewiring layer located on both sides of the adapter plate, the adapter plate, the third rewiring layer and the fourth rewiring layer are electrically connected, and the third rewiring layer is electrically connected to the second rewiring layer;

[0031] an electric chip, the electric chip being bonded to the fourth rewiring layer and the electric chip being electrically connected to the fourth rewiring layer;

[0032] A lateral light-emitting chip, wherein the lateral light-emitting chip is bonded in the through groove, the lateral light-emitting chip is electrically connected to the third rewiring layer, and a photosensitive area of ​​the lateral light-emitting chip is arranged corresponding to the glass waveguide layer;

[0033] A metal bump is located on the first rewiring layer and is electrically connected to the first rewiring layer.

[0034] Optionally, the dielectric layer includes a polyimide dielectric layer or a silicon oxide dielectric layer; and the adapter board includes a TSV adapter board or a TGV adapter board.

[0035] Optionally, there is a bottom filling layer between the electric chip and the fourth rewiring layer.

[0036] As described above, the 3D optoelectronic interconnect packaging structure and preparation method thereof of the present invention can construct a glass waveguide structure by using a glass composite in combination with a dielectric layer. By forming a through groove exposing the glass waveguide layer and bonding a side-light-emitting chip in the through groove, a light transmission path can be constructed between the photosensitive area of ​​the side-light-emitting chip and the glass waveguide layer, and optoelectronic interconnection can be achieved through the interconnection of metal columns, a rewiring layer and an adapter plate.

[0037] The 3D optoelectronic interconnect packaging structure and the preparation method thereof of the present invention can realize optoelectronic interconnect integration, reduce packaging size, reduce power consumption, improve reliability, are suitable for high-density integrated packaging, and can realize good optoelectronic transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 Shown is a schematic diagram of the process flow of preparing a 3D optoelectronic interconnect packaging structure in an embodiment of the present invention.

[0039] Figure 2 It is a schematic diagram showing the structure of a glass composite according to an embodiment of the present invention.

[0040] Figure 3 It is a schematic diagram of the structure after forming a patterned photoresist layer in an embodiment of the present invention.

[0041] Figure 4 It is a schematic diagram of the structure after forming a patterned glass waveguide layer in an embodiment of the present invention.

[0042] Figure 5 Shown are schematic structural diagrams of glass waveguide layers with different structural morphologies according to embodiments of the present invention.

[0043] Figure 6 It is a schematic diagram of the structure after forming a dielectric layer in an embodiment of the present invention.

[0044] Figure 7 It is a schematic diagram of the structure after the metal pillars are formed in an embodiment of the present invention.

[0045] Figure 8 It is a schematic diagram of the structure after forming the first redistribution layer and the second redistribution layer in an embodiment of the present invention.

[0046] Fig. 9 It is a schematic diagram of the structure after forming the through groove in the embodiment of the present invention.

[0047] Fig.10 It is a schematic diagram showing the distribution structure of the through grooves in an embodiment of the present invention.

[0048] Fig.11 It is a schematic diagram of the structure after bonding the composite adapter plate in an embodiment of the present invention.

[0049] Fig.12 Shown is a schematic diagram of the structure after bonding the electrical chip in an embodiment of the present invention.

[0050] Fig.13 It is a schematic diagram of the structure after bonding the side-light-emitting chip in an embodiment of the present invention.

[0051] Fig.14 It is a schematic diagram of the structure after forming the bottom filling layer and the metal bumps in the embodiment of the present invention.

[0052] Description of Reference Numerals

[0053] 100-glass substrate; 200-glass waveguide layer; 300-photoresist layer; 400-dielectric layer; 500-metal pillar; 610-first redistribution layer; 620-second redistribution layer; 630-third redistribution layer; 640-fourth redistribution layer; 700-through groove; 800-adapter; 910-electric chip; 920-lateral light-emitting chip; 921-photosensitive area; 110-bottom filling layer; 120-metal bump. DETAILED DESCRIPTION

[0054] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0055] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0056] For ease of description, spatial relational terms such as “under”, “below”, “below”, “below”, “over”, etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to include other orientations of the device in use or operation in addition to the orientation depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, so that the first and second features may not be in direct contact. In addition, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or one or more intervening layers may also be present.

[0057] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0058] See also Figure 1 This embodiment provides a method for preparing a 3D optoelectronic interconnect packaging structure, which can realize optoelectronic interconnect integration, reduce packaging size, reduce power consumption, improve reliability, is suitable for high-density integrated packaging, and can achieve good optoelectronic transmission.

[0059] The following is in conjunction with the instruction manual Figure 2~Figure 14 The preparation of the 3D optoelectronic interconnect packaging structure is further introduced.

[0060] First, see Figure 1 and Figure 2 , performing step S1 to provide a glass composite, wherein the glass composite includes a stacked glass substrate 100 and a glass waveguide layer 200 , and the refractive index of the glass waveguide layer 200 is greater than the refractive index of the glass substrate 100 .

[0061] As an example, the preparation method of the glass composite may include a fusion-drawing lamination method, but is not limited thereto. In the present embodiment, the glass composite adopts a fusion-drawing lamination method, and the refractive index of the glass waveguide layer 200 located at the upper layer is greater than the refractive index of the glass substrate 100 located at the lower layer, so as to facilitate the subsequent construction of a glass waveguide structure.

[0062] When the glass composite is prepared by the fusion-drawing lamination method, it is preferred that the refractive index difference between the glass waveguide layer 200 and the glass substrate 100 is 5% to 10%, such as 5%, 6%, 8%, 10%, etc., so that the glass substrate 100 can be used as the lower cladding of the glass waveguide layer 200, so as to facilitate the subsequent preparation of a glass waveguide structure with good transmission performance.

[0063] As an example, the glass composite may be wafer-scale in size.

[0064] Specifically, in this embodiment, it is preferred that the glass composite body has a wafer-level size, such as 4 inches, 6 inches, 8 inches, 12 inches, etc., to facilitate the preparation of a high-efficiency wafer-level packaging structure. The specific size of the glass composite body is not overly limited herein, and the thickness of the glass substrate 100 and the glass waveguide layer 200 in the glass composite body can also be selected as needed.

[0065] Next, see Figure 1 , Figure 3 and Figure 4 , executing step S2, patterning the glass waveguide layer 200 to expose a portion of the glass substrate 100.

[0066] For details, see Figure 3 The patterned photoresist layer 300 can be formed by coating the glass waveguide layer 200 with photoresist, selecting a mask of a desired pattern, and then performing exposure and development steps. Then, the glass waveguide layer 200 is etched based on the photoresist layer 300, and then the excess photoresist layer 300 is removed to prepare the patterned glass waveguide layer 200.

[0067] For the morphology of the glass waveguide layer 200, please refer to Figure 5 ,in, Figure 5 6 structural schematic diagrams of the glass waveguide layer 200 with different morphologies are illustrated in FIG. The morphology of the glass waveguide layer 200 is not limited thereto. A desired patterned mask can be selected and set as needed to form the photoresist layer 300 with different morphologies, and the glass waveguide layer 200 with different morphologies can be prepared by etching. The specific morphology of the glass waveguide layer 200 is not excessively limited herein.

[0068] The material of the photoresist layer 300 may be positive photoresist or negative photoresist, which may be selected according to actual needs and is not limited here.

[0069] Next, see Figure 1 and Figure 6 , executing step S3 , forming a dielectric layer 400 on the exposed glass substrate 100 , wherein the dielectric layer 400 covers the glass waveguide layer 200 , and the refractive index of the dielectric layer 400 is smaller than the refractive index of the glass waveguide layer 200 .

[0070] Specifically, the material of the dielectric layer 400 may be an insulating material such as polyimide (PI) or silicon oxide to avoid subsequent influence on electrical transmission.

[0071] Furthermore, when selecting the material of the dielectric layer 400 , the refractive index of the selected material needs to be considered so that the dielectric layer 400 can be applied as the upper cladding layer of the glass waveguide layer 200 .

[0072] Next, see Figure 1 and Figure 7 , performing step S4 to form a metal column 500 penetrating the dielectric layer 400 and the glass substrate 100 .

[0073] Specifically, the step of forming the metal pillar 500 may include forming a through hole (not shown) penetrating the dielectric layer 400 and the glass substrate 100 , and filling the through hole with metal.

[0074] The punching method may include a laser punching method or a mechanical drilling method, which may be selected according to needs, and the metal filling method may be an electroplating method or the like.

[0075] The specific steps of preparing the metal pillar 500, the size of the metal pillar 500 and the distribution of the metal pillar 500 are not overly limited here and can be selected according to needs. The material of the metal pillar 500 can be copper metal, but is not limited thereto, and other conductive metal materials can also be used.

[0076] Next, see Figure 1 and Figure 8 , executing step S5, forming a first redistribution layer 610 on the dielectric layer 400 and forming a second redistribution layer 620 on the glass substrate 100, and the first redistribution layer 610 and the second redistribution layer 620 are both electrically connected to the metal pillar 500.

[0077] Specifically, the method of forming the first redistribution layer 610 on the dielectric layer 400 may include a semiconductor process method or a substrate bonding method. Similarly, the method of forming the second redistribution layer 620 on the glass substrate 100 may include a semiconductor process method or a substrate bonding method.

[0078] Among them, the semiconductor process method is a method of preparing the first rewiring layer 610 and the second rewiring layer 620 by coating, exposure, development, deposition, etching and other steps, and the substrate bonding method is a method of preparing the required first rewiring layer 610 and the second rewiring layer 620 in advance, and then bonding the first rewiring layer 610 and the second rewiring layer 620 to the dielectric layer 400 and the glass substrate 100 respectively.

[0079] Since both the first re-distribution layer 610 and the second re-distribution layer 620 are electrically connected to the metal pillar 500 , the first re-distribution layer 610 and the second re-distribution layer 620 can be electrically interconnected through the metal pillar 500 .

[0080] There is no excessive restriction on the specific structure, material and preparation method of the first rewiring layer 610 and the second rewiring layer 620, and they can be selected according to needs. The two can use the same structure, material and preparation method, or of course different structures, materials and preparation methods.

[0081] Next, see Figure 1 , Fig. 9 and Fig.10 , performing step S6 to form a through groove 700 penetrating the first redistribution layer 610 , the dielectric layer 400 , the glass substrate 100 and the second redistribution layer 620 , and the sidewall of the through groove 700 exposes the glass waveguide layer 200 .

[0082] Specifically, the method for forming the through groove 700 may include a laser drilling method or a mechanical drilling method. The preparation method, size, morphology and distribution of the through groove 700 may be selected according to needs. Fig.10 A distribution diagram of a plurality of the through grooves 700 having a rectangular shape is shown. It should be noted that, in order to construct a subsequent light transmission path, the sidewall of the through groove 700 needs to expose the glass waveguide layer 200 .

[0083] Next, see Figure 1 and Fig.11 , execute step S7, provide a composite adapter board, the composite adapter board includes an adapter board 800 and a third rewiring layer 630 and a fourth rewiring layer 640 located on both sides of the adapter board 800, and the adapter board 800, the third rewiring layer 630 and the fourth rewiring layer 640 are electrically connected.

[0084] As an example, the adapter board 800 may include a TSV adapter board or a TGV adapter board, and the specific type may be selected according to needs.

[0085] The third rewiring layer 630 and the fourth rewiring layer 640 can be electrically interconnected in combination with the adapter plate 800 located in the middle. The specific structure and preparation method of the composite adapter plate are not limited herein.

[0086] Next, see Figure 1 and Fig.11 , executing step S8, bonding the composite transfer board to the second rewiring layer 620 and being located above the through groove 700, and the third rewiring layer 630 is electrically connected to the second rewiring layer 620.

[0087] Specifically, the composite adapter plate can be bonded to the second rewiring layer 620 by a reflow process, and the electrical interconnection between the third rewiring layer 630 and the second rewiring layer 620 can be achieved by solder balls. Of course, the bonding method between the composite adapter plate and the second rewiring layer 620 is not limited to this. The portion of the composite adapter plate exposed in the through groove 700 can have a pad, which can facilitate the subsequent electrical interconnection with the optical chip.

[0088] Next, see Figure 1 , Fig.12 and Fig.13 , execute step S9, provide an electric chip 910 and a side-light-emitting chip 920, and bond the electric chip 910 to the fourth rewiring layer 640, and the electric chip 910 is electrically connected to the fourth rewiring layer 640, and bond the side-light-emitting chip 920 into the through groove 700, the side-light-emitting chip 920 is electrically connected to the third rewiring layer 630, and the photosensitive area 921 of the side-light-emitting chip 920 is arranged corresponding to the glass waveguide layer 200.

[0089] Specifically, after the side-light emitting chip 920 is bonded in the through groove 700, the side-light emitting chip 920 can be electrically interconnected with the third rewiring layer 630, and the photosensitive area 921 of the side-light emitting chip 920 is arranged corresponding to the glass waveguide layer 200, so as to form an optical transmission path. The electrical chip 910 may include active components configured to operate exclusively using electrical signals, such as one or more transistors, voltage converters, transimpedance amplifiers (TIA), clock data recovery (CDR) components, microcontrollers, etc. The electrical chip 910 may include multiple functions, such as driving, processing and clearing signals from and to the side-light emitting chip 920, and providing necessary voltages to the side-light emitting chip 920. The specific types, quantities and distributions of the electrical chip 910 and the side-light emitting chip 920 are not overly limited here.

[0090] As an example, a bottom filling layer 110 may be provided between the electric chip 910 and the fourth rewiring layer 640 to cover the gap between the electric chip 910 and the fourth rewiring layer 640 through the bottom filling layer 110 to protect the electric chip 910 and the fourth rewiring layer 640.

[0091] Next, see Figure 1 and Fig.14 , performing step S10, forming a metal bump 120 on the first rewiring layer 610, and the metal bump 120 is electrically connected to the first rewiring layer 610. The preparation and material of the metal bump 120 are not excessively limited here.

[0092] Furthermore, when the glass composite is of wafer-level size, a cutting process step may be used after forming the metal bumps 120 to divide the prepared wafer-level packaging structure into a plurality of independently arranged packaging monomer structures to improve production efficiency. The cutting process may be mechanical cutting or laser cutting, which is not excessively limited here.

[0093] See also Figure 2~Figure 14This embodiment also provides a 3D optoelectronic interconnect packaging structure, wherein the 3D optoelectronic interconnect packaging structure can be directly prepared using the above-mentioned preparation process, so that the material, structure, etc. of the 3D optoelectronic interconnect packaging structure can refer to the above content. Of course, according to needs, the 3D optoelectronic interconnect packaging structure can also be prepared using other preparation processes.

[0094] In this embodiment, the 3D optoelectronic interconnect packaging structure includes:

[0095] A glass composite, wherein the glass composite comprises a stacked glass substrate 100 and a patterned glass waveguide layer 200, wherein the glass waveguide layer 200 exposes a portion of the glass substrate 100, and a refractive index of the glass waveguide layer 200 is greater than a refractive index of the glass substrate 100;

[0096] a dielectric layer 400 , wherein the dielectric layer 400 is located on the exposed glass substrate 100 and covers the glass waveguide layer 200 , and a refractive index of the dielectric layer 400 is smaller than a refractive index of the glass waveguide layer 200 ;

[0097] A metal column 500 , wherein the metal column 500 penetrates the dielectric layer 400 and the glass substrate 100 ;

[0098] A first rewiring layer 610, wherein the first rewiring layer 610 is located on the dielectric layer 400, and the first rewiring layer 610 is electrically connected to the metal pillar 500;

[0099] A second rewiring layer 620, wherein the second rewiring layer 620 is located on the glass substrate 100, and the second rewiring layer 620 is electrically connected to the metal pillar 500;

[0100] a through groove 700 , wherein the through groove 700 penetrates the first redistribution layer 610 , the dielectric layer 400 , the glass substrate 100 , and the second redistribution layer 620 , and the sidewall of the through groove 700 exposes the glass waveguide layer 200 ;

[0101] A composite adapter plate, the composite adapter plate is bonded to the second rewiring layer 620 and is located above the through groove 700, including an adapter plate 800 and a third rewiring layer 630 and a fourth rewiring layer 640 located on both sides of the adapter plate 800, the adapter plate 800, the third rewiring layer 630 and the fourth rewiring layer 640 are electrically connected, and the third rewiring layer 630 is electrically connected to the second rewiring layer 620;

[0102] An electrical chip 910, wherein the electrical chip 910 is bonded to the fourth rewiring layer 640, and the electrical chip 910 is electrically connected to the fourth rewiring layer 640;

[0103] A lateral light-emitting chip 920, wherein the lateral light-emitting chip 920 is bonded in the through groove 700, the lateral light-emitting chip 920 is electrically connected to the third rewiring layer 630, and a photosensitive area 921 of the lateral light-emitting chip 920 is arranged corresponding to the glass waveguide layer 200;

[0104] A metal bump 120 , wherein the metal bump 120 is located on the first re-distribution layer 610 , and the metal bump 120 is electrically connected to the first re-distribution layer 610 .

[0105] As an example, the dielectric layer 400 may include a polyimide dielectric layer or a silicon oxide dielectric layer.

[0106] Specifically, the material of the dielectric layer 400 may be an insulating material such as polyimide (PI) or silicon oxide to avoid subsequent influence on electrical transmission.

[0107] Furthermore, when selecting the material of the dielectric layer 400 , the refractive index of the selected material needs to be considered so that the dielectric layer 400 can be applied as the upper cladding layer of the glass waveguide layer 200 .

[0108] As an example, the interposer 800 may include a TSV interposer or a TGV interposer.

[0109] As an example, a bottom filling layer 110 may be provided between the electric chip 910 and the fourth rewiring layer 640 to cover the gap between the electric chip 910 and the fourth rewiring layer 640 through the bottom filling layer 110 to protect the electric chip 910 and the fourth rewiring layer 640.

[0110] In summary, the 3D optoelectronic interconnect packaging structure and preparation method thereof of the present invention adopts a glass composite combined with a dielectric layer to construct a glass waveguide structure, and by forming a through groove exposing the glass waveguide layer and bonding a side-light-emitting chip in the through groove, the photosensitive area of ​​the side-light-emitting chip and the glass waveguide layer can construct a light transmission path, and optoelectronic interconnection can be achieved through the interconnection of metal columns, a rewiring layer and an adapter plate.

[0111] The 3D optoelectronic interconnect packaging structure and the preparation method thereof of the present invention can realize optoelectronic interconnect integration, reduce packaging size, reduce power consumption, improve reliability, are suitable for high-density integrated packaging, and can realize good optoelectronic transmission.

[0112] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a 3D optoelectronic interconnect packaging structure, characterized in that: The following steps are involved: Providing a glass composite, the glass composite comprising a stacked glass substrate and a glass waveguide layer, wherein the refractive index of the glass waveguide layer is greater than the refractive index of the glass substrate; Patterning the glass waveguide layer to expose a portion of the glass substrate; forming a dielectric layer on the exposed glass substrate, wherein the dielectric layer covers the glass waveguide layer, and the refractive index of the dielectric layer is smaller than the refractive index of the glass waveguide layer; forming a metal column penetrating the dielectric layer and the glass substrate; Forming a first redistribution layer on the dielectric layer and forming a second redistribution layer on the glass substrate, wherein the first redistribution layer and the second redistribution layer are both electrically connected to the metal pillar; forming a through groove penetrating the first redistribution layer, the dielectric layer, the glass substrate and the second redistribution layer, wherein the glass waveguide layer is exposed on a sidewall of the through groove; Providing a composite adapter plate, the composite adapter plate comprising an adapter plate and a third rewiring layer and a fourth rewiring layer located on both sides of the adapter plate, and the adapter plate, the third rewiring layer and the fourth rewiring layer are electrically connected; Bonding the composite transfer board to the second rewiring layer and being located above the through groove, wherein the third rewiring layer is electrically connected to the second rewiring layer; Providing an electric chip and a side-light emitting chip, and bonding the electric chip to the fourth rewiring layer, and the electric chip is electrically connected to the fourth rewiring layer, and bonding the side-light emitting chip to the through groove, and the side-light emitting chip is electrically connected to the third rewiring layer, and the photosensitive area of ​​the side-light emitting chip is arranged corresponding to the glass waveguide layer; A metal bump is formed on the first rewiring layer, and the metal bump is electrically connected to the first rewiring layer.

2. The method for preparing the 3D optoelectronic interconnect packaging structure according to claim 1, characterized in that: The method for preparing the glass composite comprises a fusion draw lamination method.

3. The method for preparing the 3D optoelectronic interconnect packaging structure according to claim 1, characterized in that: The dielectric layer includes a polyimide dielectric layer or a silicon oxide dielectric layer.

4. The method for preparing the 3D optoelectronic interconnect packaging structure according to claim 1, characterized in that: The method of punching holes when forming the metal pillars includes a laser punching method or a mechanical drilling method; the method of forming the through-grooves includes a laser punching method or a mechanical drilling method.

5. The method for preparing the 3D optoelectronic interconnect packaging structure according to claim 1, characterized in that: The adapter board includes a TSV adapter board or a TGV adapter board.

6. The method for preparing the 3D optoelectronic interconnect packaging structure according to claim 1, characterized in that: The method further includes forming an underfill layer between the electric chip and the fourth rewiring layer.

7. The method for preparing the 3D optoelectronic interconnect packaging structure according to claim 1, characterized in that: The glass composite has a wafer-level size and further includes a dicing process step after forming the metal bumps.

8. A 3D optoelectronic interconnect packaging structure, characterized in that: The 3D optoelectronic interconnect packaging structure comprises: A glass composite, the glass composite comprising a stacked glass substrate and a patterned glass waveguide layer, the glass waveguide layer partially exposing the glass substrate, and the refractive index of the glass waveguide layer is greater than the refractive index of the glass substrate; a dielectric layer, the dielectric layer being located on the exposed glass substrate and covering the glass waveguide layer, and the refractive index of the dielectric layer being smaller than the refractive index of the glass waveguide layer; a metal column, wherein the metal column penetrates the dielectric layer and the glass substrate; A first rewiring layer, wherein the first rewiring layer is located on the dielectric layer and is electrically connected to the metal pillar; a second redistribution layer, the second redistribution layer being located on the glass substrate and electrically connected to the metal pillar; a through groove, wherein the through groove penetrates the first redistribution layer, the dielectric layer, the glass substrate and the second redistribution layer, and the sidewall of the through groove exposes the glass waveguide layer; A composite adapter plate, the composite adapter plate is bonded to the second rewiring layer and is located above the through groove, comprising an adapter plate and a third rewiring layer and a fourth rewiring layer located on both sides of the adapter plate, the adapter plate, the third rewiring layer and the fourth rewiring layer are electrically connected, and the third rewiring layer is electrically connected to the second rewiring layer; an electric chip, the electric chip being bonded to the fourth rewiring layer and the electric chip being electrically connected to the fourth rewiring layer; A lateral light-emitting chip, wherein the lateral light-emitting chip is bonded in the through groove, the lateral light-emitting chip is electrically connected to the third rewiring layer, and a photosensitive area of ​​the lateral light-emitting chip is arranged corresponding to the glass waveguide layer; A metal bump is located on the first rewiring layer and is electrically connected to the first rewiring layer.

9. The 3D optoelectronic interconnect packaging structure according to claim 8, characterized in that: The dielectric layer includes a polyimide dielectric layer or a silicon oxide dielectric layer; the adapter includes a TSV adapter or a TGV adapter.

10. The 3D optoelectronic interconnect packaging structure according to claim 8, characterized in that: A bottom filling layer is also provided between the electric chip and the fourth rewiring layer.

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