Array substrate and manufacturing method thereof, and display panel

Abstract

The present application belongs to the field of display, and specifically relates to an array substrate and a manufacturing method thereof, and a display panel. The array substrate includes a base substrate, a first metal layer, a gate insulating layer, a channel layer, and a second metal layer. The first metal layer is formed on one side of the base substrate. The first metal layer includes a gate electrode and a common electrode arranged at intervals. The gate insulating layer is formed on the side of the first metal layer away from the base substrate. The channel layer is formed on the side of the gate insulating layer away from the base substrate. The second metal layer is formed on the side of the channel layer away from the base substrate. The second metal layer includes a source electrode, a drain electrode, and a reflective electrode. The source electrode and the drain electrode are arranged at intervals. The reflective electrode is connected to the drain electrode. The pixel electrode of the array substrate includes a reflective electrode. In this embodiment, the reflective electrode is reused as a pixel electrode. The source electrode, the drain electrode, the reflective electrode, and the pixel electrode are located in the same metal layer, and can be manufactured using the same photomask process, thereby reducing the complexity of the process flow and the manufacturing cost of the array substrate.

Description

Technical Field

[0001] The present application belongs to the field of display, and specifically relates to an array substrate and a manufacturing method thereof, and a display panel. Background Art

[0002] Display panels include liquid crystal display panels (LCD) and electronic paper (e-Paper) display panels, etc., and both the LCD display panels and the electronic paper display panels include an array substrate.

[0003] The array substrate includes a base substrate, and a gate, a gate insulating layer, a channel layer, a source and drain, an insulating protection layer, a pixel electrode, a planar layer and a reflective layer formed in sequence on the base substrate. The gate, the channel layer and the source and drain constitute a transistor connected to the pixel electrode.

[0004] When manufacturing an existing array substrate, at least seven mask processes are required to form a gate, a channel layer, a source and drain, an insulating protection layer, a pixel electrode, a planarization layer and a reflective layer respectively. The process flow is complicated, resulting in a significant increase in the manufacturing cost of the array substrate. Summary of the invention

[0005] The purpose of the present application is to provide an array substrate and a manufacturing method thereof, and a display panel, so as to reduce the number of mask processes required for manufacturing the array substrate and reduce the manufacturing cost of the array substrate.

[0006] In order to achieve the above object, the present application provides an array substrate, including a base substrate, and the array substrate further includes:

[0007] A first metal layer is formed on one side of the base substrate, wherein the first metal layer includes a gate electrode and a common electrode that are spaced apart from each other;

[0008] A gate insulating layer is formed on a side of the first metal layer away from the substrate;

[0009] A channel layer is formed on a side of the gate insulating layer away from the substrate, and the channel layer at least covers the gate;

[0010] A second metal layer is formed on a side of the channel layer away from the base substrate, the second metal layer includes a source electrode, a drain electrode and a reflective electrode, the source electrode and the drain electrode are arranged at intervals, the orthographic projections of the source electrode and the drain electrode on the base substrate overlap with the gate electrode, the orthographic projection of the reflective electrode on the base substrate overlaps with the common electrode, the reflective electrode is connected to the drain electrode, and the pixel electrode of the array substrate includes the reflective electrode.

[0011] Optionally, the array substrate further includes a plurality of bosses, the common electrode includes a plurality of electrode units arranged at intervals, the bosses are arranged on a side of the electrode units away from the base substrate, the gate insulation layer, the channel layer, and the second metal layer all cover a side of the bosses away from the base substrate, and the bosses are used to make the reflective electrode uneven.

[0012] Optionally, the material of the boss is different from the material of the first metal layer.

[0013] Optionally, the material used to make the boss includes photoresist, and the photoresist includes soluble polytetrafluoroethylene.

[0014] Optionally, the material used to make the channel layer includes molybdenum disulfide.

[0015] Optionally, the array substrate further includes an insulating protective layer, the insulating protective layer is formed on a side of the second metal layer away from the base substrate, and the insulating protective layer at least covers the source electrode and the drain electrode.

[0016] Optionally, the insulating protection layer covers the second metal layer, and a material for making the insulating protection layer includes fluorinated polyimide.

[0017] The present application also provides a method for manufacturing an array substrate, comprising:

[0018] Forming a first metal layer on one side of the base substrate, wherein the first metal layer includes a gate electrode and a common electrode that are spaced apart;

[0019] Forming a gate insulating layer, a channel material layer, and a second metal material layer in sequence on a side of the first metal layer away from the base substrate;

[0020] The second metal material layer and the channel material layer are patterned to form a second metal layer and a channel layer, wherein the second metal layer includes a source electrode, a drain electrode and a reflective electrode, wherein the source electrode and the drain electrode are arranged at intervals, and the orthographic projections of the source electrode and the drain electrode on the substrate overlap with the gate electrode, and the orthographic projection of the reflective electrode on the substrate overlaps with the common electrode, and the reflective electrode is connected to the drain electrode.

[0021] Optionally, the method of forming the first metal layer includes:

[0022] forming a first metal material layer on the base substrate;

[0023] forming a photoresist layer on a side of the first metal material layer away from the substrate;

[0024] Patterning the photoresist layer using a grayscale mask to form a first etch stop region and a plurality of second etch stop regions, wherein the thickness of the first etch stop region is less than the thickness of the second etch stop region;

[0025] Etching the first metal material layer to form the first metal layer, wherein the common electrode of the first metal layer includes a plurality of electrode units arranged at intervals;

[0026] The patterned photoresist layer is etched to completely remove the first etch stop region and partially remove the second etch stop region, and the remaining second etch stop region forms a boss, and the boss is used to make the reflective electrode uneven.

[0027] The present application also provides a display panel, comprising:

[0028] the array substrate;

[0029] The opposing substrate is arranged on one side of the array substrate.

[0030] The array substrate and its manufacturing method, and the display panel disclosed in the present application have the following beneficial effects:

[0031] In the present application, the array substrate includes a base substrate, a first metal layer, a gate insulating layer, a channel layer, and a second metal layer. The first metal layer is formed on one side of the base substrate. The first metal layer may include a gate electrode and a common electrode arranged at intervals. The gate insulating layer is formed on the side of the first metal layer away from the base substrate. The channel layer is formed on the side of the gate insulating layer away from the base substrate. The channel layer at least covers the gate electrode. The second metal layer is formed on the side of the channel layer away from the base substrate. The second metal layer includes a source electrode, a drain electrode, and a reflective electrode. The reflective electrode is connected to the drain electrode. The pixel electrode of the array substrate includes a reflective electrode. In this embodiment, the reflective electrode is reused as a pixel electrode. The source electrode, the drain electrode, the reflective electrode, and the pixel electrode are located in the same metal layer. The same photomask process can be used to manufacture the same photomask process, which reduces the complexity of the process flow, improves the manufacturing efficiency of the array substrate, and reduces the manufacturing cost of the array substrate.

[0032] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by the practice of the present application.

[0033] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0035] Figure 1 It is a structural schematic diagram of the array substrate in Example 1 of the present application.

[0036] Figure 2 It is a flow chart of the method for manufacturing the array substrate in the second embodiment of the present application.

[0037] Figure 3 It is a schematic diagram of exposing the photoresist layer in the second embodiment of the present application.

[0038] Figure 4 It is a schematic diagram of the patterned photoresist layer in Example 2 of the present application.

[0039] Figure 5 This is a schematic diagram of etching the first metal layer in Example 2 of the present application.

[0040] Figure 6 It is a schematic diagram of the boss formed in the second embodiment of the present application.

[0041] Figure 7 It is a schematic diagram of forming a gate insulating layer, a channel layer and a second metal layer in the second embodiment of the present application.

[0042] Figure 8 This is a schematic diagram of etching the second metal layer in the second embodiment of the present application.

[0043] Fig. 9 It is a schematic diagram of forming source and drain in the second embodiment of the present application.

[0044] Fig.10 It is a schematic diagram of etching the insulating protection layer in the second embodiment of the present application.

[0045] Fig.11 It is a schematic diagram of the structure of the display panel in the third embodiment of the present application.

[0046] Description of reference numerals:

[0047] 10. Array substrate; 100. Base substrate; 200. First metal layer; 201. First metal material layer; 210. Gate; 220. Common electrode; 221. Electrode unit; 300. Gate insulating layer; 400. Channel layer; 401. Channel material layer; 500. Second metal layer; 501. Second metal material layer; 510. Source; 520. Drain; 530. Reflective electrode; 600. Photoresist layer; 610. First etch stop region; 620. Second etch stop region; 621. Boss; 700. Ohmic contact layer; 701. Ohmic contact material layer; 800. Insulating protection layer; 801. Insulating material layer;

[0048] 20. Counter substrate. DETAILED DESCRIPTION

[0049] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0050] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0051] The present application is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0052] Embodiment 1

[0053] See also Figure 1As shown, in this embodiment, the array substrate 10 includes a base substrate 100, a first metal layer 200, a gate insulating layer 300, a channel layer 400 and a second metal layer 500. The base substrate 100 includes a glass substrate, a polyimide (Pi) substrate, a silicon substrate, a polymer substrate and a stainless steel substrate. The first metal layer 200 is formed on one side of the base substrate 100, and the first metal layer 200 may include a gate 210 and a common electrode 220 arranged at intervals. In addition, the first metal layer 200 may also include a scan line and a marking pattern, which are not shown in the figure. The gate 210 is connected to the scan line, and the marking pattern is used as a reference for the subsequent process. The manufacturing material of the first metal layer 200 includes metal materials such as copper and aluminum and their alloys.

[0054] The gate insulating layer 300 is formed on the side of the first metal layer 200 away from the substrate 100. The materials used to make the gate insulating layer 300 include silicon dioxide (SiO2), hafnium dioxide (HfO2), aluminum oxide (Al2O3) and silicon nitride (Si3N4). The channel layer 400 is formed on the side of the gate insulating layer 300 away from the substrate 100, and the channel layer 400 at least covers the gate 210, that is, the gate 210 is located within the orthographic projection of the channel layer 400 on the substrate 100. The materials used to make the channel layer 400 include amorphous silicon (a-Si), molybdenum disulfide (MoS2), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN) and indium phosphide (InP).

[0055] The second metal layer 500 is formed on the side of the channel layer 400 away from the base substrate 100, and the second metal layer 500 includes a source electrode 510, a drain electrode 520 and a reflective electrode 530. The source electrode 510 and the drain electrode 520 are arranged at intervals, and the orthographic projection of the source electrode 510 on the base substrate 100 overlaps with the gate electrode 210, and the orthographic projection of the drain electrode 520 on the base substrate 100 overlaps with the gate electrode 210. The reflective electrode 530 is connected to the drain electrode 520, and the orthographic projection of the reflective electrode 530 on the base substrate 100 overlaps or roughly coincides with the common electrode 220. The second metal layer 500 may also include a data line not shown in the figure, and the data line is connected to the source electrode 510. The manufacturing material of the second metal layer 500 includes metal materials such as copper, aluminum and alloys thereof, and the manufacturing material of the second metal layer 500 may be the same as the manufacturing material of the first metal layer 200.

[0056] The pixel electrode of the array substrate 10 includes a reflective electrode 530, that is, the reflective electrode 530 can be reused as the pixel electrode of the array substrate 10, and the pixel electrode can form a storage capacitor with the common electrode 220. It should be noted that the reflective electrode 530 can be used as the pixel electrode of the array substrate 10, but is not limited thereto. An indium tin oxide (ITO) electrode can also be formed on the side of the reflective electrode 530 away from the base substrate 100, and the indium tin oxide electrode is connected to the reflective electrode 530. The pixel electrode of the array substrate 10 includes the reflective electrode 530 and the indium tin oxide electrode, which can be determined according to the specific situation.

[0057] In this embodiment, the array substrate 10 includes a base substrate 100, a first metal layer 200, a gate insulating layer 300, a channel layer 400 and a second metal layer 500. The first metal layer 200 is formed on one side of the base substrate 100. The first metal layer 200 may include a gate electrode 210 and a common electrode 220 that are spaced apart. The gate insulating layer 300 is formed on a side of the first metal layer 200 away from the base substrate 100. The channel layer 400 is formed on a side of the gate insulating layer 300 away from the base substrate 100. The channel layer 400 at least covers the gate electrode 210. The second metal layer 500 is formed on a side of the channel layer 400 away from the base substrate 100. The second metal layer 500 includes a source electrode 510, a drain electrode 520 and a reflective electrode 530. The reflective electrode 530 is connected to the drain electrode 520. The pixel electrode of the array substrate 10 includes the reflective electrode 530. In this embodiment, the reflective electrode 530 is reused as the pixel electrode. The source 510, the drain 520, the reflective electrode 530 and the pixel electrode are located in the same metal layer and can be manufactured using the same photomask process, thereby reducing the complexity of the process flow, improving the manufacturing efficiency of the array substrate 10, and reducing the manufacturing cost of the array substrate 10.

[0058] In addition, the reflective electrode 530 and the pixel electrode are located in the same metal layer. Compared with the solution in which the pixel electrode and the reflective layer are arranged on both sides of the planar layer, the planar layer can be omitted, thereby simplifying the structure of the array substrate 10.

[0059] In some embodiments, the array substrate 10 further includes a plurality of bosses 621, the common electrode 220 includes a plurality of electrode units 221 arranged at intervals, and the bosses 621 are arranged on the side of the electrode units 221 away from the base substrate 100. The gate insulating layer 300, the channel layer 400, and the second metal layer 500 all cover the side of the bosses 621 away from the base substrate 100. The bosses 621 can make the gate insulating layer 300 and the channel layer 400 above them uneven, and finally make the reflective electrode 530 uneven.

[0060] The reflective electrode 530 is uneven, and the reflective electrode 530 reflects light in a diffuse reflection manner. The array substrate 10 is used for a display panel, and can improve the display effect of the display panel.

[0061] In some embodiments, the material of the boss 621 is different from the material of the first metal layer 200 .

[0062] The material of the boss 621 is different from the material of the first metal layer 200 . The boss 621 and the first metal layer 200 have etching selectivity and can be manufactured in the same photomask process.

[0063] In some embodiments, the material of the boss 621 includes photoresist, and the photoresist includes soluble polytetrafluoroethylene (PFA), which is a positive photoresist. It should be noted that the boss 621 can be made of positive photoresist, but is not limited thereto. The boss 621 can also be made of negative photoresist, depending on the specific situation.

[0064] The boss 621 is made of photoresist, which can further simplify the manufacturing process of the array substrate 10 and reduce the manufacturing cost of the array substrate 10 .

[0065] In some embodiments, the array substrate 10 further includes an ohmic contact layer 700, which is formed between the second metal layer 500 and the channel layer 400. The source 510 and the drain 520 are both connected to the channel layer 400 through the ohmic contact layer 700. The ohmic contact layer 700 can be made of a doped channel layer 400 material.

[0066] The ohmic contact layer 700 can reduce the contact resistance between the source 510 , the drain 520 and the channel layer 400 , thereby improving the performance of the transistor.

[0067] In some embodiments, the material of the channel layer 400 includes molybdenum disulfide. When the array substrate 10 is used in a liquid crystal display panel or an electronic paper display panel, the pixel electrode and the common electrode 220 form a storage capacitor, and the pixel electrode and the electrode on one side of the opposite substrate form an electric field to drive the liquid crystal molecules or electronic ink to realize the picture display.

[0068] The channel layer 400 is made of molybdenum disulfide with a high dielectric constant, which can increase the storage capacitor formed by the common electrode 220 and the reflective electrode 530, thereby improving the ability of the array substrate 10 to drive liquid crystal molecules or electronic ink and improving the display effect of the display panel.

[0069] In some embodiments, the array substrate 10 further includes an insulating protective layer 800, which is formed on the side of the second metal layer 500 away from the base substrate 100, and the insulating protective layer 800 at least covers the source 510 and the drain 520. In other words, the side of the reflective electrode 530 away from the base substrate 100 does not need to be covered with the insulating protective layer 800. The materials used to make the insulating protective layer 800 include silicon dioxide, silicon nitride, silicon oxynitride (SiON), and aluminum oxide. The insulating protective layer 800 can protect the transistor formed by the gate 210, the channel layer 400, the source 510, and the drain 520, and reduce the risk of water vapor intrusion.

[0070] The pixel electrode and the insulating protective layer 800 on the side of the reflective electrode 530 away from the base substrate 100 are eliminated, and the reflective electrode 530 is reused as the pixel electrode. When external light irradiates the reflective electrode 530, it does not pass through the pixel electrode and the insulating protective layer 800, and when the reflected light is emitted, it does not pass through the pixel electrode and the insulating protective layer 800, thereby improving the light transmittance of the array substrate 10 and improving the display effect of the display panel.

[0071] It should be noted that, since the periphery of the display panel is sealed with frame glue and the insulating protective layer 800 protects the transistors that are easily affected by water vapor intrusion, even if the reflective electrode 530 is not covered with the insulating protective layer 800, the array substrate 10 and the display panel can be guaranteed to operate normally without affecting the life of the array substrate 10 and the display panel.

[0072] In some embodiments, the insulating protection layer 800 covers the second metal layer 500 , and the material of the insulating protection layer 800 includes fluorinated polyimide.

[0073] The insulating protective layer 800 is made of fluorinated polyimide. The fluorinated polyimide uses a polymerization method to synthesize two different solution-processable polyimides rich in trifluoromethyl. They have good solubility in organic solvents and have transparent and colorless optical properties. Compared with the existing insulating protective layer 800 materials, the light transmittance is significantly increased. Therefore, the insulating protective layer 800 is made of fluorinated polyimide to achieve the purpose of improving the display effect of the display panel.

[0074] In some embodiments, an anti-reflection film (not shown) is formed on the side of the insulating protection layer 800 away from the base substrate 100, and the anti-reflection film at least covers the reflective electrode 530. The anti-reflection film is made of materials including magnesium fluoride (MgF2) and silicon dioxide.

[0075] The anti-reflection film can reduce optical surface reflection and increase light transmittance. The anti-reflection film is arranged on the side of the reflective electrode 530 away from the base substrate 100, which can further increase the light transmittance of the array substrate 10 and improve the display effect of the display panel.

[0076] Embodiment 2

[0077] See also Figures 2 to 10 As shown, the manufacturing method of the array substrate 10 in this embodiment includes:

[0078] S100: forming a first metal layer 200 on one side of the base substrate 100, wherein the first metal layer 200 includes a gate electrode 210 and a common electrode 220 which are spaced apart from each other;

[0079] S200: forming a gate insulating layer 300, a channel material layer 401 and a second metal material layer 501 in sequence on a side of the first metal layer 200 away from the base substrate 100;

[0080] S300: patterning the second metal material layer 501 and the channel material layer 401 to form a second metal layer 500 and a channel layer 400, wherein the second metal layer 500 includes a source electrode 510, a drain electrode 520 and a reflective electrode 530, wherein the source electrode 510 and the drain electrode 520 are arranged at intervals, and the orthographic projections of the source electrode 510 and the drain electrode 520 on the base substrate 100 overlap with the gate electrode 210, and the orthographic projection of the reflective electrode 530 on the base substrate 100 overlaps or roughly coincides with the common electrode 220, and the reflective electrode 530 is connected to the drain electrode 520.

[0081] Before forming the second metal material layer 501, an ohmic contact material layer 701 may be formed to reduce the contact resistance between the source 510, the drain 520 and the channel layer 400, thereby improving the performance of the transistor. The second metal layer 500 may be formed by methods such as radio frequency magnetron sputtering, inkjet printing, atomic layer deposition, plasma chemical vapor deposition, and laser molecular beam epitaxy. The gate insulating layer 300, the channel material layer 401, and the ohmic contact material layer 701 may be formed by methods such as atomic layer deposition, plasma chemical vapor deposition, radio frequency magnetron sputtering, and inkjet printing.

[0082] The orthographic projection of the source electrode 510 on the base substrate 100 may be partially located in the region where the gate electrode 210 is located and partially located outside the region where the gate electrode 210 is located, and the orthographic projection of the drain electrode 520 on the base substrate 100 may be partially located in the region where the gate electrode 210 is located and partially located outside the region where the gate electrode 210 is located. The orthographic projection of the reflective electrode 530 on the base substrate 100 substantially overlaps with the common electrode 220, that is, the orthographic projection of the reflective electrode 530 on the base substrate 100 is located in the region where the common electrode 220 is located, or the region where the common electrode 220 is located is located within the orthographic projection of the reflective electrode 530 on the base substrate 100.

[0083] In this embodiment, the reflective electrode 530 is reused as the pixel electrode. The source 510, the drain 520, the reflective electrode 530 and the pixel electrode are located in the same metal layer and can be manufactured using the same photomask process, thereby reducing the complexity of the process flow, improving the manufacturing efficiency of the array substrate 10, and reducing the manufacturing cost of the array substrate 10.

[0084] In some embodiments, the same photomask is used to etch the channel material layer 401, the ohmic contact material layer 701 and the second metal material layer 501. After the second metal material layer 501 is formed, the second metal material layer 501 is etched to form a channel, the channel runs through the second metal material layer 501, the ohmic contact material layer 701 and extends into the channel material layer 401, the patterned second metal material layer 501 forms the second metal layer 500, the patterned ohmic contact material layer 701 forms the ohmic contact layer 700, and the patterned channel material layer 401 forms the channel layer 400. The ohmic contact layer 700 and the channel layer 400 on the side of the reflective electrode 530 close to the base substrate 100 do not need to be etched away.

[0085] The same mask is used for etching the channel material layer 401 , the ohmic contact material layer 701 and the second metal material layer 501 , which further reduces the complexity of the process flow, improves the manufacturing efficiency of the array substrate 10 , and reduces the manufacturing cost of the array substrate 10 .

[0086] In some embodiments, a method of forming the first metal layer 200 includes:

[0087] Forming a first metal material layer 201 on the base substrate 100;

[0088] A photoresist layer 600 is formed on a side of the first metal material layer 201 away from the substrate 100;

[0089] The photoresist layer 600 is patterned using a grayscale mask to form a first etch stop region 610 and a plurality of second etch stop regions 620 , wherein the thickness of the first etch stop region 610 is less than the thickness of the second etch stop region 620 ;

[0090] The first metal material layer 201 is etched to form a first metal layer 200 , wherein the common electrode 220 of the first metal layer 200 includes a plurality of electrode units 221 arranged at intervals;

[0091] The patterned photoresist layer 600 is etched to completely remove the first etch stop region 610 and partially remove the second etch stop region 620 , and the remaining second etch stop region 620 forms a boss 621 , which is used to make the reflective electrode 530 uneven.

[0092] Before forming the first metal material layer 201, the base substrate 100 is cleaned and dried. The base substrate 100 can be dry-cleaned using an extreme ultraviolet cleaning machine (EUV) or a plasma cleaning machine (AP) to remove organic impurities on the base substrate 100, and then cleaned using high-pressure deionized water and a brush respectively to clean the fine particle impurities on the base substrate 100, and then dried using an air knife. The same process can be used to form the first metal material layer 201 and the second metal material layer 501.

[0093] The photoresist layer 600 may be formed by a coating process, and the coating methods mainly include spin coating, scraping combined with spin coating, and fine scraping. The photoresist layer 600 may be a positive photoresist or a negative photoresist. This embodiment is described by taking the photoresist layer 600 as a positive photoresist as an example. The exposed part of the positive photoresist is soluble in the developer, while the unexposed part is insoluble in the developer. After development, the patterned photoresist layer 600 on the substrate 100 is the same as the mask pattern.

[0094] The photoresist layer 600 is patterned using a grayscale mask, the first etch stop area 610 is partially exposed (for example, 60% exposure), the second etch stop area 620 is not exposed, and the remaining area is 100% exposed, and after development, the thickness of the first etch stop area 610 is less than the thickness of the second etch stop area 620. The first metal material layer 201 is wet-etched, the first etch stop area 610 blocks the area to form the gate 210, and the second etch stop area 620 blocks the area to form the electrode unit 221 of the common electrode 220.

[0095] After forming the first metal layer 200, the patterned photoresist layer 600 is dry-etched. The etchant includes ionized oxygen (O2), and the oxygen ions react chemically with the photoresist to generate carbon monoxide, carbon dioxide, water, etc. The first etch stop region 610 is completely removed. Since the second etch stop region 620 is thicker, the second etch stop region 620 is partially removed (about 1 / 3) to form a boss 621.

[0096] The first metal layer 200 and the boss 621 are etched using the same photomask, which further reduces the complexity of the process flow, improves the manufacturing efficiency of the array substrate 10 , and reduces the manufacturing cost of the array substrate 10 .

[0097] In some embodiments, after forming the second metal layer 500, the method for manufacturing the array substrate 10 further includes:

[0098] An insulating protection layer 800 is formed on a side of the second metal layer 500 away from the base substrate 100 , and the insulating protection layer 800 at least covers the source electrode 510 and the drain electrode 520 .

[0099] The insulating protective layer 800 can protect the transistor formed by the gate 210, the channel layer 400, the source 510 and the drain 520, and reduce the risk of water vapor intrusion. When the insulating protective layer 800 covers the source 510 and the drain 520, and the side of the reflective electrode 530 away from the base substrate 100 is not covered with the insulating protective layer 800, the insulating protective layer 800 is made of materials such as silicon dioxide, silicon nitride, silicon oxynitride and aluminum oxide. When forming the insulating protective layer 800, an insulating material layer 801 can be first formed on the side of the second metal layer 500 away from the base substrate 100, and then the insulating material layer 801 is etched on the side of the reflective electrode 530 away from the base substrate 100 to form the insulating protective layer 800.

[0100] The first metal layer 200 and the boss 621 are formed by a single photomask process, the channel layer 400, the ohmic contact layer 700 and the second metal layer 500 are formed by a single photomask process, and the insulating protection layer 800 is formed by a single photomask process. Three photomask processes are used to manufacture the array substrate 10. Compared with the technical solution of manufacturing the array substrate 10 by seven photomask processes, the complexity of the process flow is reduced, the manufacturing efficiency of the array substrate 10 is improved, and the manufacturing cost of the array substrate 10 is reduced.

[0101] In some embodiments, the insulating protection layer 800 covers the second metal layer 500 , and the material of the insulating protection layer 800 includes fluorinated polyimide.

[0102] The insulating protective layer 800 is made of fluorinated polyimide, and the light transmittance of the insulating protective layer 800 is significantly increased, which can not only achieve the purpose of improving the display effect of the display panel, but also reduce a mask process, further reduce the complexity of the process flow, improve the production efficiency of the array substrate 10, and reduce the production cost of the array substrate 10.

[0103] Embodiment 3

[0104] See also Fig.11 As shown, in this embodiment, the display panel includes an array substrate 10 and an opposing substrate 20, the opposing substrate 20 is arranged on one side of the array substrate 10, and the array substrate 10 includes the array substrate 10 disclosed in Embodiment 1 and Embodiment 2. When the display panel is an electronic paper display panel, the display panel further includes an electronic ink layer, which is arranged between the array substrate 10 and the opposing substrate 20; when the display panel is a liquid crystal display panel, the display panel further includes a liquid crystal layer, which is arranged between the array substrate 10 and the opposing substrate 20.

[0105] The display panel includes an array substrate 10, which includes a base substrate 100, a first metal layer 200, a gate insulating layer 300, a channel layer 400 and a second metal layer 500. The first metal layer 200 is formed on one side of the base substrate 100, and the first metal layer 200 may include a gate electrode 210 and a common electrode 220 that are spaced apart. The gate insulating layer 300 is formed on a side of the first metal layer 200 away from the base substrate 100. The channel layer 400 is formed on a side of the gate insulating layer 300 away from the base substrate 100, and the channel layer 400 at least covers the gate electrode 210. The second metal layer 500 is formed on a side of the channel layer 400 away from the base substrate 100. The second metal layer 500 includes a source electrode 510, a drain electrode 520 and a reflective electrode 530. The reflective electrode 530 is connected to the drain electrode 520. The pixel electrode of the array substrate 10 includes the reflective electrode 530. In this embodiment, the reflective electrode 530 is reused as the pixel electrode. The source 510, the drain 520, the reflective electrode 530 and the pixel electrode are located in the same metal layer and can be manufactured using the same photomask process, thereby reducing the complexity of the process flow, improving the manufacturing efficiency of the array substrate 10, and reducing the manufacturing cost of the array substrate 10.

[0106] The terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the feature. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0107] In this application, unless otherwise clearly specified and limited, the terms "assembly", "connection" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0108] In the description of this specification, the description with reference to the terms "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0109] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent of this application.

Claims

1. A method for manufacturing an array substrate, characterized in that: include: Forming a first metal layer on one side of the base substrate, wherein the first metal layer includes a gate electrode and a common electrode that are spaced apart; Forming a gate insulating layer, a channel material layer, and a second metal material layer in sequence on a side of the first metal layer away from the base substrate; Patterning the second metal material layer and the channel material layer to form a second metal layer and a channel layer, wherein the channel layer at least covers the gate, the second metal layer includes a source electrode, a drain electrode and a reflective electrode, the source electrode and the drain electrode are arranged at intervals, the orthographic projections of the source electrode and the drain electrode on the base substrate overlap with the gate electrode, the orthographic projection of the reflective electrode on the base substrate overlaps with the common electrode, the reflective electrode is connected to the drain electrode, and the pixel electrode of the array substrate includes the reflective electrode; Wherein, the method of forming the first metal layer includes: forming a first metal material layer on the base substrate; forming a photoresist layer on a side of the first metal material layer away from the substrate; Patterning the photoresist layer using a grayscale mask to form a first etch stop region and a plurality of second etch stop regions, wherein the thickness of the first etch stop region is less than the thickness of the second etch stop region; Etching the first metal material layer to form the first metal layer, wherein the common electrode of the first metal layer includes a plurality of electrode units arranged at intervals; The patterned photoresist layer is etched to completely remove the first etch stop area and partially remove the second etch stop area, and the remaining second etch stop area forms a plurality of bosses, which are located on a side of the electrode unit away from the substrate, and are used to make the reflective electrode uneven.

2. An array substrate, characterized in that: The array substrate is manufactured by the method for manufacturing the array substrate according to claim 1.

3. The array substrate according to claim 2, characterized in that: The material of the boss includes soluble polytetrafluoroethylene.

4. The array substrate according to claim 2, characterized in that: The channel layer is made of molybdenum disulfide.

5. The array substrate according to claim 2, characterized in that: The array substrate further includes an insulating protective layer, which is formed on a side of the second metal layer away from the base substrate, and the insulating protective layer at least covers the source electrode and the drain electrode.

6. The array substrate according to claim 5, characterized in that: The insulating protection layer covers the second metal layer, and the material of the insulating protection layer includes fluorinated polyimide.

7. A display panel, characterized in that: include: The array substrate according to any one of claims 2 to 6; The opposing substrate is arranged on one side of the array substrate.

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