Method for forming an eDRAM device

Abstract

The present invention provides a method for forming an eDRAM device, comprising: forming a first oxide layer and a first nitride layer on the surface of a substrate; forming a first deep trench and a second deep trench spaced apart; forming a dielectric layer, a barrier layer and a polysilicon layer in the first deep trench and the second deep trench, wherein the lower part of the polysilicon layer is separated from the lower part sidewall by the barrier layer and the dielectric layer; forming a second oxide layer on the surface of the polysilicon layer and the surface of the first nitride layer, wherein the thickness of the second oxide layer located on the surface of the first nitride layer is less than the thickness of the second oxide layer located on the surface of the polysilicon layer; removing a portion of the thickness of the second oxide layer, and retaining a portion of the thickness of the second oxide layer on the surface of the polysilicon layer; removing the first nitride layer and the first oxide layer; forming a third oxide layer and a second nitride layer in sequence on the surface of the substrate and the surface of the second oxide layer; forming a third trench between the first deep trench and the second deep trench; and forming a linear oxide layer and a dielectric layer in sequence in the third trench.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for forming an eDRAM device. Background Art

[0002] Deep trench capacitors can be formed before MOSFETs without affecting the characteristics of MOSFETs, so DRAM (dynamic random access memory) and logic circuits using deep trench capacitors can be integrated on the same wafer, called eDRAM (embedded DRAM). The memory cell of eDRAM usually includes a deep trench capacitor and a traditional two-dimensional MOSFET or FinFET coupled thereto.

[0003] The method for forming an eDRAM device in the prior art includes: providing a substrate, sequentially forming a pad oxide layer and a first nitride layer on the surface of the substrate, and forming a patterned hard mask layer on the surface of the first nitride layer. Next, the pad nitride layer, the pad oxide layer and a portion of the thickness of the substrate are etched using the patterned hard mask layer to form a first deep trench and a second deep trench spaced apart in the substrate. A dielectric layer, a barrier layer and a polysilicon layer are respectively formed in the first deep trench and the second deep trench, the dielectric layer and the barrier layer are both located in the lower part of the first deep trench and the second deep trench, and the lower part of the polysilicon layer is separated from the lower part sidewalls of the first deep trench and the second deep trench by the barrier layer and the dielectric layer, respectively.

[0004] However, in the prior art, a patterned hard mask layer is formed, a pad nitride layer, a pad oxide layer and a partial thickness of the substrate are etched, and a first deep trench and a second deep trench are formed in the substrate. The formation of a dielectric layer and a barrier layer will involve deposition and etching steps. These etching processes will cause the pad nitride layer to be damaged. In the subsequent high-performance logic process with embedded eDRAM, it is hoped that the same pad nitride layer as the deep trench process will be shared as a hard mask for subsequent STI or Fin patterning. Therefore, after the pad nitride layer is damaged, it will increase the difficulty in the subsequent formation of STI or Fin patterning. Summary of the invention

[0005] The object of the present invention is to provide a method for forming an eDRAM device, which can form a high-quality liner nitride layer, thereby reducing the difficulty of subsequent STI or Fin patterning, and finally improving the quality of the eDRAM device.

[0006] In order to achieve the above object, the present invention provides a method for forming an eDRAM device, comprising:

[0007] Providing a substrate, and sequentially forming a first oxide layer and a first nitride layer on the surface of the substrate;

[0008] Etching the first nitride layer, the first oxide layer and a partial thickness of the substrate to form a first deep trench and a second deep trench spaced apart;

[0009] Forming a dielectric layer, a barrier layer and a polysilicon layer in the first deep trench and the second deep trench respectively, wherein the dielectric layer and the barrier layer are both located in the lower portions of the first deep trench and the second deep trench, and the lower portion of the polysilicon layer is separated from the sidewalls of the lower portions of the first deep trench and the second deep trench respectively by the barrier layer and the dielectric layer;

[0010] Oxidizing a portion of the polysilicon layer and a portion of the first nitride layer to form a second oxide layer on the surface of the polysilicon layer and the surface of the first nitride layer, wherein the thickness of the second oxide layer located on the surface of the first nitride layer is less than the thickness of the second oxide layer located on the surface of the polysilicon layer;

[0011] removing the second oxide layer on the surface of the first nitride layer and a portion of the second oxide layer on the surface of the polysilicon layer, and retaining a portion of the second oxide layer on the surface of the polysilicon layer;

[0012] removing the first nitride layer and the first oxide layer to expose the surface of the substrate;

[0013] forming a third oxide layer and a second nitride layer in sequence on the surface of the substrate and the surface of the second oxide layer;

[0014] forming a third trench between the first deep trench and the second deep trench, wherein the third trench exposes a portion of the polysilicon layer in the first deep trench and the polysilicon layer in the second deep trench and the substrate therebetween;

[0015] A linear oxide layer and a dielectric layer are sequentially formed in the third trench, and the dielectric layer is separated by the linear oxide layer and the polysilicon layer.

[0016] Optionally, in the method for forming the eDRAM device, the substrate includes a bottom silicon layer, a buried oxide layer, and a top silicon layer stacked in sequence.

[0017] Optionally, in the method for forming the eDRAM device, the dielectric layer includes a high-k dielectric layer.

[0018] Optionally, in the method for forming the eDRAM device, the barrier layer includes TiN.

[0019] Optionally, in the method for forming the eDRAM device, a polysilicon layer having a partial thickness is steam-oxidized to form a second oxide layer on the surface of the polysilicon layer.

[0020] Optionally, in the method for forming the eDRAM device, the first nitride layer and the first oxide layer are removed by wet etching to expose the surface of the substrate.

[0021] Optionally, in the method for forming the eDRAM device, hydrofluoric acid wet etching is used to remove the first nitride layer.

[0022] Optionally, in the method for forming the eDRAM device, phosphoric acid wet etching is used to remove the first oxide layer.

[0023] Optionally, in the method for forming the eDRAM device, a third oxide layer and a second nitride layer are sequentially formed on the surface of the substrate and the surface of the second oxide layer by a deposition method.

[0024] The method for forming an eDRAM device provided by the present invention includes: providing a substrate, sequentially forming a first oxide layer and a first nitride layer on the surface of the substrate; etching the first nitride layer, the first oxide layer and a partial thickness of the substrate to form a first deep trench and a second deep trench spaced apart; forming a dielectric layer, a barrier layer and a polysilicon layer in the first deep trench and the second deep trench, respectively, the dielectric layer and the barrier layer are both located in the lower part of the first deep trench and the second deep trench, and the lower part of the polysilicon layer is separated from the lower part of the sidewall of the first deep trench and the second deep trench by the barrier layer and the dielectric layer, respectively; oxidizing a partial thickness of the polysilicon layer and a partial thickness of the first nitride layer to form a second oxide layer on the surface of the polysilicon layer and the surface of the first nitride layer, and the second oxide layer is located in the first deep trench and the second deep trench; The thickness of the second oxide layer on the surface of the first nitride layer is less than the thickness of the second oxide layer on the surface of the polysilicon layer; the second oxide layer on the surface of the first nitride layer and the second oxide layer of part thickness on the surface of the polysilicon layer are removed, and the second oxide layer of part thickness on the surface of the polysilicon layer is retained; the first nitride layer and the first oxide layer are removed to expose the surface of the substrate; a third oxide layer and a second nitride layer are sequentially formed on the surface of the substrate and the surface of the second oxide layer; a third trench is formed between the first deep trench and the second deep trench, and the third trench exposes a part of the polysilicon layer in the first deep trench and the polysilicon layer in the second deep trench and the substrate therebetween; a linear oxide layer and a dielectric layer are sequentially formed in the third trench, and the dielectric layer is separated by the linear oxide layer and the polysilicon layer. The present invention removes the first nitride layer and the first oxide layer, and re-forms a high-quality third oxide layer and a second nitride layer as mask layers that can be shared when STI or Fin is subsequently formed. This reduces the difficulty of subsequent STI or Fin patterning and improves the quality of eDRAM devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a flow chart of a method for forming an eDRAM device according to an embodiment of the present invention;

[0026] Figure 2is a schematic structural diagram of an eDRAM device after forming a first deep trench and a second deep trench according to an embodiment of the present invention;

[0027] Figure 3 is a schematic structural diagram of an eDRAM device after a silicon nitride layer is formed according to an embodiment of the present invention;

[0028] Figure 4 is a schematic structural diagram of an eDRAM device after forming a second oxide layer according to an embodiment of the present invention;

[0029] Figure 5 is a schematic structural diagram of an eDRAM device after removing the second oxide layer on the surface of the first nitride layer according to an embodiment of the present invention;

[0030] Figure 6 is a schematic structural diagram of an eDRAM device after the first oxide layer is removed according to an embodiment of the present invention;

[0031] Figure 7 is a schematic structural diagram of an eDRAM device after forming a second nitride layer according to an embodiment of the present invention;

[0032] Figure 8 is a schematic structural diagram of an eDRAM device after forming a third trench according to an embodiment of the present invention;

[0033] Fig. 9 is a schematic structural diagram of an eDRAM device after a dielectric layer is formed according to an embodiment of the present invention;

[0034] In the figure: 110-substrate, 111-bottom silicon, 112-buried oxide layer, 113-top silicon, 120-first oxide layer, 130-first nitride layer, 141-first deep trench, 142-first dielectric layer, 143-first barrier layer, 144-first polysilicon layer, 151-second deep trench, 152-second dielectric layer, 153-second barrier layer, 154-second polysilicon layer, 160-second oxide layer, 170-third oxide layer, 180-second nitride layer, 190-third trench, 200-linear oxide layer, 210-dielectric layer. DETAILED DESCRIPTION

[0035] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0036] Hereinafter, the terms "first", "second", etc. are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological sequence. It is to be understood that these terms used in this manner are interchangeable where appropriate. Similarly, if the method described herein includes a series of steps, the order of these steps presented herein is not necessarily the only order in which these steps can be performed, and some of the steps described may be omitted and / or some other steps not described herein may be added to the method.

[0037] Furthermore, it should be understood that when a layer (or film), region, pattern or structure is referred to as being "on" a substrate, layer (or film), region and / or pattern, it can be directly on another layer or substrate, and / or there can be intervening layers. In addition, it should be understood that when a layer is referred to as being "under" another layer, it can be directly under another layer, and / or there can be one or more intervening layers. In addition, references to being "on" and "under" each layer can be made based on the accompanying drawings.

[0038] Please refer to Figure 1 The present invention provides a method for forming an eDRAM device, comprising:

[0039] S11: providing a substrate, and sequentially forming a first oxide layer and a first nitride layer on a surface of the substrate;

[0040] S12: etching the first nitride layer, the first oxide layer, and a portion of the thickness of the substrate to form a first deep trench and a second deep trench spaced apart from each other;

[0041] S13: forming a dielectric layer, a barrier layer and a polysilicon layer in the first deep trench and the second deep trench respectively, the dielectric layer and the barrier layer are both located in the lower part of the first deep trench and the second deep trench, and the lower part of the polysilicon layer is separated from the sidewalls of the lower part of the first deep trench and the second deep trench respectively by the barrier layer and the dielectric layer;

[0042] S14: oxidizing a portion of the polysilicon layer and a portion of the first nitride layer to form a second oxide layer on the surface of the polysilicon layer and the surface of the first nitride layer, wherein the thickness of the second oxide layer located on the surface of the first nitride layer is less than the thickness of the second oxide layer located on the surface of the polysilicon layer;

[0043] S15: removing the second oxide layer on the surface of the first nitride layer and a portion of the second oxide layer on the surface of the polysilicon layer, and retaining a portion of the second oxide layer on the surface of the polysilicon layer;

[0044] S16: removing the first nitride layer and the first oxide layer to expose the surface of the substrate;

[0045] S17: forming a third oxide layer and a second nitride layer in sequence on the surface of the substrate and the surface of the second oxide layer;

[0046] S18: forming a third trench between the first deep trench and the second deep trench, wherein the third trench exposes a portion of the polysilicon layer in the first deep trench and the polysilicon layer in the second deep trench and the substrate therebetween;

[0047] S19: forming a linear oxide layer and a dielectric layer in sequence in the third trench, wherein the dielectric layer is separated by the linear oxide layer and the polysilicon layer.

[0048] Please refer to Figure 2 First, a substrate 110 is provided. The substrate 110 is SOI, including a bottom silicon 111, a buried oxide layer 112 and a top silicon 113 stacked in sequence. A first oxide layer 120 is formed on the surface of the substrate 110, which can be formed by a method of depositing silicon oxide. Next, a first nitride layer 130 is formed on the surface of the first oxide layer 120, which can be formed by a method of depositing silicon nitride. Next, a hard mask layer is formed on the surface of the first nitride layer 130, and the hard mask layer is etched to form a patterned hard mask layer. The first nitride layer 130, the first oxide layer 120 and a partial thickness of the substrate 110 are etched downward from the surface of the first nitride layer 130 using the patterned hard mask layer to form a first deep trench 141 and a second deep trench 151 spaced apart, and the substrate 110 is between the first deep trench 141 and the second deep trench 151.

[0049] Next, please refer to Figure 3, a TiN (titanium nitride) material layer and a high-k dielectric layer are sequentially deposited on the inner walls of the first deep trench 141 and the second deep trench 151, and polysilicon is continuously filled in the trench formed by the high-k dielectric layer to form a polysilicon layer. While filling the first deep trench and the second deep trench, the titanium nitride material layer, the high-k dielectric layer and the polysilicon layer will sequentially cover the surface of the first nitride layer outside the first deep trench and the second deep trench. The polysilicon layer, the high-k dielectric layer and the titanium nitride material layer on the surface of the first nitride layer and the polysilicon layer, the high-k dielectric layer and the titanium nitride material layer on the upper part of the first deep trench and the second deep trench are ground and etched. At this time, the first nitride layer 130 may have been damaged due to the etching of the hard mask layer, the polysilicon layer, the high-k dielectric layer and the titanium nitride material layer. Next, polysilicon is partially filled on the first deep trench 141 and the second deep trench 151, so as to form a polysilicon layer in the first deep trench and the second deep trench. Specifically, finally, a first dielectric layer 142, a first barrier layer 143, and a first polysilicon layer 144 are formed in the first deep trench, and the first dielectric layer 142 and the first barrier layer 143 are both located in the lower portion of the first deep trench, and the lower portion of the first polysilicon layer 144 is separated from the lower portion of the sidewall of the first deep trench by the first barrier layer 143 and the first dielectric layer 142, respectively. A second dielectric layer 152, a second barrier layer 153, and a second polysilicon layer 154 are formed in the second deep trench, and the second dielectric layer 152 and the second barrier layer 153 are both located in the lower portion of the second deep trench, and the lower portion of the second polysilicon layer 154 is separated from the lower portion of the sidewall of the second deep trench by the second barrier layer 153 and the second dielectric layer 152, respectively.

[0050] Next, please refer to Figure 4 , steam oxidizes a portion of the thickness of the polysilicon layer, and at the same time, oxidizes a portion of the thickness of the first nitride layer to form a second oxide layer 160 on the surface of the polysilicon layer and the surface of the first nitride layer. The thickness of the second oxide layer 160 located on the surface of the first nitride layer is less than the thickness of the second oxide layer 160 located on the surface of the polysilicon layer. Next, please refer to Figure 5 , remove the second oxide layer 160 on the surface of the first nitride layer, and retain the second oxide layer 160 on the surface of the polysilicon layer.

[0051] Next, please refer to Figure 6 , wet etching is performed to remove the first nitride layer 130 and the first oxide layer 120 to expose the surface of the substrate 110. Specifically, hydrofluoric acid wet etching can be used to remove the first nitride layer 130. Phosphoric acid wet etching can be used to remove the first oxide layer 120.

[0052] Next, please refer to Figure 7The third oxide layer 170 and the second nitride layer 180 are sequentially formed on the surface of the substrate 110 and the surface of the second oxide layer 160. Specifically, the third oxide layer 170 and the second nitride layer 180 can be sequentially formed on the surface of the substrate 110 and the surface of the second oxide layer 160 by a deposition method.

[0053] Next, please refer to Figure 8 A third trench 190 is formed between the first deep trench and the second deep trench, and the third trench 190 exposes a portion of the polysilicon layer in the first deep trench and the polysilicon layer in the second deep trench and the substrate 110 therebetween.

[0054] Next, please refer to Fig. 9 , a linear oxide layer 200 and a dielectric layer 210 are sequentially formed in the third trench, and the dielectric layer 210 is separated by the linear oxide layer 200 and the polysilicon layer.

[0055] In summary, the method for forming an eDRAM device provided in an embodiment of the present invention includes: providing a substrate, sequentially forming a first oxide layer and a first nitride layer on the surface of the substrate; etching the first nitride layer, the first oxide layer and a partial thickness of the substrate to form a first deep trench and a second deep trench spaced apart; forming a dielectric layer, a barrier layer and a polysilicon layer in the first deep trench and the second deep trench, respectively, the dielectric layer and the barrier layer are both located in the lower part of the first deep trench and the second deep trench, and the lower part of the polysilicon layer is separated from the lower part of the sidewall of the first deep trench and the second deep trench by the barrier layer and the dielectric layer, respectively; oxidizing a partial thickness of the polysilicon layer and a partial thickness of the first nitride layer to form a second oxide layer on the surface of the polysilicon layer and the surface of the first nitride layer, The thickness of the second oxide layer located on the surface of the first nitride layer is less than the thickness of the second oxide layer located on the surface of the polysilicon layer; the second oxide layer on the surface of the first nitride layer and a part of the thickness of the second oxide layer on the surface of the polysilicon layer are removed, and a part of the thickness of the second oxide layer on the surface of the polysilicon layer is retained; the first nitride layer and the first oxide layer are removed to expose the surface of the substrate; a third oxide layer and a second nitride layer are sequentially formed on the surface of the substrate and the surface of the second oxide layer; a third trench is formed between the first deep trench and the second deep trench, and the third trench exposes a part of the polysilicon layer in the first deep trench and the polysilicon layer in the second deep trench and the substrate therebetween; a linear oxide layer and a dielectric layer are sequentially formed in the third trench, and the dielectric layer is separated by the linear oxide layer and the polysilicon layer. The present invention removes the first nitride layer and the first oxide layer, and re-forms a high-quality third oxide layer and a second nitride layer as a mask layer that can be shared when subsequently forming STI or Fin. This reduces the difficulty of subsequent STI or Fin patterning and improves the quality of eDRAM devices.

[0056] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. A method for forming an eDRAM device, characterized in that: include: Providing a substrate, and sequentially forming a first oxide layer and a first nitride layer on the surface of the substrate; Etching the first nitride layer, the first oxide layer and a partial thickness of the substrate to form a first deep trench and a second deep trench spaced apart; Forming a dielectric layer, a barrier layer and a polysilicon layer in the first deep trench and the second deep trench respectively, wherein the dielectric layer and the barrier layer are both located in the lower portions of the first deep trench and the second deep trench, and the lower portion of the polysilicon layer is separated from the sidewalls of the lower portions of the first deep trench and the second deep trench respectively by the barrier layer and the dielectric layer; Oxidizing a portion of the polysilicon layer and a portion of the first nitride layer to form a second oxide layer on the surface of the polysilicon layer and the surface of the first nitride layer, wherein the thickness of the second oxide layer located on the surface of the first nitride layer is less than the thickness of the second oxide layer located on the surface of the polysilicon layer; removing the second oxide layer on the surface of the first nitride layer and a portion of the second oxide layer on the surface of the polysilicon layer, and retaining a portion of the second oxide layer on the surface of the polysilicon layer; removing the first nitride layer and the first oxide layer to expose the surface of the substrate; forming a third oxide layer and a second nitride layer in sequence on the surface of the substrate and the surface of the second oxide layer; forming a third trench between the first deep trench and the second deep trench, wherein the third trench exposes a portion of the polysilicon layer in the first deep trench and the polysilicon layer in the second deep trench and the substrate therebetween; A linear oxide layer and a dielectric layer are sequentially formed in the third trench, and the dielectric layer is separated by the linear oxide layer and the polysilicon layer.

2. The method for forming an eDRAM device according to claim 1, wherein: The substrate comprises a bottom silicon layer, a buried oxide layer and a top silicon layer which are stacked in sequence.

3. The method for forming an eDRAM device according to claim 1, wherein: The dielectric layer includes a high-k dielectric layer.

4. The method for forming an eDRAM device according to claim 1, wherein: The barrier layer includes TiN.

5. The method for forming an eDRAM device according to claim 1, wherein: A partial thickness of the polysilicon layer is steam oxidized to form a second oxide layer on a surface of the polysilicon layer.

6. The method for forming an eDRAM device according to claim 1, wherein: The first nitride layer and the first oxide layer are removed by wet etching to expose the surface of the substrate.

7. The method for forming an eDRAM device according to claim 6, wherein: The first nitride layer is removed by wet etching using hydrofluoric acid.

8. The method for forming an eDRAM device according to claim 6, wherein: The first oxide layer is removed by wet etching using phosphoric acid.

9. The method for forming an eDRAM device according to claim 1, wherein: A third oxide layer and a second nitride layer are sequentially formed on the surface of the substrate and on the surface of the second oxide layer by a deposition method.

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