Silicon optical chip testing method and device

Abstract

The invention relates to the technical field of chip testing, and discloses a silicon optical chip testing method and device.A middle support of a coupling table in the device is used for placing a silicon optical chip to be tested, and six-axis supports on the left side and the right side of the coupling table are each fixedly provided with a probe card; one probe pin in the probe pin row corresponds to one pin bonding pad in the silicon optical chip, each probe pin is connected with a pin in the circuit board pin row in a one-to-one correspondence manner, and the pin in the circuit board pin row is also connected with a positive pin in the positive pin row and a negative pin in the negative pin row in a one-to-one correspondence manner; the terminals are used as positive and negative terminals; the common end of one side port of the relay is connected with the anode of the source meter, and the common end of the other side port of the relay is connected with the cathode of the source meter. According to the invention, the test can be carried out only by moving the coupling table, enabling the probe card to be in full contact with the chip pad and selecting the test configuration file, so that the time consumed by manually moving the probes of the coupling table to test one by one is shortened, and the task load is reduced.

Description

Technical Field

[0001] The present invention relates to the field of chip testing technology, and in particular to a silicon photonic chip testing method and device. Background Art

[0002] Silicon photonic chips have great potential in electronic fields such as lidar, biomedicine, and wearable devices due to their high speed, high precision, high integration, and low loss. Various complex optical devices are integrated on the chip, and the performance of the devices directly affects the use of silicon photonic chips. Therefore, chip testing is an important part of the production process of silicon photonic chips. Silicon photonic chips mainly use optical signals as information carriers. Currently, electronic devices are mainly based on electrical signals, which require on-chip photoelectric conversion and then electrical signal processing. PD (Photo-Diode) is an important device for on-chip photoelectric conversion and can be used to test various optical structures on the chip. Its performance determines the speed and reliability of information transmission. Therefore, PD testing is an important part of silicon photonic chip testing.

[0003] At present, the chip PD test method generally adopts a manual moving probe station to test the contact between a single probe and the PD pin pad. However, for multi-channel silicon photonic chips, there may be 64, 128 or even more PDs on a silicon photonic chip. Testing one by one greatly increases the test time and labor costs. Repeated movement of the probe also increases the risk of damaging the chip. Summary of the invention

[0004] In view of this, the present invention provides a silicon photonic chip testing method and device to solve the problems of long testing time, high labor cost and easy damage to the chip in the current chip PD testing method.

[0005] In a first aspect, the present invention provides a silicon photonic chip testing device, the device comprising: a coupling station, a probe card, a relay, a source meter and a host computer, wherein:

[0006] The middle bracket of the coupling platform is used to place the silicon photonic chip to be tested, and a probe card is fixed on each of the six-axis brackets on the left and right sides of the coupling platform;

[0007] Each of the probe cards comprises a probe pin row, a circuit board pin row, a positive electrode pin row and a negative electrode pin row, wherein a probe pin in the probe pin row corresponds to a pin pad in the silicon photonic chip, the probe pins in the probe pin row are connected one-to-one with the pins in the circuit board pin row, the pins in the circuit board pin row are also connected one-to-one with the positive electrode pins in the positive electrode pin row and the negative electrode pins in the negative electrode pin row, the positive electrode pins are connected one-to-one with the normally open contacts of the ports on one side of the relay, and the negative electrode pins are connected one-to-one with the normally open contacts of the ports on the other side of the relay;

[0008] The common end of the port on one side of the relay is connected to the positive pole of the source meter, and the common end of the port on the other side of the relay is connected to the negative pole of the source meter;

[0009] The relay, the source meter and the coupling station are all connected to the host computer for communication, and the host computer stores a test program.

[0010] The present invention provides a silicon photonic chip testing device, which is suitable for PD testing of multi-channel silicon photonic chips. It only needs to move the coupling table to make the probe card fully contact with the chip pad, and select the saved test configuration file to perform the test, which reduces the time spent on manually moving the coupling table probes one by one for testing, and reduces the amount of tasks. At the same time, each pin of the probe card is divided into two by means of a circuit board, so that each probe pin can be selectively connected to the positive or negative pole of the voltage source through a relay, thereby improving the applicability of the test program to different chip structures.

[0011] In an optional implementation, the relay is a small DC relay.

[0012] In an optional implementation, the power line of the coupling station is connected to the relay port, or the coupling station adopts an external heating method.

[0013] In an optional implementation, the number of pins of the probe pin row, the circuit board pin row, the positive electrode pin row, the negative electrode pin row and the number of ports of the relay are adjusted according to the number of pin pads of the silicon photonic chip.

[0014] For different chips, for multi-channel silicon photonic chips, it is only necessary to adjust the number of pins of the probe pin row, circuit board pin row, positive pin row, and negative pin row according to the number of photodiodes PD on the silicon photonic chip, and increase the number of relays accordingly, thereby realizing the applicability of the test device to different chips.

[0015] In an optional embodiment, the silicon photonic chip has a plurality of photodiodes, and each photodiode has a positive pin pad and a negative pin pad.

[0016] In a second aspect, the present invention provides a silicon photonic chip testing method, based on the silicon photonic chip testing device of the first aspect or any corresponding embodiment thereof, the method comprising:

[0017] Fix the silicon photonic chip to be tested on the middle bracket of the coupling platform;

[0018] Simultaneously move the probe cards on the left and right sides of the coupling platform so that each probe pin is respectively inserted into each pin pad of the silicon photonic chip;

[0019] Configure relay test items, source meter test items and coupling table temperature test items in the host computer test program;

[0020] Start the test program and complete the test tasks of all photodiodes of the silicon photonic chip in sequence.

[0021] A silicon photonic chip testing method provided by the present invention is suitable for PD testing of multi-channel silicon photonic chips. It only requires moving the coupling table to make the probe card fully contact with the chip pad, and selecting the saved test configuration file to perform the test, thereby reducing the time spent on manually moving the coupling table probes for testing one by one and reducing the amount of tasks.

[0022] In an optional implementation, the starting test program sequentially completes the test tasks of all photodiodes of the silicon photonic chip, including:

[0023] Find the positive and negative pin pads of the first photodiode.

[0024] Find the positive pin connected to the positive pin pad, and determine the relay port connected to the positive pin;

[0025] Find the negative pin connected to the negative pin pad, and determine the relay port connected to the negative pin;

[0026] Select different levels of source meter voltage, control the on and off of the relay port, and test the current value of the first photodiode at different voltage levels;

[0027] Repeat the above process until all photodiodes have completed the test task.

[0028] By dividing each pin of the probe card into two by means of a circuit board, each probe pin can be selectively connected to the positive or negative pole of a voltage source through a relay, thereby improving the applicability of the test program to different chip structures.

[0029] In an optional embodiment, the method further includes:

[0030] A source meter is used to perform a scan test to collect current values ​​of all photodiodes at different voltage levels, and the performance of the silicon photonic chip is judged based on the current values.

[0031] In an optional implementation, the method further includes: testing the thermistor of the silicon photonic chip at different temperatures.

[0032] In an optional implementation, the method further includes: testing the thermistor of the silicon photonic chip at different temperatures, including:

[0033] For the coupling stage, set multiple consecutive target temperatures;

[0034] The coupling platform is heated to a first target temperature, and a scanning test is performed using a source meter to collect the resistance value of the thermistor at the first target temperature;

[0035] heating the coupling platform to a second target temperature, performing a scanning test using a source meter, and collecting the resistance value of the thermistor at the second target temperature;

[0036] Repeat the above process until thermistor tests at multiple target temperatures are completed. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1 is a principle block diagram of a silicon photonic chip testing device according to an embodiment of the present invention;

[0039] Figure 2 4 is a flow chart of a silicon photonic chip testing method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0041] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0042] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0043] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0044] An embodiment of the present invention provides a silicon photonic chip testing device. By utilizing the device to test a silicon photonic chip, the silicon photonic chip can quickly perform multiple PD current tests, thereby reducing the number of manual operation repetitions, saving testing time and labor costs.

[0045] like Figure 1 As shown, the silicon photonic chip test device includes: a coupling platform 1, a probe card 2, a relay 3, a source meter 4 and a host computer 5. Among them, the middle bracket of the coupling platform 1 is used to place the silicon photonic chip to be tested, and a probe card 2 is fixed on each of the six-axis brackets on the left and right sides of the coupling platform 1. Each probe card 2 includes a probe pin row 21, a circuit board pin row 22, a positive pin row 23 and a negative pin row 24. A probe pin in the probe pin row 21 corresponds to a pin pad in the silicon photonic chip. The probe pins in the probe pin row 21 are connected to the pins in the circuit board pin row 22 in a one-to-one correspondence. The pins in the circuit board pin row 22 are also connected to the positive pins in the positive pin row 23 and the negative pins in the negative pin row 24 in a one-to-one correspondence. The positive pins are connected to the normally open contacts of the ports on one side of the relay 3 in a one-to-one correspondence, and the negative pins are connected to the normally open contacts of the ports on the other side of the relay 3 in a one-to-one correspondence. The common end of the port on one side of the relay 3 is connected to the positive pole of the source meter 4, and the common end of the port on the other side of the relay 3 is connected to the negative pole of the source meter 4. The relay 3, the source meter 4 and the coupling station 1 are all connected to the host computer 5 for communication, and the host computer 5 stores the test program.

[0046] Specifically, there are multiple photodiodes PD on the silicon photonic chip, each of which has a positive pin pad pad and a negative pin pad pad, and all the pin pad pads are evenly spaced on both sides of the silicon photonic chip. The probe card 2 is provided with fixing holes 25, and the probe cards 2 on both sides are respectively fixed on the six-axis coupling bracket of the coupling platform 1 through the fixing holes 25. One probe pin in the probe pin row 21 corresponds to one pin pad pad in the silicon photonic chip.

[0047] The probe card 2 includes a probe pin row 21 and a circuit board portion. The circuit board portion is provided with a circuit board pin row 22, a positive electrode pin row 23 and a negative electrode pin row 24. Each probe pin is connected to a pin in the circuit board pin row 22. On the circuit board, each pin in the circuit board pin row 22 is divided into two pin ends, which are arranged in sequence on both sides of the probe card circuit board, one side is the positive electrode pin row 23 used as the positive electrode, and the other side is the negative electrode pin row 24 used as the negative electrode.

[0048] Each port 31 of the relay 3 contains COM (common terminal), NO (normally open contact), and NC (normally closed contact). The positive pins in the positive pin row 23 and the negative pins in the negative pin row 24 are respectively connected to the two sides of the relay 3, and all the positive pins are respectively connected to the normally open contacts NO of the ports on one side of the relay 3 in a one-to-one correspondence, and all the negative pins are respectively connected to the normally open contacts NO of the ports on the other side of the relay 3 in a one-to-one correspondence. Electronic wires are drawn out from the COM terminals of all relay ports corresponding to the positive pins, and are all connected to the positive pole of the source meter 4. Similarly, electronic wires are drawn out from the COM terminals of all relay ports corresponding to the negative pins, and are all connected to the negative pole of the source meter 4.

[0049] When testing, the coupling station 1 is controlled to move the probe card 2 so that each probe pin of the probe card 2 is respectively inserted into each pin pad of the silicon photonic chip. The test program of the host computer 5 configures the photodiode PD port test information and then starts the test, completing the test tasks of all photodiodes of the silicon photonic chip in sequence, and returning the PD test results after the test is completed.

[0050] In the embodiment of the present invention, the main function of the probe card 2 is to serve as an interface between the tester and the chip during the chip testing process, for transmitting signals and testing electrical performance. In the wafer testing process, the probe card is particularly important because it can connect each chip to the tester to ensure the preliminary measurement of electrical performance and the screening of defective chips. The test program in the host computer 5 can meet different test items, and different test configuration files can be saved for each test chip, making the test more convenient.

[0051] In an optional implementation, the relay 3 is a small DC relay.

[0052] Specifically, since the small relay equipment is mature, the overall testing cost is reduced and the operation is simple.

[0053] In an optional implementation, the power line of the coupling station 1 is connected to the port of the relay 3, or the coupling station 1 adopts an external heating method.

[0054] Specifically, when testing the performance of the photodiode PD of the silicon photonic chip under high and low temperature working environments, the positive power line of the coupling station 1 is connected to the normally open contact NO of the port on one side of the relay 3, and the negative power line of the coupling station 1 is connected to the normally open contact NO of the port on the other side of the relay 3. In addition, the coupling station 1 can also adopt an external heating method to control the heating temperature through network port communication, without the need to be connected to the relay 3.

[0055] In an optional implementation, the number of pins of the probe pin row 21 , the circuit board pin row 22 , the positive electrode pin row 23 , the negative electrode pin row 24 and the number of ports of the relay 3 are adjusted according to the number of pin pads of the silicon photonic chip.

[0056] Specifically, for multi-channel silicon photonic chips, it is only necessary to adjust the number of pins of the probe pin row 21, the circuit board pin row 22, the positive pin row 23, and the negative pin row 24 according to the number of photodiodes PD on the silicon photonic chip, and increase the number of relays 3 accordingly, thereby realizing the applicability of the test device to different chips.

[0057] In the embodiment of the present invention, Figure 1 Taking the silicon photonic chip shown as an example, there are 10 photodiodes PD to be tested on the silicon photonic chip, each photodiode PD includes two positive and negative pin pads, and the silicon photonic chip has a total of 20 pin pads distributed on both sides of the silicon photonic chip. The two probe cards 2 each have 10 probe pins, and each probe pin corresponds to a pin pad in the silicon photonic chip.

[0058] Each probe pin is connected to a pin in the circuit board pin row 22 in a one-to-one correspondence. The pins in the circuit board pin row 22 are also connected to the positive pins in the positive pin row 23 and the negative pins in the negative pin row 24 in a one-to-one correspondence, and are used as positive and negative terminals respectively.

[0059] The relay 3 includes 44 relay ports 31. The two probe cards 2 have a total of 20 pins connected to the NO ports of the 20 relay ports on one side of the relay 3 through the circuit board pin row 22 and the positive pin row 23, and similarly, the two probe cards 2 have a total of 20 pins 8 connected to the NO ports of the 20 relay ports on the other side of the relay 3 through the circuit board pin row 22 and the negative pin row 24.

[0060] The source meter 4 is used as a test voltage source. 20 electronic wires are led out from the COM ports of the 20 relay ports connected to the positive pin row 23 on the relay 3, and all are connected to the positive pole of the source meter 11. Similarly, 20 electronic wires are led out from the COM ports of the 20 relay ports connected to the negative pin row 24 on the relay 3, and all are connected to the negative pole of the source meter 11.

[0061] In the embodiment of the present invention, the circuit board part can be separated from the probe card 2. In this case, the circuit board 3 only serves as a branch adapter board, and different branches can be flexibly designed to connect multiple devices.

[0062] In an optional implementation, other external devices may be connected to the remaining ports of the relay.

[0063] Specifically, the equipment in the silicon photonic chip test device is adjusted according to the type of silicon photonic chip and the setting items. For example, the current silicon photonic multi-channel chip is more integrated, and the chip solution chooses to process the laser in the silicon photonic chip, avoiding the problems of complex fiber coupling operation, short service life and high repetitiveness of laser patch operation. For silicon photonic chips integrated on laser chips, it is necessary to add a laser driver to the silicon photonic chip test device, and the laser driver can be connected to the remaining port of the relay. This device can also flexibly add external device test equipment, which is suitable for different chips and the required connection test of multiple external test equipment.

[0064] The present invention provides a silicon photonic chip testing device with a simple circuit board design and mature small relay equipment. It does not require an expensive large-scale automated testing system, has a low overall testing cost, and is easy to operate.

[0065] The present invention provides a silicon photonic chip testing method based on Figure 1 The silicon photonic chip testing device shown in FIG. Figure 2 As shown, the silicon photonic chip testing method includes the following steps:

[0066] Step S11 , fixing the silicon photonic chip to be tested on the middle bracket of the coupling platform 1 .

[0067] Specifically, in the preliminary preparation stage of the test, the silicon photonic chip to be tested is fixed on the middle bracket of the coupling platform 1. The placement position of the silicon photonic chip is finely adjusted so that a probe pin in the probe pin row 21 corresponds to a pin pad in the silicon photonic chip.

[0068] Step S12, simultaneously move the probe cards on the left and right sides of the coupling platform so that each probe pin is respectively inserted into each pin pad of the silicon photonic chip.

[0069] Specifically, when performing a test, the coupling platform 1 is controlled to move the probe card 2 so that each probe pin of the probe card 2 is respectively inserted into each pin pad of the silicon photonic chip.

[0070] Step S13, configuring relay test items, source meter test items and coupling table temperature test items in the host computer test program.

[0071] Specifically, a test configuration file for the silicon photonic chip is written in the user operation interface of the host computer 5 test program. The user operation interface includes modules such as relay configuration, test equipment configuration, and test task configuration. Among them, the relay configuration module is used to configure relay test items. The relay configuration module can flexibly configure multiple relays, and each relay can be configured with several ports, which is suitable for situations where the number of probe pins increases or the number of test equipment increases. The test equipment configuration module is used to configure the information of different test devices that require network port connection, including IP addresses, different equipment for different test objects, scan test starting points, scan point time intervals, etc. The test task configuration module can arbitrarily select the configured items in the test equipment configuration for each test object. A test object can simultaneously test multiple devices with different configurations, and set the delay test time for each configuration item.

[0072] In the embodiment of the present invention, the test equipment includes a source meter 4 and a coupling station 1, wherein the source meter 4 and the coupling station 1 communicate with the host computer 5 via a network cable. The test task configuration module needs to configure the source meter test items and the coupling station temperature test items.

[0073] Furthermore, for Figure 1 The silicon photonic chip shown is configured as follows:

[0074] This time, the dark current of 9 PDs and the resistance of 1 thermistor in the silicon photonic chip are tested. There are 20 pin pads in total, and 40 relay ports 31 are required. Coupling station 1 is externally heated and controlled through network port communication. It does not need to be connected to relay 3. Relay 3 has a total of 40 relay ports 31. Relay configuration is performed, and the number of ports of relay 3 is 40, and the port number sequence of relay 3 is 1 to 40.

[0075] Furthermore, for source meter 4 and coupling station 1, first configure the IP addresses of both, configure the PD scanning test item of source meter 4 for 9 photodiodes PD, input the scanning voltage starting point, scanning point number and scanning point time interval. Then configure thermistor test information, configure thermistor scanning test item of source meter 4, under fixed voltage, each point interval is 0.1s, and scan 3 points. Configure coupling station test items, set multiple continuous heating temperatures of heating station 12 and heating time of each temperature.

[0076] Further, configure the test task. First, configure the first photodiode PD, and find the positions of the two pin pads corresponding to its positive and negative pins respectively. For the pin pad pad corresponding to the positive electrode, find the number in the corresponding circuit board pin row 22, and then correspond to the number in the positive pin row 23 connected to it, and finally determine the number of the corresponding relay port connected to it, and configure the number information of the relay port corresponding to the positive pin pad pad in the configuration program. Similarly, for the pin pad pad corresponding to the negative electrode, find the number in the corresponding circuit board pin row 22, and then correspond to the number in the negative pin row 24 connected to it, and finally determine the number of the corresponding relay port connected to it, and configure the number information of the relay port corresponding to the negative pin pad pad in the configuration program. After the relay port configuration is completed, select the PD scan test item in source table 4, and repeat this configuration operation for the other 8 photodiodes PD. Finally, set the thermistor configuration information, and also find the relay port corresponding to the pin pad pad. The port configuration is completed, select the thermistor scan test item in source table 4, and the coupling table test item, select the delay time for each test of source table 4, the configuration is completed, and the configuration information is saved.

[0077] Step S14, start the test program and complete the test tasks of all photodiodes of the silicon photonic chip in sequence.

[0078] Specifically, step S14 includes the following process:

[0079] Step S141, finding the positions of the positive electrode pin pad and the negative electrode pin pad of the first photodiode.

[0080] Step S142, finding the positive electrode pin connected to the positive electrode pin pad, and determining the relay port connected to the positive electrode pin.

[0081] Step S143, finding the negative electrode pin connected to the negative electrode pin pad, and determining the relay port connected to the negative electrode pin.

[0082] Step S144, selecting source meter voltages of different levels, controlling the on and off of the relay port, and testing the current value of the first photodiode at different voltage levels.

[0083] Step S145, repeat the above process until all photodiodes complete the test task.

[0084] Step S146, use a source meter to perform a scan test, collect the current values ​​of all photodiodes at different voltage levels, and judge the performance of the silicon photonic chip based on the current values.

[0085] Specifically, the host computer 5 selects the test configuration information of the silicon photonic chip to start the test, and the photodiode PD starts to perform current testing in sequence. Specifically, the positions of the positive pin pad pad and the negative pin pad pad of the first photodiode PD are searched. Then the positive pin connected to the positive pin pad pad is found, and the relay port connected to the positive pin is determined. Similarly, the negative pin connected to the negative pin pad pad is found, and the relay port connected to the negative pin is determined. Different levels of source meter voltages are selected in sequence to control the on and off of the above-mentioned relay port, and the current value of the first photodiode at different voltage levels is tested. At the same time, the source meter is used to perform a scan test, and the current value of the first photodiode at different voltage levels is collected, and the performance of the first photodiode is judged according to the current value. Repeat the above operation for the remaining photodiodes PD until all photodiodes complete the test task, and then use the source meter to perform a scan test, collect the current values ​​of all photodiodes at different voltage levels, and judge the performance of the photodiode according to the current value, and then judge the performance of the silicon photonic chip.

[0086] In an optional implementation, the silicon photonic chip testing method further includes the following steps:

[0087] Step S15, testing the thermistor of the silicon photonic chip at different temperatures.

[0088] Specifically, step S15 includes the following process:

[0089] Step S151, setting a plurality of consecutive target temperatures for the coupling stage.

[0090] Step S152, heating the coupling platform to a first target temperature, performing a scanning test using a source meter, and collecting the resistance value of the thermistor at the first target temperature.

[0091] Step S153 , heating the coupling stage to a second target temperature, performing a scanning test using a source meter, and collecting the resistance value of the thermistor at the second target temperature.

[0092] Step S154, repeat the above process until thermistor tests at multiple target temperatures are completed.

[0093] Specifically, after the photodiode PD test is completed, the thermistor test is continued. The coupling station 1 first works for a period of time to rise to the first target temperature, and the source meter 4 performs a scan test, and the test ends. The coupling station 1 continues to rise to the second target temperature. After the temperature stabilizes, the source meter 4 performs a scan test again, rereads this test operation, and the relay is closed until all temperature tests are completed. After the test is completed, all test results are returned, including the current value of each photodiode PD at different voltages and the current test results of the thermistor at different temperatures at the operating temperature, and then the relay 3 is closed.

[0094] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A silicon photonic chip testing device, characterized in that: The device comprises: a coupling station, a probe card, a relay, a source meter and a host computer, wherein: The middle bracket of the coupling platform is used to place the silicon photonic chip to be tested, and a probe card is fixed on each of the six-axis brackets on the left and right sides of the coupling platform; Each of the probe cards comprises a probe pin row, a circuit board pin row, a positive electrode pin row and a negative electrode pin row, wherein a probe pin in the probe pin row corresponds to a pin pad in the silicon photonic chip, the probe pins in the probe pin row are connected one-to-one with the pins in the circuit board pin row, the pins in the circuit board pin row are also connected one-to-one with the positive electrode pins in the positive electrode pin row and the negative electrode pins in the negative electrode pin row, the positive electrode pins are connected one-to-one with the normally open contacts of the ports on one side of the relay, and the negative electrode pins are connected one-to-one with the normally open contacts of the ports on the other side of the relay; The common end of the port on one side of the relay is connected to the positive pole of the source meter, and the common end of the port on the other side of the relay is connected to the negative pole of the source meter; The relay, the source meter and the coupling station are all connected to the host computer for communication, and the host computer stores a test program.

2. The silicon photonic chip testing device according to claim 1, characterized in that: The relay is a small DC relay.

3. The silicon photonic chip testing device according to claim 1, characterized in that: The power line of the coupling station is connected to the relay port, or the coupling station adopts an external heating method.

4. The silicon photonic chip testing device according to claim 1, characterized in that: The number of pins of the probe pin row, the circuit board pin row, the positive electrode pin row, the negative electrode pin row and the number of ports of the relay are adjusted according to the number of pin pads of the silicon photonic chip.

5. The silicon photonic chip testing device according to claim 1, characterized in that: The silicon photonic chip has multiple photodiodes, and each photodiode has a positive pin pad and a negative pin pad.

6. A silicon photonic chip testing method, characterized in that: Based on the silicon photonic chip testing device according to any one of claims 1 to 5, the method comprises: Fix the silicon photonic chip to be tested on the middle bracket of the coupling platform; Simultaneously move the probe cards on the left and right sides of the coupling platform so that each probe pin is respectively inserted into each pin pad of the silicon photonic chip; Configure relay test items, source meter test items and coupling table temperature test items in the host computer test program; Start the test program and complete the test tasks of all photodiodes of the silicon photonic chip in sequence.

7. The silicon photonic chip testing method according to claim 6, characterized in that: The startup test program sequentially completes the test tasks of all photodiodes of the silicon photonic chip, including: Find the positive and negative pin pads of the first photodiode. Find the positive pin connected to the positive pin pad, and determine the relay port connected to the positive pin; Find the negative pin connected to the negative pin pad, and determine the relay port connected to the negative pin; Select different levels of source meter voltage, control the on and off of the relay port, and test the current value of the first photodiode at different voltage levels; Repeat the above process until all photodiodes have completed the test task.

8. The silicon photonic chip testing method according to claim 7, characterized in that: The method further comprises: A source meter is used to perform a scanning test to collect current values ​​of all photodiodes at different voltage levels, and the performance of the silicon photonic chip is judged based on the current values.

9. The silicon photonic chip testing method according to claim 7, characterized in that: The method further includes: testing the thermistor of the silicon photonic chip at different temperatures.

10. The silicon photonic chip testing method according to claim 9, characterized in that: The method further includes: testing the thermistor of the silicon photonic chip at different temperatures, including: For the coupling stage, set multiple consecutive target temperatures; The coupling platform is heated to a first target temperature, and a scanning test is performed using a source meter to collect the resistance value of the thermistor at the first target temperature; heating the coupling platform to a second target temperature, performing a scanning test using a source meter, and collecting the resistance value of the thermistor at the second target temperature; Repeat the above process until thermistor tests at multiple target temperatures are completed.

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