Chip defect detection method and device and terminal equipment

Abstract

The invention discloses a chip defect detection method and device and terminal equipment, and the method comprises the steps: obtaining the state distribution information of a chip based on the operation data of the chip, and obtaining the abnormal operation state, abnormal operation program and associated abnormal structure of the chip based on the state distribution information; constructing a three-dimensional temperature distribution diagram of the chip based on the temperature data of the chip, and determining a temperature anomaly structure based on the three-dimensional temperature distribution diagram; and predicting a target abnormal structure and abnormal information of the chip based on the associated abnormal structure and the temperature abnormal structure, and generating a defect detection result. According to the method, the target abnormal structure of each chip and the abnormal information of the target abnormal structure are analyzed from multiple angles such as the operation information and the temperature data, so that the comprehensiveness of identifying the abnormal information of each abnormal structure of the chip is improved, and the chip defect detection efficiency is comprehensively improved.

Description

Technical Field

[0001] The present invention relates to the technical field of Internet of Things chips, and in particular to a chip defect detection method, device and terminal equipment. Background Art

[0002] At present, during the operation of integrated circuit chips, the internal structure of the chip will gradually age and be damaged due to reasons such as long operation time, high operating temperature, abnormal program operation, etc. In addition to the integrated circuit chips used in large-scale equipment, which are regularly inspected and replaced manually, the integrated circuit chips in general small and medium-sized equipment are often detected only when the chip reports an error, the chip fails, or the chip is damaged. Therefore, how to predict the potential problems of the chip in advance through regular chip detection to extend the life of the chip is the current research focus.

[0003] The existing chip detection method is to manually program the chip and then use chip detection equipment to detect the chip. The detection is time-consuming, consumes a lot of human resources, and the cost of chip detection equipment is high, which leads to high chip detection costs and low efficiency of chip defect detection. Summary of the invention

[0004] The present invention provides a chip defect detection method, device and terminal equipment to reduce the cost of chip detection and improve chip detection efficiency.

[0005] In order to solve the above technical problems, an embodiment of the present invention provides a chip defect detection method, comprising:

[0006] Acquire state distribution information of the chip based on the operation data of the chip, and acquire abnormal operation state, abnormal operation program and associated abnormal structure of the chip based on the state distribution information;

[0007] constructing a three-dimensional temperature distribution map of the chip based on the temperature data of the chip, and determining a temperature abnormality structure based on the three-dimensional temperature distribution map;

[0008] The target abnormal structure and abnormal information of the chip are predicted based on the associated abnormal structure and the temperature abnormal structure to generate a defect detection result.

[0009] Further, the obtaining of chip status distribution information based on chip operation data includes:

[0010] Regularly obtain the operation information of the chip within a preset time period, and split the operation information based on the operation type to obtain sub-operation information of each operation type;

[0011] Arrange the sub-operation information of each operation type according to the time sequence to obtain the sub-operation distribution information of each operation type;

[0012] Collect chip status information corresponding to each operation type, and obtain chip status data of each operation type according to the chip status information and sub-operation information;

[0013] Distribution arrangement processing is performed based on the chip state data to obtain sub-state distribution information corresponding to each operation type, and chip state distribution information is generated based on the sub-state distribution information.

[0014] Further, the obtaining of the abnormal operation state, abnormal operation program and associated abnormal structure of the chip based on the state distribution information includes:

[0015] Acquiring an abnormal operating state of a chip based on a preset standard operating range and the state distribution information;

[0016] An abnormal operation program is determined based on the abnormal operation state, and an associated abnormal structure is acquired based on the abnormal operation program.

[0017] Further, the obtaining of the abnormal operation state of the chip based on the preset standard operation range and the state distribution information includes:

[0018] Obtaining status trend information of each operation type based on sub-status distribution information of each type;

[0019] Acquire a first abnormal operating state based on the sub-state distribution information and the standard operating range;

[0020] Acquire a second abnormal operating state based on the state trend information and the standard operating range;

[0021] An abnormal operation state of a chip is generated based on the first abnormal operation state and the second abnormal operation state.

[0022] Further, the determining the abnormal operation program based on the abnormal operation state, and acquiring the associated abnormal structure based on the abnormal operation program, includes:

[0023] Acquire the operation type corresponding to the abnormal operation state, and determine the abnormal operation program according to the operation type;

[0024] A first abnormal structure in the chip that participates in the running of the abnormal running program is obtained, and the participation degree of the first abnormal structure is obtained, and a second abnormal structure is obtained according to the participation degree; the participation degree indicates the degree of participation of the first abnormal structure in the running of the abnormal running program.

[0025] Furthermore, constructing a three-dimensional temperature distribution map of the chip based on the temperature data of the chip, and determining the temperature abnormality structure based on the three-dimensional temperature distribution map includes:

[0026] Acquire the structural information and thermal information of the chip; the structural information includes the material information, thermal information, shape information and spatial connection information of each structure; the thermal information includes the thermal conductivity coefficient and specific heat capacity coefficient of each structure;

[0027] constructing a three-dimensional structural model of the chip based on the structural information, and constructing a heat conduction model of the chip based on the thermal information and the three-dimensional structural model;

[0028] Generate temperature distribution information of each measuring point based on preset measuring points, temperature data and heat conduction model;

[0029] A three-dimensional temperature distribution map of the chip is generated based on the temperature distribution information and the three-dimensional structure model, and a temperature abnormality structure is determined based on the three-dimensional temperature distribution map.

[0030] Further, determining the temperature anomaly structure based on the three-dimensional temperature distribution map includes:

[0031] Acquire a temperature threshold of each structure, and determine a sub-temperature distribution map of each structure based on the three-dimensional temperature distribution map;

[0032] A temperature anomaly structure is determined based on the sub-temperature distribution map and the temperature threshold.

[0033] Furthermore, the predicting of the target abnormal structure and abnormal information of the chip based on the associated abnormal structure and the temperature abnormal structure to generate a defect detection result includes:

[0034] Filtering a first abnormal structure and its corresponding abnormal information based on the associated abnormal structure and the temperature abnormal structure;

[0035] Filtering a second abnormal structure and its corresponding abnormal information based on the associated abnormal structure;

[0036] Screening a third abnormal structure and its corresponding abnormal information based on the temperature abnormal structure;

[0037] The first abnormal structure, the second abnormal structure and the third abnormal structure are integrated to generate a target abnormal structure and its corresponding abnormal information, and generate a defect detection result; the abnormal information includes the abnormal cause, the target field period, the abnormal structure location point and the target abnormal state.

[0038] In a second aspect, the present invention provides a chip defect detection device, including: a state abnormality monitoring module, a temperature abnormality monitoring module and a prediction module;

[0039] The state abnormality monitoring module is used to obtain the state distribution information of the chip based on the operation data of the chip, and obtain the abnormal operation state, abnormal operation program and associated abnormal structure of the chip based on the state distribution information;

[0040] The temperature anomaly monitoring module is used to construct a three-dimensional temperature distribution map of the chip based on the temperature data of the chip, and determine the temperature anomaly structure based on the three-dimensional temperature distribution map;

[0041] The prediction module is used to predict the target abnormal structure and abnormal information of the chip based on the associated abnormal structure and the temperature abnormal structure, and generate a defect detection result.

[0042] In a third aspect, the present invention provides a terminal device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, and the processor implements the chip defect detection method when executing the computer program. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A schematic diagram of the structure of a chip defect detection method provided in an embodiment of the present invention;

[0044] Figure 2 A schematic structural diagram of a chip defect detection device provided by an embodiment of the present invention;

[0045] Figure 3 Another schematic flow chart of a chip defect detection method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0046] The specific implementation of the present invention is further described in detail below in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0047] The terms "first" and "second" and the like in the specification, claims and drawings of this application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products or devices.

[0048] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0049] Example 1

[0050] See also Figure 1 , Figure 1 The present invention provides a chip defect detection method according to an embodiment of the present invention. The present invention provides a chip defect detection method, including steps 101 to 103, which are as follows:

[0051] Step 101: acquiring state distribution information of a chip based on operation data of the chip, and acquiring abnormal operation state, abnormal operation program and associated abnormal structure of the chip based on the state distribution information;

[0052] In this embodiment, the step of acquiring the chip status distribution information based on the chip operation data includes:

[0053] Regularly obtain the operation information of the chip within a preset time period, and split the operation information based on the operation type to obtain sub-operation information of each operation type;

[0054] Arrange the sub-operation information of each operation type according to the time sequence to obtain the sub-operation distribution information of each operation type;

[0055] Collect chip status information corresponding to each operation type, and obtain chip status data of each operation type according to the chip status information and sub-operation distribution information;

[0056] Distribution arrangement processing is performed based on the chip state data to obtain sub-state distribution information corresponding to each operation type, and chip state distribution information is generated based on the sub-state distribution information.

[0057] In this embodiment, a sampling period is preset, and the terminal periodically obtains the operation information of the chip according to the sampling period, wherein the operation information includes the operation rate and the processing log information of each running program of the chip.

[0058] In this embodiment, the state distribution information of the chip is identified according to the operation information, wherein the state distribution information includes sub-state information corresponding to the operation information of different operation types.

[0059] In this embodiment, after obtaining the sub-operation information of each operation type, the sub-operation information of each operation type is arranged in chronological order to obtain the initial sub-operation distribution information of each operation type, and the initial sub-operation distribution information is fitted according to a fitting algorithm to obtain the sub-operation distribution information of each operation type. The fitting algorithm is a curve fitting algorithm based on the least squares method.

[0060] In this embodiment, each sub-operation distribution information is fitted by a fitting algorithm, thereby avoiding the discrete data interfering with the data analysis process and improving the accuracy of the obtained sub-state distribution information.

[0061] In this embodiment, each operation type corresponds to an operation program and a chip structure, and the operation type is used to indicate the functional information corresponding to the chip type. The operation type includes a structure control type, a data processing type, a data transmission type, a data receiving type, and a data sending type, and the structure control type corresponds to the chip controller, the data processing type corresponds to the chip processing structure, the data transmission type corresponds to the chip transmission structure, the data receiving type corresponds to the chip receiving port, and the data sending type corresponds to the chip data sending port.

[0062] In this embodiment, the chip status information corresponding to each operation type is obtained, and based on the chip status information corresponding to each operation type and the sub-operation distribution information of each operation type, the chip status data corresponding to each operation data in the sub-operation distribution information of each operation type is identified through the status database; and each chip status data is distributed and arranged according to the distribution method between the operation data corresponding to each chip status data to obtain the sub-state distribution information corresponding to each operation type.

[0063] In this embodiment, a state database is pre-built, and the state database includes chip state information corresponding to each operation type, and the association between the data change of each operation type and the data change of the chip state information. By querying the state database, the chip state information corresponding to each operation type and the chip state data corresponding to each operation data can be obtained.

[0064] In this embodiment, the step of acquiring the abnormal operation state, abnormal operation program, and associated abnormal structure of the chip based on the state distribution information includes:

[0065] Acquiring an abnormal operating state of a chip based on a preset standard operating range and the state distribution information;

[0066] An abnormal operation program is determined based on the abnormal operation state, and an associated abnormal structure is acquired based on the abnormal operation program.

[0067] In this embodiment, based on the sub-state distribution information corresponding to each operation type, the state trend information corresponding to each operation type is identified, and the standard operation range of each chip operation state is obtained, and the abnormal operation state of the chip is obtained based on the abnormal state determination rules, the preset standard operation range and the state distribution information.

[0068] In this embodiment, the obtaining of the abnormal operation state of the chip based on the preset standard operation range and the state distribution information includes:

[0069] Obtaining status trend information of each operation type based on sub-status distribution information of each type;

[0070] Acquire a first abnormal operating state based on the sub-state distribution information and the standard operating range;

[0071] Acquire a second abnormal operating state based on the state trend information and the standard operating range;

[0072] An abnormal operation state of a chip is generated based on the first abnormal operation state and the second abnormal operation state.

[0073] In this embodiment, the abnormal state determination rule stipulates that: for each operation type, the state distribution information of the sub-state distribution information of the operation type is filtered out and is greater than the standard operation range, as the first abnormal operation state; the segment of the sub-state trend information of the operation type is filtered out and is greater than the normal operation, as the second abnormal operation state; the first abnormal operation state and the second abnormal operation state are used as the abnormal operation states of the chip.

[0074] In this embodiment, the running program corresponding to the running type is identified based on the abnormal running state; and the running program corresponding to the running type with the abnormal running state is used as the abnormal running program corresponding to the abnormal running state.

[0075] In this embodiment, based on the sub-state distribution information corresponding to each operation type, the state trend information corresponding to each operation type is identified, and the standard operation range of each chip operation state is obtained. The state trend information is used to characterize the predicted state distribution information of each operation type in a fixed period in the future. The identification process of the state trend information is to analyze the predicted state distribution information of the sub-state distribution information by the curve slope and the curve distribution range of the sub-state distribution information corresponding to each operation type through the trend line analysis strategy of the curve, and the trend line distribution strategy is the analysis strategy corresponding to the trend line analysis program in MATLAB.

[0076] In this embodiment, determining the abnormal running program based on the abnormal running state, and acquiring the associated abnormal structure based on the abnormal running program includes:

[0077] Acquire the operation type corresponding to the abnormal operation state, and determine the abnormal operation program according to the operation type;

[0078] A first abnormal structure in the chip that participates in the running of the abnormal running program is obtained, and the participation degree of the first abnormal structure is obtained, and a second abnormal structure is obtained according to the participation degree, where the second abnormal structure is an associated abnormal structure; the participation degree indicates the degree of participation of the abnormal structure in the running of the abnormal running program.

[0079] In this embodiment, according to the abnormal state determination rule, the state distribution information of the sub-state distribution information of the operation type that is greater than the standard operation range is filtered as the first abnormal operation state; the state trend information corresponding to the operation type is identified, and the sub-state trend information segment greater than the standard operation state is filtered as the second abnormal operation state. Then, the terminal uses the first abnormal operation state and the second abnormal operation state as the abnormal operation state of the chip, and identifies the operation program corresponding to the operation type. Finally, the terminal uses the operation program corresponding to the operation type with the abnormal operation state as the abnormal operation program corresponding to the abnormal operation state.

[0080] In this embodiment, the current abnormal state of the analysis curve and the predicted abnormal state are the operating programs corresponding to each operating type, thereby improving the accuracy, comprehensiveness, and potential of the identified operating programs.

[0081] In this embodiment, in a preset chip database, the structures of the chip that participate in each abnormal running program are queried as the first abnormal structure of each abnormal running program; for each abnormal running program, the degree of participation of the first abnormal structure of the abnormal running program in participating in the abnormal running program is identified, and the first abnormal structures are sorted in order of participation from large to small, and the abnormal structures with a larger degree of participation are screened out according to a preset number as the second abnormal structure, and the second abnormal structure is the associated abnormal structure of the abnormal running program.

[0082] In this embodiment, for each abnormal running program, the participation degree of each initial associated abnormal structure (first abnormal structure) of the abnormal running program in participating in the abnormal running program is identified. Specifically, the database stores the associated structure corresponding to each running program and the running content of the running program corresponding to each associated structure. The terminal determines the participation degree of each initial associated abnormal structure in participating in the abnormal running program according to the proportion of the running content of the running program corresponding to each associated structure to all the running contents of the running program. And according to the order of participation degree from large to small, a preset number of initial associated abnormal structures are selected as the associated abnormal structures of the abnormal running program. Among them, the preset number can be set according to the structure ratio, and can also be adjusted manually.

[0083] In this embodiment, by screening abnormal structures with a high degree of association as associated abnormal structures, the accuracy of identifying associated abnormal structures is improved.

[0084] Step 102: constructing a three-dimensional temperature distribution map of the chip based on the temperature data of the chip, and determining a temperature abnormality structure based on the three-dimensional temperature distribution map;

[0085] In this embodiment, measurement points are preset in the chip, and temperature sensors are arranged at the measurement points, including the chip housing, the chip connection points and the chip mainboard.

[0086] In this embodiment, when the operation information of the chip is obtained according to the sampling period, the temperature data of the chip is obtained based on the preset temperature sensor at the same time.

[0087] In this embodiment, the three-dimensional temperature distribution map of the chip is constructed based on the temperature data of the chip, and the temperature abnormality structure is determined based on the three-dimensional temperature distribution map, including:

[0088] Acquire the structural information and thermal information of the chip; the structural information includes the material information, thermal information, shape information and spatial connection information of each structure; the thermal information includes the thermal conductivity coefficient and specific heat capacity coefficient of each structure;

[0089] constructing a three-dimensional structural model of the chip based on the structural information, and constructing a heat conduction model of the chip based on the thermal information and the three-dimensional structural model;

[0090] Generate temperature distribution information of each measuring point based on preset measuring points, temperature data and heat conduction model;

[0091] A three-dimensional temperature distribution map of the chip is generated based on the temperature distribution information and the three-dimensional structure model, and a temperature abnormality structure is determined based on the three-dimensional temperature distribution map.

[0092] In this embodiment, the structural material information of each structure of the chip, the structural shape information of each structure, and the spatial connection information between each structure are collected to generate structural information, and the thermal information corresponding to the structural material information is obtained; wherein the structural material information is the constituent material of the structure, such as single crystal silicon material, polyester plastic material, metal material, etc., wherein the thermal information includes the thermal conduction information of each structural material and the specific heat capacity information of each structural material. The thermal information is used to analyze the transmission rate and transmission loss rate of the temperature data between each structure, thereby identifying the distribution information of the temperature data in the chip.

[0093] In this embodiment, a basic chip information database is pre-built according to the structural information and thermal information of the chip, and the structural information and thermal information of the chip can be quickly acquired by querying the basic chip information database.

[0094] In this embodiment, a three-dimensional structural model of the chip is constructed based on the structural shape information of each structure and the spatial connection information between each structure. The method of constructing the three-dimensional structural model can be constructed by a finite element simulation model. Based on the thermal information of the structural material information of each structure, the thermal conductivity coefficient of each structure and the specific heat capacity coefficient of each structure are identified, and based on the thermal conductivity coefficient of each structure, the specific heat capacity coefficient of each structure and the three-dimensional structural model, the thermal conduction model of the chip is constructed. Based on the thermal conduction model of the chip and the position information of each measurement point, the initial temperature distribution information of the chip corresponding to the current temperature data of each measurement point is generated, and the initial temperature distribution information corresponding to each measurement point is fitted to obtain the current temperature distribution information of the chip.

[0095] In this embodiment, the current temperature distribution information of the chip is obtained by fitting the chip temperature distribution information corresponding to the temperature data of each measurement point, thereby improving the accuracy of the identified temperature distribution information of the chip.

[0096] In this embodiment, after obtaining the temperature distribution information of the chip, the sub-temperature distribution information of each structure of the chip is identified, and the fitting temperature data of each structure is added to the three-dimensional structural model of the chip to obtain a three-dimensional temperature distribution map of the chip. The temperature data of different position points in the three-dimensional temperature distribution map are distinguished by different marking colors.

[0097] In this embodiment, the three-dimensional temperature distribution map of the chip is obtained by visually mapping the fitted temperature distribution information to the three-dimensional structure model, thereby improving the accuracy of the obtained three-dimensional temperature distribution map.

[0098] In this embodiment, determining the temperature abnormal structure based on the three-dimensional temperature distribution map includes:

[0099] Acquire a temperature threshold of each structure, and determine a sub-temperature distribution map of each structure based on the three-dimensional temperature distribution map;

[0100] A temperature anomaly structure is determined based on the sub-temperature distribution map and the temperature threshold.

[0101] In this embodiment, the temperature threshold of each structure is collected, and based on the three-dimensional temperature distribution map of the chip, a sub-temperature distribution map of each structure is obtained; for the sub-temperature distribution map of each structure, the abnormal structure position points corresponding to the temperature data greater than the temperature threshold in each structure are screened out, and the structure with the abnormal structure position points is regarded as a temperature abnormality structure.

[0102] In this embodiment, by identifying abnormal structural positions of different structures under the structural temperature threshold conditions of the structure, the accuracy and comprehensiveness of identifying temperature abnormal structures are improved.

[0103] Step 103: predicting the target abnormal structure and abnormal information of the chip based on the associated abnormal structure and the temperature abnormal structure, and generating a defect detection result.

[0104] In this embodiment, the prediction of the target abnormal structure and abnormal information of the chip based on the associated abnormal structure and the temperature abnormal structure to generate the defect detection result includes:

[0105] Filtering a first abnormal structure and its corresponding abnormal information based on the associated abnormal structure and the temperature abnormal structure;

[0106] Filtering a second abnormal structure and its corresponding abnormal information based on the associated abnormal structure;

[0107] Screening a third abnormal structure and its corresponding abnormal information based on the temperature abnormal structure;

[0108] The first abnormal structure, the second abnormal structure and the third abnormal structure are integrated to generate a target abnormal structure and its corresponding abnormal information, and generate a defect detection result; the abnormal information includes the abnormal cause, the target field period, the abnormal structure location point and the target abnormal state.

[0109] In this embodiment, the first abnormal structure and its corresponding abnormal information are screened based on the associated abnormal structure and the temperature abnormal structure, including: among the structures of the chip, screening the first abnormal structure that is both the associated abnormal structure and the temperature abnormal structure, and identifying the abnormal cause of each first abnormal structure according to the abnormal temperature data corresponding to each abnormal structure position point of the first abnormal structure and the first abnormal operating state of each first abnormal structure; predicting the target abnormal time period of each first abnormal structure and the target abnormal state of each abnormal structure according to the second abnormal operating state of each first abnormal structure; and taking the abnormal cause of each first abnormal structure, the target abnormal time period of each first abnormal structure, and the target abnormal state of each first abnormal structure as the abnormal information of each first abnormal structure.

[0110] In this embodiment, the second abnormal structure and its corresponding abnormal information are screened based on the associated abnormal structure, including: among the structures of the chip, screening the second abnormal structure that is only the associated abnormal structure, and identifying the abnormal probability of each second abnormal structure based on the degree of participation of each second abnormal structure in the abnormal operation program, and identifying the abnormal cause of each second abnormal structure based on the first abnormal operation state of each second abnormal structure; based on the second abnormal operation state of each second abnormal structure, identifying the target abnormal state of each second abnormal structure and the target abnormal time period of each second abnormal structure, and using the abnormal probability of each second abnormal structure, the abnormal cause of each second abnormal structure, the target abnormal state of each second abnormal structure, and the target abnormal time period of each second abnormal structure as the abnormal information of each second abnormal structure.

[0111] In this embodiment, the third abnormal structure and its corresponding abnormal information are screened based on the temperature abnormal structure, including: among the structures of the chip, screening the third abnormal structure that is only the temperature abnormal structure, and identifying the temperature change information of each third abnormal structure in a fixed time period; based on the temperature change information of each third abnormal structure, identifying the temperature trend information of the third abnormal structure, and using the temperature abnormality and the temperature trend information as the abnormal information of the third abnormal structure.

[0112] In this embodiment, each first abnormal structure, each second abnormal structure, and each third abnormal structure are used as target abnormal structures of the chip, and the abnormal information of each first abnormal structure, the abnormal information of each second abnormal structure, and the abnormal information of each third abnormal structure are used as the abnormal information of each target abnormal structure of the chip.

[0113] In this embodiment, the abnormal information of different abnormal field structures is split and analyzed to obtain the abnormal information of each abnormal structure, thereby improving the pertinence and accuracy of identifying the abnormal information of the abnormal structure.

[0114] In this embodiment, the chip defect self-detection is performed by periodically acquiring the current operation information of the chip at a fixed time and the current temperature data of multiple measurement points, thereby avoiding the inefficiency of manual timed detection and improving the efficiency of chip defect self-detection. At the same time, the associated abnormal structure and temperature abnormal structure of the chip are respectively identified through the acquired data, thereby predicting each target abnormal structure of the chip and the abnormal information of each target abnormal structure, which not only improves the comprehensiveness and accuracy of chip defect self-detection, but also predicts the structure of the chip that may have abnormalities through the above information, and predicts the abnormal information of the abnormal structure, which not only improves the chip self-detection accuracy, but also can predict the abnormal structure of the chip, and improves the efficiency of early warning and processing strategy generation for the abnormal structure of the chip. Moreover, by analyzing the target abnormal structure of each chip and the abnormal information of the target abnormal structure from multiple angles such as operation information and temperature data, the comprehensiveness of the abnormal information of each abnormal structure of the chip is improved, thereby comprehensively improving the efficiency of chip defect detection.

[0115] Please refer to Figure 2 , Figure 2 A schematic diagram of the structure of a chip defect detection device provided by an embodiment of the present invention includes: a state abnormality monitoring module 201, a temperature abnormality monitoring module 202 and a prediction module 203;

[0116] The state abnormality monitoring module 201 is used to obtain the state distribution information of the chip based on the operation data of the chip, and obtain the abnormal operation state, abnormal operation program and associated abnormal structure of the chip based on the state distribution information;

[0117] The temperature anomaly monitoring module 202 is used to construct a three-dimensional temperature distribution map of the chip based on the temperature data of the chip, and determine the temperature anomaly structure based on the three-dimensional temperature distribution map;

[0118] The prediction module 203 is used to predict the target abnormal structure and abnormal information of the chip based on the associated abnormal structure and the temperature abnormal structure, and generate a defect detection result.

[0119] In this embodiment, the abnormal state monitoring module 201 is specifically used to: regularly obtain the operation information of the chip within a preset time period, and split the operation information based on the operation type to obtain sub-operation information of each operation type;

[0120] Arrange the sub-operation information of each operation type according to the time sequence to obtain the sub-operation distribution information of each operation type;

[0121] Collect chip status information corresponding to each operation type, and obtain chip status data of each operation type according to the chip status information and sub-operation distribution information;

[0122] Distribution arrangement processing is performed based on the chip state data to obtain sub-state distribution information corresponding to each operation type, and chip state distribution information is generated based on the sub-state distribution information.

[0123] In this embodiment, the abnormal state monitoring module 201 is also used for:

[0124] Acquire the abnormal operation state of the chip based on the preset abnormal state determination rule, the standard operation range and the state distribution information;

[0125] An abnormal operation program is determined based on the abnormal operation state, and an associated abnormal structure is acquired based on the abnormal operation program.

[0126] In this embodiment, the abnormal state monitoring module 201 is further used for:

[0127] Obtaining status trend information of each operation type based on sub-status distribution information of each type;

[0128] Acquire a first abnormal operating state based on the sub-state distribution information and the standard operating range;

[0129] Acquire a second abnormal operating state based on the state trend information and the standard operating range;

[0130] An abnormal operation state of a chip is generated based on the first abnormal operation state and the second abnormal operation state.

[0131] In this embodiment, the abnormal state monitoring module 201 is further used for:

[0132] Acquire the operation type corresponding to the abnormal operation state, and determine the abnormal operation program according to the operation type;

[0133] A first abnormal structure in the chip that participates in the running of the abnormal running program is obtained, and the participation degree of the first abnormal structure is obtained, and a second abnormal structure is obtained according to the participation degree, where the second abnormal structure is an associated abnormal structure; the participation degree indicates the degree of participation of the abnormal structure in the running of the abnormal running program.

[0134] In this embodiment, the temperature anomaly monitoring module 202 is specifically used for:

[0135] Acquire the structural information and thermal information of the chip; the structural information includes the material information, thermal information, shape information and spatial connection information of each structure; the thermal information includes the thermal conductivity coefficient and specific heat capacity coefficient of each structure;

[0136] constructing a three-dimensional structural model of the chip based on the structural information, and constructing a heat conduction model of the chip based on the thermal information and the three-dimensional structural model;

[0137] Generate temperature distribution information of each measuring point based on preset measuring points, temperature data and heat conduction model;

[0138] A three-dimensional temperature distribution map of the chip is generated based on the temperature distribution information and the three-dimensional structure model, and a temperature abnormality structure is determined based on the three-dimensional temperature distribution map.

[0139] In this embodiment, the temperature anomaly monitoring module 202 is further used for:

[0140] Acquire a temperature threshold of each structure, and determine a sub-temperature distribution map of each structure based on the three-dimensional temperature distribution map;

[0141] A temperature anomaly structure is determined based on the sub-temperature distribution map and the temperature threshold.

[0142] In this embodiment, the prediction module 203 is specifically used for:

[0143] Filtering a first abnormal structure and its corresponding abnormal information based on the associated abnormal structure and the temperature abnormal structure;

[0144] Filtering a second abnormal structure and its corresponding abnormal information based on the associated abnormal structure;

[0145] Screening a third abnormal structure and its corresponding abnormal information based on the temperature abnormal structure;

[0146] The first abnormal structure, the second abnormal structure and the third abnormal structure are integrated to generate a target abnormal structure and its corresponding abnormal information, and generate a defect detection result; the abnormal information includes the abnormal cause, the target field period, the abnormal structure location point and the target abnormal state.

[0147] In this embodiment, the chip defect self-detection is performed by periodically acquiring the current operation information of the chip at a fixed time and the current temperature data of multiple measurement points, thereby avoiding the inefficiency of manual timed detection and improving the efficiency of chip defect self-detection. At the same time, the associated abnormal structure and temperature abnormal structure of the chip are respectively identified through the acquired data, thereby predicting each target abnormal structure of the chip and the abnormal information of each target abnormal structure, which not only improves the comprehensiveness and accuracy of chip defect self-detection, but also predicts the structure of the chip that may have abnormalities through the above information, and predicts the abnormal information of the abnormal structure, which not only improves the chip self-detection accuracy, but also can predict the abnormal structure of the chip, and improves the efficiency of early warning and processing strategy generation for the abnormal structure of the chip. Moreover, by analyzing the target abnormal structure of each chip and the abnormal information of the target abnormal structure from multiple angles such as operation information and temperature data, the comprehensiveness of the abnormal information of each abnormal structure of the chip is improved, thereby comprehensively improving the efficiency of chip defect detection.

[0148] Please refer to Figure 3 , Figure 3 Another flowchart of a chip defect detection method provided by an embodiment of the present invention includes steps 301 to 305, which are as follows:

[0149] Step 301: regularly acquiring current operation information of a chip for a fixed time period and current temperature data of multiple measurement points of the chip, and identifying state distribution information of the chip based on the current operation information of the chip;

[0150] Step 302: performing distribution processing on the current temperature data of each of the measurement points to obtain current temperature distribution information of the chip, and constructing a three-dimensional temperature distribution map of the chip based on the current temperature distribution information of the chip;

[0151] Step 303: Based on the state distribution information of the chip, identify the abnormal operation state of the chip and the abnormal operation program corresponding to the abnormal operation state, and query the associated abnormal structure corresponding to the abnormal operation program;

[0152] Step 304: Based on the three-dimensional temperature distribution map of the chip, in each structure of the chip, screen temperature abnormal structures, and based on each associated abnormal structure and each temperature abnormal structure, predict each target abnormal structure of the chip and abnormal information of each target abnormal structure;

[0153] Step 305: taking each of the target abnormal structures and the abnormal information of each of the target abnormal structures as the target detection result of the chip.

[0154] The embodiment of the present invention also provides a chip defect detection system, including an acquisition module, a construction module, an identification module, a prediction module and a determination module;

[0155] The acquisition module is used to periodically acquire current operation information of the chip in a fixed time period and current temperature data of multiple measurement points of the chip, and identify state distribution information of the chip based on the current operation information of the chip;

[0156] The construction module is used to perform distribution processing on the current temperature data of each of the measurement points to obtain the current temperature distribution information of the chip, and to construct a three-dimensional temperature distribution map of the chip based on the current temperature distribution information of the chip;

[0157] The identification module is used to identify the abnormal operation state of the chip and the abnormal operation program corresponding to the abnormal operation state based on the state distribution information of the chip, and query the associated abnormal structure corresponding to the abnormal operation program;

[0158] The prediction module is used to screen temperature abnormal structures among various structures of the chip based on the three-dimensional temperature distribution map of the chip, and predict various target abnormal structures of the chip and abnormal information of each target abnormal structure based on each associated abnormal structure and each temperature abnormal structure;

[0159] The determination module is used to use each of the target abnormal structures and the abnormal information of each of the target abnormal structures as the target detection result of the chip.

[0160] In this embodiment, the chip defect self-detection is performed by periodically acquiring the current operation information of the chip at a fixed time and the current temperature data of multiple measurement points, thereby avoiding the inefficiency of manual timed detection and improving the efficiency of chip defect self-detection. At the same time, the associated abnormal structure and temperature abnormal structure of the chip are respectively identified through the acquired data, thereby predicting each target abnormal structure of the chip and the abnormal information of each target abnormal structure, which not only improves the comprehensiveness and accuracy of chip defect self-detection, but also predicts the structure of the chip that may have abnormalities through the above information, and predicts the abnormal information of the abnormal structure, which not only improves the chip self-detection accuracy, but also can predict the abnormal structure of the chip, and improves the efficiency of early warning and processing strategy generation for the abnormal structure of the chip. Moreover, by analyzing the target abnormal structure of each chip and the abnormal information of the target abnormal structure from multiple angles such as operation information and temperature data, the comprehensiveness of the abnormal information of each abnormal structure of the chip is improved, thereby comprehensively improving the efficiency of chip defect detection.

[0161] In an embodiment of the present invention, a terminal device is also provided, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, and the processor implements the chip defect detection method when executing the computer program.

[0162] Exemplarily, the computer program may be divided into one or more modules, one or more modules are stored in a memory and executed by a processor to implement the present invention. One or more modules may be a series of computer program instruction segments capable of implementing specific functions, and the instruction segments are used to describe the execution process of the computer program in a terminal device.

[0163] The terminal device may be a computing device such as a desktop computer, a notebook, a PDA, and a cloud server. The terminal device may include, but is not limited to, a processor, a memory, and a display. Those skilled in the art will appreciate that the above components are merely examples of the terminal device and do not constitute a limitation on the terminal device. The terminal device may include more or fewer components than the components, or may combine certain components, or different components. For example, the terminal device may also include input and output devices, network access devices, buses, etc.

[0164] The processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc. The processor is the control center of the terminal device, and uses various interfaces and lines to connect various parts of the entire terminal device.

[0165] The memory can be used to store computer programs and / or modules. The processor realizes various functions of the terminal device by running or executing the computer programs and / or modules stored in the memory and calling the data stored in the memory. The memory can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, an application required for at least one function (such as a sound playback function, a text conversion function, etc.), etc.; the data storage area can store data created according to the use of the mobile phone (such as audio data, text message data, etc.), etc. In addition, the memory can include a high-speed random access memory, and can also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a smart memory card (Smart Med ia Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), at least one disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0166] Wherein, if the module based on the terminal device is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the present invention implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Wherein, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electric carrier signal, telecommunication signal and software distribution medium, etc. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0167] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. It is particularly pointed out that for those skilled in the art, any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of protection of the present invention.

Claims

1. A chip defect detection method, characterized in that: include: Acquire state distribution information of the chip based on the operation data of the chip, and acquire abnormal operation state, abnormal operation program and associated abnormal structure of the chip based on the state distribution information; constructing a three-dimensional temperature distribution map of the chip based on the temperature data of the chip, and determining a temperature abnormality structure based on the three-dimensional temperature distribution map; The target abnormal structure and abnormal information of the chip are predicted based on the associated abnormal structure and the temperature abnormal structure to generate a defect detection result.

2. A chip defect detection method as claimed in claim 1, characterized in that: The obtaining of chip status distribution information based on chip operation data includes: Regularly obtain the operation information of the chip within a preset time period, and split the operation information based on the operation type to obtain sub-operation information of each operation type; Arrange the sub-operation information of each operation type according to the time sequence to obtain the sub-operation distribution information of each operation type; Collect chip status information corresponding to each operation type, and obtain chip status data of each operation type according to the chip status information and sub-operation distribution information; Distribution arrangement processing is performed based on the chip state data to obtain sub-state distribution information corresponding to each operation type, and chip state distribution information is generated based on the sub-state distribution information.

3. A chip defect detection method as claimed in claim 2, characterized in that: The obtaining of the abnormal operation state, abnormal operation program and associated abnormal structure of the chip based on the state distribution information includes: Acquire the abnormal operation state of the chip based on the preset abnormal state determination rule, the standard operation range and the state distribution information; An abnormal operation program is determined based on the abnormal operation state, and an associated abnormal structure is acquired based on the abnormal operation program.

4. A chip defect detection method as claimed in claim 3, characterized in that: The obtaining of the abnormal operation state of the chip based on the preset abnormal state determination rule, the standard operation range and the state distribution information includes: Obtaining status trend information of each operation type based on sub-status distribution information of each type; Acquire a first abnormal operating state based on the sub-state distribution information and the standard operating range; Acquire a second abnormal operating state based on the state trend information and the standard operating range; An abnormal operation state of a chip is generated based on the first abnormal operation state and the second abnormal operation state.

5. A chip defect detection method as claimed in claim 4, characterized in that: The determining the abnormal operation program based on the abnormal operation state, and acquiring the associated abnormal structure based on the abnormal operation program, includes: Acquire the operation type corresponding to the abnormal operation state, and determine the abnormal operation program according to the operation type; A first abnormal structure in the chip that participates in the running of the abnormal running program is obtained, and the participation degree of the first abnormal structure is obtained, and a second abnormal structure is obtained according to the participation degree, where the second abnormal structure is an associated abnormal structure; the participation degree indicates the degree of participation of the abnormal structure in the running of the abnormal running program.

6. A chip defect detection method as claimed in claim 1, characterized in that: The method of constructing a three-dimensional temperature distribution map of the chip based on the temperature data of the chip and determining the temperature abnormality structure based on the three-dimensional temperature distribution map includes: Acquire the structural information and thermal information of the chip; the structural information includes the material information, thermal information, shape information and spatial connection information of each structure; the thermal information includes the thermal conductivity coefficient and specific heat capacity coefficient of each structure; constructing a three-dimensional structural model of the chip based on the structural information, and constructing a heat conduction model of the chip based on the thermal information and the three-dimensional structural model; Generate temperature distribution information of each measuring point based on preset measuring points, temperature data and heat conduction model; A three-dimensional temperature distribution map of the chip is generated based on the temperature distribution information and the three-dimensional structure model, and a temperature abnormality structure is determined based on the three-dimensional temperature distribution map.

7. A chip defect detection method as claimed in claim 6, characterized in that: The determining of the temperature anomaly structure based on the three-dimensional temperature distribution map includes: Acquire a temperature threshold of each structure, and determine a sub-temperature distribution map of each structure based on the three-dimensional temperature distribution map; A temperature anomaly structure is determined based on the sub-temperature distribution map and the temperature threshold.

8. A chip defect detection method according to any one of claims 1 to 7, characterized in that: The method of predicting the target abnormal structure and abnormal information of the chip based on the associated abnormal structure and the temperature abnormal structure, and generating a defect detection result, includes: Filtering a first abnormal structure and its corresponding abnormal information based on the associated abnormal structure and the temperature abnormal structure; Filtering a second abnormal structure and its corresponding abnormal information based on the associated abnormal structure; Screening a third abnormal structure and its corresponding abnormal information based on the temperature abnormal structure; The first abnormal structure, the second abnormal structure and the third abnormal structure are integrated to generate a target abnormal structure and its corresponding abnormal information, and generate a defect detection result; the abnormal information includes the abnormal cause, the target field period, the abnormal structure location point and the target abnormal state.

9. A chip defect detection device, characterized in that: include: Abnormal state monitoring module, abnormal temperature monitoring module and prediction module; The state abnormality monitoring module is used to obtain the state distribution information of the chip based on the operation data of the chip, and obtain the abnormal operation state, abnormal operation program and associated abnormal structure of the chip based on the state distribution information; The temperature anomaly monitoring module is used to construct a three-dimensional temperature distribution map of the chip based on the temperature data of the chip, and determine the temperature anomaly structure based on the three-dimensional temperature distribution map; The prediction module is used to predict the target abnormal structure and abnormal information of the chip based on the associated abnormal structure and the temperature abnormal structure, and generate a defect detection result.

10. A terminal device, characterized in that: The invention comprises a processor, a memory and a computer program stored in the memory and configured to be executed by the processor, and when the processor executes the computer program, a chip defect detection method as claimed in any one of claims 1 to 8 is implemented.

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