A semiconductor chip testing method, device, equipment and medium

Abstract

The present invention discloses a semiconductor chip testing method, device, equipment and medium, and relates to the field of electronic digital data processing technology. First, the test process of the semiconductor chip is divided into a memory test phase and a performance test phase, which can more accurately evaluate the memory capacity and performance characteristics of the semiconductor chip. Then, the memory test phase of the semiconductor chip is analyzed to obtain the memory quality characterization value of each semiconductor chip, which helps to more accurately evaluate the stability and reliability of the semiconductor chip memory, and can help manufacturers and suppliers to perform quality control during the production process. Subsequently, the performance test phase of the semiconductor chip is analyzed to obtain the performance characterization value of each semiconductor chip, which can provide data support for the performance design of the semiconductor chip. Finally, each semiconductor chip is marked according to the quality index value of each semiconductor chip, which can perform more accurate resource allocation and avoid resource waste of semiconductor chips.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic digital data processing, and in particular to a method, device, equipment and medium for testing a semiconductor chip. Background Art

[0002] With the development of electronic technology, the application of semiconductor chips in today's society has become ubiquitous, covering many key fields such as communications and industrial control. As the core component in these fields, the quality requirements of semiconductor chips are becoming increasingly stringent. In order to ensure that the stability, reliability and performance of semiconductor chips meet the requirements, semiconductor chip testing technology has become particularly critical.

[0003] Prior art, such as a semiconductor chip testing method, device and system disclosed in the patent application with the publication number CN111078459B. The semiconductor chip testing method includes: generating target test data; writing the target test data into the target address of the semiconductor chip; reading the target storage data of the target address; judging whether an error occurs at the target address and the number of bits where the error occurs according to the target test data and the target storage data; if an error occurs at the target address and the number of bits where the error occurs exceeds a first preset bit, judging that the target test item test of the target address fails; wherein the first preset bit is a positive integer greater than or equal to 1; the semiconductor chip or the controller of the semiconductor chip includes an error correction circuit, and the error correction circuit is used to correct the error bit of the first preset bit of the target address of the semiconductor chip.

[0004] Prior art, such as a semiconductor chip test data storage method, device and electronic device disclosed in a patent application with publication number: CN117608484A, wherein the semiconductor chip test data storage method comprises sorting the target test items of the target chip by rows according to preset test steps, and determining the data file row information corresponding to the target test items; sorting the target test items by columns according to preset test item basic information, preset test step information and preset test item condition output information, and determining the data file column information under the target test items; and determining the target chip in each different target data storage table based on the data file row information, the data file column information and the target test data.

[0005] In combination with the above scheme, it is found that currently in the field of semiconductor chip testing technology, only test data is usually analyzed, and the testing of semiconductor chips is not comprehensive. The speed and accuracy of semiconductor chip testing are not high, and the quality control of semiconductor chip products cannot be enhanced, which will affect the utilization rate of semiconductor chip products. Summary of the invention

[0006] In view of the deficiencies in the prior art, the present invention provides a method, device, equipment and medium for testing a semiconductor chip, which can effectively solve the problems involved in the above-mentioned background technology.

[0007] To achieve the above objectives, the present invention is implemented through the following technical solutions: A semiconductor chip testing method, including S1, dividing the semiconductor chip testing process into a semiconductor chip memory testing phase and a semiconductor chip performance testing phase.

[0008] S2. Detect the memory test phase of the semiconductor chip and analyze and obtain the memory quality characterization value of each semiconductor chip.

[0009] S3. Monitor and analyze the performance test phase of the semiconductor chips to obtain performance characterization values ​​of each semiconductor chip.

[0010] S4. Determine the first test result of each semiconductor chip according to the memory quality characterization value of each semiconductor chip and the performance characterization value of each semiconductor chip. If the first test result is a defective product, mark it directly. If the first test result is not a defective product, execute step S5.

[0011] S5. Analyze the memory quality characterization value of each non-defective semiconductor chip and the performance characterization value of each non-defective semiconductor chip to obtain the quality index value of each non-defective semiconductor chip, and mark each non-defective semiconductor chip according to the quality index value of each non-defective semiconductor chip.

[0012] Furthermore, the memory test phase of the semiconductor chip is detected and analyzed to obtain the memory quality characterization value of each semiconductor chip. The specific process is: arranging a monitoring cycle, setting a number of monitoring time periods in the monitoring cycle, monitoring and counting the number of memory refreshes of each semiconductor chip in each monitoring time period, and extracting the length of the monitoring time period to obtain the memory refresh rate of each semiconductor chip in each monitoring time period.

[0013] In each monitoring time period, the power on and off test is repeatedly performed on each semiconductor chip, the memory data retention time of each semiconductor chip after each power disconnection is monitored, the number of power disconnections is counted, and the average memory data retention time of each semiconductor chip in each monitoring time period is analyzed.

[0014] The number of times the memory data of each semiconductor chip is disturbed in each monitoring time period is monitored, the total number of times the read data is disturbed is counted, and the number of times the memory data of each semiconductor chip is disturbed in each monitoring time period is divided by the total number of times the read data is disturbed to obtain the read interference frequency of each semiconductor chip in each monitoring time period.

[0015] The memory quality index value of each semiconductor chip is obtained according to the memory refresh rate of each semiconductor chip in each monitoring time period, the average memory data retention time of each semiconductor chip in each monitoring time period and the read interference frequency of each semiconductor chip in each monitoring time period.

[0016] According to the memory quality index value of each semiconductor chip, the number of consecutive successful power-on, power-off and restart of each semiconductor chip is counted, and the memory quality characterization value of each semiconductor chip is obtained through comprehensive analysis.

[0017] Furthermore, the memory test phase of the semiconductor chip is detected and analyzed to obtain the memory quality characterization value of each semiconductor chip. The specific analysis process is: during the monitoring period, the time from sending instructions to reading and writing instructions of each semiconductor chip at each temperature is counted, and the response time of each semiconductor chip at each temperature is analyzed.

[0018] According to the response time of each semiconductor chip at each temperature, the power consumption of each semiconductor chip under each load and the data transmission rate of each semiconductor chip under each load are counted, and the performance characterization value of each semiconductor chip is obtained through comprehensive analysis.

[0019] Furthermore, the first test result of each semiconductor chip is judged according to the memory quality characterization value of each semiconductor chip and the performance characterization value of each semiconductor chip. The specific process is: if the memory quality characterization value of a semiconductor chip is lower than the set memory quality characterization threshold of the semiconductor chip, the semiconductor chip is marked as a defective product; if the memory quality characterization value of a semiconductor chip is higher than or equal to the set memory quality characterization threshold of the semiconductor chip, the semiconductor chip is marked as a non-defective product.

[0020] If the performance characterization value of a semiconductor chip is lower than the set performance characterization threshold of the semiconductor chip, the semiconductor chip is marked as a defective product. If the performance characterization value of a semiconductor chip is higher than or equal to the set performance characterization threshold of the semiconductor chip, the semiconductor chip is marked as a non-defective product.

[0021] Furthermore, the non-defective semiconductor chips are labeled according to their quality index values, and the specific process is: based on the memory quality characterization value of each non-defective semiconductor chip and the performance characterization value of each non-defective semiconductor chip, a comprehensive analysis is performed to obtain the quality index value of each non-defective semiconductor chip.

[0022] The quality index value of each non-defective semiconductor chip is a numerical quantification result obtained by performing data analysis on the memory quality and performance of the non-defective semiconductor chip, and is used to quantify the influence of different factors on the quality of the semiconductor chip.

[0023] If the quality index value of a non-defective semiconductor chip is lower than or equal to the set standard quality index threshold of the semiconductor chip, the non-defective semiconductor chip is marked as an original semiconductor chip.

[0024] If the quality index value of a non-defective semiconductor chip is higher than the set standard quality index threshold of the semiconductor chip, and the quality index value of the non-defective semiconductor chip is lower than or equal to the set superior quality index threshold of the semiconductor chip, then the non-defective semiconductor chip is marked as a standard semiconductor chip.

[0025] If the quality index value of a non-defective semiconductor chip is higher than the set excellent quality index threshold of the semiconductor chip, and the quality index value of the non-defective semiconductor chip is lower than or equal to the set aging quality index threshold of the semiconductor chip, then the non-defective semiconductor chip is marked as a superior semiconductor chip.

[0026] If the quality index value of a non-defective semiconductor chip is higher than the set semiconductor chip burn-in quality index threshold, the non-defective semiconductor chip is marked as a burn-in semiconductor chip.

[0027] Furthermore, the memory quality characterization value of each semiconductor chip is specifically analyzed under the following conditions:

[0028] ;

[0029] In the formula, Indicates The memory quality characterization value of a semiconductor chip, Indicates The memory quality index value of a semiconductor chip, Indicates the impact factor corresponding to the set memory quality index value. Indicates The number of consecutive successful power-on and power-off restarts of a semiconductor chip, Indicates the impact factor corresponding to the set number of consecutive successful power-on / off restarts. Indicates the number of each semiconductor chip, , Indicates the total number of semiconductor chips.

[0030] Furthermore, the quality index values ​​of the non-defective semiconductor chips are specifically analyzed under the following conditions:

[0031] ; In the formula, Indicates The quality index value of a non-defective semiconductor chip, Indicates The memory quality characterization value of a non-defective semiconductor chip, Indicates the weight factor corresponding to the set memory quality characterization value. Indicates The performance characterization value of a non-defective semiconductor chip, Indicates the weight factor corresponding to the set performance characterization value, Indicates the number of each non-defective semiconductor chip, q, q represents the total number of non-defective semiconductor chips.

[0032] The second aspect of the present invention provides a semiconductor chip testing device, comprising: a processor, and a memory and a network interface connected to the processor: the network interface is connected to a non-volatile memory in a server: the processor calls a computer program from the non-volatile memory through the network interface during operation, and runs the computer program through the memory to execute the above-mentioned semiconductor chip testing method.

[0033] A third aspect of the present invention provides a semiconductor chip testing device, comprising: a process division module, used to divide the test process of the semiconductor chip into a memory test phase of the semiconductor chip and a performance test phase of the semiconductor chip.

[0034] The memory test module is used to detect the memory test phase of the semiconductor chip and analyze and obtain the memory quality characterization value of each semiconductor chip.

[0035] The performance testing module is used to monitor and analyze the performance testing phase of semiconductor chips to obtain the performance characterization value of each semiconductor chip.

[0036] The preliminary screening and marking module is used to determine the first test result of each semiconductor chip according to the memory quality characterization value of each semiconductor chip and the performance characterization value of each semiconductor chip.

[0037] The quality index value analysis and labeling module is used to obtain the quality index value of each non-defective semiconductor chip based on the memory quality characterization value of each non-defective semiconductor chip and the performance characterization value of each non-defective semiconductor chip, and label each non-defective semiconductor chip according to the quality index value of each non-defective semiconductor chip.

[0038] A fourth aspect of the present invention provides a semiconductor chip test medium having a computer program stored thereon, and further comprising: when the computer program is executed by a processor, the above-mentioned semiconductor chip test method is implemented.

[0039] The present invention has the following beneficial effects:

[0040] (1) The present invention provides a semiconductor chip testing method. First, the semiconductor chip testing process is divided into a memory testing stage and a performance testing stage. The memory testing stage is monitored and analyzed to obtain a memory quality characterization value of each semiconductor chip, which can more accurately evaluate the quality of the semiconductor chip. At the same time, the performance testing stage is monitored and analyzed to obtain a performance characterization value of each semiconductor chip, which provides clear data support for subsequent semiconductor chip analysis. Finally, the semiconductor chips are labeled to improve the accuracy and credibility of the semiconductor chip test results.

[0041] (2) The present invention obtains the memory quality characterization value of each semiconductor chip through analysis, which can measure the anti-interference ability of the semiconductor chip in different environments, help to quickly identify potential quality problems of the single-chip microcomputer chip, and can help manufacturers optimize the design and production process of the single-chip microcomputer chip, providing data support for the optimization of the production process.

[0042] (3) The present invention obtains the performance characterization value of each semiconductor chip by analysis, and can analyze the performance of the semiconductor chip under different loads and temperatures, and then analyze the improvement points of energy efficiency management, which helps to reduce the energy consumption of the single-chip microcomputer chip, evaluate the stability of the semiconductor chip under different conditions, and improve the accuracy of the test results of the semiconductor chip under different loads and temperatures.

[0043] (4) The present invention labels semiconductor chips according to the quality index values ​​of non-defective semiconductor chips, thereby improving the accuracy of semiconductor chip test results and classifying semiconductor chips into different grades. The classification of different grades has clear quantitative standards, which helps to evaluate the consistency and fairness of semiconductor chips. By accurately evaluating and classifying the quality of semiconductor chips, the waste of low-quality products and resource consumption caused by inaccurate quality evaluation can be reduced.

[0044] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It is a schematic diagram of the method flow of the present invention.

[0046] Figure 2 It is a schematic diagram of the connection of the equipment modules of the present invention.

[0047] Figure 3 Example images of quality indicator values ​​for semiconductor chips. DETAILED DESCRIPTION

[0048] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] See also Figure 1 As shown, a first aspect of an embodiment of the present invention provides a technical solution: a method for testing a semiconductor chip, comprising S1, dividing the test process of the semiconductor chip into a memory test phase of the semiconductor chip and a performance test phase of the semiconductor chip.

[0050] S2. Detect the memory test phase of the semiconductor chip and analyze and obtain the memory quality characterization value of each semiconductor chip.

[0051] S3. Monitor and analyze the performance test phase of the semiconductor chips to obtain performance characterization values ​​of each semiconductor chip.

[0052] S4. Determine the first test result of each semiconductor chip according to the memory quality characterization value of each semiconductor chip and the performance characterization value of each semiconductor chip. If the first test result is a defective product, mark it directly. If the first test result is not a defective product, execute step S5.

[0053] S5. Analyze the memory quality characterization value of each non-defective semiconductor chip and the performance characterization value of each non-defective semiconductor chip to obtain the quality index value of each non-defective semiconductor chip, and mark each non-defective semiconductor chip according to the quality index value of each non-defective semiconductor chip.

[0054] Specifically, the memory test phase of the semiconductor chip is detected and analyzed to obtain the memory quality characterization value of each semiconductor chip. The specific process is: arrange a monitoring cycle, set a number of monitoring time periods in the monitoring cycle, monitor and count the number of memory refresh times of each semiconductor chip in each monitoring time period, and extract the duration of the monitoring time period to obtain the memory refresh rate of each semiconductor chip in each monitoring time period.

[0055] In this embodiment, the memory refresh rate of each semiconductor chip in each monitoring time period is obtained using the following analysis conditions, specifically:

[0056] ;

[0057] In the formula, represents the memory refresh rate of the i-th semiconductor chip in the j-th monitoring time period, represents the number of memory refreshes of the i-th semiconductor chip in the j-th monitoring time period, Indicates the duration of the monitoring period. Indicates the number of each semiconductor chip, , represents the total number of semiconductor chips, j represents the number of each monitoring time period, , Indicates the total number of monitoring time periods.

[0058] It should be explained that the number of memory refreshes of each semiconductor chip in each monitoring time period refers to the number of refresh operations performed by the memory module due to the need for regular refreshes, which is usually obtained through AIDA64 software monitoring.

[0059] It should be noted that the duration of each monitoring time period is the same.

[0060] In this implementation, analyzing the memory refresh rate of each semiconductor chip in each monitoring time period helps to evaluate the ability of each semiconductor chip to maintain stability during long-term operation. A high memory refresh rate of each semiconductor chip may indicate that the semiconductor chip has a performance bottleneck and needs further optimization.

[0061] In each monitoring time period, the power on and off test is repeatedly performed on each semiconductor chip, the memory data retention time of each semiconductor chip after each power disconnection is monitored, the number of power disconnections is counted, and the average memory data retention time of each semiconductor chip in each monitoring time period is analyzed.

[0062] In this embodiment, the average memory data storage time of each semiconductor chip in each monitoring time period is obtained using the following analysis conditions, specifically:

[0063] ;

[0064] In the formula, represents the average memory data retention time of the i-th semiconductor chip in the j-th monitoring time period, It indicates the storage time of the memory data of each semiconductor chip after the i-th semiconductor chip is disconnected from the power supply for the kth time in the j-th monitoring time period, k indicates the number of times the power supply is disconnected, , represents the total number of power disconnections, j represents the number of each monitoring time period, , Indicates the total number of monitoring time periods.

[0065] It should be explained that the memory data retention time of each semiconductor chip after each power disconnection in each monitoring time period refers to the time during which the data in the memory of the semiconductor chip can remain unchanged after the power disconnection event occurs, which can be obtained through the system log.

[0066] In this implementation, analyzing the average memory data retention time of each semiconductor chip in each monitoring time period helps to evaluate the semiconductor chip's ability to protect memory data in the event of power outages or unexpected power outages, which can help system designers choose more suitable chips. By comparing the average memory data retention time of different semiconductor chips, potential performance differences between semiconductor chips can be identified.

[0067] The number of times the memory data of each semiconductor chip is disturbed in each monitoring time period is monitored, the total number of times the read data is disturbed is counted, and the number of times the memory data of each semiconductor chip is disturbed in each monitoring time period is divided by the total number of times the read data is disturbed to obtain the read interference frequency of each semiconductor chip in each monitoring time period.

[0068] It should be noted that the read interference frequency of each semiconductor chip in each monitoring time period refers to the frequency of interference when reading data, which can be measured by a signal analyzer.

[0069] The memory quality index value of each semiconductor chip is obtained according to the memory refresh rate of each semiconductor chip in each monitoring time period, the average memory data retention time of each semiconductor chip in each monitoring time period and the read interference frequency of each semiconductor chip in each monitoring time period.

[0070] It should be noted that the memory quality index value of each semiconductor chip represents a numerical quantification result obtained by analyzing the memory quality and data of the semiconductor chip, and serves as an analysis basis for the memory quality characterization value of each semiconductor chip. It can be obtained by the following analysis method, and the specific analysis conditions are as follows:

[0071] ;

[0072] In the formula, Indicates The memory quality index value of a semiconductor chip, represents the memory refresh rate of the i-th semiconductor chip in the j-th monitoring time period, Indicates the set reference memory refresh rate. Indicates the impact factor corresponding to the set memory refresh rate. represents the average memory data retention time of the i-th semiconductor chip in the j-th monitoring time period, Indicates the set reference average memory data storage time. Indicates the impact factor corresponding to the set average memory data storage time. represents the read disturbance frequency of the i-th semiconductor chip in the j-th monitoring time period, Indicates the reference read interference frequency set, Indicates the impact factor corresponding to the set read interference frequency, Indicates the number of each semiconductor chip, , represents the total number of semiconductor chips, j represents the number of each monitoring time period, , Indicates the total number of monitoring time periods.

[0073] It should be noted that, in this embodiment, the impact factor corresponding to the preset memory refresh rate, the impact factor corresponding to the average memory data retention time, and the impact factor corresponding to the read interference frequency are obtained from the semiconductor chip test database.

[0074] In a specific embodiment, historical data is used to fit the relationship between the memory refresh rate, average memory data retention time, read interference frequency and memory quality index value of each semiconductor chip in each monitoring time period to obtain a fitting curve, and the influencing factor corresponding to the memory refresh rate, the influencing factor corresponding to the average memory data retention time and the influencing factor corresponding to the read interference frequency are determined according to the fitting curve, and the memory refresh rate, average memory data retention time and read interference frequency of each semiconductor chip in each real-time monitoring time period are substituted into the fitting curve to obtain the corresponding influencing factor.

[0075] It should be noted that the impact factor corresponding to the memory refresh rate, the impact factor corresponding to the average memory data retention time, and the impact factor corresponding to the read interference frequency are all numbers between 0 and 1.

[0076] It should be explained that in this embodiment, the memory refresh rate of each semiconductor chip in each monitoring time period, the average memory data retention time of each semiconductor chip in each monitoring time period, and the read interference frequency of each semiconductor chip in each monitoring time period are analyzed, so that the memory quality of the semiconductor chip can be effectively evaluated. The analysis method of this embodiment, by combining the memory refresh rate, average memory data retention time and read interference frequency of each semiconductor chip in each monitoring time period for analysis, can comprehensively understand the performance of the chip under different conditions. Chips with low memory refresh rate and long average memory data retention time may have higher stability and data protection capabilities, while low read interference frequency can improve the reliability of data access.

[0077] In this implementation, analyzing the read interference frequency of each semiconductor chip in each monitoring time period can evaluate the performance of the chip under different working environments and usage conditions. The memory quality index value of each semiconductor chip obtained by analysis can reflect the efficiency and stability of the semiconductor chip in storing and accessing data, which helps to evaluate the reliability of the semiconductor chip and provide reliable opinions for semiconductor chip optimization.

[0078] According to the memory quality index value of each semiconductor chip, the number of consecutive successful power-on, power-off and restart of each semiconductor chip is counted, and the memory quality characterization value of each semiconductor chip is obtained through comprehensive analysis.

[0079] Specifically, the memory test phase of the semiconductor chip is detected and analyzed to obtain the memory quality characterization value of each semiconductor chip. The specific analysis process is: during the monitoring period, the time from sending instructions to reading and writing instructions of each semiconductor chip at each temperature is counted, and the response time of each semiconductor chip at each temperature is analyzed.

[0080] According to the response time of each semiconductor chip at each temperature, the power consumption of each semiconductor chip under each load and the data transmission rate of each semiconductor chip under each load are counted, and the performance characterization value of each semiconductor chip is obtained through comprehensive analysis.

[0081] It should be noted that the performance characterization value of each semiconductor chip represents a numerical quantification result obtained by analyzing the performance of the semiconductor chip, and can be obtained by the following analysis method. The specific analysis conditions are as follows:

[0082] ;

[0083] In the formula, represents the performance characterization value of the i-th semiconductor chip, represents the response time of the i-th semiconductor chip at the x-th temperature, Indicates the set reference response time. Indicates the weight factor corresponding to the set response time. Indicates The power consumption of the i-th semiconductor chip under load, Indicates the set reference power consumption. Indicates the weight factor corresponding to the set power consumption, Indicates The data transmission rate of the i-th semiconductor chip under load, Indicates the reference data transmission rate set. Indicates the weight factor corresponding to the set data transmission rate, Indicates the number of each semiconductor chip, , Represents the total number of semiconductor chips, Indicates the number of each temperature condition, , represents the total number of temperature conditions, Indicates the number of each load condition, , represents the total number of load conditions, Represents a natural constant.

[0084] It needs to be explained that the response time of each semiconductor chip at each temperature is obtained by setting different temperature conditions. At each temperature, instructions are sent to the semiconductor chip, and the sending time of the instructions and the completion time of the read and write instructions are recorded by a timer. The difference between the completion time of the read and write instructions and the sending time of the instructions is calculated to obtain the response time of each semiconductor chip at each temperature.

[0085] It should be explained that the power consumption of each semiconductor chip under each load is the amount of power consumed by the semiconductor chip per unit time under different loads, which can be measured by professional power consumption measurement equipment.

[0086] It needs to be explained that the data transmission rate of each semiconductor chip under each load indicates the speed at which the semiconductor chip processes data under different loads, and is usually measured in terms of the amount of data transmitted per second. Data transmission tasks are set for each semiconductor chip under different loads. Under each load, the data transmission task is performed and the time required for the transmission is recorded, while the amount of data transmitted is also recorded. The data transmission rate of each semiconductor chip under each load is obtained by dividing the amount of data transmitted by the time required for the transmission.

[0087] It should be noted that, in this embodiment, a weight factor corresponding to a preset response time, a weight factor corresponding to a power consumption, and a weight factor corresponding to a data transmission rate are obtained from a semiconductor chip test database.

[0088] In a specific embodiment, historical data is used to fit the relationship between the response time of each semiconductor chip at each temperature, the power consumption of each semiconductor chip under each load, the data transmission rate of each semiconductor chip under each load, and the performance characterization value of each semiconductor chip to obtain a fitting curve, and the weight factor corresponding to the response time, the weight factor corresponding to the power consumption, and the weight factor corresponding to the data transmission rate are determined according to the fitting curve, and the real-time response time of each semiconductor chip at each temperature, the power consumption of each semiconductor chip under each load, and the data transmission rate of each semiconductor chip under each load are substituted into the fitting curve to obtain the corresponding weight factors.

[0089] It should be noted that the weight factor corresponding to the response duration, the weight factor corresponding to the power consumption, and the weight factor corresponding to the data transmission rate are all numbers between 0 and 1.

[0090] It should be explained that in this embodiment, the response time of each semiconductor chip at each temperature, the power consumption of each semiconductor chip under each load, and the data transmission rate of each semiconductor chip under each load are helpful for evaluating the performance of semiconductor chips under different temperature conditions and loads. The analysis method of this embodiment, by combining the response time of each semiconductor chip at each temperature, the power consumption of each semiconductor chip under each load, and the data transmission rate of each semiconductor chip under each load for analysis, can provide data support for optimizing the design and performance of semiconductor chips.

[0091] In this embodiment, analyzing the response time of each semiconductor chip at each temperature helps to evaluate the processing speed and responsiveness of the semiconductor chip under various working environments, thereby helping to optimize the design of the semiconductor chip to meet the requirements of specific applications. Analyzing the power consumption of each semiconductor chip under each load helps to understand the energy efficiency performance of the semiconductor chip under high load, which is crucial for optimizing the energy saving and thermal management of the semiconductor chip. Analyzing the data transmission rate of each semiconductor chip under each load helps to quantify the efficiency of the chip in data processing and transmission. Analyzing the performance characterization values ​​of each semiconductor chip helps to optimize the design of the semiconductor chip and can discover potential thermal management or power consumption problems of the semiconductor chip.

[0092] Specifically, the first test result of each semiconductor chip is judged according to the memory quality characterization value of each semiconductor chip and the performance characterization value of each semiconductor chip. The specific process is: if the memory quality characterization value of a semiconductor chip is lower than the set memory quality characterization threshold of the semiconductor chip, the semiconductor chip is marked as a defective product; if the memory quality characterization value of a semiconductor chip is higher than or equal to the set memory quality characterization threshold of the semiconductor chip, the semiconductor chip is marked as a non-defective product.

[0093] If the performance characterization value of a semiconductor chip is lower than the set performance characterization threshold of the semiconductor chip, the semiconductor chip is marked as a defective product. If the performance characterization value of a semiconductor chip is higher than or equal to the set performance characterization threshold of the semiconductor chip, the semiconductor chip is marked as a non-defective product.

[0094] Specifically, each non-defective semiconductor chip is marked according to its quality index value. The specific process is: based on the memory quality characterization value of each non-defective semiconductor chip and the performance characterization value of each non-defective semiconductor chip, a comprehensive analysis is performed to obtain the quality index value of each non-defective semiconductor chip.

[0095] The quality index value of each non-defective semiconductor chip is a numerical quantification result obtained by performing data analysis on the memory quality and performance of the non-defective semiconductor chip, and is used to quantify the influence of different factors on the quality of the semiconductor chip.

[0096] If the quality index value of a non-defective semiconductor chip is lower than or equal to the set standard quality index threshold of the semiconductor chip, the non-defective semiconductor chip is marked as an original semiconductor chip.

[0097] If the quality index value of a non-defective semiconductor chip is higher than the set standard quality index threshold of the semiconductor chip, and the quality index value of the non-defective semiconductor chip is lower than or equal to the set superior quality index threshold of the semiconductor chip, then the non-defective semiconductor chip is marked as a standard semiconductor chip.

[0098] If the quality index value of a non-defective semiconductor chip is higher than the set excellent quality index threshold of the semiconductor chip, and the quality index value of the non-defective semiconductor chip is lower than or equal to the set aging quality index threshold of the semiconductor chip, then the non-defective semiconductor chip is marked as a superior semiconductor chip.

[0099] If the quality index value of a non-defective semiconductor chip is higher than the set semiconductor chip burn-in quality index threshold, the non-defective semiconductor chip is marked as a burn-in semiconductor chip.

[0100] Specifically, the memory quality characterization value of each semiconductor chip, the specific analysis conditions are:

[0101] ;

[0102] In the formula, Indicates The memory quality characterization value of a semiconductor chip, Indicates The memory quality index value of a semiconductor chip, Indicates the impact factor corresponding to the set memory quality index value. Indicates The number of consecutive successful power-on and power-off restarts of a semiconductor chip, Indicates the impact factor corresponding to the set number of consecutive successful power-on / off restarts. Indicates the number of each semiconductor chip, , Indicates the total number of semiconductor chips.

[0103] In a specific embodiment, Table 1 shows the memory quality index values ​​of different semiconductor chips and the memory quality characterization values ​​corresponding to the number of consecutive successful power on and off and restart. The impact factors corresponding to the memory quality index values ​​and the impact factors corresponding to the number of consecutive successful power on and off and restart are both numbers between 0 and 1. In this embodiment, the impact factor corresponding to the memory quality index value is 0.4, and the impact factor corresponding to the number of consecutive successful power on and off and restart is 0.6.

[0104] Table 1 Memory quality index values ​​of different semiconductor chips and the memory quality characterization values ​​corresponding to the number of consecutive successful power-on, power-off and restart

[0105]

[0106] It should be explained that in Table 1, as the memory quality index value and the number of consecutive successful power-on and power-off restarts of the semiconductor chip increase, the memory quality characterization value of the semiconductor chip gradually increases. The memory quality characterization value of the semiconductor chip in Table 1 is analyzed by combining the memory quality index value and the number of consecutive successful power-on and power-off restarts. The memory quality index values ​​and the number of consecutive successful power-on and power-off restarts of 3 different semiconductor chips are listed, and the memory quality characterization value of each semiconductor chip is obtained by the formula. The values ​​of these memory quality characterization values ​​provide the influence of different memory quality index values ​​and the number of consecutive successful power-on and power-off restarts on the memory quality characterization value. The memory quality characterization value comprehensively considers the memory quality index value and the number of consecutive successful power-on and power-off restarts, and provides data support for the test results of the semiconductor chip, thereby improving the accuracy and reliability of the semiconductor chip test.

[0107] It should be noted that the number of consecutive successful power-on, power-off and restart of each semiconductor chip refers to the number of consecutive successful power-on and restarts of the semiconductor chip memory after repeated power-on and power-off, which can be measured by an automated testing tool.

[0108] It should be noted that, in this embodiment, the impact factor corresponding to the preset memory quality index value and the impact factor corresponding to the number of consecutive successful power-on, power-off and restart are obtained from the semiconductor chip test database.

[0109] In a specific embodiment, through historical data, the relationship between the memory quality index value of each semiconductor chip, the number of consecutive successful power-on, power-off and restart of each semiconductor chip, and the memory quality characterization value of each semiconductor chip is fitted to obtain a fitting curve, and the influencing factor corresponding to the memory quality index value and the influencing factor corresponding to the number of consecutive successful power-on, power-off and restart of each semiconductor chip are determined according to the fitting curve, and the real-time memory quality index value of each semiconductor chip and the number of consecutive successful power-on, power-off and restart of each semiconductor chip are substituted into the fitting curve to obtain the corresponding influencing factor.

[0110] It should be explained that in this embodiment, the analysis of the memory quality index value of each semiconductor chip and the number of consecutive successful power-on, power-off and restart of each semiconductor chip helps to evaluate the stability of the semiconductor chip. According to the analysis method of this embodiment, the memory quality index value of the semiconductor chip and the number of consecutive successful power-on, power-off and restart of the semiconductor chip jointly affect the memory quality index value of the semiconductor chip.

[0111] In this implementation scheme, analyzing the memory quality index value of each semiconductor chip is helpful for analyzing the memory stability and data retention capability of the semiconductor chip under different working conditions. Analyzing the number of consecutive successful power-on, power-off and restart of each semiconductor chip can evaluate the performance of the semiconductor chip in power management. Analyzing the memory quality characterization value of each semiconductor chip helps to timely discover and resolve potential problems, thereby reducing unnecessary costs caused by product quality problems and improving semiconductor chip production efficiency.

[0112] Specifically, the quality index values ​​of each non-defective semiconductor chip are analyzed under the following specific conditions:

[0113] ;

[0114] In the formula, Indicates The quality index value of a non-defective semiconductor chip, Indicates The memory quality characterization value of a non-defective semiconductor chip, Indicates the weight factor corresponding to the set memory quality characterization value. Indicates The performance characterization value of a non-defective semiconductor chip, Indicates the weight factor corresponding to the set performance characterization value, Indicates the number of each non-defective semiconductor chip, , Represents the total number of non-defective semiconductor chips.

[0115] It needs to be explained that Figure 3 As shown, Figure 3is an example image of the quality index value of a semiconductor chip, wherein the x-axis represents the performance characterization value of the semiconductor chip, and the y-axis represents the quality index value of the semiconductor chip. In this embodiment, the weight factor corresponding to the memory quality characterization value is 0.4, and the weight factor corresponding to the performance characterization value is 0.6. Three different groups of example parameters are defined in the figure, corresponding to different situations of the three curves, respectively represented by solid lines, dashed lines and dotted lines, and the corresponding curve labels are a, b, and c, respectively. When the memory quality characterization value of a non-defective semiconductor chip is 5, the functional relationship image between the performance characterization value of the non-defective semiconductor chip and the quality index value of the non-defective semiconductor chip is shown as curve a. When the memory quality characterization value of a non-defective semiconductor chip is 7, the performance characterization value of the non-defective semiconductor chip is 8. The functional relationship between the performance characterization value and the quality index value of the non-defective semiconductor chip is shown in curve b. When the memory quality characterization value of a non-defective semiconductor chip is 9, the functional relationship between the performance characterization value of the non-defective semiconductor chip and the quality index value of the non-defective semiconductor chip is shown in curve c. The quality index value of the non-defective semiconductor chip increases with the increase of the performance characterization value of the non-defective semiconductor chip, and when the memory quality characterization value of the non-defective semiconductor chip increases, the quality index value of the non-defective semiconductor chip increases accordingly. The quality index value of the non-defective semiconductor chip can be quickly and accurately obtained through the curve, which solves the problem of inaccurate quality assessment of semiconductor chips in the prior art and can reduce the inaccuracy of semiconductor chip testing.

[0116] It should be noted that, in this embodiment, the weight factors corresponding to the preset memory quality characterization values ​​and the weight factors corresponding to the performance characterization values ​​are obtained from the semiconductor chip test database.

[0117] In a specific embodiment, through historical data, the relationship between the memory quality characterization value of each non-defective semiconductor chip, the performance characterization value of each non-defective semiconductor chip and the quality index value of each non-defective semiconductor chip is fitted to obtain a fitting curve, and the weight factor corresponding to the memory quality characterization value and the weight factor corresponding to the performance characterization value are determined according to the fitting curve, and the real-time memory quality characterization value of each non-defective semiconductor chip and the performance characterization value of each non-defective semiconductor chip are substituted into the fitting curve to obtain the corresponding weight factor.

[0118] It should be noted that the weight factor corresponding to the memory quality characterization value and the weight factor corresponding to the performance characterization value are both numbers between 0 and 1.

[0119] It should be explained that the analysis of the memory quality characterization value of each non-defective semiconductor chip and the performance characterization value of each non-defective semiconductor chip in this embodiment helps to improve the accuracy of the semiconductor chip test results. The analysis method of this embodiment, the memory quality characterization value of each non-defective semiconductor chip and the performance characterization value of each non-defective semiconductor chip jointly affect the screening and labeling of semiconductor chips.

[0120] In this embodiment, analyzing the memory quality characterization value of each non-defective semiconductor chip helps to evaluate the stability and reliability of the chip in storing and processing data, analyzing the performance characterization value of each non-defective semiconductor chip helps to evaluate the performance of the semiconductor chip under different conditions, and analyzing the quality index value of each non-defective semiconductor chip can understand the manufacturing quality and durability of the semiconductor chip.

[0121] The second aspect of the present invention provides a semiconductor chip testing device, comprising: a processor, and a memory and a network interface connected to the processor: the network interface is connected to a non-volatile memory in a server: the processor calls a computer program from the non-volatile memory through the network interface during operation, and runs the computer program through the memory to execute the above-mentioned semiconductor chip testing method.

[0122] A third aspect of the present invention provides a semiconductor chip testing device, comprising: a process division module, used to divide the test process of the semiconductor chip into a memory test phase of the semiconductor chip and a performance test phase of the semiconductor chip.

[0123] The memory test module is used to detect the memory test phase of the semiconductor chip and analyze and obtain the memory quality characterization value of each semiconductor chip.

[0124] The performance testing module is used to monitor and analyze the performance testing phase of semiconductor chips to obtain the performance characterization value of each semiconductor chip.

[0125] The preliminary screening and marking module is used to determine the first test result of each semiconductor chip according to the memory quality characterization value of each semiconductor chip and the performance characterization value of each semiconductor chip.

[0126] The quality index value analysis and labeling module is used to obtain the quality index value of each non-defective semiconductor chip based on the memory quality characterization value of each non-defective semiconductor chip and the performance characterization value of each non-defective semiconductor chip, and label each non-defective semiconductor chip according to the quality index value of each non-defective semiconductor chip.

[0127] A fourth aspect of the present invention provides a semiconductor chip test medium having a computer program stored thereon, and further comprising: when the computer program is executed by a processor, the above-mentioned semiconductor chip test method is implemented.

[0128] It should be noted that a semiconductor chip testing method, device, equipment and medium also include a semiconductor chip testing database, which is used to store a reference memory refresh rate, a reference average memory data retention time, a reference read interference frequency, an impact factor corresponding to the memory refresh rate, an impact factor corresponding to the average memory data retention time, an impact factor corresponding to the read interference frequency, a reference response time, a reference power consumption, a reference data transmission rate, a weight factor corresponding to the response time, a weight factor corresponding to the power consumption, a weight factor corresponding to the data transmission rate, a memory quality characterization threshold of a semiconductor chip, a performance characterization threshold of a semiconductor chip, a standard quality index threshold of a semiconductor chip, a superior quality index threshold of a semiconductor chip, an aging quality index threshold of a semiconductor chip, an impact factor corresponding to the memory quality index value, an impact factor corresponding to the number of consecutive successful power-on and power-off restarts, a weight factor corresponding to the memory quality characterization value, and a weight factor corresponding to the performance characterization value.

[0129] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0130] The preferred embodiments of the present invention disclosed above are only used to help illustrate the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for testing a semiconductor chip, characterized in that: include: S1. Divide the test process of the semiconductor chip into a memory test phase of the semiconductor chip and a performance test phase of the semiconductor chip; S2, testing the memory test phase of the semiconductor chip, and analyzing to obtain the memory quality characterization value of each semiconductor chip; S3, monitoring and analyzing the performance test phase of the semiconductor chip to obtain the performance characterization value of each semiconductor chip; S4, judging the first test result of each semiconductor chip according to the memory quality characterization value of each semiconductor chip and the performance characterization value of each semiconductor chip respectively, if the first test result is a defective product, directly marking it, if the first test result is not a defective product, executing step S5; S5. Analyze the memory quality characterization value of each non-defective semiconductor chip and the performance characterization value of each non-defective semiconductor chip to obtain the quality index value of each non-defective semiconductor chip, and mark each non-defective semiconductor chip according to the quality index value of each non-defective semiconductor chip; The memory test phase of the semiconductor chip is tested and analyzed to obtain the memory quality characterization value of each semiconductor chip. The specific process is as follows: Arrange a monitoring cycle, set a number of monitoring time periods in the monitoring cycle, monitor and count the number of memory refreshes of each semiconductor chip in each monitoring time period, and extract the length of the monitoring time period to obtain the memory refresh rate of each semiconductor chip in each monitoring time period; In each monitoring time period, the power on and off test is repeatedly performed on each semiconductor chip for multiple times, the memory data storage time of each semiconductor chip after each power off is monitored, the number of power offs is counted, and the average memory data storage time of each semiconductor chip in each monitoring time period is obtained by analysis; The number of times the memory data of each semiconductor chip is disturbed during each monitoring time period is monitored, the total number of times the data is disturbed during reading is counted, and the number of times the memory data of each semiconductor chip is disturbed during each monitoring time period is divided by the total number of times the data is disturbed during reading to obtain the read disturbance frequency of each semiconductor chip during each monitoring time period; Obtaining a memory quality index value of each semiconductor chip according to a memory refresh rate of each semiconductor chip in each monitoring time period, an average memory data retention time of each semiconductor chip in each monitoring time period, and a read interference frequency of each semiconductor chip in each monitoring time period; According to the memory quality index value of each semiconductor chip, the number of consecutive successful power-on, power-off and restart of each semiconductor chip is counted, and the memory quality characterization value of each semiconductor chip is obtained by comprehensive analysis; The memory test phase of the semiconductor chip is tested and analyzed to obtain the memory quality characterization value of each semiconductor chip. The specific analysis process is as follows: In the monitoring cycle, the time from sending instructions to reading and writing instructions of each semiconductor chip at each temperature is counted, and the response time of each semiconductor chip at each temperature is obtained by analysis; According to the response time of each semiconductor chip at each temperature, the power consumption of each semiconductor chip under each load and the data transmission rate of each semiconductor chip under each load are counted, and the performance characterization value of each semiconductor chip is obtained through comprehensive analysis.

2. A method for testing a semiconductor chip according to claim 1, characterized in that: The first test result of each semiconductor chip is determined according to the memory quality characterization value of each semiconductor chip and the performance characterization value of each semiconductor chip. The specific process is as follows: If the memory quality characterization value of a semiconductor chip is lower than a set memory quality characterization threshold of the semiconductor chip, the semiconductor chip is marked as a defective product; if the memory quality characterization value of a semiconductor chip is higher than or equal to the set memory quality characterization threshold of the semiconductor chip, the semiconductor chip is marked as a non-defective product; If the performance characterization value of a semiconductor chip is lower than the set performance characterization threshold of the semiconductor chip, the semiconductor chip is marked as a defective product. If the performance characterization value of a semiconductor chip is higher than or equal to the set performance characterization threshold of the semiconductor chip, the semiconductor chip is marked as a non-defective product.

3. A method for testing a semiconductor chip according to claim 1, characterized in that: The specific process of marking each non-defective semiconductor chip according to the quality index value of each non-defective semiconductor chip is as follows: According to the memory quality characterization value of each non-defective semiconductor chip and the performance characterization value of each non-defective semiconductor chip, a quality index value of each non-defective semiconductor chip is obtained by comprehensive analysis; The quality index value of each non-defective semiconductor chip is a numerical quantification result obtained by performing data analysis on the memory quality and performance of the non-defective semiconductor chip, and is used to quantify the degree of influence of different factors on the quality of the semiconductor chip; If the quality index value of a non-defective semiconductor chip is lower than or equal to the set standard quality index threshold of the semiconductor chip, the non-defective semiconductor chip is marked as an original semiconductor chip; If the quality index value of a non-defective semiconductor chip is higher than the set standard quality index threshold of the semiconductor chip, and the quality index value of the non-defective semiconductor chip is lower than or equal to the set superior quality index threshold of the semiconductor chip, then the non-defective semiconductor chip is marked as a standard semiconductor chip; If the quality index value of a non-defective semiconductor chip is higher than the set semiconductor chip's superior quality index threshold, and the quality index value of the non-defective semiconductor chip is lower than or equal to the set semiconductor chip's aging quality index threshold, then the non-defective semiconductor chip is marked as a superior semiconductor chip; If the quality index value of a non-defective semiconductor chip is higher than the set semiconductor chip burn-in quality index threshold, the non-defective semiconductor chip is marked as a burn-in semiconductor chip.

4. A method for testing a semiconductor chip according to claim 1, characterized in that: The memory quality characterization value of each semiconductor chip is analyzed under the following specific conditions: ； In the formula, represents the memory quality characterization value of the i-th semiconductor chip, represents the memory quality index value of the i-th semiconductor chip, Indicates the impact factor corresponding to the set memory quality index value. It indicates the number of consecutive successful power-on, power-off and restart of the i-th semiconductor chip. It represents the impact factor corresponding to the set number of consecutive successful power-on / off restarts, i represents the number of each semiconductor chip, , n represents the total number of semiconductor chips.

5. The method for testing a semiconductor chip according to claim 3, characterized in that: The specific analysis conditions of the quality index values ​​of the non-defective semiconductor chips are as follows: ； In the formula, represents the quality index value of the zth non-defective semiconductor chip, represents the memory quality characterization value of the zth non-defective semiconductor chip, Indicates the weight factor corresponding to the set memory quality characterization value. represents the performance characterization value of the zth non-defective semiconductor chip, represents the weight factor corresponding to the set performance characterization value, z represents the serial number of each non-defective semiconductor chip, , q represents the total number of non-defective semiconductor chips.

6. A semiconductor chip testing device, characterized in that: It includes: a processor, and a memory and a network interface connected to the processor; the network interface is connected to a non-volatile memory in a server; when the processor is running, it calls a computer program from the non-volatile memory through the network interface, and runs the computer program through the memory to execute the method described in any one of claims 1 to 5.

7. A device using the semiconductor chip testing method according to any one of claims 1 to 5, characterized in that: include: A process division module, used for dividing the test process of the semiconductor chip into a memory test phase of the semiconductor chip and a performance test phase of the semiconductor chip; A memory test module is used to detect the memory test phase of the semiconductor chip and analyze and obtain the memory quality characterization value of each semiconductor chip; The performance test module is used to monitor and analyze the performance test phase of the semiconductor chip to obtain the performance characterization value of each semiconductor chip; A preliminary screening and marking module, used to determine the first test result of each semiconductor chip according to the memory quality characterization value of each semiconductor chip and the performance characterization value of each semiconductor chip; The quality index value analysis and labeling module is used to obtain the quality index value of each non-defective semiconductor chip based on the memory quality characterization value of each non-defective semiconductor chip and the performance characterization value of each non-defective semiconductor chip, and label each non-defective semiconductor chip according to the quality index value of each non-defective semiconductor chip.

8. A test medium for a semiconductor chip, on which a computer program is stored, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 5 is implemented.

Images