Manufacturing process of voltage reference diode

Abstract

According to the manufacturing process of the voltage reference diode, two silicon wafers are adopted for manufacturing a reverse PN junction silicon wafer used for reference voltage and a forward PN junction silicon wafer used for temperature coefficient compensation respectively, then the two silicon wafers are bonded and then cut and split, and a table-board tube core is formed; a silicon wafer doped with a heavily doped composite center is adopted to carry out temperature compensation on a reference voltage silicon wafer, and in the actual production process, a corresponding compensation silicon wafer is prepared according to the needed reference voltage. The compensation capability of the compensation silicon wafer is represented through the reverse recovery time, and the reverse recovery time is controlled by controlling the platinum diffusion time and temperature in the production process of the compensation silicon wafer, so that higher precision can be achieved, the compensation capability can also reach higher precision, and a corresponding temperature coefficient gear can be obtained as required; and the temperature coefficient alignment rate is greatly improved, and the production input cost is reduced.

Description

Technical Field

[0001] The invention relates to a manufacturing process of a voltage reference diode. Background Art

[0002] A voltage reference diode is a voltage stabilizing diode whose stable voltage changes very little at different operating temperatures. Since the PN junction of the diode exhibits a positive temperature coefficient under reverse bias, that is, as the ambient temperature increases, its stable voltage increases, and the PN junction exhibits a negative temperature coefficient under forward bias, the current voltage reference diode usually uses a PNP or NPN structure, that is, a forward PN junction compensates the reverse PN junction, so that its stable voltage maintains an accurate and stable value at different temperatures. The difficulty in designing a traditional mesa-type voltage reference diode lies in choosing what kind of substrate to make the positive temperature coefficient of the PN junction reverse voltage equal to the negative temperature coefficient of the PN junction forward voltage. This method is subject to the selection of substrate resistivity and impurity concentration gradient. Summary of the invention

[0003] In order to solve the above technical problem, the present invention provides a manufacturing process of a voltage reference diode.

[0004] The present invention is achieved through the following technical solutions.

[0005] The present invention provides a process for manufacturing a voltage reference diode, the steps of which are as follows:

[0006] S1. Make P + N-type chip, and remove the surface of the N side;

[0007] S2. Make N + N - P + Type chip, and remove the P surface;

[0008] S3, in P + N-type chip and N + N - P + Type chip N + Noodle or P + N-type chip and N + N - P + Type chip P + An inner aluminum film layer is made on the surface;

[0009] S4, P + N-type chip and N + N - P + The inner aluminum film layers of the die plates are attached to each other and then aluminum bonding is performed;

[0010] S5, respectively making outer aluminum film layers on both end surfaces of the bonded chip;

[0011] S6. Cut the slices according to product specifications to form table dies.

[0012] The P + The N-type chip uses a P-type polished wafer with a resistivity of 0.001 to 0.0095 Ω·cm to first perform N-type epitaxial growth to form a P + N silicon wafer; then grind off the unpolished surface of the substrate, and the remaining chip thickness is 200 to 250 μm.

[0013] The N + N - P + The steps for making the chip are:

[0014] S21, using N-type single crystal with resistivity of 4 to 95Ω·cm to diffuse phosphorus, forming N + N - N + Silicon wafer;

[0015] S22, grinding away N by grinding disc + N - N + Silicon Wafer N + On one side, a N layer with a thickness of 160 to 300 μm is obtained. + N - Silicon wafers;

[0016] S23, after grinding, the N-side of the silicon wafer is subjected to boron diffusion to form N + N - P + ;

[0017] S24, after the boron diffusion, the boron surface is sandblasted to remove the surface borosilicate glass layer;

[0018] S25. After removing the surface borosilicate glass layer, the chip is subjected to platinum diffusion treatment.

[0019] The reverse recovery time of the chip after platinum diffusion is 200-600ns.

[0020] The platinum diffusion temperature is 800-960° C., and the diffusion time is 30-120 minutes.

[0021] The inner aluminum film layer is formed by electron beam evaporation process and has a thickness of 1 to 7 μm.

[0022] The outer aluminum film layer is formed by electron beam evaporation process and has a thickness of 10 to 14 μm.

[0023] The aluminum bonding temperature is 570-630°C.

[0024] The beneficial effect of the present invention is that a silicon wafer doped with heavily doped composite centers is used to perform temperature compensation on a reference voltage silicon wafer. In the actual production process, a corresponding compensation silicon wafer is prepared according to the required reference voltage. The compensation silicon wafer characterizes its compensation capability through the reverse recovery time. Since the reverse recovery time is controlled by controlling the platinum diffusion time and temperature in the production process of the compensation silicon wafer, a higher accuracy can be achieved. Therefore, its compensation capability can also achieve a higher accuracy, and the corresponding temperature coefficient gear can be obtained as needed, which greatly improves the temperature coefficient gear ratio and reduces the production input cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of the structure of a mesa-type voltage reference diode of the present invention;

[0026] Figure 2 This is a schematic diagram of the structure of a traditional mesa-type voltage reference diode. DETAILED DESCRIPTION

[0027] The technical solution of the present invention is further described below, but the scope of protection claimed is not limited to the description.

[0028] Embodiment 1: A method for controlling the temperature coefficient of a voltage reference diode provided by the present invention comprises the following process steps:

[0029] a) Reverse PN junction chip manufacturing process: Use a P-type polished wafer with a resistivity of 0.001Ω·cm to first perform N-type epitaxial growth to form a P + N silicon wafer; then the wafer is polished to remove the unpolished surface of the substrate, and the thickness of the silicon wafer is 200μm.

[0030] Forward PN junction chip manufacturing process: Use N-type single crystal with resistivity of 4Ω·cm to diffuse phosphorus first to form N + N - N + Silicon wafer, and then grind away N + On one side, a N film with a thickness of 160 μm was obtained. + After grinding, the N-side of the silicon wafer is subjected to boron diffusion to form N + NP + After boron diffusion, the boron surface is sandblasted. After removing the surface borosilicate glass layer, the silicon wafer is diffused with platinum. The diffusion temperature is 800℃ and the diffusion time is 30min. By controlling the two process parameters, the reverse recovery time is 200ns.

[0031] b) Separately place the N-type surface of the reverse PN junction chip and the N-type surface of the forward PN junction chip + Surface (or reverse PN junction chip P + Surface, forward PN junction chip P +A 1 μm aluminum thin film layer was evaporated by electron beam.

[0032] c) Place the forward and reverse PN junction chips on each other with aluminum layers, apply a certain pressure on the silicon wafer, and put it into a vacuum sintering furnace at 570°C for aluminum bonding.

[0033] d) Electron beam evaporation is performed on the two sides of the remaining un-aluminum-plated chip to form a 10 μm aluminum film layer, and then the chip is cut and split to form a mesa die.

[0034] The diode core formed has a forward PN junction chip whose reverse recovery time is controlled within 300-500ns for a diode with a reference voltage ≤ 9V, and a forward PN junction chip whose reverse recovery time is controlled within 250-450ns for a diode with a reference voltage > 9V.

[0035] Embodiment 2: A voltage reference diode temperature coefficient control method provided by the present invention comprises the following process steps:

[0036] a) Reverse PN junction chip manufacturing process: Use a P-type polished wafer with a resistivity of 0.0095Ω·cm to first perform N-type epitaxial growth to form a P + N silicon wafer; then the wafer is polished to remove the unpolished surface of the substrate, and the thickness of the silicon wafer is 250μm.

[0037] Forward PN junction chip manufacturing process: Use N-type single crystal with resistivity of 95Ω·cm to diffuse phosphorus first to form N + NN + Silicon wafer, and then grind away N + On one side, a 300 μm thick N + After grinding, the N-side of the silicon wafer is subjected to boron diffusion to form N + NP + After boron diffusion, the boron surface is sandblasted. After removing the surface borosilicate glass layer, the silicon wafer is diffused with platinum. The diffusion temperature is 960°C and the diffusion time is 120 min. By controlling the two process parameters, the reverse recovery time is 600 ns.

[0038] b) Separately place the N-type surface of the reverse PN junction chip and the N-type surface of the forward PN junction chip + Surface (or reverse PN junction chip P + Surface, forward PN junction chip P + A 7μm aluminum thin film layer was electron beam evaporated on the surface.

[0039] c) Place the forward and reverse PN junctions of the chip on the aluminum layer, apply a certain pressure on the silicon wafer, and put it into a vacuum sintering furnace at 630°C for aluminum bonding.

[0040] d) Electron beam evaporation is performed on the two sides of the remaining un-aluminum-plated chip to form a 14 μm aluminum film layer, and then the chip is cut and split to form a mesa die.

[0041] The diode core formed has a forward PN junction chip reverse recovery time of 450-650ns for diodes with a reference voltage ≤ 9V, and a forward PN junction chip reverse recovery time of 200-350ns for diodes with a reference voltage > 9V.

[0042] Embodiment 3: A voltage reference diode temperature coefficient control method provided by the present invention comprises the following process steps:

[0043] a) Reverse PN junction chip manufacturing process: Use a P-type polished wafer with a resistivity of 0.005Ω·cm to first perform N-type epitaxial growth to form a P + N silicon wafer; then the wafer is polished to remove the unpolished surface of the substrate, and the thickness of the silicon wafer is 230μm.

[0044] Forward PN junction chip manufacturing process: Use N-type single crystal with a resistivity of 50Ω·cm to diffuse phosphorus first to form N + NN + Silicon wafer, and then grind away N + On one side, a N film with a thickness of 230 μm was obtained. + After grinding, the N-side of the silicon wafer is subjected to boron diffusion to form N + NP + After boron diffusion, the boron surface is sandblasted. After removing the surface borosilicate glass layer, the silicon wafer is diffused with platinum. The diffusion temperature is 880℃ and the diffusion time is 80min. By controlling the two process parameters, the reverse recovery time is 400ns.

[0045] b) Separately place the N-type surface of the reverse PN junction chip and the N-type surface of the forward PN junction chip + Surface (or reverse PN junction chip P + Surface, forward PN junction chip P + A 4 μm aluminum film layer was electron beam evaporated on the surface.

[0046] c) Place the forward and reverse PN junctions of the chip on the aluminum layer, apply a certain pressure on the silicon wafer, and put it into a vacuum sintering furnace at 600°C for aluminum bonding.

[0047] d) Electron beam evaporation is performed on the two sides of the remaining un-aluminum-plated chip to form a 12 μm aluminum film layer, and then the chip is cut and split to form a mesa die.

[0048] The diode core formed has a forward PN junction chip whose reverse recovery time is controlled within 400-600ns for a diode with a reference voltage ≤ 9V, and a forward PN junction chip whose reverse recovery time is controlled within 200-400ns for a diode with a reference voltage > 9V.

Claims

1. A process for manufacturing a voltage reference diode, comprising the following steps: S1. Make P + N-type chip, and remove the surface of the N side; S2. Make N + N - P + Type chip, and remove the P surface; S3, in P + N-type chip and N + N - P + Type chip N + Noodle or P + N-type chip and N + N - P + Type chip P + An inner aluminum film layer is made on the surface; S4, P + N-type chip and N + N - P + The inner aluminum film layers of the die plate are attached to each other and then aluminum bonding is performed; S5, respectively making outer aluminum film layers on both end surfaces of the bonded chip; S6. Cut the slices according to product specifications to form table dies.

2. The process for manufacturing a voltage reference diode according to claim 1, wherein: The P + The N-type chip uses a P-type polished wafer with a resistivity of 0.001 to 0.0095 Ω·cm to first perform N-type epitaxial growth to form a P + N silicon wafer; then grind off the unpolished surface of the substrate, and the remaining chip thickness is 200 to 250 μm.

3. The process for manufacturing a voltage reference diode according to claim 1, wherein: The N + N - P + The steps for making the chip are: S21, using N-type single crystal with resistivity of 4 to 95Ω·cm to diffuse phosphorus, forming N + NN + Silicon wafer; S22, grinding away N by grinding disc + NN + Silicon Wafer N + On one side, a N layer with a thickness of 160 to 300 μm is obtained. + N- silicon wafer; S23, after grinding, the N-side of the silicon wafer is subjected to boron diffusion to form N + NP + ; S24, after the boron diffusion, the boron surface is sandblasted to remove the surface borosilicate glass layer; S25. After removing the surface borosilicate glass layer, the chip is subjected to platinum diffusion treatment.

4. The process for manufacturing a voltage reference diode as claimed in claim 3, characterized in that: The reverse recovery time of the chip after platinum diffusion is 200-600ns.

5. The process for manufacturing a voltage reference diode as claimed in claim 4, characterized in that: The platinum diffusion temperature is 800-960° C., and the diffusion time is 30-120 minutes.

6. The process for manufacturing a voltage reference diode according to claim 1, wherein: The inner aluminum film layer is formed by electron beam evaporation process and has a thickness of 1 to 7 μm.

7. The process for manufacturing a voltage reference diode according to claim 1, wherein: The outer aluminum film layer is formed by electron beam evaporation process and has a thickness of 10 to 14 μm.

8. The process for manufacturing a voltage reference diode according to claim 1, wherein: The aluminum bonding temperature is 570-630°C.

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