Layout structure of row decoding circuit

Abstract

The embodiment of the invention relates to the technical field of semiconductors, and provides a layout structure of a row decoding circuit, which comprises a plurality of row address signal lines located on a first wiring layer, and each row address signal line is electrically connected with a corresponding pre-decoding sub-circuit and a corresponding buffer sub-circuit, the plurality of row address signal lines are divided into first row address signal lines and second row address signal lines, and the number of the pre-decoding sub-circuits electrically connected with the first row address signal lines is larger than that of the pre-decoding sub-circuits electrically connected with the second row address signal lines; the buffer data lines are located on the second wiring layer, and each buffer data line is electrically connected with the corresponding buffer sub-circuit and the corresponding row address comparison sub-circuit; the overlapping area of the orthographic projections of the first row address signal line and the buffer data line on the second wiring layer is smaller than the overlapping area of the orthographic projections of the second row address signal line and the buffer data line on the second wiring layer, and the overlapping area is a second area. The embodiment of the invention is at least beneficial to reducing signal interference.

Description

Technical Field

[0001] The disclosed embodiments relate to the field of semiconductor technology, and in particular to a layout structure of a row decoding circuit. Background Art

[0002] In the current design of dynamic random access memory (DRAM), the row decoding area not only includes the main word line driving circuit, the sense amplifier circuit and the word line driver control circuit, but also includes circuits such as the pre-decoding circuit, the buffer circuit and the row address comparison circuit. Therefore, the electrical connection of various signal lines and the plane layout of various signal lines in the limited layout area of ​​the row decoding area will become extremely complicated, especially the layout of the row address signal line used to realize the storage and reading functions and the plane layout between other signal lines need to be carefully designed.

[0003] An unreasonable layout between signal lines will have a great impact on the performance of DRAM. For example, the electrical interference between signal lines will have a great adverse effect, which will reduce the accuracy of the signal transmitted by the signal line, causing DRAM to malfunction or fail to work properly. Therefore, under a limited layout area, how to layout various signal lines to reduce the mutual interference between various signals needs to be solved. Summary of the invention

[0004] The disclosed embodiments provide a layout structure of a row decoding circuit, which is at least beneficial to reducing signal interference.

[0005] According to some embodiments of the present disclosure, on the one hand, the embodiments of the present disclosure provide a layout structure of a row decoding circuit, including: a row decoding circuit, the row decoding circuit including a pre-decoding circuit, a buffer circuit and a row address comparison circuit, wherein the pre-decoding circuit includes a plurality of pre-decoding sub-circuits, the buffer circuit includes a plurality of buffer sub-circuits, and the row address comparison circuit includes a plurality of row address comparison sub-circuits; a plurality of row address signal lines located in a first wiring layer, arranged at intervals along a first direction and extending along a second direction, each of the row address signal lines being electrically connected to a corresponding pre-decoding sub-circuit and a corresponding buffer sub-circuit, the plurality of row address signal lines being divided into a first row address signal line and a second row address signal line, the first row address signal line being a plurality of row address signal lines; The number of pre-decoding sub-circuits electrically connected to the row address signal line is greater than the number of pre-decoding sub-circuits electrically connected to the second row address signal line, and the first direction and the second direction intersect; a plurality of buffer data lines located in the second wiring layer are arranged at intervals along the first direction and extend along the second direction, and each of the buffer data lines is electrically connected to the corresponding buffer sub-circuit and the corresponding row address comparison sub-circuit; wherein the overlapping area of ​​the orthographic projections of the first row address signal line and the buffer data line on the second wiring layer is a first area, and the overlapping area of ​​the orthographic projections of the second row address signal line and the buffer data line on the second wiring layer is a second area, and the first area is smaller than the second area.

[0006] In some embodiments, the buffer subcircuit receives a row address signal and outputs a first buffer signal and a second buffer signal; the buffer data line includes a first buffer data line and a second buffer data line, one of the second row address signal lines overlaps with an orthographic projection of at least one of the second buffer data lines on the second wiring layer, and / or one of the second row address signal lines overlaps with an orthographic projection of at least one of the first buffer data lines on the second wiring layer.

[0007] In some embodiments, in one of the second row address signal lines and one of the second buffer data lines whose orthographic projections overlap on the second wiring layer, the buffer subcircuit outputs the second buffer signal transmitted by the second buffer data line based on the row address signal transmitted by the second row address signal line; or, in one of the second row address signal line and one of the first buffer data line whose orthographic projections overlap on the second wiring layer, the buffer subcircuit outputs the first buffer signal transmitted by the first buffer data line based on the row address signal transmitted by the second row address signal line.

[0008] In some embodiments, an orthographic projection of the second buffer data line on the second wiring layer is located in an orthographic projection of the second row address signal line on the second wiring layer; or, an orthographic projection of the first buffer data line on the second wiring layer is located in an orthographic projection of the second row address signal line on the second wiring layer.

[0009] In some embodiments, the first area is zero.

[0010] In some embodiments, a direct projection of the first row address signal line on the second wiring layer is a first projection, the first projection is located between two direct projections of the two buffer data lines on the second wiring layer, and there is a gap between the first projection and the two direct projections of the two buffer data lines on the second wiring layer.

[0011] In some embodiments, among the two buffered data lines whose positive projections on the second wiring layer are located on both sides of the first projection along the first direction and the first row address signal line corresponding to the first projection, the two buffered data lines include a first buffered data line and a second buffered data line, and the buffer subcircuit outputs a first buffered signal transmitted by the first buffered data line based on the row address signal transmitted by the first row address signal line, and outputs a second buffered signal transmitted by the second buffered data line.

[0012] In some embodiments, along the first direction, each of the first row address signal lines and each of the second row address signal lines are alternately arranged.

[0013] In some embodiments, along the first direction, there is an orthographic projection of the buffer data line on the second wiring layer between the two orthographic projections of two adjacent row address signal lines on the second wiring layer, and there is an orthographic projection of the buffer data line on the second wiring layer in the orthographic projection of one of the second row address signal lines on the second wiring layer.

[0014] In some embodiments, the sum of the number of the first row address signal lines and the number of the second row address signal lines is 13.

[0015] In some embodiments, the buffer sub-circuit corresponds to the row address comparison sub-circuit one by one, and along the second direction, each of the buffer sub-circuit and each of the row address comparison sub-circuit are arranged alternately.

[0016] In some embodiments, there is at least one pre-decoding sub-circuit between two adjacent row address comparison sub-circuits.

[0017] In some embodiments, the area where the row address comparison subcircuit is located is the first area, the area where the row decoding circuit is located is the second area, the second area includes a plurality of the first areas arranged at intervals along the second direction, the row address signal line runs through the second area, and the buffer data line runs through a corresponding one of the first areas.

[0018] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0019] The row address signal line with a large number of electrically connected pre-decoding sub-circuits is used as the first row address signal line, and the row address signal line with a small number of electrically connected pre-decoding sub-circuits is used as the second row address signal line, that is, the number of loads connected to the first row address signal line is greater than the number of loads connected to the second row address signal line, then the amplitude of electrical interference of the loads connected to the first row address signal line is greater than the amplitude of electrical interference of the loads connected to the second row address signal line; and, the overlapping area of ​​the orthographic projections of the first row address signal line and the buffered data line on the second wiring layer is smaller than the overlapping area of ​​the orthographic projections of the second row address signal line and the buffered data line on the second wiring layer, that is, the first area is smaller than the second area, then the coupling influence of the buffered data line on the first row address signal line is smaller than the coupling influence of the buffered data line on the second row address signal line.

[0020] In this way, the row address signal line is divided into the first row address signal line and the second row address signal line according to the number of connected loads, and the coupling effect of the buffered data line on the row address signal line is utilized to balance the effect of the load connected to each row address signal line and the coupling effect of the buffered data line on each row address signal line, so that the magnitude of the electrical interference that different row address signal lines are ultimately affected by is roughly the same, so as to reduce the adverse effect of the electrical interference on the row address signal lines, which is beneficial to reducing the waveform difference of different row address signals transmitted by different row address signal lines on the data bus, that is, the waveforms of different row address signals transmitted by different row address signal lines are made to basically overlap, so as to improve the signal transmission accuracy of the row address signal lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Elements with the same second wiring digital labels in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0022] Figure 1 1a is a partial top view schematic diagram of the layout structure of a row decoding circuit provided in an embodiment of the present disclosure;

[0023] Figure 1 1b is an enlarged structural schematic diagram of a buffer subcircuit, a row address comparison subcircuit and a plurality of buffer data lines in 1a;

[0024] Figure 2 A schematic diagram of a partial top view of a plurality of row address signal lines and a plurality of buffer data lines in a layout structure of a row decoding circuit provided in an embodiment of the present disclosure;

[0025] Figure 3 Three partial top view structural schematic diagrams between a second row address signal line and at least one second buffer data line in the layout structure of a row decoding circuit provided in an embodiment of the present disclosure;

[0026] Figure 4 Four partial top view structural schematic diagrams between a second row address signal line and at least one first buffer data line in the layout structure of a row decoding circuit provided in an embodiment of the present disclosure;

[0027] Figure 5 Four partial top view structural schematic diagrams between a first row address signal line and at least one buffer data line in the layout structure of a row decoding circuit provided in an embodiment of the present disclosure;

[0028] Figure 6 A circuit diagram of a buffer subcircuit in a layout structure of a row decoding circuit provided in an embodiment of the present disclosure;

[0029] Figure 7 Another partial top view structural diagram of a plurality of row address signal lines and a plurality of buffer data lines in the layout structure of a row decoding circuit provided in an embodiment of the present disclosure;

[0030] Figure 8 A schematic diagram of another partial top view structure of a plurality of row address signal lines and a plurality of buffer data lines in the layout structure of a row decoding circuit provided in an embodiment of the present disclosure;

[0031] Fig. 9 A schematic diagram of a partial simplified three-dimensional structure of a layout structure of a row decoding circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] As known from the background technology, the mutual interference between various signals needs to be reduced.

[0033] After analysis, it is found that the row address signal transmitted on each row address signal line needs to be pre-decoded by the pre-decoding circuit. The pre-decoding circuit includes multiple pre-decoding sub-circuits. For any pre-decoding sub-circuit, the row address signal line electrically connected to the pre-decoding sub-circuit can be one or multiple. Then the same row address signal line can be electrically connected to only one pre-decoding sub-circuit or multiple different pre-decoding sub-circuits, so that the number of pre-decoding sub-circuits connected to different row address signal lines is different, that is, the number of loads connected to different row address signal lines is different, resulting in different impedances on different row address signal lines. In this way, the row address signals transmitted on different row address signal lines will be subject to different electrical interference amplitudes, resulting in large differences in the waveforms of the row address signals transmitted on different row address signal lines, reducing the accuracy of the row address signals transmitted by the row address signal lines.

[0034] The present disclosure implements a layout structure of a row decoding circuit, which divides the row address signal line into a first row address signal line and a second row address signal line according to the number of connected loads, and utilizes the coupling effect of the buffer data line on the row address signal line to balance the influence of the load connected to each row address signal line and the coupling effect of the buffer data line on each row address signal line, so that the amplitude of the electrical interference influence on different row address signal lines is roughly the same, so as to reduce the adverse effect of the electrical interference on the row address signal lines, which is beneficial to reduce the waveform difference of different row address signals transmitted by different row address signal lines on the data bus, that is, the waveforms of different row address signals transmitted by different row address signal lines are basically overlapped, so as to improve the signal transmission accuracy of the row address signal lines.

[0035] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0036] An embodiment of the present disclosure provides a layout structure of a row decoding circuit. The layout structure of the row decoding circuit provided by an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0037] Figure 1 1a is a partial top view schematic diagram of the layout structure of a row decoding circuit provided in an embodiment of the present disclosure; Figure 1 1b is an enlarged structural schematic diagram of a buffer subcircuit, a row address comparison subcircuit and a plurality of buffer data lines in 1a; Figure 2A schematic diagram of a partial top view of a plurality of row address signal lines and a plurality of buffer data lines in a layout structure of a row decoding circuit provided in an embodiment of the present disclosure; Figure 3 Three partial top view structural schematic diagrams between a second row address signal line and at least one second buffer data line in the layout structure of a row decoding circuit provided in an embodiment of the present disclosure; Figure 4 Four partial top view structural schematic diagrams between a second row address signal line and at least one first buffer data line in the layout structure of a row decoding circuit provided in an embodiment of the present disclosure; Figure 5 Four partial top view structural schematic diagrams between a first row address signal line and at least one buffer data line in the layout structure of a row decoding circuit provided in an embodiment of the present disclosure; Figure 6 A circuit diagram of a buffer subcircuit in a layout structure of a row decoding circuit provided in an embodiment of the present disclosure; Figure 7 Another partial top view structural diagram of a plurality of row address signal lines and a plurality of buffer data lines in the layout structure of a row decoding circuit provided in an embodiment of the present disclosure; Figure 8 A schematic diagram of another partial top view structure of a plurality of row address signal lines and a plurality of buffer data lines in the layout structure of a row decoding circuit provided in an embodiment of the present disclosure; Fig. 9 A schematic diagram of a partial simplified three-dimensional structure of a layout structure of a row decoding circuit provided in an embodiment of the present disclosure.

[0038] It should be noted that, in order to facilitate description and clearly illustrate the layout structure of the row decoding circuit, Figure 1 The buffered data line 105 is not drawn in 1a. Figure 1 The row address signal line 104 is not drawn in 1b.

[0039] refer to Figures 1 to 9The layout structure of the row decoding circuit includes: a row decoding circuit 100, the row decoding circuit 100 includes a pre-decoding circuit 101, a buffer circuit 102 and a row address comparison circuit 103, wherein the pre-decoding circuit 101 includes a plurality of pre-decoding sub-circuits 111, the buffer circuit 102 includes a plurality of buffer sub-circuits 112, and the row address comparison circuit 103 includes a plurality of row address comparison sub-circuits 113; a plurality of row address signal lines 104 located in the first wiring layer M1, arranged at intervals along the first direction X and extending along the second direction Y, each row address signal line 104 is electrically connected to a corresponding pre-decoding sub-circuit 111 and a corresponding buffer sub-circuit 112, and the plurality of row address signal lines 104 are divided into a first row address signal line 114 and a second row address signal line 124, and the first row address signal line The number of pre-decoding sub-circuits 111 electrically connected to the first row address signal line 114 is greater than the number of pre-decoding sub-circuits 111 electrically connected to the second row address signal line 124, and the first direction X and the second direction Y intersect; a plurality of buffered data lines 105 located in the second wiring layer M2 are arranged at intervals along the first direction X and extend along the second direction Y, and each buffered data line 105 is electrically connected to a corresponding buffer sub-circuit 112 and a corresponding row address comparison sub-circuit 113, respectively; wherein, an overlapping area of ​​the orthographic projections of the first row address signal line 114 and the buffered data line 105 on the second wiring layer M2 is a first area S1, and an overlapping area of ​​the orthographic projections of the second row address signal line 124 and the buffered data line 105 on the second wiring layer M2 is a second area S2, and the first area S1 is smaller than the second area S2.

[0040] It should be noted that Figure 1 In 1a, the row address signal line 104 is represented by a thicker dotted arrow, and the first row address signal line 114 and the second row address signal line 124 are not distinguished, and the buffer data line 105 is not illustrated; Figure 1 In FIG. 1b , the buffer data line 105 is represented by a thicker dotted arrow.

[0041] It can be understood that, on the one hand, the load connected to any row address signal line 104 mainly includes the pre-decoding sub-circuit 111 electrically connected to the row address signal line 104; on the other hand, the row address signal transmitted on each row address signal line 104 needs to be pre-decoded by the pre-decoding circuit 101, but for any pre-decoding sub-circuit 111, the row address signal line 104 electrically connected to the pre-decoding sub-circuit 111 can be multiple or one; on the other hand, for any row address signal line 104, the larger the overlapping area of ​​the buffered data line 105 between the orthographic projection on the second wiring layer M2 and the orthographic projection of the row address signal line 104 on the second wiring layer M2, the greater the coupling influence on the row address signal line 104, that is, the greater the electrical interference influence on the row address signal transmitted on the row address signal line 104.

[0042] Therefore, the row address signal line 104 with a larger number of electrically connected pre-decoding sub-circuits 111 is used as the first row address signal line 114, and the row address signal line 104 with a smaller number of electrically connected pre-decoding sub-circuits 111 is used as the second row address signal line 124, that is, the number of loads connected to the first row address signal line 114 is greater than the number of loads connected to the second row address signal line 124, then the amplitude of the electrical interference of the loads connected to the first row address signal line 114 is greater than the amplitude of the electrical interference of the loads connected to the second row address signal line 124; and, the overlapping area of ​​the orthographic projections of the first row address signal line 114 and the buffered data line 105 on the second wiring layer M2 is smaller than the overlapping area of ​​the orthographic projections of the second row address signal line 124 and the buffered data line 105 on the second wiring layer M2, that is, the first area S1 is smaller than the second area S2, then the coupling influence of the buffered data line 105 on the first row address signal line 114 is smaller than the coupling influence of the buffered data line 105 on the second row address signal line 124.

[0043] It should be noted that the number of loads connected to the above-mentioned row address signal line 104 is relatively large or small relative to the first row address signal line 114 and the second row address signal line 124, that is, an embodiment of the present disclosure only limits the size relationship between the number of pre-decoding sub-circuits 111 connected to the first row address signal line 114 and the number of pre-decoding sub-circuits 111 connected to the second row address signal line 124. For example, the number of pre-decoding sub-circuits 111 connected to the first row address signal line 114 is greater than the number of pre-decoding sub-circuits 111 connected to the second row address signal line 124, and does not limit the specific values ​​of the number of pre-decoding sub-circuits 111 connected to the first row address signal line 114 and the number of pre-decoding sub-circuits 111 connected to the second row address signal line 124. In practical applications, the first row address signal line 114 and the second row address signal line 124 can be reasonably divided according to the actual situation of the row decoding circuit and the number of pre-decoding sub-circuits 111 connected to each row address signal line 104.

[0044] It can be understood that the row address signal line 104 is divided into a first row address signal line 114 and a second row address signal line 124 according to the number of connected loads, and the coupling effect of the buffer data line 105 on the row address signal line 104 is utilized to balance the influence of the load connected to each row address signal line 104 and the coupling effect of the buffer data line 105 on each row address signal line 104, so that the magnitude of the electrical interference that different row address signal lines 104 are ultimately affected by is roughly the same, so as to reduce the adverse effect of the electrical interference on the row address signal line 104, which is beneficial to reduce the waveform difference of different row address signals transmitted by different row address signal lines 104 on the data bus, that is, the waveforms of different row address signals transmitted by different row address signal lines 104 are made to basically overlap, so as to improve the signal transmission accuracy of the row address signal line 104.

[0045] It should be noted that the overlapping area of ​​the orthographic projections of the first row address signal line 114 and the buffer data line 105 on the second wiring layer M2 is the first area S1, which includes the following two situations: first, the overlapping area of ​​the orthographic projections of all first row address signal lines 114 and all buffer data lines 105 on the second wiring layer M2 is the first area S1; second, the overlapping area of ​​the orthographic projections of any first row address signal line 114 and at least one buffer data line 105 on the second wiring layer M2 is the first area S1.

[0046] The overlapping area of ​​the orthographic projections of the second row address signal line 124 and the buffer data line 105 on the second wiring layer M2 is the second area S2, which includes the following two situations: first, the overlapping area of ​​the orthographic projections of all second row address signal lines 124 and all buffer data lines 105 on the second wiring layer M2 is the second area S2; second, the overlapping area of ​​the orthographic projections of any second row address signal line 124 and at least one buffer data line 105 on the second wiring layer M2 is the second area S2.

[0047] The first area S1 is smaller than the second area S2, which includes the following two situations: first, the overlapping area of ​​the orthographic projections of all first-row address signal lines 114 and all buffered data lines 105 on the second wiring layer M2 is smaller than the overlapping area of ​​the orthographic projections of all second-row address signal lines 124 and all buffered data lines 105 on the second wiring layer M2; second, the overlapping area of ​​the orthographic projections of any first-row address signal line 114 and at least one buffered data line 105 on the second wiring layer M2 is smaller than the overlapping area of ​​the orthographic projections of any second-row address signal line 124 and at least one buffered data line 105 on the second wiring layer M2, which is the second area S2.

[0048] The embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0049] In some embodiments, reference Figure 1 1a, the layout structure of the row decoding circuit also includes: a first electrical connection structure 116, which is electrically in contact with a row address signal line 104 and a pre-decoding sub-circuit 111 respectively, so as to realize the electrical connection between a row address signal line 104 and a pre-decoding sub-circuit 111; a second electrical connection structure 126, which is electrically in contact with at least one row address signal line 104 and a buffer sub-circuit 112 respectively, so as to realize the electrical connection between at least one row address signal line 104 and a buffer sub-circuit 112.

[0050] It should be noted that Figure 1 In 1a, the first electrical connection structure 116 and the second electrical connection structure 126 are drawn in the same filling manner. In practical applications, the material of the first electrical connection structure 116 and the material of the second electrical connection structure 126 can be the same or different. In addition, Figure 1 1a only illustrates four row address signal lines 104 in the layout structure of the row decoding circuit. In one embodiment of the present disclosure, there is no restriction on the number of row address signal lines 104 in the layout structure of the row decoding circuit, which can be determined according to the actual needs of the row decoding circuit.

[0051] refer to Figure 1 In 1a, a part of the row address signal lines 104 are electrically connected to three pre-decoding sub-circuits 111 respectively through three first electrical connection structures 116, a part of the row address signal lines 104 are electrically connected to two pre-decoding sub-circuits 111 respectively through two first electrical connection structures 116, and a part of the row address signal lines 104 are electrically connected to one pre-decoding sub-circuit 111 respectively through one first electrical connection structure 116 are used as examples to illustrate that for any pre-decoding sub-circuit 111, the row address signal line 104 electrically connected to the pre-decoding sub-circuit 111 can be multiple or one.

[0052] Continue to refer Figure 1 1a, the row address signal transmitted on each row address signal line 104 needs to be pre-decoded by the pre-decoding circuit 101, and the row address signal transmitted on each row address signal line 104 needs to be transmitted to the buffer circuit 102.

[0053] In some embodiments, reference Figures 1 to 9 The buffer subcircuit 112 receives the row address signal RAT and outputs a first buffer signal RADB and a second buffer signal RADT; the buffer data line 105 includes a first buffer data line 115 and a second buffer data line 125, a second row address signal line 124 overlaps with the positive projection of at least one second buffer data line 125 on the second wiring layer M2, and / or a second row address signal line 124 overlaps with the positive projection of at least one first buffer data line 115 on the second wiring layer M2.

[0054] It can be understood that the signal transmitted on the first buffer data line 115 is the first buffer signal RADB, and the signal transmitted on the second buffer data line 125 is the second buffer signal RADT. In addition, for any second row address signal line 124, the orthographic projection of the second row address signal line 124 on the second wiring layer M2 may overlap with only the orthographic projection of the second buffer data line 125 or only the orthographic projection of the first buffer data line 115 on the second wiring layer M2, or may overlap with both the orthographic projections of the second buffer data line 125 and the first buffer data line 115 on the second wiring layer M2.

[0055] It should be noted that Figure 1 In FIG. 1b , the first buffered data line 115 and the second buffered data line 125 are not distinguished.

[0056] The overlapping of the orthographic projection of any second row address signal line 124 and at least one buffer data line 105 on the second wiring layer M2 is described in detail below.

[0057] In some embodiments, reference Figure 2 , Figure 3 , Figure 7 and Figure 8 , the orthographic overlap of one second row address signal line 124 and at least one second buffer data line 125 on the second wiring layer M2 includes at least the following examples:

[0058] In some examples, reference Figure 2 , Figure 7 and Figure 8 , a second row address signal line 124 coincides with a second buffer data line 125's orthographic projection on the second wiring layer M2. For example, the orthographic projection of the second buffer data line 125 on the second wiring layer M2 is located in the orthographic projection of the second row address signal line 124 on the second wiring layer M2.

[0059] In other examples, reference Figure 3 3a, the orthographic projections of a second row address signal line 124 and a second buffer data line 125 on the second wiring layer M2 only partially overlap.

[0060] In some other examples, reference Figure 33b, a second row address signal line 124 overlaps with the orthographic projections of two second buffered data lines 125 on the second wiring layer M2. For example, along the first direction X, there is a second buffered data line 125 on each of the left and right sides of a second row address signal line 124, and the orthographic projections of the two second buffered data lines 125 on the second wiring layer M2 partially overlap with the orthographic projection of the second row address signal line 124 on the second wiring layer M2. In practical applications, it is also possible that a portion of the orthographic projection of one of the two second buffered data lines 125 on the second wiring layer M2 overlaps with the orthographic projection of the second row address signal line 124 on the second wiring layer M2, and the entire orthographic projection of the other second buffered data line 125 on the second wiring layer M2 overlaps with the orthographic projection of the second row address signal line 124 on the second wiring layer M2.

[0061] In some other examples, reference Figure 3 In 3c, a second row address signal line 124 overlaps with the orthographic projections of three second buffer data lines 125 on the second wiring layer M2. For example, along the first direction X, a second row address signal line 124 has a second buffer data line 125 on each of its left and right sides. The orthographic projection of a middle second buffer data line 125 among the three second buffer data lines 125 on the second wiring layer M2 is located in the orthographic projection of the second row address signal line 124 on the second wiring layer M2. Moreover, the orthographic projections of two second buffer data lines 125 located on both sides of the three second buffer data lines 125 on the second wiring layer M2 partially overlap with the orthographic projection of the second row address signal line 124 on the second wiring layer M2. In practical applications, it is also possible that part of the orthographic projection of one of the two second buffer data lines 125 located on both sides among the three second buffer data lines 125 on the second wiring layer M2 overlaps with the orthographic projection of the second row address signal line 124 on the second wiring layer M2, and the entire orthographic projection of the other second buffer data line 125 on the second wiring layer M2 overlaps with the orthographic projection of the second row address signal line 124 on the second wiring layer M2.

[0062] In other embodiments, reference Figure 4 , the orthographic overlap of a second row address signal line 124 and at least one first buffer data line 115 on the second wiring layer M2 includes at least the following examples:

[0063] In some examples, reference Figure 4 In 4a, a second row address signal line 124 coincides with an orthographic projection of a first buffer data line 115 on the second wiring layer M2. For example, the orthographic projection of the first buffer data line 115 on the second wiring layer M2 is located in the orthographic projection of the second row address signal line 124 on the second wiring layer M2.

[0064] In other examples, reference Figure 4 4b, a second row address signal line 124 and an orthographic projection of a first buffer data line 115 on the second wiring layer M2 only partially overlap.

[0065] In some other examples, reference Figure 4 4c, a second row address signal line 124 overlaps with the orthographic projections of two first buffer data lines 115 on the second wiring layer M2. For example, along the first direction X, there is a first buffer data line 115 on each of the left and right sides of a second row address signal line 124, and the orthographic projections of the two first buffer data lines 115 on the second wiring layer M2 partially overlap with the orthographic projection of the second row address signal line 124 on the second wiring layer M2. In practical applications, it is also possible that a portion of the orthographic projection of one of the two first buffer data lines 115 on the second wiring layer M2 overlaps with the orthographic projection of the second row address signal line 124 on the second wiring layer M2, and the entire orthographic projection of the other first buffer data line 115 on the second wiring layer M2 overlaps with the orthographic projection of the second row address signal line 124 on the second wiring layer M2.

[0066] In some other examples, reference Figure 4 4d, a second row address signal line 124 overlaps with the orthographic projections of three first buffer data lines 115 on the second wiring layer M2. For example, along the first direction X, a second row address signal line 124 has a first buffer data line 115 on each of its left and right sides. The orthographic projection of a middle first buffer data line 115 among the three first buffer data lines 115 on the second wiring layer M2 is located in the orthographic projection of the second row address signal line 124 on the second wiring layer M2. Moreover, the orthographic projections of two first buffer data lines 115 located on both sides of the three first buffer data lines 115 on the second wiring layer M2 partially overlap with the orthographic projection of the second row address signal line 124 on the second wiring layer M2. In practical applications, it is also possible that part of the orthographic projection of one of the two first buffer data lines 115 located on both sides among the three first buffer data lines 115 on the second wiring layer M2 overlaps with the orthographic projection of the second row address signal line 124 on the second wiring layer M2, and the entire orthographic projection of the other first buffer data line 115 on the second wiring layer M2 overlaps with the orthographic projection of the second row address signal line 124 on the second wiring layer M2.

[0067] It can be understood that, for any second-row address signal line 124, any second-row address signal line 124 has an overlap with the orthographic projection of at least one buffer data line 105 on the second wiring layer M2. An embodiment of the present disclosure does not limit the number of buffer data lines 105 whose orthographic projections on the second wiring layer M2 overlap with the orthographic projection of a second-row address signal line 124 on the second wiring layer M2, nor does it limit whether the buffer data line 105 is the first buffer data line 115 or the second buffer data line 125, and does not limit whether the overlap between the orthographic projections of any second-row address signal line 124 and any buffer data line 105 on the second wiring layer M2 is partial or full. The above-mentioned situations without restrictions can be adaptively adjusted according to the number of loads electrically connected to the second-row address signal line 124. Figures 2 to 5 and Figures 7 and 8 The overlapping situation of the orthographic projection of any second row address signal line 124 and at least one buffer data line 105 on the second wiring layer M2 illustrated in the figure is only an exemplary description.

[0068] It should be noted that, in order to clearly show the overlap of the orthographic projections of any second row address signal line 124 and at least one buffer data line 105 on the second wiring layer M2, Figures 2 to 4 as well as Figures 7 and 8 The second row of address signal lines 124 is drawn in a perspective manner.

[0069] It can be understood that the positive projections of any first row address signal line 114 and at least one buffer data line 105 on the second wiring layer M2 may also overlap, and the overlapping of the positive projections of any first row address signal line 114 and at least one buffer data line 105 on the second wiring layer M2 is as follows: Figure 5 As shown, and Figures 2 to 4 as well as Figures 7 and 8 The overlapping situation of the orthographic projection of any second row address signal line 124 and at least one buffer data line 105 on the second wiring layer M2 is similar, and the first area S1 is smaller than the second area S2.

[0070] It should be noted that, in order to clearly show the overlap of the orthographic projections of any first row address signal line 114 and at least one buffer data line 105 on the second wiring layer M2, Figure 5 The first row address signal line 114 and the buffer data line 105 are drawn without filling, and the buffer data line 105 is not distinguished between the first buffer data line 115 and the second buffer data line 125, and the first row address signal line 114 is drawn in a perspective drawing manner. In addition, Figures 3 to 5 The second wiring layer M2 is indicated by a dotted frame.

[0071] In some embodiments, the first buffer signal RADB is a delayed inverted signal of the row address signal RAT, and the second buffer signal RADT is a delayed inverted signal of the row address signal RAT.

[0072] In one example, refer to Figure 6 The buffer subcircuit 112 includes a first inverter 122 and a second inverter 132 connected in series, a first input end of the first inverter 122 receives a row address signal RAT, a first output end of the first inverter 122 outputs a first buffer signal RADB, a second input end of the second inverter 132 receives the first buffer signal RADB, and a second output end of the second inverter 132 outputs a second buffer signal RADT. It should be noted that. Figure 6 This is only an exemplary description of the buffer sub-circuit 112. An embodiment of the present disclosure does not limit the specific structure of the buffer sub-circuit 112, as long as the generated first buffer signal RADB is an inverted signal of the row address signal RAT after delay, and the second buffer signal RADT is the row address signal RAT after the delay is increased.

[0073] It should be noted that, along the second direction Y, Figure 2 , Figure 7 and Figure 8 In the figure, the row address signal RAT transmitted by the first row address signal line 114 is marked directly above each first row address signal line 114, the row address signal RAT transmitted by the second row address signal line 124 is marked directly above each second row address signal line 124, the first buffer signal RADB transmitted by the first buffer data line 115 is marked directly below each first buffer data line 115, and the second buffer signal RADT transmitted by the second buffer data line 125 is marked directly below each second buffer data line 125.

[0074] Understandably, Figure 2 , Figure 7 China-Israel RAT <2> To RAT <15> 14 different row address signals transmitted by the 14 row address signal lines 104 are respectively indicated, wherein RAT <2> To RAT <14> The corresponding 13 row address signal lines 104 are divided into first row address signal lines 114 and second row address signal lines 124; Figure 8 China-Israel RAT <0> To RAT <15> 14 different row address signals transmitted by 16 row address signal lines 104 are respectively indicated, wherein RAT <2> To RAT <14> The corresponding 13 row address signal lines 104 are divided into first row address signal lines 114 and second row address signal lines 124. It can be seen that not all row address signal lines 104 in the row decoding circuit 100 are considered in the layout design of the row address signal lines 104 and the buffered data lines 105. Figure 2 , Figure 7 and Figure 8 China-Israel RAT <2> To RAT <14> The corresponding 13 row address signal lines 104 are divided into the first row address signal line 114 and the second row address signal line 124 as an example. In actual applications, the number of row address signal lines 104 that need to be divided into the first row address signal line 114 and the second row address signal line 124 can be selected according to the actual situation of the row decoding circuit.

[0075] also, Figure 2 , Figure 7 and Figure 8 In the embodiment, 13 row address signal lines 104 are divided into 7 first row address signal lines 114 and 6 second row address signal lines 124. The row address signals RAT transmitted by the 7 first row address signal lines 114 are RAT <6> , RAT <7> , RAT <8> , RAT <9> , RAT <10> , RAT <11> and RAT <12> The row address signals RAT transmitted by the six second row address signal lines 124 are respectively RAT <2> , RAT <3> , RAT <4> , RAT <5> , RAT <13> and RAT <14> For example, in actual applications, the number of first row address signal lines 114 and the number of second row address signal lines 124 can be selected according to the actual situation of the row decoding circuit, and it is also possible to reasonably select which row address signal lines 104 of the RAT are transmitted as the first row address signal lines 114 and which row address signal lines 104 are transmitted as the second row address signal lines 124.

[0076] It should be noted that the following description will be made by taking the overlapping of the orthographic projections of a second row address signal line 124 and a second buffered data line 125 on the second wiring layer M2 as an example. It can be understood that the overlapping of the orthographic projections of a second row address signal line 124 and a first buffered data line 115 on the second wiring layer M2 is similar to the overlapping of the orthographic projections of a second row address signal line 124 and a second buffered data line 125 on the second wiring layer M2, and will not be described in detail later.

[0077] In some embodiments, reference Figure 2 , Figure 7 and Figure 8 In a second row address signal line 124 and a second buffer data line 125 overlapped by the orthographic projection on the second wiring layer M2, the buffer sub-circuit 112 (reference Figure 3) outputs the second buffer signal RADT transmitted by the second buffer data line 125 based on the row address signal RAT transmitted by the second row address signal line 124. In this way, it is beneficial to arrange the transmission lines (the second row address signal line 124 and the second buffer signal RADT) corresponding to the associated row address signal RAT and the second buffer signal RADT in close proximity, that is, shorten the distance between the two transmission lines, so as to reduce the length of the total transmission path for transmitting the row address signal RAT to the buffer sub-circuit 112 and outputting the second buffer signal RADT based on the buffer sub-circuit 112, and reduce the complexity of the layout of the second row address signal line 124 and the second buffer data line 125.

[0078] refer to Figure 2 , Figure 7 and Figure 8 , transmit row address signal RAT <2> The second row address signal line 124 and the second buffer signal RADT <2> The second buffer data line 125 overlaps the positive projection on the second wiring layer M2; the row address signal RAT is transmitted <3> The second row address signal line 124 and the second buffer signal RADT <3> The positive projection of the second buffer data line 125 on the second wiring layer M2 overlaps... and so on. <14> The second row address signal line 124 and the second buffer signal RADT <14> In this way, the layout between the second row address signal line 124 and the second buffer data line 125 has regularity, so as to further reduce the complexity of the layout of the second row address signal line 124 and the second buffer data line 125.

[0079] In other embodiments, in a second row address signal line and a first buffer data line overlapped by the orthographic projection on the second wiring layer, the buffer subcircuit outputs the first buffer signal transmitted by the first buffer data line based on the row address signal transmitted by the second row address signal line. In this way, it is beneficial to arrange the transmission lines (the second row address signal line and the first buffer data line) corresponding to both the associated row address signal and the first buffer signal in close proximity, that is, shorten the distance between the two transmission lines, so as to reduce the length of the total transmission path from the row address signal to the buffer subcircuit and output the first buffer signal based on the buffer subcircuit, and reduce the complexity of the layout of the second row address signal line and the first buffer data line.

[0080] In some embodiments, continue to refer to Figure 2 , Figure 7 and Figure 8, the situation where the orthographic projections of a second row address signal line 124 and a second buffer data line 125 on the second wiring layer M2 overlap includes: the orthographic projection of a second buffer data line 125 on the second wiring layer M2 is located in the orthographic projection of a second row address signal line 124 on the second wiring layer M2. In this way, it is beneficial to ensure that the orthographic projection overlap area of ​​the second row address signal line 124 and the second buffer data line 125 on the second wiring layer M2 is large, so as to ensure that the second area S2 is larger than the first area S1.

[0081] In other embodiments, reference Figure 4 In 4a, the orthographic projection of a first buffer data line 115 on the second wiring layer M2 is located in the orthographic projection of a second row address signal line 124 on the second wiring layer M2. In this way, it is beneficial to ensure that the orthographic projection overlap area of ​​the second row address signal line 124 and the first buffer data line 115 on the second wiring layer M2 is large, so as to ensure that the second area S2 is larger than the first area S1.

[0082] In some embodiments, reference Figure 2 , Figure 7 and Figure 8 , the first area S1 is 0, that is, the orthographic projections of any first row address signal line 114 and buffer data line 105 on the second wiring layer M2 do not overlap. In this way, it is beneficial to ensure that the first area S1 is smaller than the second area S2, and the layout between the first row address signal line 114 and the buffer data line 105 has regularity, so as to further reduce the complexity of the layout of the first row address signal line 114 and the buffer data line 105.

[0083] The following is a detailed description by taking the non-overlapping orthographic projections of any first row address signal line 114 and the buffer data line 105 on the second wiring layer M2 as an example.

[0084] In some embodiments, reference Figure 2 , Figure 7 and Figure 8 , the orthographic projection of the first row address signal line 114 on the second wiring layer M2 is the first projection 134, the first projection 134 is located between the two orthographic projections of the two buffered data lines 105 on the second wiring layer M2, and there is a gap between the first projection 134 and the two orthographic projections of the two buffered data lines 105 on the second wiring layer M2. It can be understood that, Figure 2 , Figure 7 and Figure 8 In the partial top view structural diagram of the first row address signal line 114, the second row address signal line 124, the first buffer data line 115 and the second buffer data line 125 shown in the figure, the first row address signal line 114 can also be regarded as its positive projection on the second wiring layer M2, that is, the first projection 134.

[0085] In this way, while the orthographic projections of any first-row address signal line 114 and the buffer data line 105 on the second wiring layer M2 do not overlap, the orthographic projections of any first-row address signal line 114 and the buffer data line 105 on the second wiring layer M2 are spaced apart, which helps to further reduce the coupling effect of the buffer data line 105 on the first-row address signal line 114, so that the first-row address signal line 114 is mainly affected by the pre-decoding sub-circuit 111 electrically connected to it.

[0086] In some embodiments, continue to refer to Figure 2 , Figure 7 and Figure 8 In the two buffered data lines 105 whose positive projections on the second wiring layer M2 are located on both sides of the first projection 134 along the first direction X and the first row address signal line 114 corresponding to the first projection 134, the two buffered data lines 105 include a first buffered data line 115 and a second buffered data line 125, and the buffer sub-circuit 112 outputs a first buffered signal RADB transmitted by the first buffered data line 115 based on the row address signal RAT transmitted by the first row address signal line 114, and outputs a second buffered signal RADT transmitted by the second buffered data line 125.

[0087] For example, in the transmission row address signal RAT <6> The first row address signal line 114 includes two buffer data lines 105 on both sides along the first direction X: transmitting a first buffer signal RADB <6> The first buffer data line 115 and the second buffer signal RADT <6> The second buffer data line 125 is located at the transmission row address signal RAT <7> The first row address signal line 114 includes two buffer data lines 105 on both sides along the first direction X: transmitting a first buffer signal RADB <7> The first buffer data line 115 and the second buffer signal RADT <7> The second buffer data line 125 ...... and so on, is located at the transmission row address signal RAT <12> The first row address signal line 114 includes two buffer data lines 105 on both sides along the first direction X: transmitting a first buffer signal RADB <12> The first buffer data line 115 and the second buffer signal RADT <12> The second buffered data line 125.

[0088] In this way, on the one hand, the layout between the first row address signal line 114 and the buffer data line 105 is made more regular, so as to further reduce the complexity of the layout of the first row address signal line 114 and the buffer data line 105; on the other hand, it is conducive to the layout of the transmission lines (first row address signal line 114, first buffer data line 115 and second buffer data line 125) corresponding to the associated row address signal RAT, first buffer signal RADB and second buffer signal RADT in close proximity, that is, shortening the distance between the three transmission lines, so as to reduce the length of the total transmission path from the row address signal RAT to the buffer sub-circuit 112 and outputting the first buffer signal RADB and the second buffer signal RADT based on the buffer sub-circuit 112, thereby further reducing the complexity of the layout of the first row address signal line 114 and the buffer data line 105.

[0089] In some embodiments, continue to refer to Figure 2 , Figure 7 and Figure 8 , along the first direction X, each first row address signal line 114 and each second row address signal line 124 are arranged alternately. It can be understood that, looking at the 7 first row address signal lines 114 alone, along the first direction X, the RAT of transmitting the row address signal <12> , RAT <11> , RAT <10> , RAT <9> , RAT <8> , R AT <7> and RAT <6> The 7 first row address signal lines 114 are arranged in sequence; looking at the 6 second row address signal lines 124 separately, along the first direction X, the RAT of the row address signal is transmitted <14> , RAT <13> , RAT <5> , RAT <4> , RAT <3> and RAT <2> The six second row address signal lines 124 are arranged in sequence.

[0090] In some embodiments, reference Figure 2 , along the first direction X, the row address signal RAT is transmitted <14> , RAT <13> , RAT <5> , RAT <4> , RAT <3> and RAT <2> The six second row address signal lines 124 are interspersed with the transmission row address signal RAT in sequence. <10> , RAT <9> , RAT <8> , RAT <7> and RAT <6> For example, the row address signal RAT is transmitted. <14> and RAT <13> The transmission row address signal RAT is interspersed between the two second row address signal lines 124. <10> The first row address signal line 114 transmits the row address signal RAT <13> and RAT <5> The transmission row address signal RAT is interspersed between the two second row address signal lines 124. <9> The first row address signal line 114 ... and so on, transmits the row address signal RAT <3> and RAT <2> The transmission row address signal RAT is interspersed between the two second row address signal lines 124. <6> The first row address signal line 114.

[0091] In some embodiments, continue to refer to Figure 2 , transmit row address signal RAT <12> and RAT <11> The two first row address signal lines 114 may be interspersed with a transmission row address signal RAT <15> The row address signal line 104, it can be understood that the row address signal RAT <15> The row address signal line 104 is distinguished from the first row address signal line 114 and the second row address signal line 124. In this way, the row address signal RAT can be transmitted. <15> The row address signal line 104 will transmit the second buffer signal RADT <12> The second buffered data line 125 and the transmission RADB <11> The first buffer data lines 115 are spaced apart from each other, which is beneficial to improving the layout regularity of the multiple row address signal lines 104 and the multiple buffer data lines 105, and further reducing the layout complexity of the multiple row address signal lines 104 and the multiple buffer data lines 105.

[0092] In other embodiments, reference Figure 7 and Figure 8 , along the first direction X, the row address signal RAT is transmitted <12> , RAT <11> , RAT <10> , RAT <9> , RAT <8> , RAT <7> and RAT <6> The seven first row address signal lines 114 are interspersed with the transmission row address signal RAT in sequence. <14> , RAT <13> , RAT <5> , RAT <4> , RAT <3> and RAT <2> 6 second row address signal lines 124. For example, the row address signal RAT is transmitted <12> and RAT <11> The transmission row address signal RAT is interspersed between the two first row address signal lines 114. <14> The second row address signal line 124 transmits the row address signal RAT <11> and RAT <10> The transmission row address signal RAT is interspersed between the two first row address signal lines 114. <13> The second row address signal line 124 ... and so on, transmits the row address signal RAT <7> and RAT <6> The transmission row address signal RAT is interspersed between the two first row address signal lines 114. <2> In this way, there is no need to use other row address signal lines 104, such as the row address signal RAT. <15> The row address signal lines 104 can improve the layout regularity of the multiple first row address signal lines 114, the multiple second row address signal lines 124 and the multiple buffer data lines 105, and further reduce the layout complexity of the multiple row address signal lines 104 and the multiple buffer data lines 105.

[0093] In some embodiments, reference Figure 8The layout structure of the row decoding circuit may also include: transmitting the row address signal RAT <0> and RAT <1> The two row address signal lines 104 transmit the first buffer signal RADB <2> , RADB <3> , RADB <4> , RADB <5> , RADB <13> and RADB <14> Six first buffer data lines 115.

[0094] In some embodiments, continue to refer to Figure 8 , along the first direction X, transmit the first buffer signal RADB <5> , RADB <4> and RADB <3> The transmission row address signal RAT is sequentially inserted into two intervals of the three first buffer data lines 115. <1> and RAT <0> The two row address signal lines 104 transmit the first buffer signal RADB. <14> , RADB <13> , RADB <2> The three first buffer data lines 115 are arranged in sequence at intervals.

[0095] It should be noted that Figure 2 , Figure 7 and Figure 8 In the example, each second row address signal line 124 only overlaps with the orthographic projection of the corresponding second buffer data line 125 on the second wiring layer M2, and the first buffer data line 115 corresponding to each second row address signal line 124 is subsequently uniformly arranged in a fixed area, which is located outside the area where the first row address signal line 114 and the second row address signal line 124 are arranged. In practical applications, reference Figure 4 Among the second row address signal lines 124 and the corresponding buffer data lines 105 overlapped by the orthographic projection on the second wiring layer M2 , the buffer data lines 105 may be the first buffer data lines 115 .

[0096] It can be understood that an embodiment of the present disclosure does not limit the number of first row address signal lines 114 and second row address signal lines 124 divided in the row address signal lines 104, and only a portion of the first buffer data lines 115 and / or the second buffer data lines 125 corresponding to the first row address signal lines 114 may be designed to overlap with the orthographic projection of the first row address signal lines 114 on the second wiring layer M2, and only a portion of the first buffer data lines 115 and / or the second buffer data lines 125 corresponding to the second row address signal lines 124 may be designed to overlap with the orthographic projection of the second row address signal lines 124 on the second wiring layer M2, and the remaining first buffer data lines 115 and / or second buffer data lines 125 are uniformly arranged in the above-mentioned fixed area.

[0097] In the above various embodiments, reference Figure 2 , Figure 7 and Figure 8, along the first direction X, between the two orthographic projections of two adjacent row address signal lines 104 on the second wiring layer M2, there is an orthographic projection of a buffered data line 105 on the second wiring layer M2, and in the orthographic projection of a second row address signal line 124 on the second wiring layer M2, there is an orthographic projection of a buffered data line 105 on the second wiring layer M2. In this way, while ensuring that the first area S1 is smaller than the second area S2, it is beneficial to improve the layout regularity of the multiple first row address signal lines 114, the multiple second row address signal lines 124, and the multiple buffered data lines 105, and further reduce the layout complexity of the multiple row address signal lines 104 and the multiple buffered data lines 105.

[0098] In the above-mentioned various embodiments, the sum of the number of the first row address signal lines 114 and the number of the second row address signal lines 124 is 13.

[0099] In one example, refer to Figure 2 , Figure 7 and Figure 8 , the 13 row address signal lines 104 are divided into 7 first row address signal lines 114 and 6 second row address signal lines 124, and the row address signals RAT transmitted by the 7 first row address signal lines 114 are RAT <6> , RAT <7> , RAT <8> , RAT <9> , RAT <10> , RAT <11> and RAT <12> The row address signals RAT transmitted by the six second row address signal lines 124 are respectively RAT <2> , RAT <3> , RAT <4> , RAT <5> , RAT <13> and RAT <14> .

[0100] In some embodiments, in conjunction with reference Figure 1 and Fig. 9 , the row address signal lines 104 transmitting the row address signal RAT<2:14> are all located in the first wiring layer M1, the first buffer data lines 115 transmitting the first buffer signal RADB<2:14> are all located in the second wiring layer M2, and the second buffer data lines 125 transmitting the second buffer signal RADT<2:14> are also all located in the second wiring layer M2, that is, the multiple row address signal lines 104 are located in the first wiring layer M1, the multiple buffer data lines 105 are located in the second wiring layer M2, and the first wiring layer M1 and the second wiring layer M2 are located in different layers.

[0101] In one example, reference Fig. 9 , the first wiring layer M1 is located above the second wiring layer M2 to comply with the transmission direction of the row address signal RAT, the first buffer signal RADB and the second buffer signal RADT.

[0102] It should be noted that, in order to illustrate that the first wiring layer M1 and the second wiring layer M2 are located in different layers, Fig. 9 Different dotted lines are used to frame the planes where the first wiring layer M1 and the second wiring layer M2 are located, and for the clarity of the diagram, Fig. 9 In the figure, a plurality of row address signal lines 104 for transmitting row address signals RAT<2:14> are drawn together, a plurality of first buffer data lines 115 for transmitting first buffer signals RADB are drawn together, and a plurality of second buffer data lines 125 for transmitting second buffer signals RADT are drawn together. It can be understood that Fig. 9 The row address signal line 104 in the embodiment can be regarded as transmitting the row address signal RAT <2> To RAT <14> For any one of the row address signal lines 104, the first buffer data line 115 can be regarded as the first buffer data line 115 that transmits the first buffer signal RADB corresponding to the row address signal RAT, and the second buffer data line 125 can be regarded as the second buffer data line 125 that transmits the second buffer signal RADT corresponding to the row address signal RAT.

[0103] In the above various embodiments, reference Figure 1 , the buffer subcircuit 112 corresponds to the row address comparison subcircuit 113 one by one, and each buffer subcircuit 112 and each row address comparison subcircuit 113 are arranged alternately along the second direction Y. In this way, it is beneficial to improve the layout regularity of the multiple buffer subcircuits 112 and the multiple row address comparison subcircuits 113, and further reduce the layout complexity of the multiple buffer subcircuits 112 and the multiple row address comparison subcircuits 113.

[0104] In some embodiments, reference Figure 1 , there is at least one pre-decoding sub-circuit 111 between two adjacent row address comparison sub-circuits 113. It should be noted that, Figure 1 In the example, one or two pre-decoding sub-circuits 111 are provided between two adjacent row address comparison sub-circuits 113. In actual applications, an embodiment of the present disclosure does not limit the number of pre-decoding sub-circuits 111 provided between two adjacent row address comparison sub-circuits 113, and the position and number of the row address comparison sub-circuits 113 can be designed according to actual needs.

[0105] In some embodiments, reference Figure 1 , the area where the row address comparison subcircuit 113 is located is the first area I, the area where the row decoding circuit 100 is located is the second area II, the second area II includes a plurality of first areas I arranged at intervals along the second direction Y, the row address signal line 104 runs through the second area II, and the buffer data line 105 runs through a corresponding first area I. It should be noted that, Figure 1 Different dotted line frames are used to frame the areas included in the first zone I and the second zone II respectively.

[0106] To summarize, the row address signal line 104 is divided into a first row address signal line 114 and a second row address signal line 124 according to the number of connected pre-decoding sub-circuits 111, and the coupling effect of the buffer data line 105 on the row address signal line 104 is utilized, and the first area S1 is arranged to be smaller than the second area S2, so as to balance the influence of the load connected to each row address signal line 104 and the coupling effect of the buffer data line 105 on it, so that the amplitude of the electrical interference finally exerted on different row address signal lines 104 is roughly the same, so as to reduce the adverse effect of the electrical interference exerted on the row address signal line 104, thereby helping to reduce the waveform difference of different row address signals transmitted by different row address signal lines 104 on the data bus, that is, the waveforms of different row address signals transmitted by different row address signal lines 104 are basically overlapped, so as to improve the signal transmission accuracy of the row address signal line 104.

[0107] Another embodiment of the present disclosure further provides a memory including the layout structure of the aforementioned row decoding circuit, so as to improve the signal transmission accuracy of the row address signal line 104 through the layout structure of the row decoding circuit, thereby improving the signal transmission accuracy of the row address signal line 104 in the memory.

[0108] In some embodiments, the memory may be a DDR memory, such as a DDR4 memory, a DDR5 memory, a DDR6 memory, a LPDDR4 memory, a LPDDR5 memory, or a LPDDR6 memory.

[0109] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, so the protection scope of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A layout structure of a row decoding circuit, characterized in that: include: A row decoding circuit, the row decoding circuit comprising a pre-decoding circuit, a buffer circuit and a row address comparison circuit, wherein the pre-decoding circuit comprises a plurality of pre-decoding sub-circuits, the buffer circuit comprises a plurality of buffer sub-circuits, and the row address comparison circuit comprises a plurality of row address comparison sub-circuits; A plurality of row address signal lines located in the first wiring layer are arranged at intervals along a first direction and extend along a second direction, each of the row address signal lines is electrically connected to a corresponding pre-decoding sub-circuit and a corresponding buffer sub-circuit, the plurality of row address signal lines are divided into first row address signal lines and second row address signal lines, the number of the pre-decoding sub-circuits electrically connected to the first row address signal line is greater than the number of the pre-decoding sub-circuits electrically connected to the second row address signal line, and the first direction and the second direction intersect; A plurality of buffer data lines located in the second wiring layer are arranged at intervals along the first direction and extend along the second direction, each of the buffer data lines being electrically connected to a corresponding buffer subcircuit and a corresponding row address comparison subcircuit; Among them, the overlapping area of ​​the orthographic projections of the first row address signal line and the buffer data line on the second wiring layer is a first area, and the overlapping area of ​​the orthographic projections of the second row address signal line and the buffer data line on the second wiring layer is a second area, and the first area is smaller than the second area.

2. The layout structure according to claim 1, characterized in that: The buffer subcircuit receives a row address signal and outputs a first buffer signal and a second buffer signal; the buffer data line includes a first buffer data line and a second buffer data line, one of the second row address signal lines overlaps with an orthographic projection of at least one of the second buffer data lines on the second wiring layer, and / or one of the second row address signal lines overlaps with an orthographic projection of at least one of the first buffer data lines on the second wiring layer.

3. The layout structure according to claim 2, characterized in that: In one of the second row address signal lines and one of the second buffer data lines overlapped by the orthographic projection on the second wiring layer, the buffer subcircuit outputs the second buffer signal transmitted by the second buffer data line based on the row address signal transmitted by the second row address signal line; or, In one of the second row address signal lines and one of the first buffer data lines whose orthographic projections overlap on the second wiring layer, the buffer subcircuit outputs the first buffer signal transmitted by the first buffer data line based on the row address signal transmitted by the second row address signal line.

4. The layout structure according to claim 2, characterized in that: The orthographic projection of one of the second buffer data lines on the second wiring layer is located in the orthographic projection of one of the second row address signal lines on the second wiring layer; or, the orthographic projection of one of the first buffer data lines on the second wiring layer is located in the orthographic projection of one of the second row address signal lines on the second wiring layer.

5. The arrangement structure according to any one of claims 1 to 4, characterized in that: The first area is zero.

6. The layout structure according to claim 5, characterized in that: The orthographic projection of the first row address signal line on the second wiring layer is a first projection, the first projection is located between the two orthographic projections of the two buffer data lines on the second wiring layer, and there is a gap between the first projection and the two orthographic projections of the two buffer data lines on the second wiring layer.

7. The layout structure according to claim 6, characterized in that: Among the two buffered data lines whose direct projections on the second wiring layer are located on both sides of the first projection along the first direction and the first row address signal line corresponding to the first projection, the two buffered data lines include a first buffered data line and a second buffered data line, and the buffer subcircuit outputs a first buffered signal transmitted by the first buffered data line based on the row address signal transmitted by the first row address signal line, and outputs a second buffered signal transmitted by the second buffered data line.

8. The arrangement according to any one of claims 1 to 4 or 6 to 7, characterized in that: Along the first direction, each of the first row address signal lines and each of the second row address signal lines are arranged alternately.

9. The arrangement according to any one of claims 1 to 4 or 6 to 7, characterized in that: Along the first direction, there is an orthographic projection of the buffer data line on the second wiring layer between the two orthographic projections of two adjacent row address signal lines on the second wiring layer, and there is an orthographic projection of the buffer data line on the second wiring layer in the orthographic projection of one of the second row address signal lines on the second wiring layer.

10. The arrangement according to any one of claims 1 to 4 or 6 to 7, characterized in that: The sum of the number of the first row address signal lines and the number of the second row address signal lines is 13.

11. The arrangement according to any one of claims 1 to 4 or 6 to 7, characterized in that: The buffer sub-circuits correspond to the row address comparison sub-circuits one-to-one, and along the second direction, each of the buffer sub-circuits and each of the row address comparison sub-circuits are arranged alternately.

12. The layout structure according to claim 11, characterized in that: There is at least one pre-decoding sub-circuit between two adjacent row address comparison sub-circuits.

13. The layout structure according to claim 11, characterized in that: The area where the row address comparison subcircuit is located is the first area, the area where the row decoding circuit is located is the second area, the second area includes a plurality of the first areas arranged at intervals along the second direction, the row address signal line runs through the second area, and the buffer data line runs through a corresponding one of the first areas.

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