Chip carrier plate preparation method, chip carrier plate and chip packaging structure

Abstract

The invention relates to a preparation method of a chip support plate, the chip support plate and a chip packaging structure, the preparation method comprises the following steps: providing a first base material and a second base material, the first base material is provided with a first through hole, the second base material is provided with a second through hole, and the first base material and the second base material comprise an inorganic material; a first conductive part is formed on the first base material, a second conductive part is formed on the second base material, part of the first conductive part is filled in the first through hole, and part of the second conductive part is filled in the second through hole; and bonding and connecting the first base material and the second base material, wherein the first conductive part in the first through hole is butted with the second conductive part in the second through hole. The chip carrier plate in the scheme is not easy to expand and warp, has higher structural reliability, and better meets the high-precision wiring requirement of the chip.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a method for preparing a chip carrier, a chip carrier and a chip packaging structure. Background Art

[0002] Integrated chip carriers can provide electrical interconnection, protection, support, heat dissipation, assembly and other functions for chips. As a bridge connecting chips and PCB circuit boards, chip carriers are one of the key raw materials for packaging products in the integrated circuit industry.

[0003] The core material of the chip carrier is usually made of organic material, for example, it can be a hard material or a flexible material. With the development trend of high-end chip carriers, organic substrates will reach the limit of their capabilities in the next few years. The current organic materials of organic packaging carriers are easy to expand and warp obviously. Therefore, it is difficult to meet the requirements of high-precision wiring, and there is a problem that it cannot meet the packaging needs of the next generation of semiconductor chips. Summary of the invention

[0004] The embodiments of the present invention provide a method for preparing a chip carrier, a chip carrier and a chip packaging structure. The chip carrier is not prone to expansion and warping, has higher structural reliability, and better meets the high-precision wiring requirements of the chip.

[0005] In a first aspect, a method for preparing a chip carrier is provided according to an embodiment of the present invention, comprising:

[0006] Providing a first substrate and a second substrate, wherein the first substrate has a first through hole, the second substrate has a second through hole, and the first substrate and the second substrate include inorganic materials;

[0007] Forming a first conductive portion on the first substrate, forming a second conductive portion on the second substrate, partially filling the first through hole with the first conductive portion, and partially filling the second through hole with the second conductive portion;

[0008] The first substrate and the second substrate are bonded and connected, and the first conductive portion in the first through hole is butted against the second conductive portion in the second through hole.

[0009] According to one aspect of an embodiment of the present invention, before the step of forming the first conductive portion on the first substrate, the preparation method further includes:

[0010] providing an intermediate plate, wherein a temporary bonding layer is disposed on a surface of the intermediate plate;

[0011] connecting the first substrate and / or the second substrate to the temporary bonding layer;

[0012] Preferably, before the step of bonding the first substrate and the second substrate, the preparation method further comprises:

[0013] The first substrate and / or the second substrate is separated from the temporary bonding layer.

[0014] According to one aspect of an embodiment of the present invention, an intermediate board is provided, and the step of forming a temporary bonding layer on a surface of the intermediate board includes:

[0015] forming a temporary bonding layer on one side surface of the intermediate plate;

[0016] Preferably, the steps of forming the first conductive portion on the first substrate and forming the second conductive portion on the second substrate include:

[0017] connecting the first substrate to the temporary bonding layer to form a first conductive portion on the first substrate;

[0018] separating the first substrate and the temporary bonding layer;

[0019] The second substrate is connected to the temporary bonding layer to form a second conductive portion on the second substrate.

[0020] According to one aspect of the embodiment of the present invention, the step of forming the first conductive portion on the first substrate and forming the second conductive portion on the second substrate further includes:

[0021] Forming a first insulating portion on the first substrate, forming a second insulating portion on the second substrate, wherein the first insulating portion covers the first conductive portion, and the second insulating portion covers the second conductive portion;

[0022] Preferably, the step of forming the first insulating portion on the first substrate includes:

[0023] Forming a first metal layer on the first substrate and patterning the first metal layer, with a portion of the first metal layer filling the first through hole;

[0024] forming a first insulating layer on the first substrate, wherein the first insulating layer covers the first metal layer;

[0025] forming a first via hole on the first insulating layer, wherein the first metal layer at the position of the first via hole is exposed at the first via hole;

[0026] Forming a second metal layer on a side of the first insulating layer away from the first metal layer and patterning the second metal layer, wherein a portion of the second metal layer is filled in the first via hole and connected to the first metal layer;

[0027] The first metal layer and the second metal layer together form a first conductive portion, and the first insulating portion includes a first insulating layer.

[0028] According to one aspect of an embodiment of the present invention, an intermediate board is provided, and the step of forming a temporary bonding layer on a surface of the intermediate board includes:

[0029] forming temporary bonding layers on both side surfaces of the intermediate plate;

[0030] The steps of forming a first conductive portion on a first substrate and forming a second conductive portion on a second substrate include:

[0031] Connecting one of the first substrate and the second substrate to the temporary bonding layer on one side of the intermediate plate, and connecting the other to the temporary bonding layer on the other side of the intermediate plate;

[0032] A metal layer is formed and patterned on the first substrate and the second substrate simultaneously to form a first conductive portion on the first substrate and a second conductive portion on the second substrate.

[0033] According to one aspect of the embodiments of the present invention, before the step of bonding the first substrate to the second substrate, the preparation method further includes:

[0034] performing grinding and cleaning treatments on the bonding surface of the first substrate and the bonding surface of the second substrate respectively;

[0035] Preferably, the aperture of the first through hole is smaller than that of the second through hole, and the orthographic projection of the first conductive portion in the first through hole in its thickness direction is located within the orthographic projection of the second conductive portion in the second through hole.

[0036] According to one aspect of the embodiment of the present invention, the orthographic projection of the first convex portion in the thickness direction of the first convex portion is located within the orthographic projection of the second convex portion.

[0037] In a second aspect, a chip carrier is provided according to an embodiment of the present invention, comprising a substrate and a conductor layer, the substrate comprising a first substrate and a second substrate butted against each other, the first substrate having a first through hole and the second substrate having a second through hole, the first through hole and the second through hole being arranged in alignment, and the first substrate and the second substrate comprising inorganic materials; the conductor layer comprising a first conductive portion and a second conductive portion, the first conductive portion being arranged on a side of the first substrate away from the second substrate and partially located in the first through hole, the second conductive portion being arranged on a side of the second substrate away from the first substrate and partially located in the second through hole.

[0038] According to one aspect of an embodiment of the present invention, a chip carrier includes a dielectric layer, the dielectric layer includes a first insulating portion and a second insulating portion, the first insulating portion is arranged on a side of the first substrate facing away from the second substrate and covers the first conductive portion, and the second insulating portion is arranged on a side of the second substrate facing away from the first substrate and covers the second conductive portion;

[0039] Preferably, the chip carrier includes a connecting portion, the connecting portion includes a first convex portion and a second convex portion, the first convex portion is connected to the first conductive portion and protrudes from the first conductive portion, and the second convex portion is connected to the second conductive portion and protrudes from the second conductive portion.

[0040] In a third aspect, a chip packaging structure is provided according to an embodiment of the present invention, comprising a circuit board, a chip and a chip carrier as described above, wherein the chip carrier is connected to the circuit board via a second conductive portion; the chip is arranged on a side of the chip carrier away from the circuit board, and the chip carrier is connected to the chip via a first conductive portion.

[0041] The embodiments of the present invention provide a method for preparing a chip carrier, a chip carrier and a chip packaging structure, wherein a first conductive portion and a first insulating portion are formed on a first substrate, a second conductive portion and a second insulating portion are formed on a second substrate, and finally the first substrate and the second substrate are bonded to obtain an overall structure of the chip carrier. Since the middle core material portion of the chip carrier is an inorganic material of the first substrate and the second substrate, the inorganic material properties are utilized to make the chip carrier less prone to expansion and warping, and the chip carrier has higher structural reliability. The surface of the inorganic material is smoother, and the high-precision wiring requirements of the chip are better met. The product has better high-frequency performance, and the overall performance of the chip carrier is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Features, advantages, and technical effects of exemplary embodiments of the present invention will be described below with reference to the accompanying drawings.

[0043] Figure 1 is a flow chart of a method for preparing a chip carrier according to an embodiment of the present invention;

[0044] Figure 2 is a schematic structural diagram of a chip carrier according to an embodiment of the present invention;

[0045] Figure 3 It is a structural diagram of a chip carrier board preparation process according to an embodiment of the present invention;

[0046] Figure 4 It is a structural diagram of a chip carrier board preparation process according to an embodiment of the present invention;

[0047] Figure 5 It is a structural diagram of a chip carrier board preparation process according to an embodiment of the present invention;

[0048] Figure 6 It is a structural diagram of a chip carrier board preparation process according to an embodiment of the present invention;

[0049] Figure 7 It is a structural diagram of a chip carrier board preparation process according to an embodiment of the present invention;

[0050] Figure 8 It is a structural diagram of a chip carrier board preparation process according to an embodiment of the present invention;

[0051] Fig. 9 is a schematic structural diagram of a chip carrier according to an embodiment of the present invention;

[0052] Fig.10 is a schematic structural diagram of another chip carrier according to an embodiment of the present invention;

[0053] Fig.11 is a schematic structural diagram of another chip carrier according to an embodiment of the present invention;

[0054] Fig.12 It is a schematic diagram of a chip packaging structure according to an embodiment of the present invention.

[0055] Reference numerals:

[0056] 100-chip carrier; 1-first through hole; 2-second through hole;

[0057] 10-first substrate; 11-first conductive portion; 12-first insulating portion; 13-first convex portion;

[0058] 20-second substrate; 21-second conductive portion; 22-second insulating portion; 23-second convex portion;

[0059] 30-intermediate plate; 31-temporary bonding layer;

[0060] 11a-first metal layer; 11b-second metal layer; 12a-first insulating layer; 11c-first via hole;

[0061] 200-chip; 300-circuit board; 400-plastic sealing layer.

[0062] In the drawings, the same reference numerals are used for the same components. The drawings are not drawn to scale. DETAILED DESCRIPTION

[0063] The features and exemplary embodiments of various aspects of the present invention will be described in detail below. In the detailed description below, many specific details are proposed in order to provide a comprehensive understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without some of these specific details. The following description of the embodiments is only to provide a better understanding of the present invention by illustrating examples of the present invention. In the drawings and the following description, at least part of the known structures and technologies are not shown in order to avoid unnecessary ambiguity of the present invention; and, for clarity, the size of some structures may be exaggerated. In addition, the features, structures or characteristics described below may be combined in one or more embodiments in any suitable manner.

[0064] The directional words appearing in the following description are all directions shown in the figures, and do not limit the specific structures of the chip carrier preparation method, chip carrier and chip packaging structure of the present invention. In the description of the present invention, it should also be noted that, unless otherwise clearly specified and limited, the terms "installation" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0065] In order to better understand the present invention, Figures 1 to 12 The chip carrier manufacturing method, the chip carrier and the chip packaging structure according to the embodiments of the present invention are described in detail.

[0066] See also Figures 1 to 9 According to an embodiment of the present invention, a method for preparing a chip carrier 100 is provided, comprising:

[0067] S1, providing a first substrate 10 and a second substrate 20, wherein the first substrate 10 has a first through hole 1, the second substrate 20 has a second through hole 2, and the first substrate 10 and the second substrate 20 include inorganic materials;

[0068] S2, forming a first conductive portion 11 on the first substrate 10, forming a second conductive portion 21 on the second substrate 20, a portion of the first conductive portion 11 is filled in the first through hole 1, and a portion of the second conductive portion 21 is filled in the second through hole 2;

[0069] S3 , bonding the first substrate 10 and the second substrate 20 together, so that the first conductive portion 11 in the first through hole 1 is butted against the second conductive portion 21 in the second through hole 2 .

[0070] In step S1 , the first substrate 10 and the second substrate 20 provided are inorganic materials, such as glass materials. The first substrate 10 is set as a first glass plate, and the second substrate 20 is set as a second glass plate, thereby replacing the currently used organic materials.

[0071] Of course, some inorganic fillers can also be added to the organic resin material, for example, inorganic materials such as SiO2 can be added, so that the first substrate 10 and the second substrate 20 form an organic composite material, which can also overcome the disadvantage of easy expansion and warping of organic materials and improve the structural strength of the first substrate 10 and the second substrate 20.

[0072] For the first through hole 1 on the first substrate 10 and the second through hole 2 on the second substrate 20, laser induced wet etching method can be preferably used, and laser melting, focused discharge method, plasma etching method, electrochemical discharge machining method, etc. can also be used. The present application does not specifically limit the specific forming method of the first through hole 1 and the second through hole 2.

[0073] In step S2, a first conductive portion 11 and a first insulating portion 12 are formed on the first substrate 10, and a second conductive portion 21 and a second insulating portion 22 are formed on the second substrate 20. The first conductive portion 11 and the second conductive portion 21 may be made of metal to form metal traces for conducting electrical signals. For example, the metal may be copper (Cu), aluminum (Al), nickel (Ni), etc. The present application does not specifically limit the specific metal type.

[0074] Optionally, the first insulating part 12 and the second insulating part 22 can be made of organic materials, and the first through hole 1 and the second through hole 2 are filled with the corresponding first conductive part 11 and second conductive part 21 respectively through physical vapor deposition (PVD) sputtering and electroplating, and then the first insulating part 12 is coated on the first conductive part 11, and the second insulating part 22 is coated on the second conductive part 21 through a deposition process.

[0075] In step S3, the first substrate 10 and the second substrate 20 are bonded specifically by heterogeneous silicon dioxide (SiO2) and metal copper (Cu), or by laser bonding, so as to form the chip carrier 100 as a whole. It is necessary to make the first conductive part 11 and the second conductive part 21 in the respective through holes be connected to form a current path to achieve signal conduction between the chip 200 and the circuit board 300.

[0076] An embodiment of the present invention provides a method for preparing a chip carrier 100, by forming a first conductive portion 11 and a first insulating portion 12 on a first substrate 10, forming a second conductive portion 21 and a second insulating portion 22 on a second substrate 20, and finally bonding the first substrate 10 and the second substrate 20 to obtain the overall structure of the chip carrier 100. Since the middle core material portion of the chip carrier 100 is an inorganic material of the first substrate 10 and the second substrate 20, the inorganic material properties are utilized to make the chip carrier 100 less prone to expansion and warping, and has higher structural reliability. The surface of the inorganic material is smoother, which better meets the high-precision wiring requirements of the chip 200, and the product has better high-frequency performance, thereby improving the overall performance of the chip carrier 100.

[0077] As an alternative embodiment, see Figures 4 to 9 Before the step of forming the first conductive portion 11 on the first substrate 10, the preparation method further includes:

[0078] Providing an intermediate plate 30, on the surface of which a temporary bonding layer 31 is provided;

[0079] Connecting the first substrate 10 and / or the second substrate 20 to the temporary bonding layer 31;

[0080] Before the step of bonding the first substrate 10 and the second substrate 20, the preparation method further includes:

[0081] The first substrate 10 and / or the second substrate 20 is separated from the temporary bonding layer 31 .

[0082] Optionally, the intermediate plate 30 serves as a temporary carrier plate and can be made of glass, ceramic or metal. In this embodiment, a temporary bonding layer 31 needs to be set on the surface of the intermediate plate 30. The temporary bonding layer 31 can be an organic polymer adhesive, such as a temporary bonding glue, etc., and can specifically include polymers such as resins, deposition films or epoxy resins, etc. During molding, it can be deposited on the surface of the intermediate plate 30 by using an extrusion printing process or other suitable material deposition process.

[0083] Taking the first substrate 10 as an example, before forming the first conductive portion 11 and the first insulating portion 12 on the first substrate 10, the first substrate 10 can be connected to the intermediate plate 30 through a temporary bonding layer 31, so that the deposition of the first conductive portion 11 and the first insulating portion 12 are both carried out on the intermediate plate 30.

[0084] After the deposition process of the first substrate 10 and the second substrate 20 is completed using the intermediate plate 30, before the first substrate 10 and the second substrate 20 need to be butt-bonded, the two need to be separated from the temporary bonding layer 31 on the intermediate plate 30 and a debonding process needs to be performed.

[0085] An embodiment of the present invention provides a method for preparing a chip carrier 100. After physically bonding a substrate with through holes to an intermediate plate 30, a blind hole filling process can be used in subsequent processes to fill the conductive part, thereby reducing the difficulty of the through hole filling process and facilitating completion of the deposition process for the first substrate 10 and the second substrate 20.

[0086] As an optional embodiment, an intermediate plate 30 is provided, and the step of forming a temporary bonding layer 31 on the surface of the intermediate plate 30 includes:

[0087] A temporary bonding layer 31 is formed on one side surface of the intermediate plate 30;

[0088] The steps of forming the first conductive portion 11 on the first substrate 10 and forming the second conductive portion 21 on the second substrate 20 include:

[0089] Connecting the first substrate 10 to the temporary bonding layer 31 to form a first conductive portion 11 on the first substrate 10;

[0090] Separating the first substrate 10 and the temporary bonding layer 31;

[0091] The second substrate 20 is connected to the temporary bonding layer 31 , and the second conductive portion 21 is formed on the second substrate 20 .

[0092] In this embodiment, a temporary bonding layer 31 is firstly provided on one side of the intermediate plate 30, which can be formed by using an extrusion printing process or other suitable material deposition process. When the first substrate 10 and the second substrate 20 need to be deposited, the first substrate 10 is first bonded to the temporary bonding layer 31, and the first conductive portion 11 and the first insulating portion 12 are sequentially deposited on the first substrate 10.

[0093] After the deposition process of the first substrate 10 is completed, the first substrate 10 is separated from the intermediate plate 30, that is, the first substrate 10 and the temporary bonding layer 31 are debonded, and then the second substrate 20 is bonded to the intermediate plate 30, and then the second conductive part 21 and the second insulating part 22 are deposited on the second substrate 20, thereby realizing the step-by-step independent molding of the first substrate 10 and the second substrate 20.

[0094] An embodiment of the present invention provides a method for preparing a chip carrier 100. By performing deposition processes on a first substrate 10 and a second substrate 20 respectively, the first substrate 10 and the second substrate 20 are separately formed, and finally the chip carrier 100 as a whole is obtained by docking and bonding the two. Independent forming reduces the complexity of the process and facilitates the forming of the entire carrier.

[0095] As an alternative embodiment, see Figure 6 The steps of forming the first conductive portion 11 on the first substrate 10 and forming the second conductive portion 21 on the second substrate 20 further include:

[0096] A first insulating portion 12 is formed on the first substrate 10 , and a second insulating portion 22 is formed on the second substrate 20 . The first insulating portion 12 covers the first conductive portion 11 , and the second insulating portion 22 covers the second conductive portion 21 .

[0097] Optionally, the step of forming the first insulating portion 12 on the first substrate 10 includes:

[0098] A first metal layer 11a is formed on the first substrate 10 and patterned, and a portion of the first metal layer 11a is filled in the first through hole 1;

[0099] A first insulating layer 12a is formed on the first substrate 10, and the first insulating layer 12a covers the first metal layer 11a;

[0100] A first via hole 11c is formed on the first insulating layer 12a, and the first metal layer 11a at the position of the first through hole 1 is exposed at the first via hole 11c;

[0101] A second metal layer 11b is formed on a side of the first insulating layer 12a away from the first metal layer 11a and the second metal layer 11b is patterned, and a portion of the second metal layer 11b is filled in the first via hole 11c and connected to the first metal layer 11a;

[0102] The first metal layer 11 a and the second metal layer 11 b together form the first conductive portion 11 , and the first insulating portion 12 includes a first insulating layer 12 a .

[0103] In the specific forming process of the first conductive part 11 and the first insulating part 12, the first metal layer 11a can be firstly formed on the first substrate 10 by sputtering through a physical vapor deposition (PVD) process, and part of the first metal layer 11a is deposited in the first through hole 1. Then, a photoresist can be coated on its surface for exposure and development, and a patterned first metal layer 11a is formed after photoresist stripping.

[0104] Then, a first insulating layer 12a is prepared on the first metal layer 11a by coating and lamination. Optionally, the first insulating layer 12a can be an organic dielectric layer, so that the first insulating layer 12a covers the first metal layer 11a, and a first via hole 11c is formed by etching on the first insulating layer 12a. The first metal layer 11a needs to be exposed at the first via hole 11c.

[0105] The second metal layer 11b is deposited on the first insulating layer 12a, and patterning is performed according to the above etching process. The second metal layer 11b deposited in the first via hole 11c is connected to the first metal layer 11a in the hole, thereby forming the conduction of the electrical signal. Similarly, the number of metal wiring layers can be selected according to different actual needs, and the wiring line width can be different. In this embodiment, two metal layers are set as an example for description, but this is not limited to this.

[0106] It can be seen that in this embodiment, the first conductive portion 11 on the first substrate 10 specifically includes the first metal layer 11a and the second metal layer 11b, and the first insulating portion 12 specifically includes the first insulating layer 12a therebetween. Similarly, the second conductive portion 21 and the second insulating portion 22 formed on the second substrate 20 are the same, and can be formed according to the same process steps as above, which will not be repeated here.

[0107] An embodiment of the present invention provides a method for preparing a chip carrier 100. By depositing a plurality of metal layers and insulating layers on a substrate, the design can be performed according to the actual number of layers required, thereby improving the diversity of the product, enabling it to better adapt to the different needs of users, meet more practical needs, and have better adaptability.

[0108] As an alternative embodiment, see Figures 3 to 9 , providing an intermediate plate 30, and forming a temporary bonding layer 31 on the surface of the intermediate plate 30 includes:

[0109] A temporary bonding layer 31 is formed on both side surfaces of the intermediate plate 30;

[0110] The steps of forming the first conductive portion 11 on the first substrate 10 and forming the second conductive portion 21 on the second substrate 20 include:

[0111] Connect one of the first substrate 10 and the second substrate 20 to the temporary bonding layer 31 on one side of the intermediate plate 30, and connect the other to the temporary bonding layer 31 on the other side of the intermediate plate 30;

[0112] Metal layers are formed and patterned on the first substrate 10 and the second substrate 20 simultaneously to form a first conductive portion 11 on the first substrate 10 and a second conductive portion 21 on the second substrate 20 .

[0113] In this embodiment, temporary bonding layers 31 are respectively provided on both side surfaces of the intermediate plate 30, which can be formed by using an extrusion printing process or other suitable material deposition process. Therefore, the first substrate 10 and the second substrate 20 can be respectively bonded to the two side surfaces of the intermediate plate 30, providing a basis for subsequent deposition processes.

[0114] Subsequently, a plurality of metal layers and insulating layers may be deposited and patterned on the side of the first substrate 10 according to the above process to obtain a first conductive portion 11 and a first insulating portion 12; at the same time, a plurality of metal layers and insulating layers may be deposited and patterned on the second substrate 20 on the other side of the intermediate plate 30 according to the above process to obtain a second conductive portion 21 and a second insulating portion 22.

[0115] After completing the above-mentioned molding process, the first substrate 10 and the second substrate 20 need to be separated from the intermediate plate 30 respectively, that is, they need to be debonded from the temporary bonding layer 31 respectively, and finally the first substrate 10 and the second substrate 20 are bonded and connected to obtain the overall structure of the chip carrier 100.

[0116] The embodiment of the present invention provides a method for preparing a chip carrier 100. By simultaneously arranging temporary bonding layers 31 on both sides of an intermediate plate 30 and simultaneously bonding and connecting the intermediate plate 30 to a first substrate 10 and a second substrate 20, the surfaces on both sides of the intermediate plate 30 are fully utilized, and the conductive parts and insulating parts of the first substrate 10 and the second substrate 20 are deposited and formed simultaneously, thereby simplifying the process steps, speeding up the forming process, improving production efficiency, reducing production costs, and having better convenience.

[0117] As an optional embodiment, before the step of bonding the first substrate 10 and the second substrate 20, the preparation method further includes:

[0118] The bonding surface of the first substrate 10 and the bonding surface of the second substrate 20 are polished and cleaned respectively.

[0119] An embodiment of the present invention provides a method for preparing a chip carrier 100, by grinding and cleaning the bonding surfaces of the first substrate 10 and the second substrate 20 after deposition and forming, respectively, so that the bonding surfaces of the two are made into smoother surfaces, which is beneficial to the bonding connection of the first substrate 10 and the second substrate 20 and improves the structural reliability of the two after the bonding connection.

[0120] As an optional embodiment, the aperture of the first through hole 1 is smaller than that of the second through hole 2 , and the orthographic projection of the first conductive portion 11 in the first through hole 1 in its thickness direction is located within the orthographic projection of the second conductive portion 21 in the second through hole 2 .

[0121] In the present embodiment, during the process of etching the first substrate 10 and the second substrate 20, the aperture of the first through hole 1 is made smaller than the aperture of the second through hole 2. The purpose is to enable the first through hole 1 and the second through hole 2 to form a reliable connection during the subsequent bonding of the first substrate 10 and the second substrate 20, wherein the first conductive portion 11 and the second conductive portion 21 can form a larger contact area and have better contact performance, which is conducive to the conduction of electrical signals. The present application does not specifically limit the specific sizes of the first through hole 1 and the second through hole 2.

[0122] An embodiment of the present invention provides a method for preparing a chip carrier 100. By making the aperture of the first through hole 1 smaller than the aperture of the second through hole 2, the first substrate 10 and the second substrate 20 have higher precision during the bonding process, ensuring that the first conductive portion 11 and the second conductive portion 21 can form reliable contact, thereby improving the stability of electrical signal conduction.

[0123] As an alternative embodiment, see Figures 9 to 11 , before the step of bonding the first substrate 10 and the second substrate 20, the method further includes:

[0124] The first protrusion 13 is connected to the side of the first conductive portion 11 facing away from the first substrate 10 , and the second protrusion 23 is connected to the side of the second conductive portion 21 facing away from the second substrate 20 .

[0125] Optionally, the orthographic projection of the first convex portion 13 in the thickness direction thereof is located within the orthographic projection of the second convex portion 23 .

[0126] In the above steps, the first protrusion 13 can be a copper column, and its function is to form a docking with the chip 200. The first protrusion 13 can be connected to the position of the first conductive part 11 through a welding process, thereby forming a current path; the second protrusion 23 is preferably a solder ball bump, and its material can be metal tin (Sn), tin-silver alloy (SnAg), metal copper (Cu) and tin-silver alloy (SnAg), metal copper (Cu) and metal nickel (Ni) and tin-silver alloy (SnAg), etc., and the manufacturing process can be electroplating, printing, ball planting, etc., and its function is to form a docking with the bottom PCB circuit board 300, and the second protrusion 23 is connected to the second conductive part 21.

[0127] Considering that the chip carrier 100 is connected to the chip 200 through the first protrusion 13 and to the circuit board 300 through the second protrusion 23, and the bonding point of the chip 200 is smaller and more delicate than that of the circuit board 300, therefore, in this embodiment, in order to adapt to the structural characteristics of the chip 200 and the circuit board 300, the size of the first protrusion 13 is set to be smaller than the size of the second protrusion 23, and the application does not specifically limit the specific size and structural form of the first protrusion 13 and the second protrusion 23.

[0128] Optionally, the obtained first substrate 10 and the second substrate 20 can be arranged and combined, that is, the substrates with protrusions of different sizes can be combined, and then the two can be bonded. The sizes of the obtained first protrusion 13 and the second protrusion 23 can be the same or different to meet different connection requirements, such as Figures 9 to 11 shown.

[0129] An embodiment of the present invention provides a method for preparing a chip carrier 100. By controlling the sizes of the first protrusion 13 and the second protrusion 23, it can better adapt to the structure of the chip 200 and the circuit board 300 connected thereto, improve the accuracy and reliability of the connection between the chip carrier 100 and the chip 200 and the circuit board 300, and have better structural characteristics.

[0130] See also Fig. 9According to an embodiment of the present invention, a chip carrier 100 is provided, comprising a substrate, a conductor layer, a dielectric layer and a connecting portion, wherein the substrate comprises a first substrate 10 and a second substrate 20 butted against each other, the first substrate 10 has a first through hole 1 and the second substrate 20 has a second through hole 2, the first through hole 1 and the second through hole 2 are arranged in alignment, and the first substrate 10 and the second substrate 20 comprise inorganic materials; the conductor layer comprises a first conductive portion 11 and a second conductive portion 21, the first conductive portion 11 is arranged on a side of the first substrate 10 away from the second substrate 20 and is partially located in the first through hole 1, and the second conductive portion 21 is arranged on the second substrate 10 The dielectric layer 20 is on a side away from the first substrate 10 and is partially located in the second through hole 2; the dielectric layer includes a first insulating portion 12 and a second insulating portion 22, the first insulating portion 12 is arranged on a side of the first substrate 10 away from the second substrate 20 and covers the first conductive portion 11, and the second insulating portion 22 is arranged on a side of the second substrate 20 away from the first substrate 10 and covers the second conductive portion 21; the connecting portion includes a first convex portion 13 and a second convex portion 23, the first convex portion 13 is connected to the first conductive portion 11 and protrudes from the first conductive portion 11, and the second convex portion 23 is connected to the second conductive portion 21 and protrudes from the second conductive portion 21.

[0131] See also Fig.12 According to an embodiment of the present invention, a chip 200 packaging structure is provided, including a circuit board 300, a chip 200 and the chip carrier 100 as described above, the chip carrier 100 is connected to the circuit board 300 through the second protrusion 23; the chip 200 is arranged on the side of the chip carrier 100 away from the circuit board 300, and the chip carrier 100 is connected to the chip 200 through the first protrusion 13.

[0132] In this embodiment, the chip carrier 100 is arranged between the chip 200 and the circuit board 300. The chip carrier 100 plays a bearing role and serves as a bridge connecting the chip 200 and the circuit board 300 to provide electrical interconnection, protection, support, heat dissipation, assembly and other functions for the chip 200.

[0133] Optionally, a plastic encapsulation layer 400 may be provided in the packaging structure, and the chip 200 may be surrounded by the plastic encapsulation layer 400 , thereby isolating and protecting the chip 200 and preventing water and oxygen impurities in the external environment from adversely affecting the chip 200 .

[0134] The embodiments of the present invention provide a method for preparing a chip carrier, a chip carrier and a chip packaging structure, wherein a first conductive portion and a first insulating portion are formed on a first substrate, a second conductive portion and a second insulating portion are formed on a second substrate, and finally the first substrate and the second substrate are bonded to obtain an overall structure of the chip carrier. Since the middle core material portion of the chip carrier is an inorganic material of the first substrate and the second substrate, the inorganic material properties are utilized to make the chip carrier less prone to expansion and warping, and the chip carrier has higher structural reliability. The surface of the inorganic material is smoother, and the high-precision wiring requirements of the chip are better met. The product has better high-frequency performance, and the overall performance of the chip carrier is improved.

[0135] Although the present invention has been described with reference to preferred embodiments, various modifications may be made thereto and parts thereof may be replaced by equivalents without departing from the scope of the present invention. In particular, the various technical features mentioned in the various embodiments may be combined in any manner as long as there are no structural conflicts. The present invention is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A method for preparing a chip carrier, characterized in that: include: Providing a first substrate and a second substrate, wherein the first substrate has a first through hole, the second substrate has a second through hole, and the first substrate and the second substrate include an inorganic material; forming a first conductive portion on the first substrate, and forming a second conductive portion on the second substrate, wherein a portion of the first conductive portion is filled in the first through hole, and a portion of the second conductive portion is filled in the second through hole; The first substrate and the second substrate are bonded and connected, and the first conductive portion in the first through hole is butted against the second conductive portion in the second through hole.

2. The preparation method according to claim 1, characterized in that: Before the step of forming the first conductive portion on the first substrate, the preparation method further includes: providing an intermediate plate, wherein a temporary bonding layer is disposed on a surface of the intermediate plate; connecting the first substrate and / or the second substrate to the temporary bonding layer; Preferably, before the step of bonding the first substrate and the second substrate, the preparation method further comprises: The first substrate and / or the second substrate is separated from the temporary bonding layer.

3. The preparation method according to claim 2, characterized in that: The step of providing an intermediate plate and forming a temporary bonding layer on the surface of the intermediate plate comprises: forming the temporary bonding layer on one side surface of the intermediate plate; Preferably, the step of forming the first conductive portion on the first substrate and the step of forming the second conductive portion on the second substrate comprises: connecting the first substrate to the temporary bonding layer to form the first conductive portion on the first substrate; separating the first substrate and the temporary bonding layer; The second substrate is connected to the temporary bonding layer to form the second conductive portion on the second substrate.

4. The preparation method according to claim 3, characterized in that: The step of forming a first conductive portion on the first substrate and forming a second conductive portion on the second substrate further includes: forming a first insulating portion on the first substrate, and forming a second insulating portion on the second substrate, wherein the first insulating portion covers the first conductive portion, and the second insulating portion covers the second conductive portion; Preferably, the step of forming the first insulating portion on the first substrate includes: forming a first metal layer on the first substrate and patterning the first metal layer, wherein a portion of the first metal layer is filled in the first through hole; forming a first insulating layer on the first substrate, wherein the first insulating layer covers the first metal layer; forming a first via hole on the first insulating layer, wherein the first metal layer at the location of the first via hole is exposed at the first via hole; forming a second metal layer on a side of the first insulating layer away from the first metal layer and patterning the second metal layer, wherein a portion of the second metal layer is filled in the first via hole and connected to the first metal layer; The first metal layer and the second metal layer together form the first conductive portion, and the first insulating portion includes the first insulating layer.

5. The preparation method according to claim 2, characterized in that: The step of providing an intermediate plate and forming a temporary bonding layer on the surface of the intermediate plate comprises: forming the temporary bonding layer on both side surfaces of the intermediate plate; The step of forming the first conductive portion on the first substrate and the step of forming the second conductive portion on the second substrate comprises: Connecting one of the first substrate and the second substrate to the temporary bonding layer on one side of the intermediate plate, and connecting the other to the temporary bonding layer on the other side of the intermediate plate; Metal layers are formed and patterned on the first substrate and the second substrate simultaneously to form the first conductive portion on the first substrate and the second conductive portion on the second substrate.

6. The preparation method according to claim 1, characterized in that: Before the step of bonding the first substrate and the second substrate, the preparation method further comprises: performing grinding and cleaning treatments on the bonding surface of the first substrate and the bonding surface of the second substrate respectively; Preferably, the aperture of the first through hole is smaller than that of the second through hole, and the orthographic projection of the first conductive portion in the first through hole in its thickness direction is located within the orthographic projection of the second conductive portion in the second through hole.

7. The preparation method according to claim 1, characterized in that: Before the step of bonding the first substrate and the second substrate, the method further comprises: A first protrusion is connected to a side of the first conductive portion facing away from the first substrate, and a second protrusion is connected to a side of the second conductive portion facing away from the second substrate; Preferably, the orthographic projection of the first convex portion in its own thickness direction is located within the orthographic projection of the second convex portion.

8. A chip carrier, characterized in that: include: A substrate, comprising a first substrate and a second substrate butted against each other, the first substrate having a first through hole and the second substrate having a second through hole, the first through hole and the second through hole being arranged in alignment, and the first substrate and the second substrate comprising an inorganic material; The conductor layer includes a first conductive portion and a second conductive portion, wherein the first conductive portion is arranged on a side of the first substrate away from the second substrate and is partially located in the first through hole, and the second conductive portion is arranged on a side of the second substrate away from the first substrate and is partially located in the second through hole.

9. The chip carrier according to claim 8, characterized in that: The chip carrier includes a dielectric layer, the dielectric layer includes a first insulating portion and a second insulating portion, the first insulating portion is arranged on a side of the first substrate away from the second substrate and covers the first conductive portion, and the second insulating portion is arranged on a side of the second substrate away from the first substrate and covers the second conductive portion; Preferably, the chip carrier includes a connecting portion, the connecting portion includes a first convex portion and a second convex portion, the first convex portion is connected to the first conductive portion and protrudes from the first conductive portion, and the second convex portion is connected to the second conductive portion and protrudes from the second conductive portion.

10. A chip packaging structure, characterized in that: include: Circuit boards; The chip carrier according to any one of claims 8 to 9, wherein the chip carrier is connected to the circuit board via the second conductive portion; The chip is arranged on a side of the chip carrier away from the circuit board, and the chip carrier is connected to the chip through the first conductive part.

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