Gallium oxide monolithic heterogeneous integrated device and manufacturing method thereof

Abstract

The invention discloses a gallium oxide monolithic heterogeneous integrated device and a manufacturing method thereof, which can be used in the field of semiconductor devices, in the device, an N-type gallium oxide epitaxial wafer comprises an epitaxial layer and a substrate layer; one side of the epitaxial layer of the N-type gallium oxide epitaxial wafer is bonded with one side of the P-type material layer; the N-type doped region is arranged in the P-type material layer and is in contact with the epitaxial layer of the N-type gallium oxide epitaxial wafer; the gate control region covers the N-type doped region and is arranged on the other side of the P-type material layer; ohmic contact is formed between the source electrode and the P-type material layer. The drain electrode is arranged on one side of the substrate layer of the N-type gallium oxide epitaxial wafer and forms ohmic contact with the substrate layer; and the substrate layer is bonded with the drain electrode. Therefore, small-size gallium oxide is bonded to the substrate for tape-out, so that large-scale preparation of the device on a production line can be realized, and the heat dissipation performance of the gallium oxide device is improved; by bonding the N-type gallium oxide and the P-type material, a heterogeneous PN junction is formed to make up for a missing gallium oxide homogeneous PN junction, and the stability of the structure is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor devices, and in particular to a gallium oxide monolithic heterogeneous integrated device and a manufacturing method thereof. Background Art

[0002] Gallium oxide (Ga2O3) is a new type of ultra-wide bandgap semiconductor material with the advantages of ultra-wide bandgap, ultra-high breakdown field strength, ultra-strong transparent conductivity and radiation resistance. It is an ideal material for making high-voltage devices, radio frequency devices and solar-blind ultraviolet detectors.

[0003] Most existing gallium oxide wafers are 2 inches and 4 inches, while semiconductor mass production line equipment is mostly 6 inches or 8 inches, so it is often the case that gallium oxide wafers cannot be used to achieve large-scale production of devices on the production line. In addition, existing gallium oxide transistor devices lack P-type to achieve effective gate control, and can only be achieved using unstable P-type oxides or Fin structures with difficult processes, resulting in complex preparation processes and poor stability of gallium oxide transistor devices.

[0004] Therefore, how to prepare highly stable gallium oxide heterogeneous integrated devices based on low-difficulty processes under mass production conditions is a problem that technical personnel in this field urgently need to solve. Summary of the invention

[0005] Based on the above problems, the present application provides a gallium oxide monolithic heterogeneous integrated device and a manufacturing method thereof. By bonding the gallium oxide monolith to a substrate for tape-out, large-scale preparation of gallium oxide devices on a production line can be achieved. By bonding N-type gallium oxide to P-type material to form a heterogeneous PN junction to make up for the missing gallium oxide homogeneous PN junction, the stability of the structure is improved.

[0006] In a first aspect, an embodiment of the present application provides a gallium oxide monolithic heterogeneous integrated device, characterized in that the device comprises: an N-type gallium oxide epitaxial wafer, a P-type material layer, an N-type doped region, a gate control region, an interlayer dielectric, a source, a drain, and a substrate layer; the N-type gallium oxide epitaxial wafer comprises an epitaxial layer and a substrate layer;

[0007] One side of the epitaxial layer of the N-type gallium oxide epitaxial wafer is bonded to one side of the P-type material layer;

[0008] The N-type doped region is disposed in the P-type material layer and is in contact with the epitaxial layer of the N-type gallium oxide epitaxial wafer;

[0009] The gate control region covers the N-type doped region and is disposed on the other side of the P-type material layer;

[0010] The source electrode contacts the N-type doped region and forms an ohmic contact with the P-type material layer, and the source electrode is isolated from the gate electrode by the interlayer dielectric;

[0011] The drain electrode is arranged on one side of the substrate layer of the N-type gallium oxide epitaxial wafer and forms an ohmic contact with the substrate layer;

[0012] The substrate layer is bonded to the drain electrode.

[0013] Optionally, the N-type doped region includes: a deep-implanted N-type region and a shallow-implanted N-type region;

[0014] The injection depth of the shallowly injected N-type region does not exceed the thickness of the P-type material layer;

[0015] The implantation depth of the deep implanted N-type region exceeds the thickness of the P-type material layer, and one end is in contact with the epitaxial layer of the N-type gallium oxide epitaxial wafer.

[0016] Optionally, the gate control region includes: a gate dielectric and a gate metal;

[0017] The gate dielectric, the gate metal and the interlayer dielectric are sequentially arranged on the other side of the P-type material layer;

[0018] The gate dielectric has the same width as the interlayer dielectric and is wider than the gate metal;

[0019] The gate metal covers the deep implanted N-type region and a portion of the shallow implanted N-type region.

[0020] Optionally, the device further comprises: a first electrode;

[0021] The first electrode is disposed on the other side of the interlayer dielectric and is in contact with the upper surface of the source and a portion of the upper surface of the gate metal.

[0022] Optionally, the substrate layer includes: a high-resistance substrate and a conductive metal layer;

[0023] The conductive metal layer is deposited on the upper surface of the high-resistance substrate, and the other end is bonded to the drain electrode;

[0024] The width of the conductive metal layer is greater than the width of the drain electrode.

[0025] Optionally, the device further comprises: a second electrode;

[0026] The second electrode is disposed on the lower surface of the high-resistance substrate, penetrates the high-resistance substrate, and is connected to the conductive metal layer.

[0027] Optionally, a groove is etched on the upper surface of the high-resistance substrate;

[0028] The width of the groove is greater than the width of the substrate layer outside the N-type gallium oxide epitaxial wafer, and the depth of the groove is less than or equal to the height of the N-type gallium oxide epitaxial wafer.

[0029] In a second aspect, an embodiment of the present application provides a method for manufacturing a gallium oxide monolithic heterogeneous integrated device, characterized in that the method is used to manufacture the gallium oxide monolithic heterogeneous integrated device as described above, and the method comprises:

[0030] Provide N-type gallium oxide epitaxial wafers and substrates;

[0031] Bonding a P-type material layer on one side of the epitaxial layer of the N-type gallium oxide epitaxial wafer;

[0032] Etching the upper surface of the substrate to form a groove, and bonding one side of the substrate layer of the N-type gallium oxide epitaxial wafer into the groove;

[0033] Based on the ion implantation process, an N-type doped region is formed in the P-type material layer;

[0034] Based on a deposition process, depositing a first insulating dielectric on the upper surface of the P-type material layer to form a gate dielectric;

[0035] Based on a deposition process, a first metal film is deposited on the gate dielectric layer, and pattern etching is performed to form a gate;

[0036] Based on a deposition process, depositing a second insulating medium on the gate to form an interlayer dielectric;

[0037] Pattern-etching the gate dielectric and the interlayer dielectric to expose a portion of the upper surface of the P-type material layer;

[0038] Depositing a second metal film on the pattern-etched regions of the interlayer dielectric and the gate dielectric and annealing the film to form an ohmic contact as a source electrode;

[0039] Pattern-etching the interlayer dielectric to expose a portion of the upper surface of the gate;

[0040] Depositing a third metal film on the upper surface of the interlayer dielectric and contacting the gate and the source as a first electrode;

[0041] The substrate layer side of the N-type gallium oxide epitaxial wafer and the groove are debonded, and a fourth metal film is deposited on the substrate layer side of the N-type gallium oxide epitaxial wafer and annealed to form an ohmic contact as a drain.

[0042] Optionally, the method further includes:

[0043] Depositing a fifth metal film on the surface of the groove, and bonding the drain electrode to the fifth metal film;

[0044] The lower surface of the substrate is perforated to expose the back side of the fifth metal film, and metal deposition is continued on the lower surface of the substrate based on a deposition process. The deposited metal contacts the back side of the fifth metal film and serves as a second electrode.

[0045] It can be seen from the above technical solutions that compared with the prior art, the present application has the following advantages:

[0046] The heterogeneous integrated device of a gallium oxide monolithic wafer provided in the present application includes: an N-type gallium oxide epitaxial wafer, a P-type material layer, an N-type doped region, a gate control region, an interlayer dielectric, a source, a drain and a substrate layer; the N-type gallium oxide epitaxial wafer includes an epitaxial layer and a substrate layer; one side of the epitaxial layer of the N-type gallium oxide epitaxial wafer is bonded to one side of the P-type material layer; the N-type doped region is arranged in the P-type material layer and contacts the epitaxial layer of the N-type gallium oxide epitaxial wafer; the gate control region covers the N-type doped region and is arranged on the other side of the P-type material layer; an ohmic contact is formed between the source and the P-type material layer; the drain is arranged on one side of the substrate layer of the N-type gallium oxide epitaxial wafer and forms an ohmic contact with the substrate layer; the substrate layer is bonded to the drain. Therefore, bonding the gallium oxide monolithic wafer to the substrate for wafer taping can realize the device scale preparation of the wafer on the production line, and by bonding the N-type gallium oxide to the P-type material, a heterogeneous PN junction is formed to make up for the missing gallium oxide homogeneous PN junction, thereby improving the stability of the structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0048] Figure 1 A schematic structural diagram of a gallium oxide monolithic heterogeneous integrated device provided in an embodiment of the present application;

[0049] Figure 2 A schematic diagram of the structure of an N-type doping region provided in an embodiment of the present application;

[0050] Figure 3 A schematic diagram of the structure of a gate control region provided in an embodiment of the present application;

[0051] Figure 4 A schematic diagram of the structure of a first electrode provided in an embodiment of the present application;

[0052] Figure 5 A schematic diagram of the structure of a substrate layer provided in an embodiment of the present application;

[0053] Figure 6 A schematic diagram of the structure of a second electrode provided in an embodiment of the present application;

[0054] Figure 7 A schematic structural diagram of a high-resistance substrate provided in an embodiment of the present application;

[0055] Figure 8 A schematic diagram of the structure of a diode device provided in an embodiment of the present application;

[0056] Fig. 9 A schematic diagram of the structure of a gallium oxide SBD device provided in an embodiment of the present application;

[0057] Fig.10 A schematic diagram of the structure of another diode device provided for the implementation of this application;

[0058] Fig.11 A flow chart of a method for manufacturing a gallium oxide monolithic heterogeneous integrated device provided in an embodiment of the present application;

[0059] Fig.12 A flowchart of a method for manufacturing a second electrode provided in an embodiment of the present application;

[0060] Fig.13 A schematic diagram of current flow provided in an embodiment of the present application. DETAILED DESCRIPTION

[0061] As mentioned above, existing gallium oxide wafers cannot be used for mass production and the existing gallium oxide transistor devices have complex preparation processes and poor stability. Specifically, existing gallium oxide wafers are mostly 2 inches and 4 inches, while semiconductor mass production line equipment is mostly 6 inches or 8 inches, so it is often the case that gallium oxide wafers cannot achieve large-scale preparation of devices on the production line. Moreover, existing gallium oxide transistor devices lack P-type to achieve effective gate control and can only be achieved using unstable P-type oxides or Fin structures with difficult processes, resulting in complex preparation processes and poor stability of gallium oxide transistor devices.

[0062] To solve the above problems, an embodiment of the present application provides a gallium oxide monolithic heterogeneous integrated device and a manufacturing method thereof, wherein the device includes: an N-type gallium oxide epitaxial wafer, a P-type material layer, an N-type doped region, a gate control region, a source, a drain and a substrate layer; the N-type gallium oxide epitaxial wafer includes an epitaxial layer and a substrate layer; one side of the epitaxial layer of the N-type gallium oxide epitaxial wafer is bonded to one side of the P-type material layer; the N-type doped region is arranged in the P-type material layer and contacts the epitaxial layer of the N-type gallium oxide epitaxial wafer; the gate control region covers the N-type doped region and is arranged on the other side of the P-type material layer; the source penetrates the gate control region and forms an ohmic contact with the P-type material layer; the drain is arranged on one side of the substrate layer of the N-type gallium oxide epitaxial wafer and forms an ohmic contact with the substrate layer; the substrate layer is bonded to the drain.

[0063] Therefore, bonding the gallium oxide monolith to the substrate for tape-out can achieve device-scale preparation of wafers on the production line, and by bonding N-type gallium oxide with P-type material to form a heterogeneous PN junction to make up for the missing gallium oxide homogeneous PN junction, the stability of the structure is improved.

[0064] It should be noted that the gallium oxide monolithic heterogeneous integrated device and its manufacturing method provided in this application can be applied to the field of semiconductor devices. The above is only an example and does not limit the application field of the gallium oxide monolithic heterogeneous integrated device and its manufacturing method provided in this application.

[0065] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0066] Figure 1 A schematic diagram of the structure of a gallium oxide monolithic heterogeneous integrated device provided in an embodiment of the present application. Figure 1 As shown, the device includes: an N-type gallium oxide epitaxial wafer 100, a P-type material layer 200, an N-type doped region 300, a gate control region 400, an interlayer dielectric 403, a source 500, a drain 600 and a substrate layer 700; the N-type gallium oxide epitaxial wafer includes an epitaxial layer 101 and a substrate layer 102;

[0067] One side of the epitaxial layer 101 of the N-type gallium oxide epitaxial wafer 100 is bonded to one side of the P-type material layer 200 ;

[0068] The N-type doping region 300 is disposed in the P-type material layer 200 and is in contact with the epitaxial layer 101 of the N-type gallium oxide epitaxial wafer 100;

[0069] The gate control region 400 covers the N-type doping region 300 and is disposed on the other side of the P-type material layer 200;

[0070] The source electrode 500 contacts the N-type doped region and forms an ohmic contact with the P-type material layer 200, and the source electrode is isolated from the gate electrode by the interlayer dielectric;

[0071] The drain electrode 600 is disposed on one side of the substrate layer 102 of the N-type gallium oxide epitaxial wafer 100 and forms an ohmic contact with the substrate layer 102;

[0072] The substrate layer 700 is bonded to the drain electrode 600 .

[0073] Specifically, the size of the N-type gallium oxide epitaxial wafer 100 is not limited, and can be a 2-inch, 4-inch wafer or a cut piece, including a heavily doped gallium oxide substrate layer 102 and a lightly doped gallium oxide epitaxial layer 101 with a thickness of 10 to 20 μm. The P-type material in the P-type material layer 200 bonded to the epitaxial layer 101 can be P-Si, P-SiC or P-GaN, and the thickness of the P-type material layer 200 is about 1 μm, and the size is the same as that of the N-type gallium oxide epitaxial wafer 100. The source 500 metal is Ti / Au or Ti / Al.

[0074] Figure 2 A schematic diagram of the structure of an N-type doping region provided in an embodiment of the present application. Figure 2 As shown, the N-type doping region 300 includes: a deep-implanted N-type region 301 and a shallow-implanted N-type region 302; the implantation depth of the shallow-implanted N-type region 302 does not exceed the thickness of the P-type material layer 200;

[0075] The implantation depth of the deep implanted N-type region 301 exceeds the thickness of the P-type material layer 200 , and one end of the deep implanted N-type region 301 is in contact with the epitaxial layer 101 of the N-type gallium oxide epitaxial wafer 100 .

[0076] Specifically, two N-type doped regions 300 with different implantation depths are formed in the P-type material as conductive channels through ion implantation of N, Si or P ions, etc. The implantation depth of the shallow implanted N-type region 302 does not exceed 1 μm, while the implantation depth of the deep implanted N-type region 301 exceeds 1 μm and contacts the epitaxial layer 101.

[0077] As an implementation method, a device cell includes at least one shallowly implanted N-type region 302 and one deeply implanted N-type region 301.

[0078] Specifically, the N-type doping region 300 may include two shallowly implanted N-type regions 302 and one deeply implanted N-type region 301 , wherein the shallowly implanted regions 302 are distributed on both sides of the deeply implanted N-type region 301 .

[0079] Figure 3 A schematic diagram of the structure of a gate control region provided in an embodiment of the present application. Figure 3 As shown, the gate control region 400 includes: a gate dielectric 401 and a gate metal 402;

[0080] The gate dielectric 401, the gate metal 402 and the interlayer dielectric 403 are sequentially arranged on the other side of the P-type material layer 200;

[0081] The gate dielectric 401 has the same width as the interlayer dielectric 403 and is wider than the gate metal 402;

[0082] The gate metal 402 covers the deep implanted N-type region 301 and a portion of the shallow implanted N-type region 302 .

[0083] Specifically, a gate dielectric 401, a gate metal 402, and an interlayer dielectric 403 are sequentially deposited on the P-type material layer 200 with a width that can cover the deep-implanted N-type region 301 and part of the shallow-implanted N-type region 302. Among them, the gate dielectric 401 is an insulating dielectric SiO2, Al2O3, or Si3N4, etc.; the gate metal 402 is a metal material Al or Ni; and the interlayer dielectric 403 is also an insulating dielectric SiO2, Al2O3, or Si3N4, etc. It can be understood that the gate dielectric 401 and the interlayer dielectric 403 can be selected from Al2O3 or SiO2, etc. according to the density requirements or cost requirements.

[0084] Figure 4 A schematic diagram of the structure of a first electrode provided in an embodiment of the present application. Figure 4 As shown, the device further includes: a first electrode 800;

[0085] The first electrode 800 is disposed on the other side of the interlayer dielectric 403 , and is in contact with the upper surface of the source 500 and a portion of the upper surface of the gate metal 402 .

[0086] Specifically, a thicker layer of Ti / Ni / Al is deposited and patterned on the source electrode 500 and the interlayer dielectric 403 to serve as a thickened electrode of the gate and the source electrode 500 , namely, the first electrode 800 .

[0087] Figure 5 A schematic diagram of the structure of a substrate layer provided in an embodiment of the present application. Figure 5 As shown, the substrate layer 700 includes: a high-resistance substrate 701 and a conductive metal layer 702;

[0088] The conductive metal layer 702 is deposited on the upper surface of the high-resistance substrate 701, and the other end is bonded to the drain electrode 600;

[0089] The width of the conductive metal layer 702 is greater than the width of the drain electrode 600 .

[0090] Specifically, the high-resistance substrate 701 may be a Si substrate, a SiC substrate or a sapphire substrate, and may be 6, 8 or 12 inches in size. The conductive metal layer 702 is Al or Cu metal, and is smaller than the high-resistance substrate 701 and larger than the substrate layer 102 .

[0091] Figure 6 A schematic diagram of the structure of a second electrode provided in an embodiment of the present application. Figure 6 The device shown further includes: a second electrode 900;

[0092] The second electrode 900 is disposed on the lower surface of the high-resistance substrate 701 , penetrates the high-resistance substrate 701 , and is connected to the conductive metal layer 702 .

[0093] Specifically, the second electrode 900 can be regarded as an extension of the conductive metal layer 702 , and is also made of Al or Cu metal. It is disposed on the lower surface of the high-resistance substrate 701 , penetrates the high-resistance substrate 701 , and is connected to the conductive metal layer 702 .

[0094] Figure 7 A schematic diagram of the structure of a high-resistance substrate provided in an embodiment of the present application. Figure 7 As shown, a groove is etched on the upper surface of the high-resistance substrate 701;

[0095] The width of the groove is greater than the width of the substrate layer 102 outside the N-type gallium oxide epitaxial wafer 100 , and the depth of the groove is less than or equal to the height of the N-type gallium oxide epitaxial wafer 100 .

[0096] Specifically, the shape of the groove should be close to the shape of the N-type gallium oxide epitaxial wafer 100 to be bonded, and the size should be slightly larger than the N-type gallium oxide epitaxial wafer 100. The depth of the groove is determined by three factors: the thickness of the high-resistance substrate 701, the thickness of the N-type gallium oxide epitaxial wafer 100, and the wafer thickness limit allowed by the production line equipment. It is usually 300-650μm. It is necessary to ensure that the N-type gallium oxide epitaxial wafer 100 is higher than the high-resistance substrate 701 or flush with the high-resistance substrate 701, and the height from the bottom of the high-resistance substrate 701 to the top of the N-type gallium oxide epitaxial wafer 100 does not exceed the maximum wafer thickness allowed by the process equipment.

[0097] In summary, the heterogeneous integrated device of a gallium oxide monolithic wafer provided in the present application includes: an N-type gallium oxide epitaxial wafer, a P-type material layer, an N-type doped region, a gate control region, an interlayer dielectric, a source, a drain and a substrate layer; the N-type gallium oxide epitaxial wafer includes an epitaxial layer and a substrate layer; one side of the epitaxial layer of the N-type gallium oxide epitaxial wafer is bonded to one side of the P-type material layer; the N-type doped region is arranged in the P-type material layer and contacts the epitaxial layer of the N-type gallium oxide epitaxial wafer; the gate control region covers the N-type doped region and is arranged on the other side of the P-type material layer; an ohmic contact is formed between the source and the P-type material layer; the drain is arranged on one side of the substrate layer of the N-type gallium oxide epitaxial wafer and forms an ohmic contact with the substrate layer; the substrate layer is bonded to the drain. Therefore, bonding the gallium oxide monolithic wafer to the substrate for wafer taping can realize the device scale preparation of the wafer on the production line, and by bonding the N-type gallium oxide to the P-type material, a heterogeneous PN junction is formed to make up for the missing gallium oxide homogeneous PN junction, thereby improving the stability of the structure.

[0098] Figure 8 A schematic diagram of the structure of a diode device provided in an embodiment of the present application. Figure 8 As shown, the gallium oxide device can be replaced by other devices based on the above-mentioned technical solution of bonding a small-sized epitaxial wafer to a substrate for tape-out to achieve large-scale preparation of devices on the production line. a is a gallium oxide Schottky barrier diode (SBD), in which one side of the substrate layer of the gallium oxide epitaxial wafer is directly bonded to a substrate (Si, SiC, sapphire) with a groove and a metal layer deposited in the groove, and a metal layer is also deposited on one side of the epitaxial layer of the gallium oxide epitaxial wafer. b is a gallium oxide field effect transistor, which also has a P-type material layer bonded between the epitaxial layer and the metal layer.

[0099] Fig. 9 A schematic diagram of the structure of a gallium oxide SBD device provided in an embodiment of the present application. Fig. 9 As shown, based on the above-mentioned gallium oxide SBD device, part of the gallium oxide epitaxial layer can be etched away to connect the back metal with the side wall of the substrate layer and part of the side wall of the epitaxial layer, thereby achieving the purpose of increasing the current flow area and reducing the on-resistance of the device.

[0100] Fig.10 A schematic diagram of the structure of another diode device provided for the implementation of this application. Fig.10 As shown, based on the above-mentioned diode device, the high-resistance substrate used for bonding with the epitaxial wafer can be replaced with a conductive Si wafer, SiC or diamond, so that there is no need to drill a hole on the back of the device to form a back electrode. The back metal electrode can be formed directly by metal deposition and stripping, and the current channel will pass through conductive materials such as Si, SiC or diamond.

[0101] In addition, as another embodiment, an electrode may be prepared on the side where Si or SiC is bonded to gallium oxide, and a cathode electrode of a gallium oxide diode device or a drain electrode of a transistor device may be formed by means of a front electrode.

[0102] Fig.11 A flow chart of a method for manufacturing a gallium oxide monolithic heterogeneous integrated device provided in an embodiment of the present application. Fig.11 As shown, the method may include:

[0103] S1: Provide N-type gallium oxide epitaxial wafers and substrates.

[0104] In practical applications, the substrate, i.e. the high-resistance substrate mentioned above, can be a Si substrate, a SiC substrate or a sapphire substrate. In order to be mass-produced on the equipment, the size is generally 6, 8, or 12 inches. The size of the N-type gallium oxide (Ga2O3) epitaxial wafer is not limited, but is not larger than the size of the high-resistance substrate, and includes a heavily N-type gallium oxide substrate layer and a lightly N-type gallium oxide epitaxial layer with a thickness of 10 to 20 μm.

[0105] S2: Bonding a P-type material layer on one side of the epitaxial layer of the N-type gallium oxide epitaxial wafer.

[0106] In practical applications, the P-type material can be P-Si, P-SiC or P-GaN. The P-type material with a thickness of about 1 μm can be firstly peeled off by smart cut technology, and then flattened by CMP process, and then directly bonded to the N-type gallium oxide epitaxial wafer based on surface activation bonding or plasma activation bonding, and the bonding surface is the epitaxial layer and P-type material layer of the N-type gallium oxide epitaxial wafer. Alternatively, a certain thickness of P-type material can be directly bonded to the N-type gallium oxide epitaxial wafer by surface activation bonding or plasma activation bonding, and then thinned to about 1 μm thick, and the bonding surface is the epitaxial layer and P-type material layer of the N-type gallium oxide epitaxial wafer.

[0107] S3: etching the upper surface of the substrate to form a groove, and bonding one side of the substrate layer of the N-type gallium oxide epitaxial wafer into the groove.

[0108] In practical applications, the substrate can be a Si substrate, a SiC substrate or a sapphire substrate. Then, based on photolithography and etching technology, the upper surface of the substrate is etched by dry etching or wet etching to form a groove with a shape close to the shape of the N-type gallium oxide epitaxial wafer to be bonded and a size slightly larger than the size of the N-type gallium oxide epitaxial wafer. Then, the N-type gallium oxide epitaxial wafer heterogeneously integrated with the P-type material layer is bonded in the groove by the coupon to wafer technology. The bonding surface is the groove surface of the substrate and the back of the substrate layer of the N-type gallium oxide epitaxial wafer. The bonding method can be to directly bond the substrate to it using an adhesive. The adhesive can be a bonding glue or a foaming glue. This bonding method can achieve bonding and debonding by controlling the temperature and can be flexibly applied to the device tape-out preparation process.

[0109] S4: Based on an ion implantation process, an N-type doped region is formed in the P-type material layer.

[0110] In practical applications, the N-type gallium oxide epitaxial wafer is bonded to the substrate, and can be operated on a mass production machine through the substrate. On the mass production machine, two N-type doped regions with different implantation depths are formed in the P-type material layer as a conductive channel through an ion implantation process such as N, Si or P ions. The N-type doped region can include two shallow implantation N-type regions and one deep implantation N-type region. Among them, shallow implantation regions are distributed on both sides of the deep implantation N-type region.

[0111] S5: Based on a deposition process, depositing a first insulating dielectric on the upper surface of the P-type material layer to form a gate dielectric;

[0112] Based on a deposition process, a first metal film is deposited on the gate dielectric layer, and pattern etching is performed to form a gate;

[0113] Based on a deposition process, depositing a second insulating medium on the gate to form an interlayer dielectric;

[0114] The gate dielectric and the interlayer dielectric are pattern-etched to expose a portion of the upper surface of the P-type material layer.

[0115] In practical applications, after forming the N-type doped region, the deposition process can be continued on the P-type material layer through a mass production machine. Specifically, first, a layer of insulating material (i.e., the first insulating medium, which can be SiO2, Al2O3 or Si3N4, etc.) is deposited on the upper surface of the P-type material layer through thin film deposition as a gate dielectric. Then, metal film deposition is continued on the gate dielectric to deposit a layer of metal film (i.e., the first metal film, which can be Al or Ni), and then a pattern is etched on the first metal film through a photolithography etching process to form a gate. It should be noted that the gate needs to cover the deep-injected N-type region and part of the shallow-injected N-type region. Then, a layer of insulating medium (i.e., the second insulating medium, which can be SiO2, Al2O3 or Si3N4, etc.) is continued to be deposited on the first metal film to form an interlayer dielectric. Finally, through photolithography and etching, a pattern is opened at the source position and part of the upper surface of the P-type material layer is exposed. It should be noted that the width of the gate dielectric and the interlayer dielectric is slightly wider than the gate width, and also covers the deep-injected N-type region and part of the shallow-injected N-type region on both sides.

[0116] S6: depositing a second metal film on the pattern-etched regions of the interlayer dielectric and the gate dielectric and annealing the film to form an ohmic contact, which serves as a source.

[0117] In practical applications, a second metal film (Ti / Au or Ti / Al metal) is deposited in the dielectric etching area by metal evaporation and lift-off process and annealed to form an ohmic contact between the second metal film and the P-type material and serve as a source.

[0118] S7: pattern-etching the interlayer dielectric to expose a portion of the upper surface of the gate;

[0119] A third metal film is deposited on the upper surface of the interlayer dielectric and is in contact with the gate and the source to serve as a first electrode.

[0120] Finally, through photolithography and etching, a pattern is opened above the gate and a portion of the upper surface of the gate is exposed. The metal film deposition is continued on the upper surface of the interlayer dielectric. A thicker third metal film (Ti / Ni / Al metal) is deposited and patterned so that the third metal film can contact the gate metal and the source metal to serve as a thickened electrode (first electrode) for the gate and source.

[0121] S8: Debonding one side of the substrate layer of the N-type gallium oxide epitaxial wafer and the groove, and depositing a fourth metal film on one side of the substrate layer of the N-type gallium oxide epitaxial wafer and annealing to form an ohmic contact as a drain.

[0122] In practical applications, the substrate is heated to melt the adhesive between the bottom of the substrate layer and the surface of the groove, so as to achieve debonding of the N-type gallium oxide epitaxial wafer and the substrate. The N-type gallium oxide epitaxial wafer is then turned over, and a metal film is deposited on the back of the substrate layer, and a fourth metal film (Ti / Au or Ti / Al) is deposited and annealed, so that the fourth metal film, as an ohmic metal, forms a non-rectifying contact (ohmic contact) with the N-type material, and serves as a drain to complete the preparation of a gallium oxide monolithic heterogeneous integrated device.

[0123] In summary, the method provided in the embodiment of the present application uses the coupon to wafer technology to bond a small-sized gallium oxide epitaxial wafer to a 6 / 8 / 12-inch substrate that can adapt to a mass production machine for wafer tape-out, thereby realizing mass production-scale preparation of heterogeneous integrated devices of a single gallium oxide wafer. In addition, by bonding an N-type gallium oxide epitaxial wafer to a P-type material and using the P-type material as a gate control region, effective gate control can be achieved without the need to use an unstable P-type oxide or a Fin structure with high process difficulty, thereby improving the stability of the structure and providing a heat dissipation path, thereby improving the heat dissipation capacity of the gallium oxide device.

[0124] Fig.12 A flowchart of a method for manufacturing a second electrode provided in an embodiment of the present application. Fig. 9 As shown, the method also includes:

[0125] S9: depositing a fifth metal film on the surface of the groove, and bonding the drain electrode to the fifth metal film.

[0126] In practical applications, in combination with the above, metal film deposition can continue on the surface of the groove, deposit a layer of fifth metal film (Al or Cu metal), and then bond the N-type gallium oxide epitaxial wafer to the substrate through the coupon to wafer technology. The bonding surface is the metal surface in the groove of the substrate and the electrode metal surface (drain surface) on the back of the substrate layer of the N-type gallium oxide epitaxial wafer. The bonding method can be metal-metal direct bonding, or the N-type gallium oxide epitaxial wafer can be placed in the groove, and the metal is melted by direct heating or laser heating of the substrate to achieve bonding.

[0127] S10: drilling a hole in the lower surface of the substrate to expose the back side of the fifth metal film, and continuing to deposit metal on the lower surface of the substrate based on a deposition process, the deposited metal contacts the back side of the fifth metal film and serves as a second electrode.

[0128] In practical applications, the substrate is turned over and the back of the substrate is punched until the metal inner surface in the groove is exposed. Then, by metal film deposition, (Al or Cu) metal is deposited on the back of the substrate or by welding to form a back electrode (as the second electrode). The second electrode covers the entire back of the substrate and is connected to the fifth metal film. In this way, when the substrate is Si, Si wafer fabrication can be performed to prepare CMOS, and through the silicon and gallium oxide monolithic heterogeneous integration technology, an integrated circuit of heterogeneous integration of CMOS digital control circuits and Ga2O3 devices is formed.

[0129] Fig.13 A schematic diagram of current flow provided in an embodiment of the present application. Fig.10 As shown, when the gallium oxide monolithic heterogeneous integrated device is forward-conducted, the ion-implanted N-type region is expanded through gate control, thereby depleting the P-type region under the gate to form a conduction path, and the current flows from the source through the shallowly implanted N-type region, the depletion region, the deeply implanted N-type region, the epitaxial layer of the N-type gallium oxide epitaxial wafer, and the substrate layer of the N-type gallium oxide epitaxial wafer to the drain and the back electrode.

[0130] In summary, since the thermal conductivity of the substrate and P-type materials (Si, SiC, GaN) is better than that of gallium oxide, this heterogeneous integration scheme also improves the heat dissipation of gallium oxide devices. The P-type material on the top of the gallium oxide device and the heterogeneous substrate on the bottom both provide heat dissipation paths for the Ga2O3 device, achieving double-sided heat dissipation of the gallium oxide device.

[0131] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A gallium oxide monolithic heterogeneous integrated device, characterized in that: The device comprises: an N-type gallium oxide epitaxial wafer, a P-type material layer, an N-type doped region, a gate control region, an interlayer dielectric, a source electrode, a drain electrode and a substrate layer; the N-type gallium oxide epitaxial wafer comprises an epitaxial layer and a substrate layer; One side of the epitaxial layer of the N-type gallium oxide epitaxial wafer is bonded to one side of the P-type material layer; The N-type doped region is disposed in the P-type material layer and is in contact with the epitaxial layer of the N-type gallium oxide epitaxial wafer; The gate control region covers the N-type doped region and is disposed on the other side of the P-type material layer; The source electrode contacts the N-type doped region and forms an ohmic contact with the P-type material layer, and the source electrode is isolated from the gate electrode by the interlayer dielectric; The drain electrode is arranged on one side of the substrate layer of the N-type gallium oxide epitaxial wafer and forms an ohmic contact with the substrate layer; The substrate layer is bonded to the drain electrode.

2. The device according to claim 1, characterized in that The N-type doping region includes: a deep-implanted N-type region and a shallow-implanted N-type region; The injection depth of the shallowly injected N-type region does not exceed the thickness of the P-type material layer; The implantation depth of the deep implanted N-type region exceeds the thickness of the P-type material layer, and one end is in contact with the epitaxial layer of the N-type gallium oxide epitaxial wafer.

3. The device according to claim 2, characterized in that The gate control region includes: a gate dielectric and a gate metal; The gate dielectric, the gate metal and the interlayer dielectric are sequentially arranged on the other side of the P-type material layer; The gate dielectric has the same width as the interlayer dielectric and is wider than the gate metal; The gate metal covers the deep implanted N-type region and a portion of the shallow implanted N-type region.

4. The device according to claim 3, characterized in that The device further comprises: a first electrode; The first electrode is disposed on the other side of the interlayer dielectric and is in contact with the upper surface of the source and a portion of the upper surface of the gate metal.

5. The device according to claim 1, characterized in that The substrate layer comprises: a high-resistance substrate and a conductive metal layer; The conductive metal layer is deposited on the upper surface of the high-resistance substrate, and the other end is bonded to the drain electrode; The width of the conductive metal layer is greater than the width of the drain electrode.

6. The device according to claim 5, characterized in that The device further comprises: a second electrode; The second electrode is disposed on the lower surface of the high-resistance substrate, penetrates the high-resistance substrate, and is connected to the conductive metal layer.

7. The device according to claim 5, characterized in that A groove is etched on the upper surface of the high-resistance substrate; The width of the groove is greater than the width of the substrate layer outside the N-type gallium oxide epitaxial wafer, and the depth of the groove is less than or equal to the height of the N-type gallium oxide epitaxial wafer.

8. A method for manufacturing a gallium oxide monolithic heterogeneous integrated device, characterized in that: For manufacturing a gallium oxide monolithic heterogeneous integrated device according to any one of claims 1 to 7, the method comprises: Provide N-type gallium oxide epitaxial wafers and substrates; Bonding a P-type material layer on one side of the epitaxial layer of the N-type gallium oxide epitaxial wafer; Etching the upper surface of the substrate to form a groove, and bonding one side of the substrate layer of the N-type gallium oxide epitaxial wafer into the groove; Based on the ion implantation process, an N-type doped region is formed in the P-type material layer; Based on a deposition process, depositing a first insulating dielectric on the upper surface of the P-type material layer to form a gate dielectric; Based on a deposition process, a first metal film is deposited on the gate dielectric layer, and pattern etching is performed to form a gate; Based on a deposition process, depositing a second insulating medium on the gate to form an interlayer dielectric; Pattern-etching the gate dielectric and the interlayer dielectric to expose a portion of the upper surface of the P-type material layer; Depositing a second metal film on the pattern-etched regions of the interlayer dielectric and the gate dielectric and annealing the film to form an ohmic contact as a source electrode; Pattern-etching the interlayer dielectric to expose a portion of the upper surface of the gate; Depositing a third metal film on the upper surface of the interlayer dielectric and contacting the gate and the source as a first electrode; The substrate layer side of the N-type gallium oxide epitaxial wafer and the groove are debonded, and a fourth metal film is deposited on the substrate layer side of the N-type gallium oxide epitaxial wafer and annealed to form an ohmic contact as a drain.

9. The method according to claim 8, characterized in that The method further comprises: Depositing a fifth metal film on the surface of the groove, and bonding the drain electrode to the fifth metal film; The lower surface of the substrate is perforated to expose the back side of the fifth metal film, and metal deposition is continued on the lower surface of the substrate based on a deposition process. The deposited metal contacts the back side of the fifth metal film and serves as a second electrode.

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