Light emitting diode and manufacturing method thereof

Abstract

The invention provides a light-emitting diode and a manufacturing method thereof, and belongs to the field of light-emitting devices. The light-emitting diode comprises a first semiconductor layer, an active layer and a second semiconductor layer which are stacked in sequence, wherein the first semiconductor layer, the active layer and the second semiconductor layer are of a step structure; the ITO current expansion layer is located on the surface of the second semiconductor layer; the first electrode is located on the step surface of the step structure, and the second electrode is located on the ITO current expansion layer; a plurality of first microstructures are arranged on the surface of the ITO current expansion layer, a plurality of second microstructures are arranged on the surfaces of the first microstructures, the first microstructures are prismatic tables or pyramids, and the second microstructures are pyramids.

Description

Technical Field

[0001] The present disclosure relates to the field of light-emitting devices, and in particular to a light-emitting diode and a manufacturing method thereof. Background Art

[0002] Light-emitting diodes are electronic components that can emit light and are commonly used in lighting, display and other fields.

[0003] The related art provides a structure of a light-emitting diode, including: a substrate, a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence on the surface of the substrate, an indium tin oxide (ITO) current spreading layer located on the surface of the second semiconductor layer, and an electrode connected to the ITO current spreading layer.

[0004] However, the difference in refractive index between ITO and other film layers causes the light emitted by the active layer to be totally reflected between the layers, greatly reducing the brightness of the LED chip. Summary of the invention

[0005] The embodiment of the present disclosure provides a light emitting diode and a method for manufacturing the same, which can improve brightness. The technical solution is as follows:

[0006] In one aspect, a light emitting diode is provided, the light emitting diode comprising:

[0007] A first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence, wherein the first semiconductor layer, the active layer, and the second semiconductor layer are in a step structure;

[0008] An ITO current spreading layer, located on the surface of the second semiconductor layer;

[0009] a first electrode and a second electrode, wherein the first electrode is located on a step surface of the step structure, and the second electrode is located on the ITO current spreading layer;

[0010] The surface of the ITO current spreading layer has a plurality of first microstructures, the surface of the first microstructure has a plurality of second microstructures, the first microstructure is a prism or a pyramid, and the second microstructure is a pyramid.

[0011] Optionally, the first microstructure is a prism, and the upper base surface of the prism is a square.

[0012] Optionally, the side length of the square is 200-300 nm, and the height of the prism is 300-500 nm.

[0013] Optionally, the second microstructure is a regular quadrangular pyramid.

[0014] Optionally, the side length of the regular quadrangular prism is 10-20 nm, and the height of the regular quadrangular prism is 5-15 nm.

[0015] In another aspect, a method for manufacturing a light emitting diode is provided, the method comprising:

[0016] Manufacturing a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence, wherein the first semiconductor layer, the active layer, and the second semiconductor layer are in a step structure;

[0017] An ITO current spreading layer is formed on the surface of the second semiconductor layer, wherein the surface of the ITO current spreading layer has a plurality of first microstructures, the surface of the first microstructure has a plurality of second microstructures, the first microstructure is a prism or a pyramid, and the second microstructure is a pyramid;

[0018] A first electrode and a second electrode are manufactured, wherein the first electrode is located on the step surface of the step structure, and the second electrode is located on the ITO current spreading layer.

[0019] Optionally, an ITO current spreading layer is formed on the surface of the second semiconductor layer, comprising:

[0020] Forming an ITO film on the surface of the second semiconductor layer;

[0021] Coating a layer of positive photoresist on the ITO film;

[0022] Fabricating a mask pattern on the positive photoresist by nanoimprint technology;

[0023] The ITO film is etched by using the mask pattern to obtain the ITO current spreading layer.

[0024] Optionally, coating a layer of positive photoresist on the ITO film comprises:

[0025] In an environment where the rotation speed of a coating machine is 2000-3000 r / min and the temperature is 20-30° C., a layer of positive photoresist with a thickness of 0.5-1 μm is coated on the ITO film.

[0026] Optionally, the step of fabricating a mask pattern on the positive photoresist by nanoimprint technology comprises:

[0027] In an environment of 60-70° C., a mask pattern is produced on the positive photoresist by using a silicon-based nanoimprint plate.

[0028] Optionally, the ITO film is etched by using the mask pattern to obtain the ITO current spreading layer, including:

[0029] Using the mask pattern to shield and perform ICP etching on the ITO film to obtain the ITO current spreading layer;

[0030] The etching gas for the ICP etching is Ar gas, the ignition power is 150-250W, the etching power is 250-350W, the etching time is 200-400s, and the etching rate is 0.5-0.8 angstroms / s.

[0031] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:

[0032] In the embodiment of the present disclosure, by arranging a plurality of prisms or pyramids on the surface of the ITO current spreading layer, and the surfaces of these prisms or pyramids also have pyramids, the above-mentioned microstructure can significantly reduce the total reflection phenomenon between the internal layers of the chip, thereby improving the light extraction efficiency of the LED chip, and helping to improve the power output and photoelectric conversion efficiency of the LED chip. Among them, since total reflection requires the ITO current spreading layer to be a mirror surface, that is, the surface of the ITO current spreading layer is approximately a plane, the embodiment of the present disclosure destroys the total reflection condition by arranging the first microstructure and the second microstructure on the surface, thereby reducing the total reflection phenomenon. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 is a structural schematic diagram of a light emitting diode provided by an embodiment of the present disclosure;

[0035] Figure 2 A schematic diagram of the structure of an ITO current spreading layer surface provided in an embodiment of the present disclosure;

[0036] Figure 3 is a flow chart of a method for manufacturing a light emitting diode provided by an embodiment of the present disclosure;

[0037] Figure 4 This is a flow chart of another method for manufacturing a light emitting diode provided in an embodiment of the present disclosure.

[0038] The reference numerals are as follows:

[0039] 100: substrate; 101: first semiconductor layer; 102: active layer; 103: second semiconductor layer; 104: ITO current spreading layer; 105: first electrode; 106: second electrode; 107: passivation layer.

[0040] 141: first microstructure; 142: second microstructure; 200: step structure. DETAILED DESCRIPTION

[0041] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0042] Figure 1 A schematic diagram of the structure of a light emitting diode provided by an embodiment of the present disclosure. Figure 1 The light emitting diode includes: a first semiconductor layer 101, an active layer 102, a second semiconductor layer 103, an ITO current spreading layer 104, a first electrode 105 and a second electrode 106.

[0043] Among them, the first semiconductor layer 101, the active layer 102 and the second semiconductor layer 103 are stacked in sequence, and the first semiconductor layer 101, the active layer 102 and the second semiconductor layer 103 are in a step structure 200; the ITO current spreading layer 104 is located on the surface of the second semiconductor layer 103; the first electrode 105 is located on the step surface of the step structure 200, and the second electrode 106 is located on the ITO current spreading layer 104.

[0044] Figure 2 This is a schematic diagram of the structure of an ITO current spreading layer surface provided by an embodiment of the present disclosure. Figure 1 and Figure 2 The surface of the ITO current spreading layer 104 has a plurality of first microstructures 141 , and the surface of the first microstructures 141 has a plurality of second microstructures 142 . The first microstructures 141 are prisms or pyramids, and the second microstructures 142 are pyramids.

[0045] In the embodiment of the present disclosure, by arranging a plurality of prisms or pyramids on the surface of the ITO current spreading layer, and the surfaces of these prisms or pyramids also have pyramids, the above-mentioned microstructure can significantly reduce the total reflection phenomenon between the internal layers of the chip, thereby improving the light extraction efficiency of the LED chip, and helping to improve the power output and photoelectric conversion efficiency of the LED chip. Among them, since total reflection requires the ITO current spreading layer to be a mirror surface, that is, the surface of the ITO current spreading layer is approximately a plane, the embodiment of the present disclosure destroys the total reflection condition by arranging the first microstructure and the second microstructure on the surface, thereby reducing the total reflection phenomenon.

[0046] See again Figure 1 The light emitting diode may further include a substrate 100 , and a first semiconductor layer 101 is located on the substrate 100 .

[0047] Exemplarily, the substrate 100 is a sapphire substrate.

[0048] In the embodiment of the present disclosure, the first semiconductor layer 101 , the active layer 102 , and the second semiconductor layer 103 form a stepped structure.

[0049] In the embodiment of the present disclosure, the active layer 102 may include a multi-quantum well structure, such as an InGaN / GaN multi-quantum well structure.

[0050] In the embodiment of the present disclosure, the first semiconductor layer 101 may be an N-type semiconductor layer, and the second semiconductor layer 103 may be a P-type semiconductor layer.

[0051] In an example, the first semiconductor layer 101 may be an N-type GaN layer, and the second semiconductor layer 103 may be a P-type GaN layer.

[0052] In other examples, the first semiconductor layer 101 and the second semiconductor layer 103 may include other film layers.

[0053] In other embodiments, the first semiconductor layer 101 is a P-type semiconductor layer, and the second semiconductor layer 103 is an N-type semiconductor layer.

[0054] In the embodiment of the present disclosure, the light emitting diode further includes: a passivation layer 107 , the passivation layer 107 covers the step structure, and the first electrode 105 and the second electrode 106 both pass through the passivation layer 107 .

[0055] In the embodiment of the present disclosure, the passivation layer 107 may be a SiO 2 layer. Of course, the passivation layer may also be a film layer formed by other insulating materials, which is not limited in the present disclosure.

[0056] See again Figure 2 The first microstructure 141 on the surface of the ITO current spreading layer 104 is a prism, and the second microstructure 142 on the surface of the first microstructure 141 is a pyramid.

[0057] In a possible embodiment of the present disclosure, the first microstructure 141 may be a quadrangular pyramid. In other embodiments, the first microstructure 141 may also be other prisms.

[0058] In one example of the present disclosure, the upper bottom surface of the prism-shaped first microstructure 141 is a square, which is easy to manufacture and has good contact with the electrode. In addition, the structure can reduce total reflection without significantly reducing chip yield.

[0059] The side length of the square is 200-300 nm, and the height of the prism is 300-500 nm. The above dimensions can improve total reflection on the one hand, and have lower manufacturing difficulty and better electrical performance on the other hand.

[0060] Exemplarily, the side length of the square is 250 nm, and the height of the pyramid is 400 nm.

[0061] In other examples of the present disclosure, the upper bottom surface of the prism-shaped first microstructure 141 may also be other shapes, such as a parallelogram, a trapezoid, etc.

[0062] In a possible embodiment of the present disclosure, the first microstructure 141 may be a quadrangular pyramid. In other embodiments, the first microstructure 141 may also be other pyramids.

[0063] In a possible embodiment of the present disclosure, the second microstructure 142 may be a quadrangular pyramid. In other embodiments, the second microstructure 142 may also be other pyramids, such as a triangular pyramid.

[0064] In one example, the tetrahedron may be a regular tetrahedron, which is convenient to manufacture, can better improve the total reflection problem, and is not easy to increase the chip voltage.

[0065] The side length of the regular quadrangular prism is 10-20 nm, and the height of the regular quadrangular prism is 5-15 nm. The above dimensions can improve total reflection and reduce the manufacturing difficulty.

[0066] Exemplarily, the side length of the regular quadrangular prism is 15 nm, and the height of the regular quadrangular prism is 10 nm.

[0067] In other examples, the tetrahedron may be a non-regular tetrahedron.

[0068] In the embodiment of the present disclosure, the shapes of the plurality of first microstructures 141 may be the same or different, for example, all the same or partly the same.

[0069] In the embodiment of the present disclosure, the shapes of the plurality of second microstructures 142 on the same first microstructure 141 may be the same or different, for example, all the same or partly the same.

[0070] In the embodiment of the present disclosure, the shapes of the plurality of second microstructures 142 on different first microstructures 141 may be the same or different, for example, all the same or partly the same.

[0071] In the embodiment of the present disclosure, all or part of the plurality of first microstructures 141 may be densely arranged, that is, there is no gap between them. The plurality of first microstructures 141 may also be distributed at intervals.

[0072] In the embodiment of the present disclosure, all or part of the plurality of second microstructures 142 on the same first microstructure 141 may be densely arranged, that is, there is no gap between them. The plurality of second microstructures 142 may also be distributed at intervals.

[0073] Figure 3 A flowchart of a method for manufacturing a light emitting diode provided in an embodiment of the present disclosure. Figure 3 The method steps include:

[0074] S11, manufacturing a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence, wherein the first semiconductor layer, the active layer, and the second semiconductor layer have a step structure.

[0075] S12. An ITO current spreading layer is fabricated on the surface of the second semiconductor layer. The surface of the ITO current spreading layer has a plurality of first microstructures. The surface of the first microstructure has a plurality of second microstructures. The first microstructure is a prism or a pyramid. The second microstructure is a pyramid.

[0076] S13, manufacturing a first electrode and a second electrode, wherein the first electrode is located on a step surface of the step structure, and the second electrode is located on the ITO current spreading layer.

[0077] In the embodiment of the present disclosure, by arranging a plurality of prisms or pyramids on the surface of the ITO current spreading layer, and the surfaces of these prisms or pyramids also have pyramids, the above-mentioned microstructure can significantly reduce the total reflection phenomenon between the internal layers of the chip, thereby improving the light extraction efficiency of the LED chip, and helping to improve the power output and photoelectric conversion efficiency of the LED chip. Among them, since total reflection requires the ITO current spreading layer to be a mirror surface, that is, the surface of the ITO current spreading layer is approximately a plane, the embodiment of the present disclosure destroys the total reflection condition by arranging the first microstructure and the second microstructure on the surface, thereby reducing the total reflection phenomenon.

[0078] Figure 4 This is a flow chart of another method for manufacturing a light emitting diode provided in an embodiment of the present disclosure. Figure 4 The method steps include:

[0079] S21, manufacturing a first semiconductor layer on the surface of the substrate.

[0080] In the embodiment of the present disclosure, the first semiconductor layer may be an N-type semiconductor layer.

[0081] In the disclosed embodiment, a VeecoK465i or C4 or RB metal organic chemical vapor deposition (MOCVD) device or an AIXTRON metal organic chemical vapor deposition device can be used to grow the semiconductor layer. High-purity H2 (hydrogen) or high-purity N2 (nitrogen) or a mixed gas of high-purity H2 and high-purity N2 is used as a carrier gas, high-purity NH3 is used as an N source, trimethyl gallium (TMGa) and triethyl gallium (TEGa) are used as gallium sources, trimethyl indium (TMIn) is used as an indium source, silane (SiH4) is used as an N-type dopant, trimethyl aluminum (TMAl) is used as an aluminum source, and bis(cyclopentadienyl) magnesium (CP2Mg) is used as a P-type dopant.

[0082] S22, manufacturing an active layer on the surface of the first semiconductor layer.

[0083] In the embodiments of the present disclosure, a multi-quantum well structure may be included, such as an InGaN / GaN multi-quantum well structure.

[0084] S23, fabricating a second semiconductor layer on the surface of the active layer.

[0085] In the embodiment of the present disclosure, the second semiconductor layer 103 may be a P-type semiconductor layer.

[0086] In the embodiment of the present disclosure, the first semiconductor layer and the second semiconductor layer may be a single layer. For example, the second semiconductor layer may be a P-type GaN layer.

[0087] The first semiconductor layer and the second semiconductor layer may also be a composite layer. For example, the second semiconductor layer includes a low-temperature P-type layer, a P-type electron blocking layer, a high-temperature P-type layer and a P-type contact layer stacked in sequence.

[0088] S24, performing patterning processing on the first semiconductor layer, the active layer and the second semiconductor layer, so that the first semiconductor layer, the active layer and the second semiconductor layer form a step structure.

[0089] Exemplarily, the first semiconductor layer, the active layer, and the second semiconductor layer are patterned by etching technology to form a step structure, wherein the step surface of the step structure is located in the first semiconductor layer.

[0090] S25. An ITO current spreading layer is fabricated on the surface of the second semiconductor layer. The surface of the ITO current spreading layer has a plurality of first microstructures. The surface of the first microstructure has a plurality of second microstructures. The first microstructure is a prism or a pyramid. The second microstructure is a pyramid.

[0091] See again Figure 2The first microstructure 141 on the surface of the ITO current spreading layer 104 is a prism, and the second microstructure 142 on the surface of the first microstructure 141 is a pyramid.

[0092] In a possible embodiment of the present disclosure, the first microstructure 141 may be a quadrangular pyramid. In other embodiments, the first microstructure 141 may also be other prisms.

[0093] In one example of the present disclosure, the upper bottom surface of the prism-shaped first microstructure 141 is a square, which is easy to manufacture and has good contact with the electrode. In addition, the structure can reduce total reflection without significantly reducing chip yield.

[0094] The side length of the square is 200-300 nm, and the height of the prism is 300-500 nm. The above dimensions can improve total reflection on the one hand, and have lower manufacturing difficulty and better electrical performance on the other hand.

[0095] Exemplarily, the side length of the square is 250 nm, and the height of the pyramid is 400 nm.

[0096] In other examples of the present disclosure, the upper bottom surface of the prism-shaped first microstructure 141 may also be other shapes, such as a parallelogram, a trapezoid, etc.

[0097] In a possible embodiment of the present disclosure, the first microstructure 141 may be a quadrangular pyramid. In other embodiments, the first microstructure 141 may also be other pyramids.

[0098] In a possible embodiment of the present disclosure, the second microstructure 142 may be a quadrangular pyramid. In other embodiments, the second microstructure 142 may also be other pyramids, such as a triangular pyramid.

[0099] In one example, the quadrangular pyramid may be a regular quadrangular pyramid. A regular quadrangular pyramid is convenient to manufacture, can better improve the total reflection problem, and is not easy to increase the chip voltage.

[0100] The side length of the regular quadrangular prism is 10-20 nm, and the height of the regular quadrangular prism is 5-15 nm. The above dimensions can improve total reflection and reduce the manufacturing difficulty.

[0101] Exemplarily, the side length of the regular quadrangular prism is 15 nm, and the height of the regular quadrangular prism is 10 nm.

[0102] In other examples, the tetrahedron may be a non-regular tetrahedron.

[0103] In the embodiment of the present disclosure, the shapes of the plurality of first microstructures 141 may be the same or different, for example, all the same or partly the same.

[0104] In the embodiment of the present disclosure, the shapes of the plurality of second microstructures 142 on the same first microstructure 141 may be the same or different, for example, all the same or partly the same.

[0105] In the embodiment of the present disclosure, the shapes of the plurality of second microstructures 142 on different first microstructures 141 may be the same or different, for example, all the same or partly the same.

[0106] In the embodiment of the present disclosure, all or part of the plurality of first microstructures 141 may be densely arranged, that is, there is no gap between them. The plurality of first microstructures 141 may also be distributed at intervals.

[0107] In the embodiment of the present disclosure, all or part of the plurality of second microstructures 142 on the same first microstructure 141 may be densely arranged, that is, there is no gap between them. The plurality of second microstructures 142 may also be distributed at intervals.

[0108] In the embodiment of the present disclosure, step S25 may include:

[0109] The first step is to form an ITO film on the surface of the second semiconductor layer.

[0110] The second step is to coat a layer of positive photoresist on the ITO film.

[0111] Exemplarily, the second step may include:

[0112] In an environment where the rotation speed of a coating machine is 2000-3000 r / min and the temperature is 20-30° C., a layer of positive photoresist with a thickness of 0.5-1 μm is coated on the ITO film.

[0113] The above environment and parameters can produce a positive photoresist film layer with good uniformity, providing a basis for the subsequent production of mask patterns.

[0114] For example, a layer of positive photoresist with a thickness of 0.8 μm is coated on the ITO film at a rotation speed of 2500 r / min and a temperature of 25° C. on a coating machine.

[0115] The amount of photoresist used is 1.2-1.8 ml, for example 1.5 ml.

[0116] After the photoresist is spread, it can be placed in a baking tray for baking to reduce the amount of bubbles caused by the photoresist spread and the residual moisture in the photoresist.

[0117] In other implementations, negative photoresist may also be used.

[0118] The third step is to make a mask pattern on the positive photoresist by nanoimprint technology.

[0119] Exemplarily, the third step may include:

[0120] In an environment of 60-70° C., a mask pattern is produced on the positive photoresist by using a silicon-based nanoimprint plate.

[0121] In this implementation, the use of a silicon-based nanoimprint plate at the above temperature can better form a refined mask pattern and can reduce the pressure required for imprinting (reducing chip stress damage). The use of a silicon-based nanoimprint plate is low in cost and can meet the imprinting requirements.

[0122] For example, under an environment of 65° C. and a pressure of 20 to 30 bar (eg, 25 bar), the pattern on the silicon-based nanoimprint plate is imprinted onto the positive photoresist to produce a mask pattern.

[0123] Optionally, after the third step, the photoresist mask pattern may be cured by an exposure technique.

[0124] The fourth step is to use the mask pattern to block and etch the ITO film to obtain the ITO current spreading layer.

[0125] Exemplarily, the fourth step may include:

[0126] Using the mask pattern to shield the ITO film, inductively coupled plasma (ICP) etching is performed to obtain the ITO current spreading layer;

[0127] The etching gas for the ICP etching is Ar gas, the ignition power is 150-250W, the etching power is 250-350W, the etching time is 200-400s, and the etching rate is 0.5-0.8 angstroms / s.

[0128] The above-mentioned process and parameters can be used to achieve fine etching of the ITO film, thereby transferring the mask pattern to the ITO to obtain the first microstructure and the second microstructure.

[0129] For example, the ignition power is 200 W, the etching power is 300 W, the etching time is 300 s, and the etching rate is 0.6 angstroms / s.

[0130] The AR gas concentration may be 800-1200 sccm, for example, 1000 sccm.

[0131] In this implementation, the combination of positive photoresist and nano-printing technology can achieve refined graphic design, effectively reduce the use of expensive photoresist and developer, and thus reduce the production cost of the chip. In addition, this solution can effectively reduce the use of photomasks, greatly reducing the cost of photomasks in LED chip manufacturing.

[0132] Optionally, the method may further include:

[0133] After the above manufacturing is completed, the chip is placed in a stripping solution to remove residual photoresist.

[0134] The degumming solution may be an organic degumming solution, and the soaking time is 300 seconds.

[0135] After soaking in the above degumming solution, soak in water for 100 seconds.

[0136] After soaking in water, the chip was placed in a spin dryer at a speed of 3600 r / min for 360 s to remove residual moisture on the chip surface.

[0137] S26, making a passivation layer, wherein the passivation layer covers the step structure.

[0138] In one example, step S26 includes:

[0139] A passivation layer is formed on the surface of the step structure by using a plasma enhanced chemical vapor deposition (PECVD) technique or an atomic layer deposition (ALD) technique.

[0140] Wherein, the deposition rate may be 0.8 angstroms / s.

[0141] In the embodiment of the present disclosure, the passivation layer is a SiO2 layer.

[0142] In other examples, the passivation layer may be a film layer formed of other insulating materials.

[0143] S27, manufacturing a first electrode and a second electrode, wherein the first electrode penetrates the passivation layer and is connected to the first semiconductor layer, and the second electrode penetrates the passivation layer and is connected to the second semiconductor layer.

[0144] In the embodiment of the present disclosure, step S27 includes:

[0145] In the first step, the passivation layer is patterned to form a first through hole and a second through hole.

[0146] A first through hole and a second through hole are formed on the surface of the passivation layer by using etching technology and photolithography technology. The first through hole is connected to the first semiconductor layer, and the second through hole is connected to the second semiconductor layer.

[0147] In the second step, a first electrode is fabricated in the first through hole, and a second electrode is fabricated in the second through hole.

[0148] The first electrode is manufactured in the first through hole by using electron beam evaporation technology or magnetron sputtering technology, and the second electrode is manufactured in the second through hole.

[0149] In the embodiments of the present disclosure, a plurality of light-emitting diodes are usually formed on the surface of a substrate with intervals therebetween. After the first electrode and the second electrode are manufactured, the substrate may be thinned, laser-cut and split to form a plurality of separate light-emitting diodes.

[0150] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A light emitting diode, characterized in that: The light emitting diode comprises: A first semiconductor layer (101), an active layer (102), and a second semiconductor layer (103) stacked in sequence, wherein the first semiconductor layer (101), the active layer (102), and the second semiconductor layer (103) are in a step structure (200); An ITO current spreading layer (104) located on the surface of the second semiconductor layer (103); A first electrode (105) and a second electrode (106), wherein the first electrode (105) is located on a step surface of the step structure (200), and the second electrode (106) is located on the ITO current spreading layer (104); The surface of the ITO current spreading layer (104) has a plurality of first microstructures (141), the surface of the first microstructure (141) has a plurality of second microstructures (142), the first microstructure (141) is a prism or a pyramid, and the second microstructure (142) is a pyramid.

2. The light emitting diode according to claim 1, characterized in that: The first microstructure (141) is a prism, and the upper base of the prism is a square.

3. The light emitting diode according to claim 2, characterized in that: The side length of the square is 200-300 nm, and the height of the prism is 300-500 nm.

4. The light emitting diode according to any one of claims 1 to 3, characterized in that: The second microstructure (142) is a regular quadrangular pyramid.

5. The light emitting diode according to claim 4, characterized in that: The side length of the regular quadrangular prism is 10-20 nm, and the height of the regular quadrangular prism is 5-15 nm.

6. A method for manufacturing a light emitting diode, characterized in that: The method comprises: Manufacturing a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence, wherein the first semiconductor layer, the active layer, and the second semiconductor layer are in a step structure; An ITO current spreading layer is formed on the surface of the second semiconductor layer, wherein the surface of the ITO current spreading layer has a plurality of first microstructures, the surface of the first microstructure has a plurality of second microstructures, the first microstructure is a prism or a pyramid, and the second microstructure is a pyramid; A first electrode and a second electrode are manufactured, wherein the first electrode is located on the step surface of the step structure, and the second electrode is located on the ITO current spreading layer.

7. The method according to claim 6, characterized in that Producing an ITO current spreading layer on the surface of the second semiconductor layer, comprising: Forming an ITO film on the surface of the second semiconductor layer; Coating a layer of positive photoresist on the ITO film; Fabricating a mask pattern on the positive photoresist by nanoimprint technology; The ITO film is etched by using the mask pattern to obtain the ITO current spreading layer.

8. The method according to claim 7, characterized in that A layer of positive photoresist is coated on the ITO film, comprising: In an environment where the rotation speed of a coating machine is 2000-3000 r / min and the temperature is 20-30° C., a layer of positive photoresist with a thickness of 0.5-1 μm is coated on the ITO film.

9. The method according to claim 7, characterized in that: The method of producing a mask pattern on the positive photoresist by nanoimprint technology comprises: In an environment of 60-70° C., a mask pattern is produced on the positive photoresist by using a silicon-based nanoimprint plate.

10. The method according to claim 7, characterized in that The ITO film is etched by using the mask pattern to obtain the ITO current spreading layer, including: Using the mask pattern to shield and perform ICP etching on the ITO film to obtain the ITO current spreading layer; The etching gas for the ICP etching is Ar gas, the ignition power is 150-250W, the etching power is 250-350W, the etching time is 200-400s, and the etching rate is 0.5-0.8 angstroms / s.

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