Display panel and display device

Abstract

The invention provides a display panel and a display device, and solves the problem of how to fully utilize the wiring space in the display panel in the prior art. The display panel comprises a substrate; a first element portion on the substrate; a second element portion on the substrate; the third element part is located on the substrate, the third element part and the first element part are arranged in different layers, and the third element part and the second element part are arranged in different layers; the first via hole exposes at least part of the surface, far away from the substrate, of the third element part, at least part of the surface, far away from the substrate, of the first element part and at least part of the surface, far away from the substrate, of the second element part; the first via hole is filled with the first connecting part, and the first connecting part is electrically connected with the third element part, the first element part and the second element part.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, the industry's requirements for the thickness and resolution of display products are constantly increasing, resulting in increasingly tight wiring space. Summary of the invention

[0003] In view of this, the embodiments of the present application provide a display panel and a display device, which solve the problem of how to fully utilize the wiring space in the display panel in the prior art.

[0004] In a first aspect, the present application provides a display panel. The display panel includes a substrate; a first component portion, located on the substrate; a second component portion, located on the substrate; a third component portion, located on the substrate, the third component portion and the first component portion are arranged in different layers, and the third component portion and the second component portion are arranged in different layers; a first via hole, exposing at least a portion of the surface of the third component portion away from the substrate, at least a portion of the surface of the first component portion away from the substrate, and at least a portion of the surface of the second component portion away from the substrate; a first connecting portion, filling the first via hole, and the first connecting portion is electrically connected to the third component portion, the first component portion, and the second component portion.

[0005] In combination with the first aspect, in some possible implementations, the first component portion and the second component portion are arranged on the same layer or on different layers.

[0006] In combination with the first aspect, in some possible implementations, the third component portion extends along the first direction; the orthographic projection of the first component portion on the substrate and the orthographic projection of the second component portion on the substrate are located on one side or both sides of the orthographic projection of the third component portion on the substrate along the second direction, and the first direction and the second direction intersect.

[0007] In combination with the first aspect, in some possible implementations, it further includes a second connecting portion, which is connected between the first component portion and the second component portion, and the overlapping area of ​​the orthographic projection of the second connecting portion on the substrate and the orthographic projection of the third component portion on the substrate overlaps with the orthographic projection of the first connecting portion on the substrate. Preferably, the first component portion, the second component portion, and the second connecting portion are arranged in the same layer; preferably, the first component portion, the second component portion, and the second connecting portion are located in the same active layer, and the third component portion is located in the gate layer; preferably, the third component portion is a first routing line, and the first routing line includes a first routing segment and a second routing segment arranged along the extension direction of the first routing line, and the second connecting portion is at The overlapping area of ​​the orthographic projection on the substrate and the orthographic projection of the first routing segment on the substrate overlaps with the orthographic projection of the first connecting portion on the substrate; the width of at least part of the first routing segment is less than or equal to the width of the second routing segment; preferably, a notch is provided on one or both sides of the first routing segment along its own width direction, and the orthographic projection of the notch on the substrate overlaps with the orthographic projection of the first via on the substrate; and / or, the first routing is provided with a break, and the orthographic projection of the break on the substrate overlaps with the orthographic projection of the first via on the substrate; the orthographic projection of the break on the substrate overlaps with the orthographic projection of the second connecting portion on the substrate; preferably, the first routing is an initialization signal line.

[0008] In combination with the first aspect, in some possible implementations, there is a first gap between the first component portion and the second component portion, and the orthographic projection of the first gap on the substrate overlaps with the orthographic projection of the third component portion on the substrate; preferably, the first component portion and the second component portion are located in the same active layer, and the third component portion is located in the gate layer; preferably, the third component portion is a first routing line, and the first routing line includes a first routing segment and a second routing segment arranged along an extension direction of the first routing line, and an overlapping area of ​​an orthographic projection of the first gap on the substrate and an orthographic projection of the first routing segment on the substrate overlaps with the orthographic projection of the first connecting portion on the substrate; the width of at least part of the first routing segment is less than or equal to the width of the second routing segment; preferably, a notch is provided on one or both sides of the first routing segment along its own opposite sides in a width direction, and the orthographic projection of the notch on the substrate overlaps with the orthographic projection of the first via on the substrate.

[0009] In combination with the first aspect, in some possible implementations, the film layer where the third component portion is located is located on a side of the film layer where the first component portion and the film layer where the second component portion are located, away from the substrate; or, the film layer where the third component portion is located is located on a side of the film layer where the first component portion and the film layer where the second component portion are located, close to the substrate; or, the film layer where the third component portion is located is located between the film layer where the first component portion and the film layer where the second component portion are located.

[0010] In combination with the first aspect, in some possible implementations, the display panel further includes a first transistor; the first component portion is an active portion of the first transistor; the display panel further includes a second transistor; the second component portion is an active portion of the second transistor; preferably, the active portion of the first transistor and the active portion of the second transistor are arranged in different layers; or the active portion of the first transistor and the active portion of the second transistor are arranged in the same layer, and the gate of the first transistor, the gate of the second transistor, and the third component portion are arranged in the same layer; preferably, the display panel further includes a second connecting portion, connected between the first component portion and the second component portion, and the orthographic projection of the second connecting portion on the substrate is aligned with the projection of the third component portion on the substrate. An overlapping area of ​​the orthographic projection on the substrate overlaps with the orthographic projection of the first connecting portion on the substrate, the first component portion, the second component portion, and the second connecting portion are located in the same active layer, the conductivity of the second connecting portion is less than the conductivity of the source region or the drain region of the active portion of the first transistor, or the doping concentration of the conductive particles of the second connecting portion is less than the doping concentration of the conductive particles of the source region or the drain region of the active portion of the first transistor; and / or the conductivity of the second connecting portion is less than the conductivity of the source region or the drain region of the active portion of the second transistor, or the doping concentration of the conductive particles of the second connecting portion is less than the doping concentration of the conductive particles of the source region or the drain region of the active portion of the second transistor.

[0011] In combination with the first aspect, in some possible implementations, the orthographic projection of the first connecting portion on the substrate is a rectangle; and / or the orthographic projection of the first via on the substrate is a rectangle; and / or the third component portion is an initialization signal line; and / or the first connecting portion covers at least a portion of the surface of the third component portion away from the substrate exposed by the first via, at least a portion of the surface of the first component portion away from the substrate, and at least a portion of the surface of the second component portion away from the substrate; and / or the display panel includes a first insulating layer, which is located between the film layer where the third component portion is located and the film layer where the first component portion is located, the first component portion and the second component portion are arranged in the same layer, and the first via penetrates the first insulating layer to expose at least a portion of the surface of the first component portion away from the substrate. A small portion of the surface of the second component portion away from the substrate; and / or, the display panel includes a second insulating layer, which is located on the side of the film layer where the third component portion is located and the film layer where the first component portion is located away from the substrate, and the first via penetrates the second insulating layer to expose at least a portion of the surface of the third component portion away from the substrate; the first via penetrates the first insulating layer and the second insulating layer to expose at least a portion of the surface of the first component portion away from the substrate and at least a portion of the surface of the second component portion away from the substrate; and / or, the orthographic projection of the first via on the substrate is located within the orthographic projection of the active layer where the first component portion is located on the substrate, or, the orthographic projection of the first via on the substrate is located within the orthographic projection of the active layer where the second component portion is located on the substrate.

[0012] In combination with the first aspect, in some possible implementations, the display panel also includes a plurality of pixel circuits arranged in an array, the pixel circuit including a first component portion and a second component portion; preferably, in two pixel circuits located in the same column and adjacent to each other, the first component portion in one pixel circuit and the second component portion in another pixel circuit are electrically connected to a third component portion through a first via and a first connecting portion, and the third component portion extends along a row direction, and the row direction and the column direction intersect; preferably, the pixel circuit includes a first transistor and a second transistor, the first component portion is an active portion of the first transistor, the second component portion is an active portion of the second transistor, and the first transistor and the second transistor have different functions; preferably, the third component portion is an initialization signal line; preferably, the initialization signal line is located at the gate layer of the first transistor and / or the gate layer of the second transistor; the pixel circuit also includes a driving transistor, the first transistor is used to initialize the gate, source or drain of the driving transistor, and / or, the display panel also includes a light-emitting device, and the second transistor is used to initialize the first electrode of the light-emitting device.

[0013] In combination with the first aspect, in some possible implementations, the display panel also includes a plurality of pixel circuits arranged in an array, the pixel circuit including a first component portion and / or a second component portion; preferably, in two pixel circuits located in the same column and adjacent to each other, the first component portion in one pixel circuit and the second component portion in the other pixel circuit have the same function, and are electrically connected to a third component portion through a first via and a first connecting portion, the third component portion extends along a row direction, and the row direction and the column direction intersect; and / or, the display panel includes a plurality of pixel circuit groups, the pixel circuit group includes two pixel circuits located in the same column and adjacent to each other, in the same pixel circuit group, the first component portion in one pixel circuit and the second component portion in the other pixel circuit have the same function, and are electrically connected to the third component portion through a first via and a first connecting portion; preferably, the pixel circuit includes a first transistor, at least one second component portion and at least one first component portion are active portions of the first transistor in different pixel circuits, the pixel circuit also includes a driving transistor, the first transistor is used to drive the gate, The source or drain is initialized, and / or the pixel circuit includes a second transistor, at least one second component part and at least one first component part are active parts of the second transistor in different pixel circuits, the display panel also includes a light-emitting device, and the second transistor is used to initialize the first electrode of the light-emitting device; preferably, the third component part is an initialization signal line; preferably, the initialization signal line is located at the gate layer of the first transistor and / or the gate layer of the second transistor; preferably, the active layers of two pixel circuits located in the same column and adjacent to each other are arranged in a mirror-symmetrical manner; and / or, the active layers of two pixel circuits located in the same row and adjacent to each other are arranged in a mirror-symmetrical manner; preferably, the active part of the first transistor and the active part of the second transistor are electrically connected to the same initialization signal line, or, different initialization signal lines; preferably, the initialization signal line includes a first initialization signal line and a second initialization signal line which are insulated and alternately arranged along the column direction, the active part of the first transistor is electrically connected to the first initialization signal line, and the active part of the second transistor is electrically connected to the second initialization signal line.

[0014] In combination with the first aspect, in some possible implementations, the pixel circuit further includes a data writing transistor, the data writing transistor is connected between the data line and the first electrode of the driving transistor, the gate of the second transistor and the gate of the data writing transistor are electrically connected to the first scanning line; the first scanning line and the initialization signal line are arranged on the same layer; and / or the data line and the first connecting portion are arranged on the same layer; preferably, the first scanning line and the initialization signal line extend along the first direction; the gate of the first transistor is electrically connected to the second scanning line, and the second scanning line and the initialization signal line are arranged on the same layer; preferably, the second scanning line and the initialization signal line extend along the first direction; preferably, the initialization signal line is located between the first scanning line and the second scanning line; preferably, the gate of the driving transistor and the initialization signal line are arranged on the same layer; preferably, the pixel circuit further includes a storage capacitor, the driving transistor The gate of the display panel is reused as the first plate of the storage capacitor; preferably, the display panel also includes a light-emitting control signal line, and the first scan line is located between the light-emitting control signal line and the initialization signal line; preferably, the pixel circuit also includes a first light-emitting control transistor, which is connected between the second electrode of the driving transistor and the first electrode of the light-emitting device, and the gate of the first light-emitting control transistor is electrically connected to the light-emitting control signal line; preferably, the data write transistor is used to be turned on in the write frame to transmit the data voltage on the data line to the driving transistor, and in the hold frame to transmit the bias voltage on the data line to the driving transistor; preferably, the pixel circuit also includes a threshold compensation transistor, which is connected between the gate and the second electrode of the driving transistor, and the gate of the threshold compensation transistor is electrically connected to the third scan line; preferably, the second scan line is located between the initialization signal line and the third scan signal line.

[0015] In combination with the first aspect, in some possible implementations, the display panel also includes a first power line, the first power line and the first connecting portion are arranged in the same layer, and the first power line extends along the second direction. Preferably, in the first direction, the first power line and the first connecting portion are arranged alternately; preferably, the display panel also includes a pixel circuit, and the first power line is electrically connected to the pixel circuit; preferably, the pixel circuit includes a storage capacitor, and at least part of the first power line is reused as the second plate of the storage capacitor; preferably, the data line extends in the second direction, and the first power line and the data line are arranged overlappingly in the first direction; preferably, in the first direction, the first connecting portion is located between the first power line and the data line; preferably, the pixel circuit includes a driving transistor and a second light-emitting control transistor, and the second light-emitting control transistor is connected between the first electrode of the driving static tube and the first power line; the gate of the second light-emitting control transistor is electrically connected to the light-emitting control signal line, and the light-emitting control signal line is arranged in the same layer as the third element portion; the light-emitting control signal line and the third element portion extend along the first direction, and the first direction and the second direction intersect.

[0016] In combination with the first aspect, in some possible implementations, the display panel also includes a first scanning circuit, the first scanning circuit includes a multi-stage first shift register, and the output end of each first shift register in at least one first shift register is electrically connected to the gate of the corresponding first transistor and the gate of the threshold compensation transistor; preferably, the first transistor and the threshold compensation transistor electrically connected to the same first shift register are located in different pixel circuits; preferably, in two adjacent rows of pixel circuits, the first transistor in one row of pixel circuits and the threshold compensation transistor in another row of pixel circuits are electrically connected to the same first shift register.

[0017] In combination with the first aspect, in some possible implementations, the active portion of the first transistor and the active portion of the threshold compensation transistor are connected in the positive projection of the substrate to form a groove shape, and the bottom and notch of the groove are arranged along the first direction; preferably, the first transistor includes at least two first sub-transistors connected in series; and / or, the threshold compensation transistor includes at least two second sub-transistors connected in series.

[0018] In combination with the first aspect, in some possible implementations, the third component portion is an initialization signal line; the display panel also includes a first scan line, the first scan line includes a third routing segment and a fourth routing segment arranged along an extension direction of the first scan line, and the distance between the third routing segment and the initialization signal line is smaller than the distance between the fourth routing segment and the initialization signal line; preferably, the first via hole is opposite to the third routing segment; preferably, the pixel circuit also includes a data write transistor, and the gate of the data write transistor is electrically connected to the first scan line; the display panel also includes a second via hole, the second via hole exposes a portion of the first electrode of the data write transistor; the orthographic projection of the second via hole on the substrate is located between the orthographic projection of the initialization signal line on the substrate and the orthographic projection of the first scan line on the substrate.

[0019] In combination with the first aspect, in some possible implementations, the display panel also includes a light-emitting control signal line, which is located on the side of the first scan line away from the initialization signal line; the display panel also includes a third via, a fourth via and a fifth via, and the orthographic projections of the third via, the fourth via and the fifth via on the substrate are all located between the light-emitting control signal line and the first scan line; preferably, the orthographic projections of the third via and the fourth via on the substrate are both located between the orthographic projection of the third routing segment on the substrate and the orthographic projection of the light-emitting control signal line on the substrate; preferably, the orthographic projection of the fifth via on the substrate is located between the orthographic projection of the fourth routing segment on the substrate and the orthographic projection of the light-emitting control signal line on the substrate.

[0020] In combination with the first aspect, in some possible implementations, the pixel circuit further includes a first light-emitting control transistor; the display panel further includes a third connection portion, the third via hole exposes the second electrode of the first light-emitting control transistor, and the third connection portion fills the third via hole; preferably, the display panel further includes a light-emitting device, which is located on the side of the pixel circuit away from the substrate, and the first electrode of the light-emitting device is electrically connected to the third connection portion; preferably, the pixel circuit further includes a second light-emitting control transistor; the display panel further includes a power signal line, the fourth via hole exposes the first electrode of the second light-emitting control transistor, and the power signal line fills the fourth via hole; preferably, the pixel circuit further includes a data writing transistor and a driving transistor; the display panel further includes a fourth connection portion, the fifth via hole exposes the second electrode of the data writing transistor, and the sixth via hole exposes the first electrode of the driving transistor; the fourth connection portion fills the fifth via hole and the sixth via hole; preferably, the third via hole, the fourth via hole and the fifth via hole are arranged in sequence along the first direction; preferably, the orthographic projection of the sixth via hole on the substrate is located on the side of the orthographic projection of the light-emitting control signal line on the substrate away from the orthographic projection of the first scanning line on the substrate.

[0021] The second aspect of the present application provides another display panel, comprising: a substrate; a first component portion, located on the substrate; a second component portion, located on the substrate; a third component portion, located on the substrate, the third component portion and the first component portion are arranged in different layers, and the third component portion and the second component portion are arranged in different layers; a plurality of first vias, at least one of the first vias exposing at least a portion of the surface of the third component portion away from the substrate and at least a portion of the surface of the first component portion away from the substrate, and at least one of the first vias exposing at least a portion of the surface of the third component portion away from the substrate and at least a portion of the surface of the second component portion away from the substrate; a plurality of first connecting portions, filling the corresponding first vias, electrically connecting the third component portion and the first connecting portion of the first component portion, and spaced apart from the first connecting portion electrically connecting the third component portion and the second component portion.

[0022] In combination with the second aspect, in some possible implementations, the display panel also includes a plurality of pixel circuits arranged in an array, the pixel circuits including the first component portion and / or the second component portion, preferably, the display panel includes a plurality of pixel circuit groups, the pixel circuit group includes two pixel circuits located in the same row and adjacent to each other, in the same pixel circuit group, the first component portion in one pixel circuit and the second component portion in another pixel circuit are electrically connected to the third component portion through the first via and the first connecting portion, the third component portion extends along the row direction, and the row direction and the column direction intersect; preferably, the pixel circuit includes a first transistor, at least one of the second component portions and at least one of the first component portions are active portions of the first transistor in different pixel circuits, the pixel circuit also includes a driving transistor, the first transistor is used to initialize the gate, source or drain of the driving transistor, and / or the pixel circuit includes a second transistor , at least one of the second component parts and at least one of the first component parts are active parts of the second transistor in different pixel circuits, the display panel also includes a light-emitting device, and the second transistor is used to initialize the first electrode of the light-emitting device; preferably, the third component part is an initialization signal line; preferably, the initialization signal line is located in the gate layer of the first transistor and / or the gate layer of the second transistor; preferably, the active layers of two adjacent pixel circuits in the same row are arranged in mirror symmetry; preferably, the active part of the first transistor and the active part of the second transistor are electrically connected to the same initialization signal line, or, different initialization signal lines; preferably, the initialization signal line includes a first initialization signal line and a second initialization signal line which are insulated and alternately arranged along the column direction, the active part of the first transistor is electrically connected to the first initialization signal line, and the active part of the second transistor is electrically connected to the second initialization signal line.

[0023] A third aspect of the present application provides a display device, comprising a display panel provided by any of the above embodiments.

[0024] According to the display panel and display device provided in the embodiments of the present application, the first via is used to realize the connection between the first component part and the second component part and the third component part respectively. Compared with the layout in the related art that requires three vias to achieve electrical connection, the wiring space of the display panel is saved, which makes it possible to realize high-resolution display. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] By describing the embodiments of the present application in more detail in conjunction with the accompanying drawings, the above and other purposes, features and advantages of the present application will become more apparent. The accompanying drawings are used to provide a further understanding of the embodiments of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation of the present application. In the accompanying drawings, the same reference numerals generally represent the same components or steps.

[0026] Figure 1 A schematic diagram of a partial cross-sectional structure of a display panel provided in the first embodiment of the present application.

[0027] Figure 2 The first embodiment of the present application provides Figure 1 A partial top view structural diagram of a display panel is shown.

[0028] Figure 3 The second embodiment of the present application provides Figure 1 A partial top view structural diagram of a display panel is shown.

[0029] Figure 4a A schematic diagram of a partial cross-sectional structure of a display panel provided in the second embodiment of the present application.

[0030] Figure 4b for Figure 4a A partial top view structural diagram of a display panel is shown.

[0031] Figure 5a A schematic diagram of a partial cross-sectional structure of a display panel provided in the third embodiment of the present application.

[0032] Figure 5b A schematic diagram of a partial cross-sectional structure of a display panel provided in the fourth embodiment of the present application.

[0033] Figure 5c A schematic diagram of a partial cross-sectional structure of a display panel provided in the fifth embodiment of the present application.

[0034] Figure 6a A partial top view structural schematic diagram of a display panel provided in the sixth embodiment of the present application.

[0035] Figure 6b for Figure 6a The figure is a schematic diagram of the partial cross-sectional structure of the display panel along the N7N8 line.

[0036] Figure 7a A partial top view structural schematic diagram of a display panel provided in the seventh embodiment of the present application.

[0037] Figure 7b for Figure 7a The figure shows a schematic diagram of the partial cross-sectional structure of the display panel along the N9N10 line.

[0038] Figure 8 A first layout of a display panel provided in an embodiment of the present application.

[0039] Figure 9a for Figure 8 Wiring diagram for the active layer in the layout shown.

[0040] Figure 9b for Figure 8 Wiring diagram for the first conductive layer in the layout shown.

[0041] Fig.9c for Figure 8 Schematic diagram of the stacked structure of the active layer and the first conductive layer in the layout shown.

[0042] Figure 9d for Figure 8 A schematic diagram of the arrangement of vias in the layout.

[0043] Fig.9e for Figure 8 Schematic diagram of the stacked structure of vias, active layer and first conductive layer in the layout shown.

[0044] Figure 9f for Figure 8 Schematic diagram of the stacked structure of the second conductive layer in the layout shown.

[0045] Figure 9g for Figure 8 Schematic diagram of the stacked structure of the active layer, the first conductive layer and the second conductive layer in the layout shown.

[0046] Fig.10 for Figure 8 Circuit diagram of the pixel circuit included in the shown layout.

[0047] Fig.11 A second layout of a display panel provided in an embodiment of the present application.

[0048] Fig.12 Another embodiment of the present application provides Figure 8 Wiring diagram for the first conductive layer in the layout shown.

[0049] Fig.13 An embodiment of the present application provides Figure 8 Schematic diagram of the cross-sectional structure of the display panel shown in the layout.

[0050] Fig.14 A driving timing sequence of a pixel circuit provided in an embodiment of the present application.

[0051] Fig.15a A circuit diagram of a pixel circuit provided in accordance with another embodiment of the present application.

[0052] Fig.15b This is a third layout of a display panel provided in an embodiment of the present application.

[0053] Fig.16 This is a fourth layout of a display panel provided in an embodiment of the present application.

[0054] Fig.17 This is a fifth layout of a display panel provided in an embodiment of the present application.

[0055] Fig.18 This is a sixth layout of a display panel provided in an embodiment of the present application.

[0056] Fig.19 This is a seventh layout of a display panel provided in an embodiment of the present application.

[0057] Fig. 20 This is an eighth layout of a display panel provided in an embodiment of the present application.

[0058] Fig.21 This is a ninth layout of a display panel provided in an embodiment of the present application.

[0059] Fig. 22 A circuit diagram of a pixel circuit provided in accordance with another embodiment of the present application.

[0060] Fig.23 A circuit diagram of a pixel circuit provided in accordance with another embodiment of the present application.

[0061] Fig.24a A partial top view structural schematic diagram of a display panel provided in another embodiment of the present application.

[0062] Figure 24b A schematic diagram of a partial cross-sectional structure of a display panel provided in another embodiment of the present application.

[0063] Fig.24c This is the tenth layout of the display panel provided in one embodiment of the present application.

[0064] Fig.25 A schematic diagram of the structure of a display device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0065] As mentioned in the background technology, with the development of display technology, the industry's requirements for the thickness and resolution of display products are constantly increasing, resulting in increasingly tight wiring space. The inventors have found that one of the reasons for this problem is that in the related art, in order to achieve the purpose of connecting the electrodes (such as the drain or source) of two transistors to the reference voltage signal line Vref at the same time, three conductive vias are required. On the one hand, the three conductive vias greatly occupy the wiring space of the second conductive layer; on the other hand, the wiring width of the reference voltage signal line Vref needs to be compressed to accommodate the three conductive vias, which increases the resistance of the reference voltage signal line Vref.

[0066] In view of this, embodiments of the present application provide a display panel, a substrate, and a display device, which save wiring space by merging three conductive vias into one.

[0067] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0068] In the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is understood that when a structure is referred to as being "on or under" another structure, the structure may be directly on or under the other structure, or there may be intermediate structures. The same reference numerals always indicate the same structure. The structures mentioned herein include any of a film layer, an element, a device, a component, and an assembly.

[0069] When a structure is referred to as being “connected” to another structure, the structure may be directly connected to the other structure or indirectly connected to the other structure with one or more intermediate structures interposed therebetween.

[0070] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0071] A first aspect of the present application provides a display panel. Figure 1 FIG. 1 is a schematic diagram of a partial cross-sectional structure of a display panel provided in the first embodiment of the present application. Figure 1 As shown, the display panel includes a substrate 11, a first component part 12, a second component part 13, a third component part 14, a first via hole H1 and a first connecting part 15. The first component part 12 is located on the substrate 11. The second component part 13 is located on the substrate 11. The third component part 14 is located on the substrate 11. The third component part 14 and the first component part 12 are arranged in different layers, for example, an insulating layer is arranged between the film layer where the third component part 14 is located and the film layer where the first component part 12 is located. The third component part 14 and the second component part 13 are arranged in different layers, for example, an insulating layer is arranged between the film layer where the third component part 14 is located and the film layer where the second component part 13 is located. The first via hole H1 exposes at least part of the surface of the third component part 14 away from the substrate 11, at least part of the surface of the first component part 12 away from the substrate 11, and at least part of the surface of the second component part 13 away from the substrate 11. The first connecting part 15 fills the first via hole H1. The first connecting part 15 is electrically connected to the third component part 14, the first component part 12, and the second component part 13, for example, electrically contacted.

[0072] Exemplarily, the first component part 12 and the second component part 13 are arranged in the same layer, for example, the first component part 12 and the second component part 13 can be obtained by patterning the same film layer. For example, the third component part 14 can extend along the first direction x, for example, it can extend along the first direction x in a straight line, a broken line, a curve, a dendrite, an irregular shape, etc. For example, the orthographic projection of the first component part 12 on the substrate 11 and the orthographic projection of the second component part 13 on the substrate 11 can be located on opposite sides of the orthographic projection of the third component part 14 on the substrate 11 along the second direction y. The second direction y intersects with the first direction x, for example, the second direction y is perpendicular to the first direction x.

[0073] For example, Figure 1 As shown, the film layer where the third component part 14 is located is located on the side of the film layer where the first component part 12 and the film layer where the second component part 13 are located away from the substrate 11. For another example, the film layer where the third component part 14 is located is located on the side of the film layer where the first component part 12 and the film layer where the second component part 13 are located close to the substrate 11.

[0074] Exemplarily, the display panel further includes a second connection portion 16, which is connected between the first element portion 12 and the second element portion 13. The overlapping area of ​​the orthographic projection of the second connection portion 16 on the substrate 11 and the orthographic projection of the third element portion 14 on the substrate 11 overlaps with the orthographic projection of the first connection portion 12 on the substrate 11. For example, the first element portion 12, the second element portion 13, and the second connection portion 16 are arranged in the same layer. The first element portion 12, the second element portion 13, and the second connection portion 16 are located in the same active layer, for example, the active layer may include materials such as polysilicon or metal oxide. The metal oxide may include indium gallium zinc oxide (IGZO) and the like. The third element portion 14 is located in the gate layer.

[0075] Exemplarily, the display panel further includes a first insulating layer 17, which is located between the film layer where the third component part 14 is located and the film layer where the first component part 13 is located. For example, the first component part 12 and the second component part 13 are arranged in the same layer or in different layers. The first via H1 penetrates the first insulating layer 17 along the thickness direction z of the substrate 11 to expose at least a portion of the surface of the first component part 12 away from the substrate 11 and at least a portion of the surface of the second component part 13 away from the substrate 11. For example, the first insulating layer 17 can be a gate insulating layer.

[0076] Exemplarily, the display panel may further include a second insulating layer 18, which is located on the side of the film layer where the third component portion 14 is located and the first insulating layer 17 away from the substrate 11. The first via H1 penetrates the second insulating layer 18 to expose at least part of the surface of the third component portion 14 away from the substrate 11. The first via H1 penetrates the first insulating layer 17 and the second insulating layer 18 to expose at least part of the surface of the first component portion 12 away from the substrate 11 and at least part of the surface of the second component portion 13 away from the substrate 11. For example, the second insulating layer may include a capacitor dielectric layer and / or an interlayer insulating layer.

[0077] According to the display panel provided in this embodiment, a via hole, i.e., the first via hole H1, is used to realize the connection between the first component part 12 and the second component part 13 and the third component part 14 respectively. Compared with the layout in the related art that requires three via holes to achieve electrical connection, the wiring space of the display panel is saved, which makes it possible to realize high-resolution display.

[0078] Figure 2 The first embodiment of the present application provides Figure 1 A partial top view structural diagram of a display panel is shown. Figure 1 The cross-sectional view of the display panel shown may be Figure 2The cross-sectional view corresponding to the middle section line N1N2. In this embodiment, the third component part 14 is a first routing line, and the first routing line includes a first routing line segment 141 and a second routing line segment 142 arranged along the extension direction of the first routing line, and the overlapping area of ​​the orthographic projection of the second connecting part 16 on the substrate 11 and the orthographic projection of the first routing line segment 141 on the substrate 11 overlaps with the orthographic projection of the first connecting part 15 on the substrate 11. The width of the first routing line segment 141 is equal to the width of the second routing line segment 142.

[0079] Exemplarily, the first wiring is the initialization signal line Ref.

[0080] Exemplarily, the orthographic projection of the first connection portion 15 on the substrate 11 is a rectangle. Exemplarily, the orthographic projection of the first via hole H1 on the substrate 11 is a rectangle.

[0081] For example, the width of at least a portion of the first routing segment 141 is less than or equal to the width of the second routing segment 142 .

[0082] Figure 3 The second embodiment of the present application provides Figure 1 A partial top view structural diagram of a display panel is shown. Figure 1 The cross-sectional view of the display panel shown may be Figure 3 The cross-sectional view corresponding to the cross-sectional line N3N4 in FIG. Figure 3 The display panel and Figure 2 The difference of the display panel shown is that, in this embodiment, the width of at least part of the first wiring segment 141 is smaller than the width of the second wiring segment 142. In this way, the layout space occupied can be further reduced.

[0083] Exemplarily, a gap G is provided on one or both sides of the first wiring segment 141 along its width direction (eg, parallel to the second direction Y), and the orthographic projection of the gap G on the substrate overlaps with the orthographic projection of the first via H1 on the substrate.

[0084] Figure 4a A schematic diagram of a partial cross-sectional structure of a display panel provided in the second embodiment of the present application. Figure 4b for Figure 4a A partial top view structural diagram of a display panel is shown. Figure 4a The cross-sectional view shown may be Figure 4b The cross-sectional view corresponding to the section line N5N6 in FIG. Figure 4a , Figure 4b The display panel and Figure 1The difference of the display panel shown is that, in this embodiment, there is a first gap Q between the first element portion 12 and the second element portion 13, and the orthographic projection of the first gap Q on the substrate 11 overlaps with the orthographic projection of the third element portion 14 on the substrate 11. The first element portion 12 and the second element portion 13 are located in the same active layer, for example, the active layer may include materials such as polysilicon or metal oxide. The third element portion 14 is located in the gate layer.

[0085] For example, the orthographic projection of the first via hole H1 on the substrate 11 is located within the orthographic projection of the active layer where the first element portion 12 is located on the substrate 11 , or the orthographic projection of the first via hole H1 on the substrate is located within the orthographic projection of the active layer where the second element portion 13 is located on the substrate 11 .

[0086] Figure 5a A schematic diagram of a partial cross-sectional structure of a display panel provided in the third embodiment of the present application. Figure 5b A schematic diagram of a partial cross-sectional structure of a display panel provided in the fourth embodiment of the present application. Figure 5c A schematic diagram of a partial cross-sectional structure of a display panel provided in the fifth embodiment of the present application. Figure 5a , Figure 5b and Figure 5c The display panel and Figure 2 The difference between the display panels shown is that Figure 5a , Figure 5b and Figure 5c In the display panel shown, the first element portion 12 and the second element portion 13 are arranged in different layers.

[0087] For example, Figure 5a As shown, the film layer where the third component part 14 is located is located on the side of the film layer where the first component part 12 is located and the film layer where the second component part 13 is located away from the substrate 11. For example, in the direction away from the substrate 11, the film layer where the second component part 13 is located, the film layer where the first component part 12 is located, and the film layer where the third component part 14 is located are stacked in sequence. For another example, in the direction away from the substrate 11, the film layer where the first component part 12 is located, the film layer where the second component part 13 is located, and the film layer where the third component part 14 is located are stacked in sequence.

[0088] For example, an insulating layer is disposed between any two adjacent film layers where the second element portion 13 is located, the film layer where the first element portion 12 is located, and the film layer where the third element portion 14 is located.

[0089] For example, Figure 5bAs shown, the film layer where the third component part 14 is located is located on the side of the film layer where the first component part 12 is located and the film layer where the second component part 13 is located close to the substrate 11. For example, in the direction away from the substrate 11, the film layer where the third component part 14 is located, the film layer where the second component part 13 is located, and the film layer where the first component part 12 is located are stacked in sequence. For another example, in the direction away from the substrate 11, the film layer where the third component part 14 is located, the film layer where the first component part 12 is located, and the film layer where the second component part 13 is located are stacked in sequence.

[0090] For example, Figure 5c As shown, the film layer where the third component part 14 is located is located between the film layer where the first component part 12 is located and the film layer where the second component part 13 is located. For example, in the direction away from the substrate 11, the film layer where the first component part 12 is located, the film layer where the third component part 14 is located, and the film layer where the second component part 13 is located are stacked in sequence. For another example, in the direction away from the substrate 11, the film layer where the second component part 13 is located, the film layer where the third component part 14 is located, and the film layer where the first component part 12 is located are stacked in sequence.

[0091] For example, the orthographic projection of the first element portion 12 on the substrate 11 and the orthographic projection of the second element portion 13 on the substrate 11 are located on one or both sides of the orthographic projection of the third element portion 14 on the substrate 11 along the second direction y.

[0092] Figure 6a A partial top view structural schematic diagram of a display panel provided in the sixth embodiment of the present application. Figure 6b for Figure 6a The partial cross-sectional structure diagram of the display panel along the N7N8 line is shown. Figure 6a and Figure 6b The display panel and Figure 1-Figure 5c The difference between the display panels provided in any of the embodiments is that, in this embodiment, the orthographic projection of the first element portion 12 on the substrate 11 and the orthographic projection of the second element portion 13 on the substrate 11 are located on one side of the opposite sides of the orthographic projection of the third element portion 14 on the substrate 11 along the second direction y.

[0093] Figure 7a A partial top view structural schematic diagram of a display panel provided in the seventh embodiment of the present application. Figure 7b for Figure 7a The partial cross-sectional structure diagram of the display panel along the N9N10 line is shown. Figure 7a and Figure 7bAs shown, the difference between the display panel provided in this embodiment and the display panel provided in any of the above embodiments is that, in this embodiment, the third component part 14 is provided with a break D. The orthographic projection of the break D on the substrate 11 overlaps with the orthographic projection of the first via H1 on the substrate 11. For example, the third component part 14 is a first routing line, and illustratively, the first routing line is an initialization signal line. The first routing line is provided with a break D. The orthographic projection of the break D on the substrate 11 overlaps with the orthographic projection of the second connecting part 16 (and / or the first via H1) on the substrate 11. By providing a break to reduce the shielding of the second connecting part, the connection effect can be improved and the connection impedance can be reduced. At least part of the second connecting part is exposed by the break D, so that the doping concentration of the conductive particles of at least part of the second connecting part is increased, for example, equal to the doping concentration of the conductive particles of the source region or drain region of the first transistor T4 and / or the source region or drain region of the second transistor T7, and the same conductivity as the source region or drain region of the first transistor T4 and / or the source region or drain region of the second transistor T7.

[0094] Figure 8 A first layout of a display panel provided in an embodiment of the present application. Figure 9a for Figure 8 Wiring diagram for the active layer in the layout shown. Figure 9b for Figure 8 Wiring diagram for the first conductive layer in the layout shown. Fig.9c for Figure 8 Schematic diagram of the stacked structure of the active layer and the first conductive layer in the layout shown. Figure 9d for Figure 8 A schematic diagram of the arrangement of vias in the layout. Fig.9e for Figure 8 Schematic diagram of the stacked structure of vias, active layer and first conductive layer in the layout shown. Figure 9f for Figure 8 Schematic diagram of the stacked structure of the second conductive layer in the layout shown. Figure 9g for Figure 8 Schematic diagram of the stacked structure of the active layer, the first conductive layer and the second conductive layer in the layout shown.

[0095] Combination Figure 8 and Figure 9a-9g As shown, the display panel includes a first transistor T4, and the first element portion 12 is an active portion of the first transistor T4. And / or, the display panel further includes a second transistor T7, and the second element portion 13 is an active portion of the second transistor T7.

[0096] For example, the active portion of the first transistor T4 and the active portion of the second transistor T7 are arranged in different layers. For example, the active portion of the first transistor T4 and the active portion of the second transistor T7 are made of different or the same materials. For example, one of the active portion of the first transistor T4 and the active portion of the second transistor T7 includes polysilicon, and the other includes metal oxide.

[0097] The active portion of the first transistor T4 and the active portion of the second transistor T7 are arranged in the same layer, for example, the active portion of the first transistor T4 and the active portion of the second transistor T7 are made of the same material. For example, the gate of the first transistor T4, the gate of the second transistor T7, and the third element portion 14 are arranged in the same layer to reduce the number of film layers, simplify the process, and reduce costs.

[0098] Exemplarily, the first transistor T4 and the second transistor T7 may be initialization transistors.

[0099] Exemplarily, the pixel circuit 20 includes a first transistor T4 and a second transistor T7. The first element portion 12 is an active portion of the first transistor T4, and the second element portion 13 is an active portion of the second transistor T7. The first transistor T4 and the second transistor T7 have different functions.

[0100] Exemplarily, the pixel circuit 20 further includes a driving transistor T1. The first transistor T4 is used to initialize the gate, source or drain of the driving transistor T1. For example, the first transistor T4 may be electrically connected to the gate, source or drain of the driving transistor T1. And / or, the display panel further includes a light emitting device OLED. The second transistor T7 is used to initialize the first electrode of the light emitting device OLED.

[0101] Exemplarily, the display panel further includes a second connection portion 16 connected between the first element portion 12 and the second element portion 13. The overlapping area of ​​the orthographic projection of the second connection portion 16 on the substrate 11 and the orthographic projection of the third element portion 13 on the substrate 11 overlaps with the orthographic projection of the first connection portion 15 on the substrate 11. The first element portion 12, the second element portion 13, and the second connection portion 16 are located on the same active layer 19.

[0102] Exemplarily, the doping concentration of the conductive particles of the second connection portion 16 is less than the doping concentration of the conductive particles of the source region or the drain region of the active portion of the first transistor T4. And / or, the conductivity of the second connection portion 16 is less than the conductivity of the source region or the drain region of the active portion of the first transistor T4. Due to the shielding of the third element portion 13, the doping concentration of the conductive particles of the second connection portion 16 is lower than the doping concentration of the conductive particles of the source region or the drain region of the active portion of the first transistor T4, and the conductivity of the second connection portion 16 is less than the conductivity of the source region or the drain region of the active portion of the first transistor T4. If the first via H1 and the first connection portion 15 are not provided, the connection impedance between the active portion of the first transistor T4 and the active portion of the second transistor T7 will be large. Therefore, by providing the first via H1 and the first connection portion 15, the active portion of the first transistor T4 and the active portion of the second transistor T7 are electrically connected to the third element portion 14 (i.e., the first wiring, the initialization signal line), and the electrical connection impedance is reduced.

[0103] Exemplarily, the doping concentration of the conductive particles of the second connection portion 16 is less than the doping concentration of the conductive particles of the source region or the drain region of the active portion of the second transistor T7. And / or, the conductivity of the second connection portion 16 is less than the conductivity of the source region or the drain region of the active portion of the second transistor T7. Due to the shielding of the second connection portion 16 by the third element portion 13, the doping concentration of the conductive particles of the second connection portion 16 is lower than the doping concentration of the conductive particles of the source region or the drain region of the active portion of the second transistor T7, and the conductivity of the second connection portion 16 is less than the conductivity of the source region or the drain region of the active portion of the second transistor T7.

[0104] For example, in the same transistor, the portion where the scan line overlaps with the active portion may be a gate, the portion where the active portion overlaps with the scan line may be a channel region, and the source region and / or drain region are located on both sides of the channel region.

[0105] Fig.10 for Figure 8 The circuit diagram of the pixel circuit included in the layout shown. Figure 8 , Figure 9a-9g and Fig.10 As shown, the display panel further includes a plurality of pixel circuits 20 arranged in an array, and the pixel circuit 20 includes a first element portion 12 and a second element portion 13 .

[0106] Exemplarily, in two adjacent pixel circuits 20 located in the same column, the first component portion 12 in one pixel circuit 20 and the second component portion 13 in the other pixel circuit 20 are electrically connected to the third component portion 14 through the first via H1 and the first connecting portion 15. The third component portion 14 extends along the row direction, and the row direction (which may be parallel to the first direction x) and the column direction (which may be parallel to the second direction y) intersect.

[0107] Exemplarily, the third element portion 14 is an initialization signal line Ref.

[0108] Exemplarily, the pixel circuit further includes a data writing transistor T2. The data writing transistor T2 is connected between the data line Data and the first electrode of the driving transistor T1. The gate of the second transistor T7 and the gate of the data writing transistor T2 are electrically connected to the first scanning line S3.

[0109] Exemplarily, the first scan line S3 and the initialization signal line Ref are disposed at the same layer; and / or the data line Data and the first connection portion 15 are disposed at the same layer.

[0110] For example, two structures arranged in the same layer can be obtained by patterning the same film layer to simplify the process and the setting of the number of film layers.

[0111] Exemplarily, the first scan line S3 and the initialization signal line Ref extend along the first direction x.

[0112] For example, each signal line may extend along a corresponding direction in a straight line, a broken line, a curve, a tree branch shape, an irregular shape, or the like.

[0113] Exemplarily, the gate of the first transistor T4 is electrically connected to the second scan line S1 . For example, the second scan line S1 and the initialization signal line Ref are disposed at the same layer.

[0114] Exemplarily, the second scan line S1 and the initialization signal line Ref extend along the first direction x.

[0115] Exemplarily, the initialization signal line Ref is located between the first scan line S3 and the second scan line S1.

[0116] Exemplarily, the gate of the driving transistor T1 is disposed at the same layer as the initialization signal line Ref.

[0117] Exemplarily, the pixel circuit further includes a storage capacitor C, and the gate of the driving transistor T1 is reused as a first plate of the storage capacitor C.

[0118] Exemplarily, the display panel further includes a light emitting control signal line Em. The first scan line S3 is located between the light emitting control signal line Em and the initialization signal line Ref.

[0119] Exemplarily, the pixel circuit further includes a first light emission control transistor T6 connected between the second electrode of the driving transistor T1 and the first electrode of the light emitting device OLED. The gate of the first light emission control transistor T6 is electrically connected to the light emission control signal line Em.

[0120] Exemplarily, the data writing transistor T2 is used to be turned on in a writing frame to transmit the data voltage on the data line Data to the driving transistor T1 ; and turned on in a holding frame to transmit the bias voltage on the data line Data to the driving transistor T1 .

[0121] Exemplarily, the pixel circuit further includes a threshold compensation transistor T3 connected between the gate electrode and the second electrode of the driving transistor T1. The gate electrode of the threshold compensation transistor T3 is electrically connected to the third scan line S2.

[0122] Exemplarily, the second scan line S1 is located between the initialization signal line Ref and the third scan signal line S2.

[0123] Exemplarily, the display panel further includes a first power line VDD, for example, the first power line VDD is arranged in the same layer as the first connection portion 15. The first power line VDD extends along the second direction y. By providing the first via H1, the film layer space occupied by the first connection portion 15 is reduced, thereby ensuring the width of the first power line VDD in the same layer as the first connection portion 15, or facilitating increasing the width of the first power line VDD, reducing the line impedance of the first power line VDD, and thus improving display uniformity.

[0124] Exemplarily, the first power line VDD is electrically connected to the pixel circuit 20 .

[0125] Exemplarily, in the first direction x, the first power lines VDD and the first connection portions 15 are arranged alternately.

[0126] Exemplarily, at least part of the first power line VDD is reused as the second plate of the storage capacitor C. For example, a capacitor dielectric layer may be provided between the first plate and the second plate of the storage capacitor C. The orthographic projections of the first plate and the second plate of the storage capacitor C overlap on the substrate.

[0127] Exemplarily, the data line Data extends along the second direction y, and the first power line VDD and the data line Data are alternately arranged along the first direction x. Exemplarily, at least one of the first power line VDD and the data line Data may extend along the second direction y in a straight line, a folded line, a curve, a dendrite, an irregular shape, or the like.

[0128] Exemplarily, in the first direction x, the first connection portion 15 is located between the first power line VDD and the data line Data.

[0129] Exemplarily, the pixel circuit further includes a second light emission control transistor T6, which is connected between the first electrode of the driving transistor T1 and the first power line VDD. The gate of the second light emission control transistor T6 is electrically connected to the light emission control signal line Em, and the light emission control signal line Em is arranged on the same layer as the third element unit 14.

[0130] Exemplarily, the light emission control signal line Em and the third element portion 14 extend along the first direction x.

[0131] For example, Figure 9a As shown, the active portion T4_S of the first transistor and the active portion T3_S of the threshold compensation transistor are connected to form a groove shape in the orthographic projection of the substrate, and the bottom and the notch of the groove are arranged along the first direction x.

[0132] Exemplarily, the first transistor T4 includes at least two first sub-transistors connected in series, for example, the first transistor T4 may be a dual-gate transistor, for example, including first sub-transistors T4-1 and T4-2 connected in series. And / or, the threshold compensation transistor T3 includes at least two second sub-transistors connected in series, for example, the threshold compensation transistor T3 may be a dual-gate transistor, for example, including second sub-transistors T3-1 and T3-2 connected in series. Such an arrangement can reduce the leakage of the gate of the driving transistor and improve the low-frequency flicker phenomenon.

[0133] Exemplary, combined Figure 8 , Figure 9a-9g and Fig.10 As shown, the display panel further includes a second via hole H2, the second via hole H2 exposes the first electrode of the data writing transistor T2, and the data line Data fills the second via hole H2 and contacts, for example, electrically contacts, the first electrode of the data writing transistor T2. The display panel further includes a first scan line S3, which is electrically connected to the gate of the data writing transistor T2. The orthographic projection of the second via hole H2 on the substrate 11 is located between the orthographic projection of the first scan line S3 on the substrate 11 and the orthographic projection of the initialization signal line Ref on the substrate 11. For example, the second electrode of the data writing transistor T2 is electrically connected to the first electrode of the driving transistor T1.

[0134] Exemplary, combined Figure 8 , Figure 9a-9g and Fig.10 As shown, the display panel further includes a third via hole H3, and the third via hole H3 exposes the second electrode of the first light-emitting control transistor T6. The display panel further includes a third connecting portion 17, and the third connecting portion 17 fills the third via hole H3. Exemplarily, the third connecting portion 17 and the power signal line VDD are in the same layer. The third connecting portion 17 is connected to a first electrode of the light-emitting device OLED, such as an anode. The orthographic projection of the third via hole H3 on the substrate 11 is located between the orthographic projection of the first scan line S3 on the substrate 11 and the orthographic projection of the light-emitting control signal line Em on the substrate 11. For example, the first electrode of the first light-emitting control transistor T6 can be electrically connected to the second electrode of the driving transistor T1.

[0135] Exemplary, combined Figure 8 , Figure 9a-9g and Fig.10 As shown, the display panel further includes a fourth via hole H4, and the fourth via hole H4 exposes the first electrode of the second light emission control transistor T5. The power signal line VDD fills the fourth via hole H4 and contacts the first electrode of the second light emission control transistor T5. The orthographic projection of the fourth via hole H4 on the substrate 11 is located between the orthographic projection of the first scan line S3 on the substrate 11 and the orthographic projection of the light emission control signal line Em on the substrate 11. For example, the second electrode of the second light emission control transistor T5 is electrically connected to the first electrode of the driving transistor T1.

[0136] Exemplary, combined Figure 8 , Figure 9a-9g and Fig.10 As shown, the display panel also includes a fifth via H5 and a sixth via H6. The fifth via H5 exposes the second electrode of the data write transistor T2, and the sixth via H6 exposes the first electrode of the drive transistor T1. The display panel also includes a fourth connection portion 18, and the fourth connection portion 18 fills the fifth via H5 and the sixth via H6 to connect the second electrode of the data write transistor T2 and the first electrode of the drive transistor T1. Exemplarily, the fourth connection portion 18 and the power signal line VDD are on the same layer. The orthographic projection of the fifth via H5 on the substrate 11 is located between the orthographic projection of the first scan line S3 on the substrate 11 and the orthographic projection of the light emitting control signal line Em on the substrate 11. The orthographic projection of the sixth via H6 on the substrate 11 is located on the side of the orthographic projection of the light emitting control signal line Em on the substrate 11 away from the orthographic projection of the first scan line S3 on the substrate 11.

[0137] Exemplary, combined Figure 8 , Figure 9a-9g and Fig.10 As shown, the first scan line S3 includes a third routing segment S31 and a fourth routing segment S32 arranged along the extension direction of the first scan line S3. The distance D1 between the third routing segment S31 and the initialization signal line Ref is smaller than the distance D2 between the fourth routing segment S32 and the initialization signal line Ref, and / or the distance D3 between the third routing segment S31 and the light-emitting control signal line Em is larger than the distance D4 between the fourth routing segment S32 and the light-emitting control signal line Em.

[0138] Exemplarily, the first via H1 is directly opposite to the third wiring segment S31 .

[0139] Exemplarily, the orthographic projection of the second via H2 on the substrate 11 is located between the orthographic projection of the fourth wiring segment S32 on the substrate 11 and the orthographic projection of the initialization signal line Ref on the substrate 11 .

[0140] Exemplarily, the orthographic projection of the third via hole H3 on the substrate 11 is located between the orthographic projection of the third wiring segment S31 on the substrate 11 and the orthographic projection of the light emitting control signal line Em on the substrate 11 .

[0141] Exemplarily, the orthographic projection of the fourth via hole H4 on the substrate 11 is located between the orthographic projection of the third wiring segment S31 on the substrate 11 and the orthographic projection of the light emitting control signal line Em on the substrate 11 .

[0142] Exemplarily, the orthographic projection of the fifth via hole H5 on the substrate 11 is located between the orthographic projection of the fourth wiring segment S32 on the substrate 11 and the orthographic projection of the light emitting control signal line Em on the substrate 11 .

[0143] Exemplarily, along the extending direction of the initialization signal line Ref, for example, the first direction x, the third via hole H3 , the fourth via hole H4 , and the fifth via hole H5 are arranged in sequence.

[0144] Fig.11 This is a second layout of a display panel provided in an embodiment of the present application. Fig.11 and Figure 8 It can be seen that the display panel provided in this embodiment has Figure 8 The display panel shown further includes a first scanning circuit 40. The first scanning circuit 40 includes a plurality of first shift registers 41, and the output end of each first shift register 41 in at least one first shift register 41 is electrically connected to the gate of the corresponding first transistor T4 and the gate of the threshold compensation transistor T3. For example, the plurality of first shift registers 41 may be cascaded.

[0145] Exemplarily, the first transistor T4 and the threshold compensation transistor T3 electrically connected to the same first shift register 41 are located in different pixel circuits 20 .

[0146] Exemplarily, in two adjacent rows of pixel circuits 20 , the first transistors T4 in one row of pixel circuits 20 and the threshold compensation transistors T3 in another row of pixel circuits 20 are electrically connected to the same first shift register 41 .

[0147] Exemplarily, the first transistor T4 and the threshold compensation transistor T3 in the same pixel circuit 20 are electrically connected to different first shift registers 41 .

[0148] Optionally, the display panel may further include a second scanning circuit electrically connected to the gate of the data writing transistor T2. The second scanning circuit may include a multi-stage second shift register.

[0149] Fig.12 Another embodiment of the present application provides Figure 8 The wiring diagram of the first conductive layer in the layout shown. Fig.12 and Figure 9b It can be seen that the wiring and Figure 9b The difference between the wiring of the first conductive layer provided is that, in this embodiment, the initialization signal line Ref is provided with a break D. Fig.12 and Figure 9a , Figure 9c-9g As shown, the orthographic projection of the fracture D on the substrate 11 overlaps with the orthographic projection of the first via hole H1 (or the first connecting portion 15 ) on the substrate 11 .

[0150] Fig.13 An embodiment of the present application provides Figure 8 A schematic diagram of the cross-sectional structure of the display panel of the layout shown. Fig.13 and Figure 8 As shown, the display panel generally includes a plurality of electrically connected signal lines, a pixel circuit 20 and a light-emitting device OLED. The signal line provides a driving signal to the pixel circuit, and the pixel circuit 20 drives the light-emitting device OLED to emit light according to a predetermined brightness under the action of the driving signal. From the perspective of the film layer structure, the display panel includes: a substrate 11; and an active layer 19, a first insulating layer 17, a first conductive layer M1 (which may be a metal layer), a second insulating layer 18 and a second conductive layer M2 (which may be a metal layer) stacked on the substrate 11 in sequence. The light-emitting device OLED is located on the side of the second conductive layer M2 away from the substrate 11. The first conductive layer M1 (which may be a metal layer) may include a first scan line S3, a second scan line S1, a third scan line S2, a light-emitting control signal line Em, an initialization signal line Ref, a gate of a driving transistor T1, etc. The second conductive layer M2 may include a first power line VDD, a data line Data, etc.

[0151] In some embodiments, the substrate 11 may be a rigid substrate, such as a glass-based substrate, or the substrate 11 may be a flexible substrate, such as a flexible substrate including an organic material such as polyimide.

[0152] In some embodiments, the substrate 11 may include an organic resin material such as epoxy resin, triazine, silicone resin or polyimide. For example, the substrate 11 may be a FR4 type printed circuit board (PCB), or may be a flexible PCB that is easily deformed.

[0153] In some embodiments, the substrate 11 may include a ceramic material such as silicon nitride, aluminum nitride or aluminum oxide, or may include a metal or a metal compound. For example, the substrate 11 may be a metal core printed circuit board (MCPCB) or a metal-base copper-clad laminate (MCCL).

[0154] The materials of the first insulating layer 17 and the second insulating layer 18 are the same or different. Exemplarily, the material of at least one of the first insulating layer 17 and the second insulating layer 18 includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0155] The materials of the first conductive layer M1 and the second conductive layer M2 are the same or different. Exemplarily, the material of the first conductive layer M1 includes molybdenum. The second conductive layer M2 has a Ti / Al / Ti triple-layer structure.

[0156] The light-emitting device OLED may be an organic light-emitting diode (OLED), a micro light-emitting diode (Micro LED), a quantum dot light-emitting diode (QLED), etc. The light-emitting device OLED may be a light-emitting device of various colors, such as a red light-emitting device R, a green light-emitting device G, a blue light-emitting device B, etc.

[0157] like Fig.13 As shown, the light-emitting device OLED includes a first electrode 21, a light-emitting layer 22, and a second electrode 23 stacked in sequence in a direction gradually away from the substrate 11. Exemplarily, the first electrode 21 is an anode and the second electrode 23 is a cathode. Alternatively, the first electrode 21 is a cathode and the second electrode 23 is an anode. Exemplarily, the light-emitting device OLED may also include at least one of a hole injection layer, a hole transport layer, and an electron blocking layer located between the anode and the light-emitting layer 22, and at least one of an electron injection layer, an electron transport layer, and a hole blocking layer located between the cathode and the light-emitting layer 22. Exemplarily, one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all light-emitting devices OLED may be a common layer connected together, and the light-emitting layers of adjacent light-emitting devices OLED may overlap slightly, or may be isolated from each other.

[0158] In some embodiments, Fig.13 As shown, the display panel further includes a third insulating layer 33 and a pixel definition layer 34. The third insulating layer 33 is located between the second conductive layer M2 and the light-emitting device OLED. The pixel definition layer 34 is located on the side of the second conductive layer M2 away from the substrate 11, and the pixel definition layer 34 encloses a pixel opening. At least part of the light-emitting device OLED is located in the pixel opening. For example, the pixel opening exposes part of the first electrode 21, the light-emitting layer 22 is located in the pixel opening, and the second electrode 22 is a common layer.

[0159] Fig.14 The driving timing of the pixel circuit provided in one embodiment of the present application. Fig.14 As shown, the driving process of the display panel includes writing a frame and maintaining a frame.

[0160] The writing frame includes:

[0161] In the first reset stage t1, for example, the gate reset stage, the light-emitting control signal em is at an off level, for example, a high level, the second scanning signal s2 and the third scanning signal s3 are all at an off level, for example, a high level, and the first scanning signal s1 is at an on level, for example, a low level, so that the first transistor T1 is turned on, and the data writing transistor T2, the threshold compensation transistor T3, the first transistor T4, the second light-emitting control transistor T5, the first light-emitting control transistor T6 and the second transistor T7 are all turned off, so as to use the initialization signal Vref to reset the gate of the driving transistor T1.

[0162] In the data writing stage t2, the second reset stage (e.g., the anode reset stage) may overlap with the data writing stage, the first scanning signal s1 becomes an off level, such as a high level, the second scanning signal s2 and the third scanning signal s3 become an on level, such as a low level, so that the data writing transistor T2, the threshold compensation transistor T3 and the second transistor T7 are all turned on, and the first transistor T1, the first transistor T4, the second light-emitting control transistor T5 and the first light-emitting control transistor T6 are all turned off. In the data writing stage, the data writing transistor T2 and the threshold compensation transistor T3 are turned on, and the data signal in the data line Data is passed through the turned-on driving transistor and the threshold compensation transistor T3, and the threshold voltage of the driving transistor T1 is compensated to the data signal, so as to write the threshold compensated data signal to the gate of the driving transistor T1. In the second reset stage, the second transistor T7 is turned on, and is used to reset the first electrode (e.g., anode) of the light-emitting device OLED using the initialization signal Vref. The second reset stage of the writing frame may also not overlap with the data writing stage. The second reset stage of the writing frame may also overlap or not overlap with the first reset stage.

[0163] In the light-emitting stage t3, the second scanning signal s2 and the third scanning signal s3 become off-level, such as high level, and the light-emitting control signal em becomes on-level, such as low level, so that the data writing transistor T2, the threshold compensation transistor T3, the first transistor T4 and the second transistor T7 are turned off, and the second light-emitting control transistor T5 and the first light-emitting control transistor T6 are turned on, which are used to control the driving current generated by the driving transistor T1 to drive the light-emitting device to emit light.

[0164] The hold frame includes:

[0165] In the third reset stage t4, the light-emitting control signal em, the first scan signal s1 and the second scan signal s2 are all at the off level, such as the high level, and the third scan signal s3 is at the on level, such as the low level, so that the data writing transistor T2 and the second transistor T7 are turned on, and the first transistor T1, the threshold compensation transistor T3, the first transistor T4, the second light-emitting control transistor T5, and the first light-emitting control transistor T6 are all turned off. Among them, in the third reset stage, the data writing transistor T2 is turned on to transmit the bias voltage Vref3 in the data line Data to the driving transistor T1 to improve the stress in the driving transistor. In the second reset stage (that is, the second reset stage of the holding frame can overlap with the third reset stage), the second transistor T7 is turned on to reset the first electrode (for example, the anode) of the light-emitting device OLED using the initialization signal Vref. The second reset stage of the holding frame may also not overlap with the third reset stage.

[0166] The light-emitting phase t5 of the hold frame is the same as or similar to the light-emitting phase of the write frame, and will not be described in detail here.

[0167] Fig.15a A circuit diagram of a pixel circuit provided in accordance with another embodiment of the present application. Fig.15b This is a third layout of a display panel provided in an embodiment of the present application. Fig.15b As shown, the display panel further includes a plurality of pixel circuits 20 arranged in an array, and the pixel circuit 20 includes a first component part 12 and / or a second component part 13. Exemplarily, the first component part 12 is an active part of the first transistor T4, and the second component part 13 is an active part of the second transistor T7.

[0168] In two pixel circuits 20 located in the same column and adjacent to each other, the first component part 12 in one pixel circuit 20 and the second component part 13 in the other pixel circuit 20 are electrically connected to the third component part 14 through the first via H1 and the first connecting part 15, and the third component part 14 extends in the row direction, and the row direction and the column direction intersect. And the first component part 12 in one pixel circuit 20 and the second component part 13 in the other pixel circuit 20 have the same function. Exemplarily, the third component part 14 is an initialization signal line Ref, and the initialization signal line Ref may include a first initialization signal line Ref1 and a second initialization signal line Ref2. In this case, the third component part 14 may be any one of the first initialization signal line Ref1 and the second initialization signal line Ref2. For example, the first initialization signal line Ref1 can be used to transmit a first initialization voltage Vref1. For example, the second initialization signal line Ref2 can be used to transmit a second initialization voltage Vref2.

[0169] Exemplarily, the pixel circuit 20 includes a first transistor T4, at least one second component portion 13 and at least one first component portion 12 are active portions of the first transistor T4 in different pixel circuits 20, and the pixel circuit 20 also includes a driving transistor T1, and the first transistor T4 is used to initialize the gate, source or drain of the driving transistor T1.

[0170] For example, the display panel includes a plurality of first pixel circuit subunits, and the first pixel circuit subunit includes two pixel circuits 20 located in the same column and adjacent to each other. In the same first pixel circuit subunit, the first transistor T4 in one pixel circuit 20 and the first transistor T4 in another pixel circuit 20 are electrically connected to the third element portion 14 (for example, the first initialization signal line Ref1) through the first via H1 and the first connecting portion 15, as shown in FIG. Fig.15b shown.

[0171] like Fig.15b The layout shown and Figure 8 The difference between the layouts shown is that, in this embodiment, the active layers of the two pixel circuits 20 located in the same column and adjacent to each other are arranged in mirror symmetry. For example, the pixel circuit 20 includes seven transistors, which are sequentially denoted as Ti, and i is 1 to 7. The active parts of the i-th transistor in the two pixel circuits 20 located in the same column and adjacent to each other are arranged in mirror symmetry. For example, in the two pixel circuits 20 located in the same column and adjacent to each other, the active part of the first transistor T1 in one pixel circuit 20 and the active part of the first transistor T1 in the other pixel circuit 20 are arranged in mirror symmetry; the active part of the second transistor T2 in one pixel circuit 20 and the active part of the second transistor T2 in the other pixel circuit 20 are arranged in mirror symmetry, and the same is true for other transistors.

[0172] Exemplarily, the pixel circuit 20 includes a first transistor T4 and a second transistor 7. The first element portion 12 is an active portion of the first transistor T4, and the second element portion 13 is an active portion of the second transistor T7. The active portion of the first transistor T4 and the active portion of the second transistor T7 are electrically connected to the same initialization signal line, or different initialization signal lines.

[0173] For example, Fig.15b As shown, the initialization signal line Ref includes a first initialization signal line Ref1 and a second initialization signal line Ref2 which are insulated and alternately arranged along a column direction (which may be parallel to the second direction y). The active portion of the first transistor T4 is electrically connected to the first initialization signal line Ref1, and the active portion of the second transistor T7 is electrically connected to the second initialization signal line Ref2. The voltages of the first initialization signal line Ref1 and the second initialization signal line Ref2 may be different.

[0174] Fig.16This is a fourth layout of a display panel provided in an embodiment of the present application. Fig.16 The layout shown and Fig.15b The difference between the illustrated layouts is that, in this embodiment, the pixel circuit 20 includes a second transistor T7, and at least one second component portion 13 and at least one first component portion 12 are active portions of the second transistor T7 in different pixel circuits 20. The display panel also includes a light emitting device OLED, and the second transistor T7 is used to initialize the first electrode of the light emitting device OLED.

[0175] For example, the display panel includes a plurality of second pixel circuit sub-units, and the second pixel circuit sub-unit includes two pixel circuits 20 located in the same column and adjacent to each other. In the same second pixel circuit sub-unit, the second transistor T7 in one pixel circuit 20 and the second transistor T7 in another pixel circuit 20 are electrically connected to the third element portion 14 (for example, the second initialization signal line Ref2) through the first via H1 and the first connecting portion 15, as shown in FIG. Fig.16 shown.

[0176] Fig.17 This is the fifth layout of the display panel provided in one embodiment of the present application. Fig.17 The layout shown and Fig.16 , Fig.15b The difference between the layout shown is that, in the present embodiment, among the three pixel circuits 20 located in the same column and adjacent to each other, the first transistor T4 in the pixel circuit 20 located on one side and the first transistor T4 in the pixel circuit 20 located in the middle are electrically connected to the third element portion 14 (for example, the first initialization signal line Ref1) through the first via hole H1 and the first connecting portion 15; the second transistor T7 in the pixel circuit 20 located on the other side and the second transistor T7 in the pixel circuit 20 located in the middle are electrically connected to the third element portion 14 (for example, the second initialization signal line Ref2) through the first via hole H1 and the first connecting portion 15, as shown in FIG. Fig.17 shown.

[0177] Fig.18 This is the sixth layout of the display panel provided in one embodiment of the present application. Fig.18 The display panel and Figure 8 The difference of the display panel shown is that, in this embodiment, the display panel includes a plurality of pixel circuit groups 201, and the pixel circuit group includes two pixel circuits located in the same row and adjacent to each other. In the same pixel circuit group, the first component part 12 in one pixel circuit 20 and the second component part 13 in another pixel circuit 20 have the same function and are electrically connected to the third component part 14 through the first via H1 and the first connecting part 15.

[0178] For example, the pixel circuit 20 includes a first transistor T4 , and at least one second element portion 13 and at least one first element portion 12 are active portions of the first transistor T4 in different pixel circuits 20 .

[0179] Specifically, in two pixel circuits in the same row and adjacent to each other in the same pixel circuit group, the active portion of the first transistor T4 in one pixel circuit 20 and the active portion of the first transistor T4 in the other pixel circuit 20 are electrically connected to the third element portion 14 (for example, the first initialization signal line Ref1) through the first via H1 and the first connecting portion 15. Fig.18 shown.

[0180] For another example, the pixel circuit 20 includes a second transistor T7 , and at least one second element portion 13 and at least one first element portion 12 are active portions of the second transistor T7 in different pixel circuits 20 .

[0181] Specifically, in two pixel circuits in the same row and adjacent to each other in the same pixel circuit group, the active portion of the second transistor T7 in one pixel circuit 20 and the active portion of the second transistor T7 in the other pixel circuit 20 are electrically connected to the third element portion 14 (for example, the second initialization signal line Ref2) through the first via H1 and the first connecting portion 15. Fig.18 shown.

[0182] In some embodiments, active layers of two adjacent pixel circuits 20 in the same row are arranged in mirror symmetry.

[0183] In some embodiments, the active portion of the first transistor T4 and the active portion of the second transistor T7 are electrically connected to the same initialization signal line, or, different initialization signal lines Ref.

[0184] Fig.19 This is the seventh layout of the display panel provided in one embodiment of the present application. Fig.19 The layout shown and Figure 8 The difference between the illustrated layouts is that, in this embodiment, the display panel includes a plurality of pixel circuit groups, and the pixel circuit group includes two pixel circuits 20 located in the same row and adjacent to each other. In the same pixel circuit group, the first component part 12 in one pixel circuit 20 and the second component part 13 in another pixel circuit 20 are electrically connected to the third component part through the first via H1 and the first connecting part. Two adjacent pixel circuit groups located in the same column are electrically connected to the same third component part located between the two pixel circuit groups through the same first via H1 and the same first connecting part 15.

[0185] Exemplarily, the pixel circuit 20 includes a first transistor T4. The second component portion 13 and the first component portion 12 are active portions of the first transistor T4 in different pixel circuits 20. For example, the display panel includes one or more first pixel circuit units, and the first pixel circuit unit includes two pixel circuit groups located in the same column and adjacent to each other. In the same first pixel circuit unit, the active portions of the four first transistors T4 in the two adjacent pixel circuit groups in the same column are electrically connected to the same third component portion (for example, the first initialization signal line Ref1) through the same first via H1 and the same first connecting portion 15.

[0186] Fig. 20 This is the eighth layout of the display panel provided in one embodiment of the present application. Fig. 20 The layout shown and Fig.19 The difference of the layout shown is that, in the present embodiment, the pixel circuit 20 includes a second transistor T7. The second component portion 13 and the first component portion 12 are active portions of the second transistor T7 in different pixel circuits 20. For example, the display panel includes one or more second pixel circuit units, and the second pixel circuit unit includes two pixel circuit groups located in the same column and adjacent to each other. In the same second pixel circuit unit, the active portions of the four second transistors T7 in the two adjacent pixel circuit groups in the same column are electrically connected to the same third component portion (e.g., the second initialization signal line Ref2) through the same first via H1 and the same first connecting portion 15.

[0187] Exemplarily, in two adjacent pixel circuit groups located in the same column, the active portions of the two first transistors T4 and the active portions of the two second transistors T7 are electrically connected to the same third element portion (e.g., initialization signal line) located between the two pixel circuit groups through the same first via H1 and the same first connecting portion 15.

[0188] Fig.21 This is the ninth layout of the display panel provided in an embodiment of the present application. Fig.21 The layout shown and Fig. 20 , Fig.19 The difference between the shown layouts is that, in the present embodiment, in the three adjacent pixel circuit groups in the column direction, the first transistor T4 of the adjacent pixel circuits 20 in the pixel circuit group on one side and the first transistor T4 in the pixel circuit 20 in the middle pixel circuit group are electrically connected to the third element portion 14 (for example, the first initialization signal line Ref1) through the first via H1 and the first connecting portion 15; the second transistor T7 in the pixel circuit 20 in the pixel circuit group on the other side and the second transistor T7 in the pixel circuit 20 in the middle pixel circuit group are electrically connected to the same third element portion 14 (for example, the second initialization signal line Ref2) through the same first via H1 and the same first connecting portion 15.

[0189] Figure 8 , Fig.11 , Figure 15b to Figure 17 , Figures 19 to 21 The partial enlarged top view and cross-sectional view of the first connecting portion 15 can be seen in Figures 1 to 5c , Figure 7a and Figure 7b . Fig.18 The partial enlarged top view and cross-sectional view of the first connecting portion 15 can be seen in Figure 6a and Figure 6b .

[0190] Optionally, the pixel circuit may include one or at least two of a first initialization transistor Ta, a second initialization transistor Tb, and a third initialization transistor Tc, see Fig. 22 and Fig.23. The first initialization transistor Ta may be electrically connected to the gate of the driving transistor, the first initialization transistor Ta may be connected to the first initialization voltage Vref1, and the first initialization transistor Ta may be used to initialize the gate of the driving transistor T1. The second initialization transistor Tb may be electrically connected to the first electrode (e.g., source) of the driving transistor, the second initialization transistor Tb may be connected to the second initialization voltage Vref2, and the second initialization transistor Tb may be used to initialize the first electrode (e.g., source) of the driving transistor T1. The third initialization transistor Tc may be electrically connected to the second electrode (e.g., drain) of the driving transistor, the third initialization transistor Tc may be connected to the third initialization voltage Vref3, and the third initialization transistor Tc may be used to initialize the second electrode (e.g., drain) of the driving transistor T1. For example, one or more first transistors T4 may be the first initialization transistor Ta. And / or, for example, one or more first transistors T4 may be the second initialization transistor Tb. And / or, for example, one or more first transistors T4 may be the third initialization transistor Tc. And / or, for example, one or more second transistors T7 may be the first initialization transistor Ta. And / or, for example, one or more second transistors T7 may be the second initialization transistor Tb. And / or, for example, one or more second transistors T7 may be a third initialization transistor Tc. And / or, for example, one or more initialization signal lines ref may be used to transmit a first initialization voltage Vref1. And / or, for example, one or more initialization signal lines ref may be used to transmit a second initialization voltage Vref2. And / or, for example, one or more initialization signal lines ref may be used to transmit a third initialization voltage Vref3. And / or, for example, the first initialization signal line ref1 may be used to transmit one of the first initialization voltage Vref1, the second initialization voltage Vref2, and the third initialization voltage Vref3, and the second initialization signal line ref2 may be used to transmit the other of the first initialization voltage Vref1, the second initialization voltage Vref2, and the third initialization voltage Vref3. The connection mode between the transistor and the scan line and the channel type of the transistor may be set as required. For example, the first initialization transistor Ta may be an N-type transistor or a P-type transistor. For example, the second initialization transistor Tb may be an N-type transistor or a P-type transistor. For example, the third initialization transistor Tc may be an N-type transistor or a P-type transistor.

[0191] A second aspect of the present application provides another display panel. Fig.24c This is the tenth layout of the display panel provided in one embodiment of the present application. Figure 24b The cross-sectional view of the display panel shown may be Fig.24a The cross-sectional view corresponding to the mid-section line N11N12. Fig.24c The difference between the display panel shown in the figure and the display panel provided in any of the above embodiments is that, in the present embodiment, referring to Fig.24a ,24b , 24c, the display panel includes a plurality of first via holes H1 and a plurality of first connecting portions 15. At least one first via hole H1 exposes at least a portion of the surface of the third component portion 14 away from the substrate 11 and at least a portion of the surface of the first component portion 12 away from the substrate 11, and at least one first via hole H1 exposes at least a portion of the surface of the third component portion 14 away from the substrate 11 and at least a portion of the surface of the second component portion 13 away from the substrate 11. The plurality of first connecting portions 15 fill the corresponding first via holes H1, electrically connect the third component portion 14 and the first component portion 12, and are spaced from the first connecting portions 15 electrically connecting the third component portion 14 and the second component portion 13.

[0192] In some embodiments, the display panel further includes a plurality of pixel circuits 20 arranged in an array, and the pixel circuit 20 includes a first component portion 12 and / or a second component portion 13 .

[0193] In some embodiments, the display panel includes a plurality of pixel circuit groups, and the pixel circuit group includes two pixel circuits 20 located in the same row and adjacent to each other. In the same pixel circuit group, the first component part 12 in one pixel circuit 20 and the second component part 13 in another pixel circuit 20 are electrically connected to the third component part 14 through the first via H1 and the first connecting part 15, and the third component part 14 extends along the row direction, and the row direction and the column direction intersect.

[0194] In some embodiments, the pixel circuit 20 includes a first transistor T4, and at least one second component portion 13 and at least one first component portion 12 are active portions of the first transistor T4 in different pixel circuits 20. The pixel circuit 20 also includes a driving transistor T1, and the first transistor T4 is used to initialize the gate, source or drain of the driving transistor T1.

[0195] And / or, the pixel circuit 20 includes a second transistor T7, and at least one second element portion 13 and at least one first element portion 12 are active portions of the second transistor T7 in different pixel circuits 20. The display panel also includes a light emitting device OLED, and the second transistor T7 is used to initialize the first electrode of the light emitting device OLED.

[0196] In some embodiments, the third element portion 14 is an initialization signal line Ref.

[0197] In some embodiments, the initialization signal line Ref is located at a gate layer of the first transistor T4 and / or a gate layer of the second transistor T7 .

[0198] In some embodiments, active layers of two adjacent pixel circuits 20 in the same row are arranged in mirror symmetry.

[0199] In some embodiments, the active portion of the first transistor T4 and the active portion of the second transistor T7 are electrically connected to the same initialization signal line Ref, or, different initialization signal lines Ref.

[0200] In some embodiments, the initialization signal line Ref includes a first initialization signal line Ref1 and a second initialization signal line Ref2 that are insulated and alternately arranged along the column direction. The active portion of the first transistor T4 is electrically connected to the first initialization signal line Ref1, and the active portion of the second transistor T7 is electrically connected to the second initialization signal line Ref2.

[0201] For example, in the same pixel circuit group, the active portion of the first transistor T4 in one pixel circuit 20 and the active portion of the first transistor T4 in another pixel circuit 20 are electrically connected to the third element portion 14 (for example, the first initialization signal line Ref1) through two first vias H1 and two first connecting portions 15. Fig.24c shown.

[0202] For example, in the same pixel circuit group, the active portion of the second transistor T7 in one pixel circuit 20 and the active portion of the second transistor T7 in another pixel circuit 20 are electrically connected to the third element portion 14 (for example, the second initialization signal line Ref2) through two first vias H1 and two first connecting portions 15. Fig.24c shown.

[0203] The display panel provided in this embodiment and the display panel provided in any of the above embodiments belong to the same inventive concept. For technical details not described in this embodiment, please refer to the above related embodiments, which will not be repeated here. This embodiment can be combined with some or all of the features in the above embodiments, which will not be repeated here.

[0204] The present application provides a substrate. Figure 1 As shown, the substrate includes a substrate 11, a first component part 12, a second component part 13, a third component part 14, a first via H1 and a first connecting part 15. The first component part 12 is located on the substrate 11. The second component part 13 is located on the substrate 11. The third component part 14 is located on the substrate 11. The third component part 14 and the first component part 12 are arranged in different layers, and the third component part 14 and the second component part 13 are arranged in different layers. The first via H1 exposes at least a portion of the surface of the third component part 14 away from the substrate 11, at least a portion of the surface of the first component part 12 away from the substrate 11, and at least a portion of the surface of the second component part 13 away from the substrate 11. The first connecting part 15 fills the first via H1. The first connecting part 15 is electrically connected to the third component part 14 and the second component part 13.

[0205] The substrate provided in the embodiment of the present application can be the display panel provided in any of the above embodiments, or can be other substrates with circuit structures. This embodiment can be combined with some or all of the features of the above embodiments, which will not be described in detail here.

[0206] This embodiment can be combined with some or all of the technical features in the above embodiments, which will not be described in detail here. The present application provides a display device. Fig.25 This is a schematic diagram of the structure of a display device provided in one embodiment of the present application. Fig.25 As shown, the display device 1300 includes a display panel or substrate provided by any embodiment of the present application.

[0207] The display device is a product with an image display function. For example, the display device 1300 can be used to display static images, such as pictures or photos. The display device 1300 can also be used to display dynamic images, such as videos.

[0208] The display device 1300 may be a laptop computer, a mobile phone, a handheld or portable computer, a camera, a camcorder, a vehicle-mounted smart central control screen, a calculator, a smart watch, a GPS navigator, an electronic photo, an electronic billboard or sign, a projector, etc.

[0209] In addition, the display device 1300 may also have functions such as taking pictures, recording videos, fingerprint recognition, and face recognition. Accordingly, the display device 1300 also includes at least one functional module for implementing the above functions, such as an under-screen camera, an under-screen fingerprint recognition sensor, and the like.

[0210] The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present application. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, not for limitation, and the above details do not limit the present application to being implemented by adopting the above specific details.

[0211] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present application to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A display panel, It is characterized in that include: substrate; A first element portion, located on the substrate; A second component portion is located on the substrate; A third component part is located on the substrate, the third component part and the first component part are arranged in different layers, and the third component part and the second component part are arranged in different layers; a first via hole exposing at least a portion of a surface of the third component portion away from the substrate, at least a portion of a surface of the first component portion away from the substrate, and at least a portion of a surface of the second component portion away from the substrate; The first connecting portion fills the first via hole, and the first connecting portion is electrically connected to the third element portion, the first element portion, and the second element portion.

2. The display panel according to claim 1, It is characterized in that The first component part and the second component part are arranged in the same layer or in different layers.

3. The display panel according to claim 1, It is characterized in that The third element portion extends along the first direction; The orthographic projection of the first component portion on the substrate and the orthographic projection of the second component portion on the substrate are located on one or both sides of the orthographic projection of the third component portion on the substrate along a second direction, and the first direction and the second direction intersect.

4. The display panel according to claim 1, It is characterized in that It also includes a second connecting portion connected between the first component portion and the second component portion, wherein an overlapping area of ​​an orthographic projection of the second connecting portion on the substrate and an orthographic projection of the third component portion on the substrate overlaps with an orthographic projection of the first connecting portion on the substrate, Preferably, the first element portion, the second element portion, and the second connecting portion are arranged in the same layer; Preferably, the first component part, the second component part and the second connecting part are located in the same active layer, and the third component part is located in the gate layer; Preferably, the third component portion is a first routing line, the first routing line includes a first routing segment and a second routing segment arranged along an extension direction of the first routing line, an overlapping area of ​​an orthographic projection of the second connecting portion on the substrate and an orthographic projection of the first routing segment on the substrate overlaps with an orthographic projection of the first connecting portion on the substrate; a width of at least a portion of the first routing segment is less than or equal to a width of the second routing segment; Preferably, a notch is provided on one or both sides of the first wiring segment along its width direction, and the orthographic projection of the notch on the substrate overlaps with the orthographic projection of the first via on the substrate; And / or, the first wiring is provided with a break, and an orthographic projection of the break on the substrate overlaps with an orthographic projection of the first via on the substrate; The orthographic projection of the fracture on the substrate overlaps with the orthographic projection of the second connecting portion on the substrate; Preferably, the first wiring is an initialization signal line.

5. The display panel according to claim 1, It is characterized in that A first gap is provided between the first component portion and the second component portion, and an orthographic projection of the first gap on the substrate overlaps with an orthographic projection of the third component portion on the substrate; Preferably, the first component part and the second component part are located in the same active layer, and the third component part is located in the gate layer; Preferably, the third component portion is a first routing line, the first routing line includes a first routing segment and a second routing segment arranged along an extension direction of the first routing line, an overlapping area of ​​an orthographic projection of the first gap on the substrate and an orthographic projection of the first routing segment on the substrate overlaps with an orthographic projection of the first connecting portion on the substrate; a width of at least a portion of the first routing segment is less than or equal to a width of the second routing segment; Preferably, a notch is provided on one or both sides of the first wiring segment along its width direction, and an orthographic projection of the notch on the substrate overlaps with an orthographic projection of the first via on the substrate.

6. The display panel according to claim 1, It is characterized in that The film layer where the third component part is located is located on a side of the film layer where the first component part is located and the film layer where the second component part is located away from the substrate; Alternatively, the film layer where the third component part is located is located on a side of the film layer where the first component part is located and the film layer where the second component part is located close to the substrate; Alternatively, the film layer where the third component portion is located is located between the film layer where the first component portion is located and the film layer where the second component portion is located.

7. The display panel according to claim 1, It is characterized in that The display panel further includes a first transistor; the first element portion is an active portion of the first transistor; The display panel further includes a second transistor; the second element portion is an active portion of the second transistor; Preferably, the active portion of the first transistor and the active portion of the second transistor are arranged in different layers; Alternatively, the active portion of the first transistor and the active portion of the second transistor are arranged in the same layer, and the gate of the first transistor, the gate of the second transistor, and the third element portion are arranged in the same layer; Preferably, the display panel further comprises a second connecting portion connected between the first element portion and the second element portion, an overlapping area of ​​an orthographic projection of the second connecting portion on the substrate and an orthographic projection of the third element portion on the substrate overlaps with an orthographic projection of the first connecting portion on the substrate, and the first element portion, the second element portion and the second connecting portion are located in the same active layer. The conductivity of the second connection portion is lower than the conductivity of the source region or the drain region of the active portion of the first transistor, or the doping concentration of the conductive particles of the second connection portion is lower than the doping concentration of the conductive particles of the source region or the drain region of the active portion of the first transistor; and / or the conductivity of the second connection portion is lower than the conductivity of the source region or the drain region of the active portion of the second transistor, or the doping concentration of the conductive particles of the second connection portion is lower than the doping concentration of the conductive particles of the source region or the drain region of the active portion of the second transistor.

8. The display panel according to claim 1, It is characterized in that The orthographic projection of the first connecting portion on the substrate is a rectangle; And / or, the orthographic projection of the first via hole on the substrate is a rectangle; And / or, the third component portion is an initialization signal line; and / or, the first connecting portion covers at least a portion of a surface of the third component portion away from the substrate, at least a portion of a surface of the first component portion away from the substrate, and at least a portion of a surface of the second component portion away from the substrate, which is exposed by the first via hole; And / or, the display panel includes a first insulating layer, which is located between the film layer where the third component part is located and the film layer where the first component part is located, the first component part and the second component part are arranged in the same layer, and the first via hole penetrates the first insulating layer to expose at least a portion of a surface of the first component part away from the substrate and at least a portion of a surface of the second component part away from the substrate; And / or, the display panel includes a second insulating layer, which is located on a side of the film layer where the third component portion is located and the first insulating layer away from the substrate, and the first via hole penetrates the second insulating layer to expose at least a portion of the surface of the third component portion away from the substrate; the first via hole penetrates the first insulating layer and the second insulating layer to expose at least a portion of the surface of the first component portion away from the substrate and at least a portion of the surface of the second component portion away from the substrate; And / or, the orthographic projection of the first via hole on the substrate is located within the orthographic projection of the active layer where the first component part is located on the substrate, or the orthographic projection of the first via hole on the substrate is located within the orthographic projection of the active layer where the second component part is located on the substrate.

9. The display panel according to claim 1, It is characterized in that Also included are a plurality of pixel circuits arranged in an array, wherein the pixel circuits include the first component portion and the second component portion; Preferably, in two pixel circuits located in the same column and adjacent to each other, the first component portion in one pixel circuit and the second component portion in the other pixel circuit are electrically connected to the third component portion through the first via hole and the first connecting portion, and the third component portion extends along a row direction, and the row direction intersects with the column direction; Preferably, the pixel circuit includes a first transistor and a second transistor, the first element portion is an active portion of the first transistor, and the second element portion is an active portion of the second transistor. The first transistor and the second transistor have different functions; Preferably, the third component portion is an initialization signal line; Preferably, the initialization signal line is located at the gate layer of the first transistor and / or the gate layer of the second transistor; The pixel circuit further includes a driving transistor, wherein the first transistor is used to initialize a gate, a source or a drain of the driving transistor. And / or, the display panel further includes a light emitting device, and the second transistor is used for initializing a first electrode of the light emitting device.

10. The display panel according to claim 1, It is characterized in that Also included are a plurality of pixel circuits arranged in an array, wherein the pixel circuits include the first component portion and / or the second component portion, Preferably, in two pixel circuits located in the same column and adjacent to each other, the first component portion in one pixel circuit and the second component portion in the other pixel circuit have the same function and are electrically connected to the third component portion through the first via hole and the first connecting portion, and the third component portion extends along a row direction, and the row direction intersects with the column direction; And / or, the display panel includes a plurality of pixel circuit groups, the pixel circuit group includes two pixel circuits located in the same row and adjacent to each other, and in the same pixel circuit group, the first component portion in one pixel circuit and the second component portion in another pixel circuit have the same function and are electrically connected to the third component portion through the first via hole and the first connecting portion; Preferably, the pixel circuit comprises a first transistor, at least one of the second component parts and at least one of the first component parts are active parts of the first transistor in different pixel circuits, the pixel circuit further comprises a driving transistor, and the first transistor is used to initialize the gate, source or drain of the driving transistor, And / or, the pixel circuit includes a second transistor, at least one of the second element parts and at least one of the first element parts are active parts of the second transistor in different pixel circuits, the display panel further includes a light emitting device, and the second transistor is used to initialize a first electrode of the light emitting device; Preferably, the third component portion is an initialization signal line; Preferably, the initialization signal line is located at the gate layer of the first transistor and / or the gate layer of the second transistor; Preferably, the active layers of the two adjacent pixel circuits in the same column are arranged in a mirror-symmetrical manner; and / or the active layers of the two adjacent pixel circuits in the same row are arranged in a mirror-symmetrical manner; Preferably, the active portion of the first transistor and the active portion of the second transistor are electrically connected to the same initialization signal line, or different initialization signal lines; Preferably, the initialization signal line comprises a first initialization signal line and a second initialization signal line which are insulated and alternately arranged along the column direction, the active part of the first transistor is electrically connected to the first initialization signal line, and the active part of the second transistor is electrically connected to the second initialization signal line; And / or, in two adjacent pixel circuit groups located in the same column, they are electrically connected to the same third element portion located between the two pixel circuit groups through the same first via hole and the same first connecting portion.

11. The display panel according to claim 9 or 10, It is characterized in that The pixel circuit further includes a data writing transistor, wherein the data writing transistor is connected between the data line and the first electrode of the driving transistor, and the gate of the second transistor and the gate of the data writing transistor are electrically connected to the first scanning line; The first scan line and the initialization signal line are arranged on the same layer; and / or the data line and the first connection portion are arranged on the same layer; Preferably, the first scan line and the initialization signal line extend along a first direction; Preferably, the gate of the first transistor is electrically connected to a second scan line, and the second scan line is provided at the same layer as the initialization signal line; Preferably, the second scan line and the initialization signal line extend along a first direction; Preferably, the initialization signal line is located between the first scan line and the second scan line; Preferably, the gate of the driving transistor is arranged on the same layer as the initialization signal line; Preferably, the pixel circuit further comprises a storage capacitor, and the gate of the driving transistor is multiplexed as a first plate of the storage capacitor; Preferably, the display panel further comprises a light emitting control signal line, and the first scanning line is located between the light emitting control signal line and the initialization signal line; Preferably, the pixel circuit further comprises a first light emission control transistor connected between the second electrode of the driving transistor and the first electrode of the light emitting device, and a gate of the first light emission control transistor is electrically connected to the light emission control signal line; Preferably, the data writing transistor is used to be turned on in a writing frame to transmit the data voltage on the data line to the driving transistor, and turned on in a holding frame to transmit the bias voltage on the data line to the driving transistor; Preferably, the pixel circuit further comprises a threshold compensation transistor connected between the gate electrode and the second electrode of the driving transistor, and the gate electrode of the threshold compensation transistor is electrically connected to the third scanning line; Preferably, the second scan line is located between the initialization signal line and the third scan signal line.

12. The display panel according to claim 1, It is characterized in that The display panel further includes a first power line, the first power line is disposed in the same layer as the first connecting portion, and the first power line extends along the second direction. Preferably, in the first direction, the first power lines and the first connecting portions are arranged alternately; Preferably, the display panel further comprises a pixel circuit, and the first power line is electrically connected to the pixel circuit; Preferably, the pixel circuit comprises a storage capacitor, and at least a portion of the first power line is reused as a second plate of the storage capacitor; Preferably, the data lines extend along the second direction, and the first power lines and the data lines are alternately arranged along the first direction; Preferably, in the first direction, the first connecting portion is located between the first power line and the data line; Preferably, the pixel circuit comprises a driving transistor and a second light-emitting control transistor, wherein the second light-emitting control transistor is connected between the first electrode of the driving transistor and the first power line; the gate of the second light-emitting control transistor is electrically connected to a light-emitting control signal line, and the light-emitting control signal line is arranged on the same layer as the third element portion; The light emission control signal line and the third element portion extend along a first direction, and the first direction intersects the second direction.

13. The display panel according to claim 11, It is characterized in that The display panel further includes a first scanning circuit, the first scanning circuit includes a plurality of first shift registers, and an output end of each of the first shift registers in at least one of the first shift registers is electrically connected to a gate of a corresponding first transistor and a gate of the threshold compensation transistor; Preferably, the first transistor and the threshold compensation transistor electrically connected to the same first shift register are located in different pixel circuits; Preferably, in two adjacent rows of pixel circuits, the first transistors in one row of pixel circuits and the threshold compensation transistors in another row of pixel circuits are electrically connected to the same first shift register.

14. The display panel according to claim 11, It is characterized in that The active portion of the first transistor and the active portion of the threshold compensation transistor are connected to form a groove shape in the positive projection of the substrate, and the bottom and the notch of the groove shape are arranged along the first direction; Preferably, the first transistor includes at least two first sub-transistors connected in series; and / or the threshold compensation transistor includes at least two second sub-transistors connected in series.

15. The display panel according to claim 1, It is characterized in that The third component part is an initialization signal line; the display panel further includes a first scan line, the first scan line includes a third routing segment and a fourth routing segment arranged along an extension direction of the first scan line, and a distance between the third routing segment and the initialization signal line is smaller than a distance between the fourth routing segment and the initialization signal line; Preferably, the first via hole is directly opposite to the third routing segment; Preferably, the pixel circuit also includes a data writing transistor, a gate of which is electrically connected to the first scanning line; the display panel also includes a second via, which exposes a portion of the first electrode of the data writing transistor; the orthographic projection of the second via on the substrate is located between the orthographic projection of the initialization signal line on the substrate and the orthographic projection of the first scanning line on the substrate.

16. The display panel according to claim 15, It is characterized in that It also includes a light-emitting control signal line, which is located on the side of the first scan line away from the initialization signal line; the display panel also includes a third via hole, a fourth via hole and a fifth via hole, and the orthographic projections of the third via hole, the fourth via hole and the fifth via hole on the substrate are all located between the light-emitting control signal line and the first scan line; Preferably, the orthographic projections of the third via hole and the fourth via hole on the substrate are both located between the orthographic projection of the third routing segment on the substrate and the orthographic projection of the light emitting control signal line on the substrate; Preferably, the orthographic projection of the fifth via hole on the substrate is located between the orthographic projection of the fourth routing segment on the substrate and the orthographic projection of the light emitting control signal line on the substrate.

17. The display panel according to claim 16, It is characterized in that The pixel circuit further includes a first light emission control transistor; the display panel further includes a third connection portion, the third via hole exposes the second electrode of the first light emission control transistor, and the third connection portion fills the third via hole; Preferably, the display panel further comprises a light emitting device, which is located on a side of the pixel circuit away from the substrate, and the first electrode of the light emitting device is electrically connected to the third connecting portion; Preferably, the pixel circuit further includes a second light emission control transistor; the display panel further includes a power signal line, the fourth via hole exposes the first electrode of the second light emission control transistor, and the power signal line fills the fourth via hole; Preferably, the pixel circuit further comprises a data writing transistor and a driving transistor; The display panel further includes a fourth connection portion, the fifth via hole exposes the second electrode of the data writing transistor, and the sixth via hole exposes the first electrode of the driving transistor; the fourth connection portion fills the fifth via hole and the sixth via hole; Preferably, the third via hole, the fourth via hole and the fifth via hole are arranged in sequence along the first direction; Preferably, the orthographic projection of the sixth via hole on the substrate is located on a side of the orthographic projection of the light emitting control signal line on the substrate away from the orthographic projection of the first scanning line on the substrate.

18. A display panel, It is characterized in that include: substrate; A first element portion, located on the substrate; A second component portion is located on the substrate; A third component part is located on the substrate, the third component part and the first component part are arranged in different layers, and the third component part and the second component part are arranged in different layers; a plurality of first vias, at least one of the first vias exposing at least a portion of a surface of the third component portion away from the substrate and at least a portion of a surface of the first component portion away from the substrate; and at least one of the first vias exposing at least a portion of a surface of the third component portion away from the substrate and at least a portion of a surface of the second component portion away from the substrate; A plurality of first connection parts fill the corresponding first via holes, electrically connect the first connection parts of the third component part and the first component part, and are spaced apart from the first connection parts electrically connecting the third component part and the second component part.

19. The display panel according to claim 18, It is characterized in that Also included are a plurality of pixel circuits arranged in an array, wherein the pixel circuits include the first component portion and / or the second component portion, Preferably, the display panel includes a plurality of pixel circuit groups, the pixel circuit group includes two pixel circuits located in the same row and adjacent to each other, the first component portion in one pixel circuit and the second component portion in another pixel circuit in the same pixel circuit group have the same functions, and are electrically connected to the third component portion through the first via hole and the first connecting portion, the third component portion extends along a row direction, and the row direction intersects with the column direction; Preferably, the pixel circuit comprises a first transistor, at least one of the second component parts and at least one of the first component parts are active parts of the first transistor in different pixel circuits, the pixel circuit further comprises a driving transistor, and the first transistor is used to initialize the gate, source or drain of the driving transistor, And / or, the pixel circuit includes a second transistor, at least one of the second element parts and at least one of the first element parts are active parts of the second transistor in different pixel circuits, the display panel further includes a light emitting device, and the second transistor is used to initialize a first electrode of the light emitting device; Preferably, the third component portion is an initialization signal line; Preferably, the initialization signal line is located at the gate layer of the first transistor and / or the gate layer of the second transistor; Preferably, the active layers of two adjacent pixel circuits in the same row are arranged in mirror symmetry; Preferably, the active portion of the first transistor and the active portion of the second transistor are electrically connected to the same initialization signal line, or different initialization signal lines; Preferably, the initialization signal line includes a first initialization signal line and a second initialization signal line which are insulated and alternately arranged along the column direction, the active portion of the first transistor is electrically connected to the first initialization signal line, and the active portion of the second transistor is electrically connected to the second initialization signal line.

20. A display device, It is characterized in that A display panel comprising any one of claims 1-19.

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