Chip packaging structure and electronic equipment

Abstract

The utility model provides a chip packaging structure and electronic equipment. The chip packaging structure comprises a carrier plate, a first chip and a second chip, a mounting part is arranged on the carrier plate, and the mounting part is a dug hole, or the mounting part is a groove; at least part or all of the second chip is located in the mounting part, and the second chip is interconnected with the first chip; the area, except for the area where the second chip is connected with the first chip, on the first chip is connected with the carrier plate. According to the chip packaging structure, the mounting part is arranged on the carrier plate to accommodate and mount the second chip, so that the packaging occupied area of the second chip on the carrier plate is reduced, the processing difficulty and the processing cost of the first connecting piece of the chip are reduced, and the packaging efficiency of the first chip and the second chip is improved. And the processing difficulty and the processing cost of welding between the first chip and the carrier plate are reduced, and the overall product thickness is reduced. Meanwhile, the interconnection path between the first chip and the carrier plate and the interconnection path between the first chip and the second chip are shortened, and the performance of a packaged chip product is improved.

Description

Technical Field

[0001] The present application relates to the field of packaging technology, and in particular to a chip packaging structure and electronic equipment. Background Art

[0002] In electronic products, chips are the core components that process and control signals and data. Chips are a way to miniaturize circuits and are usually manufactured on the surface of semiconductor wafers. After the chip is prepared, it usually needs to be attached to a packaging substrate, such as a ceramic substrate. Other electrical modules are also provided on the packaging substrate for electrical connection with the chip to form a chip packaging structure.

[0003] In the existing chip packaging structure, when the shortest interconnection between different chips is required, the chip butt soldering points are often inconsistent in height, the spacing between the solder joints between the chip and the substrate is large, and the second chip is behind the solder balls and pads on the back of the substrate. This leads to complex processes and large packaging thickness, which cannot meet the design requirements of miniaturization and ultra-thin chip packaging structures. Utility Model Content

[0004] The purpose of the embodiment of the present application is to provide a chip packaging structure and an electronic device. In the chip packaging structure of the present application, a mounting portion is provided on a carrier to accommodate and mount a second chip, thereby reducing the packaging area occupied by the second chip on the carrier and reducing the overall product thickness. At the same time, the interconnection paths between the first chip and the carrier, and between the first chip and the second chip can be shortened, thereby improving the performance of the packaged chip product.

[0005] In a first aspect, the present application provides a chip packaging structure, comprising: a carrier, a first chip and a second chip; a mounting portion is provided on the carrier, the mounting portion is a through hole, or the mounting portion is a groove; the second chip is at least partially or entirely located in the mounting portion, and the second chip is interconnected with the first chip; the area on the first chip except for the interconnection between the second chip and the first chip is interconnected with the carrier.

[0006] In one embodiment, the second chip is interconnected with the first chip through a first connector, and the first chip is interconnected with a region outside the mounting portion through the first connector.

[0007] In one embodiment, the second chip is at least partially or entirely located in the through hole; or, the second chip is at least partially or entirely located in the groove.

[0008] In one embodiment, the chip packaging structure further includes: a dielectric layer; the lower surface of the dielectric layer is flush with the lower surface of the carrier, or the dielectric layer completely or partially wraps the carrier.

[0009] In one embodiment, the first connector includes: a first sub-connector and a second sub-connector, the second chip is interconnected with the first chip through the first sub-connector, and the area on the first chip except for the interconnection between the second chip and the first chip is interconnected with the carrier through the second sub-connector; wherein the size of the first sub-connector is larger than the size of the second sub-connector.

[0010] In one embodiment, the first connector includes: a first sub-connector and a second sub-connector, the second chip is interconnected with the first chip through the first sub-connector, and the area on the first chip except for the interconnection between the second chip and the first chip is interconnected with the carrier through the second sub-connector; wherein the size of the first sub-connector is smaller than the size of the second sub-connector.

[0011] In one embodiment, the carrier board is a frame, the frame has frame pins, the frame is provided with the groove or the through hole, the second chip is placed in the groove or the through hole; the area on the first chip except for the interconnection between the second chip and the first chip is interconnected with the frame surface through a first connector; and / or the first chip is electrically connected to the frame pins through the first connector.

[0012] In one embodiment, the first connecting member is one or a combination of a bump, a pad, and a solder ball.

[0013] In one embodiment, the surface of the dielectric layer is flush with the surface of the first chip, and the silicon wafer of the first chip is exposed on the surface of the dielectric layer.

[0014] In one embodiment, the surface of the second chip is flush with the bottom of the carrier, and the silicon wafer of the second chip is exposed on the bottom surface of the carrier.

[0015] In one embodiment, there is at least one second chip, each of the second chips is located in the mounting portion and each of the second chips is interconnected with the first chip via a first connector, and the first chip is interconnected with an area outside the mounting portion via the first connector.

[0016] In one embodiment, a second connector is connected to an end of the carrier away from the first chip.

[0017] In one embodiment, the second connecting member is one or a combination of a solder pad and a solder ball.

[0018] In a second aspect, the present application provides an electronic device, comprising a chip packaging structure as described in any embodiment of the first aspect of the present application.

[0019] Compared with the prior art, the technical solution of the present application has at least the following advantages: in the chip packaging structure of the present application, a mounting portion is provided on the carrier to accommodate and install the second chip, thereby reducing the packaging area occupied by the second chip on the carrier, reducing the processing difficulty and processing cost of the first connecting part of the chip, and reducing the processing difficulty and processing cost of welding between the first chip and the second chip, and between the first chip and the carrier.

[0020] At the same time, the interconnection paths between the first chip and the carrier board, and between the first chip and the second chip can be shortened, thereby improving the performance of the packaged chip product.

[0021] Secondly, the first chip is arranged relative to and connected to the second chip and the carrier board, which saves wiring space, makes the packaging thickness of the entire chip packaging structure thinner, and has a smaller volume and size, thereby reducing the packaging cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0023] FIG. 1( a ) is a schematic diagram 1 of a chip packaging structure provided in a first embodiment of the present application;

[0024] FIG1( b ) is a second schematic diagram of a chip packaging structure provided in the first embodiment of the present application;

[0025] FIG1( c ) is a third schematic diagram of a chip packaging structure provided in the first embodiment of the present application;

[0026] FIG. 2( a ) is a schematic diagram 1 of a chip packaging structure provided in a second embodiment of the present application;

[0027] FIG2( b ) is a second schematic diagram of a chip packaging structure provided in the second embodiment of the present application;

[0028] FIG2( c ) is a third schematic diagram of a chip packaging structure provided in the second embodiment of the present application;

[0029] FIG. 3( a ) is a schematic diagram of a chip packaging structure provided in a third embodiment of the present application.

[0030] FIG3( b ) is a second schematic diagram of a chip packaging structure provided in the third embodiment of the present application;

[0031] Figure 4 A schematic diagram of a chip packaging structure provided in a fourth embodiment of the present application;

[0032] Figure 5 A schematic diagram of a chip packaging structure provided in the fifth embodiment of the present application.

[0033] Reference numerals:

[0034] 1-chip packaging structure; 100-carrier; 110-installation part; 111-dig hole; 112-groove; 200-first chip; 300-second chip; 310-surface adhesive; 400-medium layer; 500-first connector; 510-first sub-connector; 520-second sub-connector; 600-second connector; 700-frame; 710-frame pin. DETAILED DESCRIPTION

[0035] The terms “first”, “second”, “third”, etc. are only used for distinguishing descriptions and do not indicate the order of arrangement, nor can they be understood as indicating or implying relative importance.

[0036] In addition, the terms "horizontal", "vertical", "overhanging" and the like do not mean that the components are required to be absolutely horizontal or overhanging, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0037] In the description of the present application, it should be noted that the terms "inside", "outside", "left", "right", "up", "down", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, or are directions or positional relationships in which the products of the present application are usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0038] In the description of this application, unless otherwise clearly specified and limited, the terms "set", "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal connection of two elements.

[0039] The technical solution of the present application will be described below in conjunction with the accompanying drawings.

[0040] Please refer to Figures 1(a) and 1(b), the chip packaging structure 1 includes: a carrier 100, a first chip 200 and a second chip 300; a mounting portion 110 is provided on the carrier 100, and the mounting portion 110 is a through hole, or the mounting portion 110 is a groove; the second chip 300 is at least partially or entirely located in the mounting portion 110, and the second chip 300 is interconnected with the first chip 200; the area of ​​the first chip 200 other than the area where the second chip 300 is interconnected with the first chip 200 is interconnected with the carrier 100.

[0041] The carrier 100 can protect, support and fix the chip, and enhance the thermal conductivity and heat dissipation performance of the chip. The upper layer of the carrier 100 is connected to the chip, and the lower layer of the carrier 100 can be connected to the printed circuit board (PCB board) to achieve electrical and physical connection, signal distribution, and communication between the internal and external circuits of the chip.

[0042] In this embodiment, by providing a mounting portion 110 on the carrier 100, the mounting portion 110 is used to accommodate and install the second chip 300, so that the package area occupied by the second chip 300 on the carrier 100 can be reduced, and the processing difficulty and processing cost of welding between the first chip 200 and the second chip 300, and the first chip 200 and the carrier 100 are reduced. At the same time, the interconnection path between the first chip 200 and the carrier 100, and between the first chip 200 and the second chip 300 can be shortened, thereby improving the performance of the packaged chip product. Secondly, the first chip 200 is arranged and connected to the second chip 300 and the carrier 100 relative to each other, which saves wiring space, makes the package thickness of the whole chip package structure 1 thinner, and has a smaller volume and size, thereby reducing the package cost.

[0043] In some embodiments, referring to FIG. 1( a ), the mounting portion 110 is a through hole 111 , that is, the carrier 100 is hollowed out along the thickness direction to form a through hole 111 structure similar to a hole, and the second chip 300 is at least partially or completely located in the through hole 111 .

[0044] In order to further improve the installation stability and product reliability between the second chip 300 and the through hole 111 , in some embodiments, the chip packaging structure 1 further includes: a dielectric layer 400 , the lower surface of the dielectric layer 400 is flush with the lower surface of the carrier 100 .

[0045] In this embodiment, when the carrier 100 is etched to form the through hole 111, the size of the through hole 111 is slightly larger than the size of the second chip 300, so that a certain gap is left between the through hole 111 and the second chip 300, so that the second chip 300 can be installed in the through hole 111. The lower surface of the dielectric layer 400 is flush with the lower surface of the carrier 100. By providing the dielectric layer 400, the second chip 300 can be prevented from being offset and reliability failure. As an example, the dielectric layer 400 can be made of a plastic packaging material or the like.

[0046] 1( b ), the mounting portion 110 is a groove 112 , that is, a groove is dug out along the thickness direction of the carrier 100 , and a certain depth is retained at the bottom of the groove without digging through the carrier 100 , and the second chip 300 is at least partially or completely located in the groove 112 .

[0047] In some embodiments, a patch adhesive 310 is disposed at the bottom of the second chip 300, and the other end of the patch adhesive is in contact with the bottom of the groove 112 of the carrier 100. In other embodiments, a DAF film (Die Attach Film) may also be disposed at the bottom of the second chip 300.

[0048] In the chip packaging structure 1 shown in FIG. 1(a) and FIG. 1(b), a second connector 600 is connected to one end of the carrier 100 away from the first chip 200. In some embodiments, the second connector 600 is one or a combination of a solder pad and a solder ball. By arranging the second connector 600 at one end of the carrier 100 away from the first chip 200, the second connector 600 can be connected to a printed circuit board (PCB board), thereby realizing electrical and physical connection between the chip packaging structure 1 and an external circuit.

[0049] As shown in FIG1(c), the chip packaging structure 1 of this embodiment is different from the chip packaging structure 1 of FIG1(a) in that the second connector 600 is not provided at the end of the carrier 100 away from the first chip 200. This chip packaging structure 1 is thinner in design, which can reduce the overall thickness of the product and improve the performance reliability of the product.

[0050] 1( a ), 1( b ) and 1( c ), in some embodiments, the second chip 300 is interconnected with the first chip 200 via the first connector 500 , and the first chip 200 is interconnected with an area outside the mounting portion 110 via the first connector 500 .

[0051] In this embodiment, the size of the first chip 200 is larger than that of the second chip 300 . Therefore, when the second chip 300 is interconnected with the first chip 200 through the first connector 500 , the area of ​​the first chip 200 other than the area where the second chip 300 is interconnected with the first chip 200 is also interconnected with the carrier 100 .

[0052] Optionally, the first connector 500 is one or a combination of a bump, a pad, and a solder ball. Taking a bump as an example, the size of the bump can be a microbump to a regular bump. The material of the bump can be one of a tin material (solderbump), a copper material (copper pillar bump) or a gold material (Au bump), which can be selected according to design requirements.

[0053] As an example, the second chip 300 is physically and electrically connected to the first chip 200 through bumps for electrical connection, and the first chip 200 is physically and electrically connected to the area of ​​the carrier 100 except the mounting portion 110 through bumps for electrical connection.

[0054] In an actual chip packaging process, the interconnection path between the first chip 200 and the second chip 300 or the interconnection path between the first chip 200 and the carrier 100 may be adjusted according to the process requirements of chip packaging.

[0055] Referring to FIG. 2( a ), the second chip 300 is interconnected with the first chip 200 through the first connector 500, and the first chip 200 is interconnected with the area outside the mounting portion 110 through the first connector 500. The first connector 500 includes: a first sub-connector 510 and a second sub-connector 520, the second chip 300 is interconnected with the first chip 200 through the first sub-connector 510, and the area on the first chip 200 other than the area where the second chip 300 is interconnected with the first chip 200 is interconnected with the carrier 100 through the second sub-connector 520; wherein the size of the first sub-connector 510 is larger than the size of the second sub-connector 520.

[0056] In this embodiment, the mounting part 110 on the carrier 100 is exemplified by a through hole 111, the first sub-connector 510 is exemplified by a solder ball, and the second sub-connector 520 is exemplified by a bump. The size of the solder ball for interconnecting the second chip 300 and the first chip 200, and the size of the bump for interconnecting the first chip 200 and the carrier 100 can be flexibly designed, and the stability and reliability of the chip packaging structure 1 can be ensured by adjusting the height of the solder ball or the bump, and the depth of the through hole 111 of the second chip 300 and the carrier 100.

[0057] When the thickness of the second chip 300 is relatively small, when the second chip 300 is completely installed in the installation portion 110, the thickness of the second chip 300 does not exceed the thickness of the through hole 111. At this time, because the distance between the second chip 300 and the first chip 200 is greater than the distance between the carrier 100 and the first chip 200, the thickness of the solder balls interconnecting the first chip 200 and the second chip 300 can be increased to achieve simultaneous interconnection between the first chip 200 and the second chip 300, as well as the first chip 200 and the carrier 100 when the first chip 200, the second chip 300 and the carrier 100 are opposite to each other.

[0058] In this embodiment, the lower surface of the dielectric layer 400 is flush with the lower surface of the carrier 100 , and the second connector 600 is connected to one end of the carrier 100 away from the first chip 200 .

[0059] As shown in FIG2(b), the second chip 300 is interconnected with the first chip 200 through the first connector 500, and the first chip 200 is interconnected with the area outside the mounting portion 110 through the first connector 500. In the chip package structure 1 shown in FIG2(b), the first connector 500 includes: a first sub-connector 510 and a second sub-connector 520, the second chip 300 is interconnected with the first chip 200 through the first sub-connector 510, and the area of ​​the first chip 200 other than the area where the second chip 300 is interconnected with the first chip 200 is interconnected with the carrier 100 through the second sub-connector 520; wherein the size of the first sub-connector 510 is smaller than the size of the second sub-connector 520. The lower surface of the dielectric layer 400 is flush with the lower surface of the carrier 100, and the end of the carrier 100 away from the first chip 200 is connected with the second connector 600.

[0060] In this embodiment, the mounting part 110 on the carrier 100 is exemplified by a through hole 111, the first sub-connector 510 is exemplified by a solder ball, and the second sub-connector 520 is exemplified by a bump. The size of the solder ball interconnecting the second chip 300 and the first chip 200 is smaller than the size of the bump interconnecting the first chip 200 and the carrier 100. This chip packaging structure can be applied not only to the case where the thickness of the second chip 300 is very small, but also to the case where the thickness of the second chip 300 is very large.

[0061] For example, when the thickness of the second chip 300 is relatively small, a portion of the second chip 300 can be installed in the mounting portion 110, and the other portion can be exposed outside the mounting portion 110 of the carrier 100. At this time, the distance between the second chip 300 and the first chip 200 is smaller than the distance between the carrier 100 and the first chip 200. Therefore, by reducing the thickness of the solder balls interconnecting the first chip 200 and the second chip 300, the first chip 200 and the second chip 300, as well as the first chip 200 and the carrier 100, can be interconnected simultaneously when the first chip 200 is opposite to the second chip 300 and the carrier 100.

[0062] For another example, please refer to FIG. 2( c ). When the thickness of the second chip 300 is relatively large, after the second chip 300 is completely placed in the through hole 111 of the mounting portion 110, the thickness of the second chip 300 exceeds the thickness of the through hole 111, so that a portion of the second chip 300 is exposed outside the mounting portion 110 of the carrier 100, and the dielectric layer 400 completely or partially wraps the carrier 100. At this time, the distance between the second chip 300 and the first chip 200 is smaller than the distance between the carrier 100 and the first chip 200. Similarly, by reducing the thickness of the solder balls interconnecting the first chip 200 and the second chip 300, the first chip 200 and the second chip 300, as well as the first chip 200 and the carrier 100, can be interconnected simultaneously when the first chip 200 and the second chip 300 are opposite to the carrier 100.

[0063] In order to further improve the heat dissipation and light transmission effect of the chip packaging structure 1. Please refer to FIG. 3(a). In the chip packaging structure 1 shown in FIG. 3(a), the mounting portion 110 is exemplified by a through hole 111, the surface of the second chip 300 is flush with the bottom of the carrier 100, and the silicon wafer of the second chip 300 is exposed on the bottom surface of the carrier 100. The end of the carrier 100 away from the first chip 200 is connected to a second connector 600.

[0064] As shown in FIG. 3( b ), the mounting portion 110 is exemplified by a through hole 111, the surface of the dielectric layer 400 is flush with the surface of the first chip 200, the silicon wafer of the first chip 200 is exposed on the surface of the dielectric layer 400, and the dielectric layer 400 completely or partially wraps the carrier 100. The end of the carrier 100 away from the first chip 200 is connected to a second connector 600.

[0065] In the above-mentioned several embodiments, the second chip 300 is only provided as one. In some other embodiments, the second chip 300 may be provided as at least one. Figure 4 .like Figure 4In the chip package structure 1 shown, two second chips 300 are used as an example, and the mounting part 110 is used as an example of a groove 112. Each second chip 300 is located in the mounting part 110 and each second chip 300 is interconnected with the first chip 200 through the first connector 500. The first chip 200 is interconnected with the area outside the mounting part 110 through the first connector 500. A patch adhesive 310 is provided at the bottom of the second chip 300, and the other end of the patch adhesive 310 is in contact with the bottom of the groove 112 of the carrier 100. In other embodiments, a DAF film (Die Attach Film) may also be provided at the bottom of the second chip 300.

[0066] The chip packaging structure 1 shown in this embodiment can realize the interconnection between a plurality of second chips 300 and the first chip 200 , and between the first chip 200 and the carrier 100 .

[0067] In order to further reduce the cost and package thickness of the chip package structure 1, in some embodiments, please refer to Figure 5 As shown, the carrier 100 is a frame 700, the frame 700 has a frame pin 710, a groove 112 or a through hole 111 is provided in the middle of the frame 700, the second chip 300 is placed in the groove 112 or the through hole 111, and the area of ​​the first chip 200 other than the interconnection between the second chip 300 and the first chip 200 is interconnected with the surface of the frame 700 through the first connector 500; and / or, the first chip 200 is electrically connected to the frame pin 710 through the first connector 500. The lower surface of the dielectric layer 400 is flush with the lower surface of the frame 700.

[0068] The frame 700 is designed to support the chip, and it is usually made of metal or plastic. The function of the frame is mainly to provide support and fixation to ensure that the electronic product will not be physically damaged during operation. In the packaging process of electronic products, the frame is often used to carry chips and other components. In this embodiment, the carrier 100 is replaced by the frame 700, and a through hole or groove is provided on the frame 700. The second chip 300 is placed in the through hole or groove, and the second chip 300 is electrically connected to the first chip 200 through the bump. The portion of the first chip 200 other than the area where the first chip 200 and the second chip 300 are interconnected is also electrically connected to the surface of the frame 700 through the bump, or is electrically connected to the surface of the frame pin 710 through the bump.

[0069] In addition, the chip packaging structure 1 shown in this embodiment can also realize the interconnection of multiple chips. As an example, the number of the second chip 300 can also be at least one.

[0070] In summary, in the chip packaging structure 1 of the present application, by providing a mounting portion 110 on the carrier 100 to accommodate and install the second chip 300, the packaging area occupied by the second chip 300 on the carrier 100 can be reduced, the processing difficulty and processing cost of the first connector 500 of the chip are reduced, and the processing difficulty and processing cost of welding between the first chip 200 and the second chip 300, and the first chip 200 and the carrier 100 are reduced. At the same time, the interconnection path between the first chip 200 and the carrier 100, and between the first chip 200 and the second chip 300 can be shortened, thereby improving the performance of the packaged chip product. Secondly, the first chip 200 and the second chip 300 are arranged and connected relative to the carrier 100, saving wiring space, making the packaging thickness of the entire chip packaging structure 1 thinner, smaller in volume and size, and reducing the packaging cost.

[0071] The present application also provides an electronic device, comprising at least one chip packaging structure 1 as described in all the above figures. The electronic device may include a terminal device such as a smart phone, or a tablet computer, a smart wearable device, a smart door lock or other types of electronic devices using the chip packaging structure 1.

[0072] It should be noted that, in the absence of conflict, the features in the embodiments of this application may be combined with each other.

[0073] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A chip packaging structure, characterized in that: include: A carrier, a first chip and a second chip; a mounting portion is provided on the carrier, the mounting portion is a through hole, or the mounting portion is a groove; the second chip is at least partially or completely located in the mounting portion, and the second chip is interconnected with the first chip; the area of ​​the first chip except the area where the second chip is interconnected with the first chip is interconnected with the carrier.

2. The chip packaging structure according to claim 1, characterized in that: The second chip is interconnected with the first chip through a first connection member, and the first chip is interconnected with a region outside the mounting portion through the first connection member.

3. The chip packaging structure according to claim 1, characterized in that: The second chip is at least partially or entirely located in the dug hole; or, the second chip is at least partially or entirely located in the groove.

4. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure further includes: a dielectric layer; the lower surface of the dielectric layer is flush with the lower surface of the carrier, or the dielectric layer completely or partially wraps the carrier.

5. The chip packaging structure according to claim 2, characterized in that: The first connector includes: a first sub-connector and a second sub-connector, the second chip is interconnected with the first chip through the first sub-connector, and the area on the first chip except for the interconnection between the second chip and the first chip is interconnected with the carrier through the second sub-connector; wherein the size of the first sub-connector is larger than that of the second sub-connector.

6. The chip packaging structure according to claim 2, characterized in that: The first connector includes: a first sub-connector and a second sub-connector, the second chip is interconnected with the first chip through the first sub-connector, and the area on the first chip except for the interconnection between the second chip and the first chip is interconnected with the carrier through the second sub-connector; wherein the size of the first sub-connector is smaller than that of the second sub-connector.

7. The chip packaging structure according to claim 1, characterized in that: The carrier board is a frame, the frame has frame pins, the groove or the through hole is provided in the middle of the frame, and the second chip is placed in the groove or the through hole; the area on the first chip except the interconnection between the second chip and the first chip is interconnected with the surface of the frame through a first connector; and / or the first chip is electrically connected to the frame pins through the first connector.

8. The chip packaging structure according to any one of claims 2, 5-7, characterized in that: The first connecting member is one or a combination of a bump, a pad, and a solder ball.

9. The chip packaging structure according to claim 4, characterized in that: The surface of the dielectric layer is flush with the surface of the first chip, and the silicon wafer of the first chip is exposed on the surface of the dielectric layer.

10. The chip packaging structure according to claim 4, characterized in that: The surface of the second chip is flush with the bottom of the carrier, and the silicon wafer of the second chip is exposed on the bottom surface of the carrier.

11. The chip packaging structure according to claim 1, characterized in that: There is at least one second chip, each of which is located in the mounting portion and interconnected with the first chip via a first connector, and the first chip is interconnected with an area outside the mounting portion via the first connector.

12. The chip packaging structure according to any one of claims 1 to 6 and 9 to 10, characterized in that: One end of the carrier away from the first chip is connected with a second connector.

13. The chip packaging structure according to claim 12, characterized in that: The second connecting member is one or a combination of a solder pad and a solder ball.

14. An electronic device, characterized in that: The invention comprises at least one chip packaging structure according to any one of claims 1 to 13.

Images