High-bandwidth digital signal feedback type sensor for SiC-MOSFET module

Abstract

The invention relates to the technical field of third-generation grid control type power semiconductor devices, and discloses a high-bandwidth digital signal feedback type sensor for a SiC-MOSFET module, which comprises two input attenuation stages, each input attenuation stage comprises a pair of surface-mounted resistance-capacitance input bridge arms with a differential structure, one end of one input attenuation stage is connected with the drain electrode and the source electrode of the SiC-MOSFET module, the other end of the input attenuation stage is connected with the input end of the first fully differential buffer stage, one end of the other input attenuation stage is connected with the Kelvin terminal and the source electrode of the SiC-MOSFET module, and the other end of the other input attenuation stage is connected with the input end of the second fully differential buffer stage. The output end of the first fully-differential buffer stage and the output end of the second fully-differential buffer stage are connected with the input end of the sampling calculation stage. According to the high-bandwidth digital signal feedback type sensor for the SiC-MOSFET module, the drain-source voltage, the drain-source voltage change rate, the drain current and the drain current change rate are obtained through the multiple digital filters, real-time detection of the state quantity of the SiC-MOSFET module is achieved, and the measurement precision is high.

Description

Technical Field

[0001] The present invention relates to the technical field of third-generation gate-controlled power semiconductor devices, and in particular to a high-bandwidth digital signal feedback sensor for a SiC-MOSFET module. Background Art

[0002] In recent years, the application of power electronic converters has become increasingly mature, which has put forward higher requirements for power semiconductor devices. In particular, the emergence of the third-generation gate-controlled power semiconductors represented by SiC-MOSFET has gradually become the first choice for high-power density power electronic devices due to its higher operating temperature, faster switching speed and lower switching loss.

[0003] In most analysis and modeling of power electronic converters, the transient characteristics of power devices are regarded as ideal switching processes, but in fact, power semiconductor devices still comply with the laws of semiconductor physics during transient processes. Compared with the ideal switching pulse signal issued by the controller, the transient waveform of wide bandgap devices exhibits severe spike stress and EMI. In order to further improve the switching characteristics of gate-controlled power semiconductors, gate active control methods have emerged, which can effectively optimize the non-ideal characteristics of transient processes. Among them, the closed-loop gate active control method that introduces negative feedback can effectively get rid of the dependence on model accuracy and has received more widespread attention than the open-loop method.

[0004] In theory, the gate active control device based on the digital signal feedback circuit can not only realize real-time tracking control, but also provide threshold comparison function through the on-chip system. More importantly, it is conducive to building complex control algorithm functions and is suitable for variable device characteristics and different operating points.

[0005] However, in reality, existing active gate control devices rarely use digital signal feedback circuits as part of them. On the one hand, it is difficult to design sensors with high bandwidth and high integration. On the other hand, compared with continuous state feedback circuits and discrete event feedback circuits, digital signal feedback circuits have additional digital-to-analog conversion and analog-to-digital conversion time for the conversion of state quantities, making it difficult to control in real time. Research on digital signal feedback circuits with high bandwidth and low latency is crucial to realizing the theoretical advantages of digital active gate control devices in SiC-MOSFET modules.

[0006] In addition, the current digital feedback sensors are not designed in the same way as the detection methods for various known applications. Due to the limitations of practical application conditions such as high bandwidth and short delay, the available voltage and current measurement methods are almost fixed, and the main problems are as follows:

[0007] First, the differential signal needs to pass through the attenuation stage and buffer stage in sequence. Incompletely symmetrical resistors, capacitors, buffers and parasitic parameters will reduce the measurement accuracy. For example, the mismatch of feedback coefficients will introduce additional noise to limit the range of the measurement range and attenuation ratio.

[0008] Second, the transient time of the SiC-MOSFET module is very short. Affected by the circuit parasitic parameters and the non-ideal characteristics of the operational amplifier, the existing detection circuit is difficult to have a high bandwidth to meet the needs of measuring the transient process;

[0009] Third, the measurement problem of non-isolated voltage not only affects the measurement of drain-source voltage, but also affects the measurement of drain current. Compared with the measurement method of magnetic isolation, this method of calculating the current by non-isolated voltage measurement will introduce the coupled electrical quantity I D ·R SER :

[0010]

[0011] Among them, V KS Refers to the voltage between the Kelvin terminal and the source of the SiC-MOSFET module, R SER It refers to the parasitic resistance between the Kelvin terminal and the source of the SiC-MOSFET module, L KS It refers to the parasitic inductance between the Kelvin terminal and the source of the SiC-MOSFET module, I D It refers to the drain current of the SiC-MOSFET module.

[0012] However, most current detection methods ignore I D ·R SER This coupled electrical quantity directly gives the following integral formula to realize current detection, and the current measurement accuracy is generally low.

[0013]

[0014] In view of this, the present invention provides a high-bandwidth digital signal feedback sensor applied to a SiC-MOSFET module, aiming to solve the above-mentioned problem. Summary of the invention

[0015] The purpose of the present invention is to address the deficiencies of the above-mentioned technology and provide a high-bandwidth digital signal feedback sensor for SiC-MOSFET modules. The sensor obtains the drain-source voltage, the drain-source voltage change rate, the drain current and the drain current change rate through multiple digital filters, thereby realizing real-time detection of the state quantity of the SiC-MOSFET module with high measurement accuracy.

[0016] To achieve the above-mentioned purpose, the high-bandwidth digital signal feedback sensor for SiC-MOSFET module designed by the present invention comprises a first input attenuation stage and a second input attenuation stage, wherein the first input attenuation stage and the second input attenuation stage each comprise a pair of surface-mounted RC input bridge arms of a differential structure, one end of the two surface-mounted RC input bridge arms of the first input attenuation stage are respectively connected to the drain and source of the SiC-MOSFET module, and the other end are both connected to the input end of the first fully differential buffer stage, one end of the two surface-mounted RC input bridge arms of the second input attenuation stage are respectively connected to the Kelvin terminal and the source of the SiC-MOSFET module, and the other end are both connected to the input end of the second fully differential buffer stage, and the output ends of the first fully differential buffer stage and the second fully differential buffer stage are both connected to the input end of the sampling and calculation stage.

[0017] Preferably, the output ends of the two surface-mount RC input bridge arms are each connected to a voltage-dividing surface-mount resistor, and the two voltage-dividing surface-mount resistors are connected to a variable resistor whose sliding end is grounded.

[0018] Preferably, the output ends of the two surface-mount RC input bridge arms are each grounded via a frequency compensation surface-mount capacitor located downstream of the voltage-dividing surface-mount resistor.

[0019] Preferably, the surface-mount RC input bridge arm is formed by a plurality of surface-mount resistor and capacitor groups of equal value connected in series in sequence, wherein each surface-mount resistor and capacitor group is composed of a surface-mount resistor and a surface-mount capacitor connected in parallel.

[0020] Preferably, the first fully differential buffer stage and the second fully differential buffer stage each include two field effect transistor operational amplifiers and a fully differential operational amplifier connected to the field effect transistor operational amplifier, the input ends of the first fully differential buffer stage and the second fully differential buffer stage are each provided with a clamping diode, the clamping diode is connected to the two field effect transistor operational amplifiers, the feedback circuits of the two field effect transistor operational amplifiers each include a fixed value parallel resistor and capacitor group, and share an adjustable value parallel resistor and capacitor group, and the feedback circuit of the fully differential operational amplifier includes two fixed value parallel resistor and capacitor groups located upstream and two fixed value parallel resistor and capacitor groups located downstream, respectively.

[0021] Preferably, the relative error of the resistors in the fixed-value parallel resistor and capacitor group is less than 0.1%, and the relative error of the capacitors is less than 1%.

[0022] Preferably, the sampling and calculation stage includes two ADCs, one end of the two ADCs is respectively connected to the first fully differential buffer stage and the second fully differential buffer stage, and the other end is connected to the FPGA, and also includes a clock distributor that provides clock signals for the ADCs and the FPGA.

[0023] Preferably, the clock distributor can eliminate clock jitter and provide at least three clock signals, the ADC has differential analog signal input, parallel LVDS digital signal output and low latency, and the FPGA implements sampling calculation and filter circuit functions.

[0024] Preferably, the clock distributor is connected to a reference clock crystal oscillator and a voltage-controlled crystal oscillator, and the reference clock crystal oscillator provides a reference clock signal for the clock distributor. At the same time, the clock distributor drives a phase-locked loop filter through a built-in charge pump to control the voltage-controlled crystal oscillator to output a clock signal with adjustable period and phase, which is then distributed to the FPGA and ADC through the clock distributor.

[0025] Preferably, the ADC converts the sampled analog signals of the drain-source voltage and the voltage between the Kelvin terminal and the source into low-latency parallel LVDS digital signals through a first input attenuation stage, a second input attenuation stage, a first fully differential buffer stage and a second fully differential buffer stage, and finally sends them to the FPGA. The FPGA obtains the drain-source voltage change rate through a first-order high-pass filter circuit, obtains the drain current change rate through a correction filter circuit, and then obtains the drain current through an integral filter circuit.

[0026] Compared with the prior art, the present invention has the following advantages:

[0027] 1. Only two ADC channels are used to detect the voltage drop and drain-source voltage across the parasitic inductance between the Kelvin and power terminals of the SiC MOSFET module under high bandwidth and high integration density conditions;

[0028] 2. With the shortest delay as the goal, the filter algorithm is used to calculate and restore the drain-source voltage change rate, drain current change rate, and drain current;

[0029] 3. It can effectively avoid the impact of non-isolated voltage detection, including non-ideal buffer levels, load effects and distributed parameters, thereby achieving real-time status perception of SiC-MOSFET modules. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a schematic diagram of the structure of a high-bandwidth digital signal feedback sensor for SiC-MOSFET modules of the present invention;

[0031] Figure 2 for Figure 1 Schematic diagram of the structure of the input attenuation stage;

[0032] Figure 3 for Figure 1 Schematic diagram of the structure of the fully differential buffer stage;

[0033] Figure 4 for Figure 1 Schematic diagram of the structure of the sampling calculation level;

[0034] Figure 5 Schematic diagram of the input capacitance of the fully differential buffer stage formed by the non-ideal factors of the field effect transistor operational amplifier and the non-ideal factors of the clamping diode.

[0035] The components in the figure are numbered as follows:

[0036] First input attenuation stage 1, second input attenuation stage 2, surface mount resistor and capacitor input bridge arm 3, SiC-MOSFET module 4, drain 5, source 6, first fully differential buffer stage 7, Kelvin terminal 8, second fully differential buffer stage 9, sampling calculation stage 10, variable resistor 11, frequency compensation surface mount capacitor 12, surface mount resistor and capacitor group 13, surface mount resistor 14, surface mount capacitor 15, field effect transistor operational amplifier 16, fully differential operational amplifier 17, clamping diode 18, fixed value parallel resistor and capacitor group 19, adjustable value parallel resistor and capacitor group 20, ADC 21, FPGA 22, clock distributor 23, reference clock crystal oscillator 24, voltage-controlled crystal oscillator 25, phase-locked loop filter 26, voltage divider surface mount resistor 27. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0039] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the meaning of "and / or" appearing in the full text includes three parallel schemes. Taking "A and / or B" as an example, it includes scheme A, or scheme B, or a scheme that satisfies both A and B. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary technicians in the field to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0040] like Figure 1 and Figure 2 As shown, a high-bandwidth digital signal feedback sensor for a SiC-MOSFET module comprises a first input attenuation stage 1 and a second input attenuation stage 2, wherein the first input attenuation stage 1 and the second input attenuation stage 2 each comprise a pair of surface-mounted RC input bridge arms 3 of a differential structure, one end of the two surface-mounted RC input bridge arms 3 of the first input attenuation stage 1 are respectively connected to a drain 5 and a source 6 of a SiC-MOSFET module 4, and the other end are both connected to an input end of a first fully differential buffer stage 7, one end of the two surface-mounted RC input bridge arms 3 of the second input attenuation stage 2 are respectively connected to a Kelvin terminal 8 and a source 6 of the SiC-MOSFET module 4, and the other end are both connected to an input end of a second fully differential buffer stage 9, and the output ends of the first fully differential buffer stage 7 and the second fully differential buffer stage 9 are both connected to an input end of a sampling and calculation stage 10.

[0041] Among them, combined Figure 2 As shown, the output ends of the two surface-mounted RC input bridge arms 3 are each connected to a voltage-dividing surface-mounted resistor 27, and the two voltage-dividing surface-mounted resistors 27 are connected to a variable resistor 11 with a grounded sliding end, and the output ends of the two surface-mounted RC input bridge arms 3 are each grounded through a frequency compensation surface-mounted capacitor 12 at the downstream of the voltage-dividing surface-mounted resistor 27.

[0042] like Figure 2 As shown, the surface mount RC input bridge arm 3 is formed by a plurality of surface mount resistor and capacitor groups 13 of equal value connected in series in sequence, wherein each surface mount resistor and capacitor group 13 is composed of a surface mount resistor 14 and a surface mount capacitor 15 connected in parallel.

[0043] like Figure 3As shown, the first fully differential buffer stage 7 and the second fully differential buffer stage 9 each include two field effect transistor operational amplifiers 16 and a fully differential operational amplifier 17 connected to the field effect transistor operational amplifier 16, the input ends of the first fully differential buffer stage 7 and the second fully differential buffer stage 9 are each provided with a clamping diode 18, the clamping diode 18 is connected to the two field effect transistor operational amplifiers 16, the feedback circuits of the two field effect transistor operational amplifiers 16 each include a fixed value parallel resistor and capacitor group 19, and share an adjustable value parallel resistor and capacitor group 20, and the feedback circuit of the fully differential operational amplifier 17 includes two fixed value parallel resistor and capacitor groups 20 located upstream and two fixed value parallel resistor and capacitor groups 20 located downstream, respectively.

[0044] Among them, the relative error of the resistors in the fixed-value parallel resistor and capacitor group 19 is less than 0.1%, and the relative error of the capacitors is less than 1%.

[0045] like Figure 4 As shown, the sampling calculation stage 10 includes two ADCs 21, one end of the two ADCs 21 is connected to the first full differential buffer stage 7 and the second full differential buffer stage 9 respectively, and the other end is connected to the FPGA 22, and also includes a clock distributor 23 that provides clock signals to the ADCs 21 and the FPGA 22.

[0046] Among them, the clock distributor 23 can eliminate clock jitter and provide at least three clock signals. ADC21 is a differential analog signal input and a parallel LVDS digital signal output with low latency. FPGA22 realizes sampling calculation and filter circuit functions. Specifically, the clock distributor 23 is connected to a reference clock crystal oscillator 24 and a voltage-controlled crystal oscillator 25. The reference clock crystal oscillator 24 provides a reference clock signal for the clock distributor 23. At the same time, the clock distributor 23 drives the phase-locked loop filter 26 through the built-in charge pump to control the voltage-controlled crystal oscillator 25 to output a clock signal with adjustable period and phase, which is then distributed to FPGA22 and ADC21 through the clock distributor 23.

[0047] In this embodiment, ADC21 converts the sampled drain-source voltage and the analog signal of the voltage between the Kelvin terminal 8 and the source 6 into a low-latency parallel LVDS digital signal through the first input attenuation stage 1, the second input attenuation stage 2, the first fully differential buffer stage 7 and the second fully differential buffer stage 9, and finally sends it to FPGA22. FPGA22 obtains the drain-source voltage change rate through a first-order high-pass filter circuit, obtains the drain current change rate through a correction filter circuit, and then obtains the drain current through an integral filter circuit.

[0048] Compared with the traditional non-isolated voltage detection device, in the technical solution provided by the present invention, since the two surface mount RC input bridge arms 3 are formed by a plurality of surface mount resistor and capacitor groups 13 of equal value connected in series in sequence, it is possible to ensure uniform voltage division of each surface mount resistor and capacitor group 13 on the surface mount RC input bridge arm 3. Among them, the number of the plurality of surface mount resistor and capacitor groups 13 of equal value connected in series on the two surface mount RC input bridge arms 3 not only satisfies that the sum of the rated voltages is greater than the rated voltage of the SiC-MOSFET module 4 under test, but also satisfies that the thermal power consumption of each surface mount resistor and capacitor group 13 is less than its own thermal breakdown power consumption, so as to ensure the normal operation of the input attenuation stage.

[0049] In addition, the two voltage-dividing surface mount resistors 27 in each differential structure are connected via a variable resistor 11 with a grounded sliding end. By adjusting the variable resistor 11, the reduction of the common mode rejection ratio caused by the asymmetric resistance of the two surface mount RC input bridge arms 3 can be effectively avoided.

[0050] Again, the output ends of the first input attenuation stage 1 and the second input attenuation stage 2 are grounded via the frequency compensation surface mount capacitor 12 , which can effectively avoid bandwidth attenuation caused by non-ideal factors of the two field effect transistor operational amplifiers 16 .

[0051] It should be noted that the resistors and capacitors used in the first input attenuation stage 1 and the second input attenuation stage 2 can be high-voltage resistant surface-mount resistors and capacitors, but are not limited to high-voltage resistant surface-mount resistors and capacitors. As long as there are multiple equal-value parallel resistors and capacitors connected in series, and an adjustable variable resistor 11 is provided between the output voltage-dividing surface-mount resistors 27, and the circuit design structure with a frequency compensation surface-mount capacitor 12 connected to ground at the connection with the subsequent operational amplifier belongs to the first input attenuation stage 1 and the second input attenuation stage 2 in the example of the present invention. At the same time, there are multiple choices for the specific values ​​of the surface-mount resistor 14 and the surface-mount capacitor 15, as well as the specific values ​​of the corresponding attenuation ratios they constitute, as long as the rated voltage (several thousand volts) of the SiC-MOSFET module 4 can be converted to a voltage (several volts) that can be used for signal conditioning, and this embodiment does not limit this.

[0052] It is understandable that if Figure 5 As shown, the non-ideal factors (parasitic capacitance C DM , C CM ) and the non-ideal factor of the clamping diode 18 (junction capacitance C D ) will form a low-pass filter with the two surface-mounted RC input bridge arms 3, and limit the upper limit of the measurement bandwidth of the detection device. After adding the frequency compensation surface-mounted capacitor 12 to ground, the pole caused by the low-pass filter is compensated.

[0053] In this embodiment, the clamping diode 18 is used to limit the voltage that exceeds the range available for signal conditioning, the two field effect transistor operational amplifiers 16 are used as buffer stages to provide a larger input resistance and a smaller output resistance to achieve impedance conversion, and the fully differential operational amplifier 17 provides a DC coupling function with the ADC 21.

[0054] In this embodiment, the first fully differential buffer stage 7 and the second fully differential buffer stage 9 include but are not limited to two field effect transistor operational amplifiers 16 and one fully differential operational amplifier 17. As long as the three-op amp instrumentation amplifier structure formed by a high-bandwidth operational amplifier (bandwidth greater than 20MHz) with a large input impedance and a small output impedance and forming a DC-coupled differential output with ADC21 belongs to the first fully differential buffer stage 7 and the second fully differential buffer stage 9 in the embodiment of the present invention; at the same time, there are many settings for the first fully differential buffer stage 7 and the second fully differential buffer stage 9. As long as the resistance of the fixed-value parallel resistor-capacitor group 19 and the adjustable-value parallel resistor-capacitor group 20 in the feedback circuit can meet the balance requirements of the differential structure (the relative error of the fixed-value resistor in the relative position is less than 0.1%), the specific value of this resistor is not limited in this embodiment.

[0055] Similarly, the capacitors of the fixed-value parallel resistor and capacitor group 19 and the adjustable-value parallel resistor and capacitor group 20 also play a role in frequency compensation (the basic principle is the same as the frequency compensation surface-mount capacitors 12 in the first input attenuation stage 1 and the second input attenuation stage 2, and the relative error of the fixed-value capacitors in relative position is less than 1%).

[0056] In this embodiment, the sampling and calculation stage 10 includes two differential analog signal inputs and a low-latency high-speed ADC 21 with a parallel LVDS digital signal output. In order to achieve the purpose of real-time detection, the conversion delay of ADC21 is related to the communication interface and the sampling period. Compared with the communication interface of JESD204B, the conversion delay of ADC21 of the parallel LVDS communication interface is lower and proportional to the sampling period, and can simultaneously ensure a small and fixed total delay. Therefore, within the real-time detection requirements and the high-speed communication range (more than 100Msps), as long as a high-speed ADC21 with a parallel LVDS communication interface is selected, it belongs to the sampling and calculation stage 10 in the embodiment of the present invention. At the same time, the sampling and calculation stage 10 has a variety of implementation methods, and this embodiment does not make special model restrictions on the FPGA22, ADC21 and clock distributor 23 that meet the sampling requirements.

[0057] In addition, in this embodiment, the sampling calculation stage 10 includes the FPGA 22 and its built-in IIR filter circuit (including a first-order high-pass filter, a correction filter, and an integral filter), wherein the transfer function of the correction filter circuit is as follows:

[0058]

[0059] Among them, V′ KS It refers to the voltage between the Kelvin terminal 8 and the source 6 of the SiC-MOSFET module 4, which is input to the digital signal of the FPGA 22 after passing through the ADC 21. S refers to the sampling period, It refers to the rate of change of the drain current of the SiC-MOSFET module 4. As long as the circuit with the correction filter function shown in the above formula is selected, it belongs to the sampling calculation stage 10 in the embodiment of the present invention. At the same time, the first-order high-pass filter circuit and the integral filter circuit can have a variety of different configurations. This embodiment does not specifically limit the filter circuit structure that satisfies the first-order high-pass filter function and the integral filter function.

[0060] It can be understood that the correction filter removes The electrical quantity I D ·R SER , only the term of the rate of change is retained to enter the integral filter link, and the drain current is restored with high precision.

[0061] The high-bandwidth digital signal feedback sensor for SiC-MOSFET modules of the present invention uses only two ADC21 channels to achieve detection of the voltage drop across the parasitic inductance and the drain-source voltage between the Kelvin terminal 8 of the SiC MOSFET module 4 and the power terminal under high bandwidth and high integration density conditions; the drain-source voltage change rate, the drain current change rate and the drain current are calculated and restored through a filtering algorithm with the shortest delay as the goal; the influence of non-isolated voltage detection, including non-ideal buffer levels, load effects and distributed parameters, can be effectively avoided, thereby achieving real-time status perception of the SiC-MOSFET module.

[0062] It should be noted that the description of the above technical solutions is exemplary, and the present specification can be embodied in different forms and should not be interpreted as being limited to the technical solutions described herein. On the contrary, providing these descriptions will make the disclosure of the present invention thorough and complete, and will fully convey the scope disclosed in this specification to those skilled in the art.

[0063] For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, and the above structures should be regarded as belonging to the protection scope of the present invention.

Claims

1. A high-bandwidth digital signal feedback sensor for SiC-MOSFET modules, characterized in that: The invention comprises a first input attenuation stage (1) and a second input attenuation stage (2), wherein the first input attenuation stage (1) and the second input attenuation stage (2) each comprise a pair of surface-mounted RC input bridge arms (3) of a differential structure, wherein one end of the two surface-mounted RC input bridge arms (3) of the first input attenuation stage (1) are respectively connected to a drain (5) and a source (6) of a SiC-MOSFET module (4), and the other end is connected to an input end of a first fully differential buffer stage (7), and one end of the two surface-mounted RC input bridge arms (3) of the second input attenuation stage (2) are respectively connected to a Kelvin terminal (8) and a source (6) of the SiC-MOSFET module (4), and the other end is connected to an input end of a second fully differential buffer stage (9), and the output ends of the first fully differential buffer stage (7) and the second fully differential buffer stage (9) are both connected to an input end of a sampling and calculation stage (10).

2. The high-bandwidth digital signal feedback sensor for SiC-MOSFET modules according to claim 1, characterized in that: The output ends of the two surface mount RC input bridge arms (3) are each connected to a voltage dividing surface mount resistor (27), and the two voltage dividing surface mount resistors (27) are connected to a variable resistor (11) with a sliding end grounded.

3. The high-bandwidth digital signal feedback sensor for SiC-MOSFET modules according to claim 2, characterized in that: The output ends of the two surface-mounted RC input bridge arms (3) are each grounded via a frequency compensation surface-mounted capacitor (12) at the downstream of the voltage-dividing surface-mounted resistor (27).

4. The high-bandwidth digital signal feedback sensor for SiC-MOSFET modules according to claim 1, characterized in that: The surface-mounted resistor-capacitor input bridge arm (3) is formed by a plurality of surface-mounted resistor and capacitor groups (13) of equal value connected in series in sequence, wherein each surface-mounted resistor and capacitor group (13) is composed of a surface-mounted resistor (14) and a surface-mounted capacitor (15) connected in parallel.

5. The high-bandwidth digital signal feedback sensor for SiC-MOSFET module according to claim 1, characterized in that: The first fully differential buffer stage (7) and the second fully differential buffer stage (9) both comprise two field effect transistor operational amplifiers (16) and a fully differential operational amplifier (17) connected to the field effect transistor operational amplifier (16); a clamping diode (18) is provided at the input end of each of the first fully differential buffer stage (7) and the second fully differential buffer stage (9); the clamping diode (18) is connected to the two field effect transistor operational amplifiers (16); the feedback circuits of the two field effect transistor operational amplifiers (16) each comprise a fixed value parallel resistor and capacitor group (19) and share an adjustable value parallel resistor and capacitor group (20); the feedback circuit of the fully differential operational amplifier (17) comprises two fixed value parallel resistor and capacitor groups (20) located upstream and two fixed value parallel resistor and capacitor groups (20) located downstream, respectively.

6. The high-bandwidth digital signal feedback sensor for SiC-MOSFET modules according to claim 5, characterized in that: The relative error of the resistors in the fixed-value parallel resistor and capacitor group (19) is less than 0.1%, and the relative error of the capacitors is less than 1%.

7. The high-bandwidth digital signal feedback sensor for SiC-MOSFET modules according to claim 1, characterized in that: The sampling calculation stage (10) comprises two ADCs (21), one end of the two ADCs (21) is respectively connected to the first full differential buffer stage (7) and the second full differential buffer stage (9), and the other end is connected to an FPGA (22), and also comprises a clock distributor (23) for providing a clock signal to the ADCs (21) and the FPGA (22).

8. The high-bandwidth digital signal feedback sensor for SiC-MOSFET modules according to claim 7, characterized in that: The clock distributor (23) can eliminate clock jitter and provide at least three clock signals. The ADC (21) has differential analog signal input and parallel LVDS digital signal output with low latency. The FPGA (22) realizes sampling calculation and filter circuit functions.

9. The high-bandwidth digital signal feedback sensor for SiC-MOSFET modules according to claim 8, characterized in that: The clock distributor (23) is connected to a reference clock crystal oscillator (24) and a voltage-controlled crystal oscillator (25). The reference clock crystal oscillator (24) provides a reference clock signal for the clock distributor (23). At the same time, the clock distributor (23) drives a phase-locked loop filter (26) through a built-in charge pump to control the voltage-controlled crystal oscillator (25) to output a clock signal with adjustable period and phase, which is then distributed to the FPGA (22) and ADC (21) through the clock distributor (23).

10. The high-bandwidth digital signal feedback sensor for SiC-MOSFET modules according to claim 9, characterized in that: The ADC (21) converts the sampled drain-source voltage and the analog signal of the voltage between the Kelvin terminal (8) and the source (6) into a low-latency parallel LVDS digital signal through a first input attenuation stage (1), a second input attenuation stage (2), a first fully differential buffer stage (7) and a second fully differential buffer stage (9), and finally sends the signal to the FPGA (22). The FPGA (22) obtains the drain-source voltage change rate through a first-order high-pass filter circuit, obtains the drain current change rate through a correction filter circuit, and obtains the drain current through an integration filter circuit.

Images