Liquid crystal display panel, preparation method thereof and display device

Abstract

The invention provides a liquid crystal display panel, a preparation method thereof and a display device. The display device comprises a backlight module, the liquid crystal display panel comprises a first substrate, a second substrate opposite to the first substrate and a liquid crystal layer clamped between the first substrate and the second substrate, and the second substrate and the first substrate are sequentially arranged in the light emitting direction of the liquid crystal display panel; the first substrate comprises a first substrate body and a plurality of pixel units, the first substrate body is provided with a first surface, the pixel units are arranged in a matrix mode in the first direction and the second direction, each pixel unit comprises a color film layer and a thin film transistor, the color film layer is stacked on the first surface and provided with a light-transmitting area and a non-light-transmitting area, and the non-light-transmitting area surrounds the light-transmitting area; the thin film transistor covers the surface, back to the first substrate, of the color film layer, and the orthographic projection of the thin film transistor on the color film layer is located in the non-light-transmitting area in the thickness direction of the liquid crystal display panel. The display quality of the liquid crystal display panel can be guaranteed.

Description

Technical Field

[0001] The present application relates to the field of display technology, in particular to a liquid crystal display panel and a preparation method thereof, and a display device. Background Art

[0002] As the technology of flat-panel liquid crystal display products matures, mankind is entering a fast-growing era of the Internet of Things. Traditional panel manufacturers have shifted from the original flat display to the innovation of curved display. Curved liquid crystal display technology came into being. Existing TFT-LCDs (Thin film transistor liquid crystal display) usually include an array substrate and a color film substrate arranged opposite to the array substrate. The array substrate is usually provided with thin film transistors and drive circuits. The color film substrate is usually provided with a black matrix to shield the thin film transistors. However, during the process of aligning the color film substrate and the array substrate, the black matrix on the color film substrate may be displaced from the thin film transistor on the array substrate, resulting in the black matrix being unable to shield the thin film transistor, which in turn causes serious light leakage in the liquid crystal display panel. Summary of the invention

[0003] The purpose of the present application is to provide a liquid crystal display panel and a preparation method thereof, and a display device, which can ensure the display quality of the liquid crystal display panel and avoid light leakage of the liquid crystal display panel.

[0004] A first aspect of the present application provides a liquid crystal display panel, the liquid crystal display panel comprising a first substrate, a second substrate arranged opposite to the first substrate, and a liquid crystal layer sandwiched between the first substrate and the second substrate, wherein the second substrate and the first substrate are arranged in sequence along a light emitting direction of the liquid crystal display panel;

[0005] The first substrate comprises a first substrate and a plurality of pixel units, the first substrate has a first surface, the plurality of pixel units are arranged in a matrix along a first direction and a second direction, each of the pixel units comprises a color filter layer and a thin film transistor, the color filter layer is stacked on the first surface, the color filter layer has a light-transmitting area and a non-light-transmitting area, the non-light-transmitting area surrounds the light-transmitting area, and the first direction and the second direction are perpendicular to each other;

[0006] The thin film transistor covers the surface of the color filter layer facing away from the first substrate. Along the thickness direction of the liquid crystal display panel, the orthographic projection of the thin film transistor on the color filter layer is located in the non-light-transmitting area.

[0007] In a possible implementation manner, the color filter layer includes a first passivation layer, the first passivation layer has a first surface, the first passivation layer has a first bump and a second bump, the first bump and the second bump are arranged in parallel, the first bump and the second bump are both convexly arranged on the first surface, and the first bump and the second bump are located in the non-light-transmitting area;

[0008] The first substrate further includes a first electrode layer, and the first electrode layer is stacked on a surface of the plurality of pixel units facing away from the first substrate;

[0009] The color filter layer further includes a second electrode layer, which is stacked on the first surface and covers the first bump and the second bump.

[0010] In a possible implementation manner, the color filter layer further includes a second passivation layer, the second passivation layer covers the surface of the second electrode layer facing away from the first substrate, the second passivation layer is provided with a first deposition groove, the first deposition groove is located in the non-light-transmitting area, the first deposition groove includes a first sub-groove, a second sub-groove and a third sub-groove, the first sub-groove and the second sub-groove are respectively located on opposite sides of the third sub-groove, and the first sub-groove and the second sub-groove are both connected to the third sub-groove, the first convex block is embedded in the second passivation layer, along the thickness direction of the liquid crystal display panel, the orthographic projection of the first sub-groove on the first surface at least partially overlaps with the orthographic projection of the first convex block on the first surface, and the first sub-groove extends to the second electrode layer;

[0011] The thin film transistor comprises a first electrode, a second electrode and an active layer, the first electrode and the second electrode are respectively filled in the first sub-groove and the second sub-groove, and the active layer is filled in the third sub-groove;

[0012] The second electrode layer is electrically connected to the first electrode of the thin film transistor.

[0013] In a possible implementation, the thin film transistor has a gate and a gate insulating layer, the gate insulating layer is stacked on the surface of the second passivation layer facing away from the first substrate and covers the first electrode, the second electrode and the active layer, the gate insulating layer is provided with a first receiving groove, the second bump is embedded in the gate insulating layer, along the thickness direction of the liquid crystal display panel, the orthographic projection of the second bump on the first surface is located within the orthographic projection of the first receiving groove on the first surface, and the first receiving groove extends to the second electrode layer;

[0014] The gate is received in the first receiving groove, and the gate is electrically connected to the second electrode layer.

[0015] In a possible embodiment, the color film layer also includes a black matrix layer and a color resist layer unit, the black matrix layer is stacked on the first surface, the black matrix layer has an opening, the opening is located in the light-transmitting area, the color resist layer unit fills the opening and covers the surface of the black matrix layer facing away from the first substrate, and the first passivation layer is stacked on the surface of the color resist layer unit facing away from the first substrate.

[0016] In a possible implementation manner, the first substrate further includes a plurality of scan lines and a plurality of data lines;

[0017] The second passivation layer is provided with a second deposition groove, the second deposition groove extends along the second direction, the second deposition groove is located in the non-light-transmitting area, the second deposition grooves of the pixel units in the same column are interconnected to form a data line groove, and each of the data line grooves accommodates one data line;

[0018] The gate insulating layer is provided with a second accommodating groove, the second accommodating groove extends along the first direction, the orthographic projection of the second accommodating groove on the color filter layer is located in the non-light-transmitting area, the second accommodating grooves of the pixel units in the same row are interconnected to form scan line grooves, and each of the scan line grooves accommodates one scan line;

[0019] The plurality of scanning lines and the plurality of data lines cross to form a plurality of pixel regions, and the plurality of pixel units correspond to the plurality of pixel regions one by one.

[0020] In a possible implementation manner, the first substrate includes a first alignment layer, and the first alignment layer covers a surface of the first electrode layer facing away from the first substrate;

[0021] The second substrate comprises a second substrate and a second alignment layer, the second substrate has a second surface, and the second alignment layer covers the second surface;

[0022] The liquid crystal display panel also includes a plurality of support columns, which are supported between the first alignment layer and the second alignment layer. Along the thickness direction of the liquid crystal display panel, the orthographic projection of each support column on the color filter layer is located in the non-light-transmitting area.

[0023] A second aspect of the present application provides a display device, comprising a backlight module and the liquid crystal display panel as described above, wherein along the thickness direction of the display device, the backlight module is located on a side of the second substrate facing away from the first substrate.

[0024] A third aspect of the present application provides a method for preparing a liquid crystal display panel, comprising the following steps:

[0025] A first substrate is provided, wherein the first substrate comprises a first substrate, the first substrate has a first surface, a plurality of pixel units are formed on the first surface, the plurality of pixel units are arranged in a matrix, each of the pixel units comprises a color filter layer and a thin film transistor, the color filter layer has a light-transmitting area and a non-light-transmitting area, the non-light-transmitting area surrounds the light-transmitting area, and along the thickness direction of the liquid crystal display panel, the orthographic projection of the thin film transistor on the color filter layer is located in the non-light-transmitting area;

[0026] forming a first electrode layer on a surface of the plurality of pixel units facing away from the first substrate;

[0027] forming a first alignment layer on a surface of the first electrode layer facing away from the first substrate;

[0028] Providing a second substrate, wherein the second substrate comprises a second substrate, and the second substrate has a second surface; forming a second alignment layer on the second surface;

[0029] The first substrate and the second substrate are aligned, a plurality of liquid crystal molecules and a plurality of support pillars are filled between the first alignment layer and the second alignment layer, and the first substrate and the second substrate are bonded together by using a sealant.

[0030] In a possible implementation, the step of “providing a first substrate, the first substrate comprising a first substrate, the first substrate having a first surface, forming a plurality of pixel units on the first surface, the plurality of pixel units being arranged in a matrix, each of the pixel units comprising a color filter layer and a thin film transistor, the color filter layer having a light-transmitting area and a non-light-transmitting area, the non-light-transmitting area surrounding the light-transmitting area, and along the thickness direction of the liquid crystal display panel, the orthographic projection of the thin film transistor on the color filter layer is located in the non-light-transmitting area” comprises:

[0031] forming a black matrix base layer on the first surface, and patterning the black matrix base layer to form the black matrix layer, wherein the black matrix layer has an opening;

[0032] A color-resistance layer unit is formed on a surface of the black matrix layer facing away from the first substrate, and the color-resistance layer unit fills the black matrix layer and covers the opening;

[0033] forming a first passivation base layer on a surface of the color-resistance layer unit facing away from the first substrate, and patterning the first passivation base layer to form the first passivation layer, wherein the first passivation layer has a first bump and a second bump;

[0034] Forming a first electrode layer on a surface of the first passivation layer facing away from the first substrate, wherein the first electrode layer covers the first bump and the second bump;

[0035] A second passivation base layer is formed on a surface of the first electrode layer facing away from the first substrate, and the second passivation base layer is patterned to form a second passivation layer, wherein the second passivation layer has a first deposition groove, wherein the first deposition groove comprises a first sub-groove, a second sub-groove and a third sub-groove, wherein the first sub-groove and the second sub-groove are respectively located at two opposite sides of the third sub-groove, and both the first sub-groove and the second sub-groove are connected to the third sub-groove;

[0036] A thin film transistor is formed on the surface of the second passivation layer facing away from the first substrate, the thin film transistor includes a first electrode, a second electrode, an active layer, a gate insulating layer and a gate, the first electrode is accommodated in the first sub-groove, the second sub-groove is accommodated in the second sub-groove, the active layer is accommodated in the third sub-groove, a gate insulating layer is formed on the surface of the second passivation layer facing away from the first substrate, the gate insulating layer is patterned to form a first accommodating groove, and the gate is accommodated in the first accommodating groove.

[0037] The beneficial effects of the present application are as follows: the first substrate includes a color filter layer, a thin film transistor, a scan line and a data line. The color filter layer includes a black matrix layer. The black matrix layer is used to shield the thin film transistor, the scan line and the data line. By arranging the black matrix layer, the plurality of thin film transistors, the scan line and the data line on the first substrate, during the vacuum boxing of the first substrate and the second substrate, the displacement of the black matrix layer and the thin film transistor, the scan line and the data line can be avoided, thereby avoiding the backlight emitted by the backlight module from passing through the thin film transistor, the scan line or the data line and entering the liquid crystal display panel, thereby avoiding the light leakage phenomenon of the liquid crystal display panel, and improving the display quality of the liquid crystal display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is a schematic diagram of the structure of a liquid crystal display panel provided in an embodiment of the present application;

[0039] Figure 2 yes Figure 1 Another structural schematic diagram of the liquid crystal display panel shown;

[0040] Figure 3 yes Figure 2 A partial structural top view of a display area of ​​a first substrate of the liquid crystal display panel;

[0041] Figure 4 yes Figure 3 A schematic cross-sectional view of a portion of the display area of ​​the first substrate along line Ⅰ-Ⅰ;

[0042] Figure 5 yes Figure 4 An enlarged structural schematic diagram of a pixel unit in a display area of ​​the first substrate is shown;

[0043] Figure 6 yes Figure 3 A schematic cross-sectional view of a portion of the display area of ​​the first substrate along line II-II;

[0044] Figure 7 yes Figure 1 The process flow chart of manufacturing the liquid crystal display panel shown;

[0045] Figure 8-1 to Figure 8-6 yes Figure 1 A structural schematic diagram of the steps in the preparation process of the first substrate of the liquid crystal display panel is shown.

[0046] The nouns corresponding to the reference numerals in the figures are:

[0047] 1000-liquid crystal display panel, 100-first substrate, 200-second substrate, 300-frame glue, 400-liquid crystal layer, 500-display area, 600-non-display area, G-scan line, D-data line, M-pixel area, M1-opening area, M2-non-opening area, 20-pixel unit, 30-color filter layer, 40-thin film transistor, 10-first substrate, 80-first electrode layer, 90-first alignment layer, 11-first surface, 12-third surface, 31-black matrix layer, 32-color resistance layer unit, 33-first passivation layer, 34-second electrode layer, 35-second Passivation layer, 311-opening, 331-first surface, 332-second surface, 333-first bump, 334-second bump, 351-third surface, 352-fourth surface, 353-first deposition groove, 354-second deposition groove, 3531-first sub-groove, 3532-second sub-groove, 3533-third sub-groove, 41-first pole, 42-second pole, 43-active layer, 44-gate insulating layer, 45-gate, 441-first accommodating groove, 210-second substrate, 220-second alignment layer, 212-second surface, 214-fourth surface, 700-support column. DETAILED DESCRIPTION

[0048] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0049] The display device includes a liquid crystal display panel (LCD), a backlight module and a housing. The LCD panel and the backlight module are both installed in the housing. The backlight module is located on one side of the LCD panel and provides backlight for the LCD panel.

[0050] Please refer to Figure 1and Figure 2 , Figure 1 is a schematic diagram of the structure of a liquid crystal display panel provided in an embodiment of the present application; Figure 2 yes Figure 1 Another angle structural schematic diagram of the liquid crystal display panel shown. The liquid crystal display panel 1000 includes a first substrate 100, a second substrate 200, a sealant 300 and a liquid crystal layer 400. Along the light emitting direction of the liquid crystal display panel 1000, the second substrate 200 and the first substrate 100 are arranged in sequence. The sealant 300 is arranged around the edges of the first substrate 100 and the second substrate 200 to fix the first substrate 100 and the second substrate 200. The first substrate 100, the second substrate 200 and the sealant 300 enclose a receiving cavity, and a plurality of liquid crystal molecules are filled in the receiving cavity to form a liquid crystal layer 400. The liquid crystal display panel 1000 includes a display area 500 and a non-display area 600, and the non-display area 600 is arranged around the periphery of the display area 500.

[0051] It should be noted that Figure 1 The liquid crystal display panel 1000 in the embodiment is curved, and the liquid crystal display panel 1000 is a curved display, but it does not constitute a limitation on the shape of the liquid crystal display panel 1000 provided in this embodiment. The liquid crystal display panel 1000 provided in this embodiment can be a flat display or a curved display. In order to more clearly illustrate the layer structure of the liquid crystal display panel 1000, the subsequent figures are described by taking the liquid crystal display panel 1000 as a flat display as an example.

[0052] See also Figure 3 , Figure 3 yes Figure 2 A partial structural top view of the display area of ​​the first substrate of the liquid crystal display panel shown. The liquid crystal display panel 1000 includes a plurality of scan lines G and a plurality of data lines D. The plurality of scan lines G extend along the first direction (row direction) and are arranged at intervals along the second direction (column direction). The plurality of data lines D extend along the second direction (column direction) and are arranged at intervals along the first direction (row direction). The first direction and the second direction are perpendicular. All scan lines G are connected to a scan driver integrated circuit (not shown). The scan driver integrated circuit is used to provide a gate drive signal for the scan line G, and the scan driver integrated circuit is arranged in the non-display area 600. All data lines D are connected to a data driver integrated circuit (not shown). The data driver integrated circuit is used to provide a data voltage for the data line D, and the data driver integrated circuit is arranged in the non-display area 600. The plurality of scan lines G and the plurality of data lines D cross to define a pixel area M arranged in a matrix. The plurality of pixel areas M are arrayed along the first direction (row direction) and the second direction (column direction).

[0053] Each pixel region M is divided into an opening region M1 and a non-opening region M2. The non-opening region M2 in each pixel region M is arranged around the opening region M1. Each pixel region M contains a pixel unit 20. Each pixel unit 20 includes a color filter layer 30 and a thin film transistor 40. The color filter layer 30 has a light-transmitting region and a non-light-transmitting region, and the non-light-transmitting region surrounds the light-transmitting region. Along the thickness direction of the liquid crystal display panel 1000, the light-transmitting region of the color filter layer 30 of each pixel unit 20 corresponds to the opening region M1 of the pixel region M where it is located; the non-light-transmitting region of the color filter layer 30 of each pixel unit 20 corresponds to the non-opening region M2 of the pixel region M where it is located. The positive projection of the thin film transistor 40 of each pixel unit 20 on the color filter layer 30 is located in the non-light-transmitting region. The thin film transistors 40 of the pixel units 20 in the same row are electrically connected to the same scan line G. The thin film transistors 40 of the pixel units 20 in the same column are electrically connected to the same data line D.

[0054] It should be noted that Figure 3 The solid lines extending along the first direction represent the scan lines G, and the solid lines extending along the second direction represent the data lines D. Figure 3 The dot-dash line in FIG. 1 is only used to divide the opening area M1 and the non-opening area M2 , and does not constitute a specific limitation on the structure of the first substrate 100 . Figure 3 The pixel region M, the opening region M1 and the non-opening region M2 are merely examples, and do not limit the shape and number of the pixel region M and the relative positional relationship between the opening region M1 and the non-opening region M2. Figure 3 The double-dotted dash line in FIG. 1 is only used to illustrate that the pixel unit 20 is located in the non-opening area M2, and does not define the specific position and shape of the pixel unit 20. Along the thickness direction of the liquid crystal display panel 1000, the space defined between two adjacent scan lines G and two adjacent data lines D belongs to the defined pixel area M.

[0055] Please refer to Figures 4 to 5 , Figure 4 yes Figure 3 A schematic cross-sectional view of a portion of the display area of ​​the first substrate along line Ⅰ-Ⅰ; Figure 5 yes Figure 4 An enlarged structural schematic diagram of a pixel unit in a display area of ​​the first substrate is shown.

[0056] The first substrate 100 includes a first substrate 10, a plurality of pixel units 20, a first electrode layer 80 and a first alignment layer 90. The plurality of pixel units 20 are formed on the surface of the first substrate 10, and the plurality of pixel units 20 are arranged in a matrix. The first electrode layer 80 is formed on the surface of the plurality of pixel units 20 facing away from the first substrate 10. The first alignment layer 90 is formed on the surface of the first electrode layer 80 facing away from the first substrate 10.

[0057] The first substrate 10 includes a first surface 11 and a third surface 12, and the first surface 11 and the third surface 12 are arranged in opposite directions along the thickness direction of the first substrate 10. The material of the first substrate 10 includes but is not limited to transparent materials such as glass and plastic.

[0058] In one embodiment, the liquid crystal display panel 1000 is a flat display. The first surface 11 and the third surface 12 are both flat and parallel to each other (with a certain process tolerance).

[0059] In one embodiment, the liquid crystal display panel 1000 is a curved display. The first surface 11 and the third surface 12 are both curved surfaces and parallel to each other (with a certain process tolerance).

[0060] Each pixel unit 20 includes a color filter layer 30 and a thin film transistor 40. The color filter layer 30 is stacked on the first surface 11 of the first substrate 10, and the thin film transistor 40 is stacked on the surface of the color filter layer 30 facing away from the first substrate 10.

[0061] It should be noted that, in the present embodiment, the structure of each pixel unit 20 is the same, and the present embodiment of the application only takes the structure of one pixel unit 20 as an example for description.

[0062] In this embodiment, the color filter layer 30 includes a black matrix layer 31 , a color resist layer unit 32 , a first passivation layer 33 , a second electrode layer 34 and a second passivation layer 35 .

[0063] It should be noted that, in this embodiment, the second electrode layer 34 is a pixel electrode layer, and the first electrode layer 80 is a common electrode layer. In other embodiments, the second electrode layer 34 may be a common electrode layer, and the first electrode layer 80 may be a pixel electrode layer.

[0064] The black matrix layer 31 is stacked on the first surface 11 of the first substrate 10. The black matrix layer 31 has an opening 311. The opening 311 penetrates two surfaces of the black matrix layer 31 that are arranged opposite to each other in the thickness direction. The opening 311 of the black matrix layer 31 is located in the light-transmitting area of ​​the color filter layer 30. The material of the black matrix layer 31 includes, but is not limited to, opaque materials such as black resin.

[0065] The color-resist layer unit 32 is stacked on the surface of the black matrix layer 31 facing away from the first substrate 10 . The color-resist layer unit 32 fills the opening 311 of the black matrix layer 31 and covers the surface of the black matrix layer 31 facing away from the first substrate 10 .

[0066] The first passivation layer 33 is stacked on the surface of the color-resistance layer unit 32 facing away from the first substrate 10, and covers the color-resistance layer unit 32. The first passivation layer 33 includes a first surface 331 and a second surface 332. The first surface 331 and the second surface 332 are arranged in opposite directions along the thickness direction of the first passivation layer 33. The first passivation layer 33 is also provided with a first bump 333 and a second bump 334. The first bump 333 and the second bump 334 are arranged in parallel. The first bump 333 is convexly arranged on the first surface 331 of the first passivation layer 33, and extends in a direction away from the first surface 331. The first bump 333 is arranged at an angle with the first surface 331. The second bump 334 is convexly arranged on the first surface 331 of the first passivation layer 33, and extends in a direction away from the first surface 331. The second bump 334 is arranged at an angle with the first surface 331. The first bump 333 and the second bump 334 are both located in the non-light-transmitting area of ​​the color filter layer 30. The material of the first passivation layer 33 includes but is not limited to transparent insulating materials such as AlOx and SiNx.

[0067] The second electrode layer 34 is stacked on the first surface 331 of the first passivation layer 33, and covers the first bump 333 and the second bump 334 of the first passivation layer 33. The material of the second electrode layer 34 includes but is not limited to transparent conductive materials such as ITO.

[0068] The second passivation layer 35 is stacked on the surface of the second electrode layer 34 facing away from the first substrate 10. The second passivation layer 35 includes a third surface 351 and a fourth surface 352, and the third surface 351 and the fourth surface 352 are arranged in opposite directions along the thickness direction of the second passivation layer 35. Along the thickness direction of the second passivation layer 35, the first bump 333 is embedded in the second passivation layer 35. The second bump 334 penetrates the second passivation layer 35 and protrudes from the third surface 351 of the second passivation layer 35. The material of the second passivation layer 35 includes but is not limited to transparent insulating materials such as AlOx and SiNx.

[0069] The second passivation layer 35 is provided with a first deposition groove 353 and a second deposition groove 354. The first deposition groove 353 and the second deposition groove 354 are arranged in parallel. The first deposition groove 353 is recessed in the third surface 351 of the second passivation layer 35. The first deposition groove 353 includes a first sub-groove 3531, a second sub-groove 3532 and a third sub-groove 3533. The first sub-groove 3531 and the second sub-groove 3532 of the first deposition groove 353 are respectively located on opposite sides of the third sub-groove 3533, and the first sub-groove 3531 and the second sub-groove 3532 are both connected to the third sub-groove 3533. The first deposition groove 353 is located in the non-light-transmitting area of ​​the color filter layer 30. Along the thickness direction of the liquid crystal display panel 1000, the orthographic projection of the first sub-groove 3531 on the first surface 11 at least partially overlaps with the orthographic projection of the first bump 333 on the first surface 11. The first sub-groove 3531 extends to the second electrode layer 34. It can be understood that the bottom wall of the first sub-groove 3531 is the portion of the second electrode layer 34 covering the first bump 333 .

[0070] The second deposition groove 354 is recessed in the third surface 351 of the second passivation layer 35. The second deposition groove 354 extends along the second direction. The second deposition groove 354 is located in the non-light-transmitting area.

[0071] Please continue reading Figure 5 The thin film transistor 40 includes a first electrode 41, a second electrode 42, an active layer 43, a gate insulating layer 44 and a gate 45. The first electrode 41 and the second electrode 42 of the thin film transistor 40 are respectively accommodated in the first sub-groove 3531 and the second sub-groove 3532 of the first deposition groove 353 of the second passivation layer 35, and the active layer 43 is accommodated in the third sub-groove 3533 of the first deposition groove 353.

[0072] It should be noted that the first electrode 41 can be the source or drain of the thin film transistor 40, and correspondingly, the second electrode 42 can be the drain or source of the thin film transistor 40, that is, when the first electrode 41 is the source of the thin film transistor 40, the second electrode 42 of the thin film transistor 40 is the drain of the thin film transistor 40; and when the first electrode 41 of the thin film transistor 40 is the drain of the thin film transistor 40, the second electrode 42 of the thin film transistor 40 is the source of the thin film transistor 40, and this embodiment does not make any specific limitation on this.

[0073] The gate insulating layer 44 of the thin film transistor 40 is stacked on the surface of the second passivation layer 35 facing away from the first substrate 10, and covers the first electrode 41, the second electrode 42 and the active layer 43. The material of the gate insulating layer 44 includes but is not limited to transparent insulating materials such as AlOx and SiOx.

[0074] The gate insulating layer 44 of the thin film transistor 40 is provided with a first receiving groove 441 and a second receiving groove. The first receiving groove 441 and the second receiving groove are arranged in parallel. The first receiving groove 441 is recessed on the surface of the gate insulating layer 44 facing away from the first substrate 10. The second bump 334 is embedded in the gate insulating layer 44. Along the thickness direction of the liquid crystal display panel 1000, the orthographic projection of the second bump 334 on the first surface 11 is located within the orthographic projection of the first receiving groove 441 on the first surface 11. The first receiving groove 441 extends to the second electrode layer 34. It can be understood that at least part of the bottom wall of the first receiving groove 441 is the part of the second electrode layer 34 covering the second bump 334.

[0075] The second receiving groove is recessed on the surface of the gate insulating layer 44 facing away from the first substrate 10. The second receiving groove extends along the first direction. The second receiving groove is located in the non-light-transmitting area.

[0076] The gate 45 of the thin film transistor 40 is filled in the first receiving groove 441. The gate 45 is electrically connected to the second electrode layer 34. The material of the gate 45 includes but is not limited to a single metal such as Al, Cu, Ti, Mo, and a composite metal or a multilayer structure composed of any combination of Al, Cu, Ti, Mo, etc.

[0077] Please refer to Figures 3 to 6 , Figure 6 yes Figure 3 A schematic cross-sectional view of a partial structure of the display area of ​​the first substrate along line II-II. A plurality of pixel units 20 are arranged in a matrix along the first direction and the second direction. The second deposition grooves 354 of the pixel units 20 in the same column are interconnected to form a data line groove, and the data line groove extends along the second direction. Each data line groove accommodates a data line D. The second receiving grooves of the pixel units 20 in the same row are interconnected to form a scan line groove, and the scan line groove extends along the first direction. Each scan line groove accommodates a scan line G.

[0078] It can be understood that each data line D extends along the second direction, and multiple data lines D are arranged at intervals along the first direction. Each data line D is located at the junction of two adjacent pixel regions M. The material of the data line D includes but is not limited to a single metal such as Al, Cu, Ti, Mo, and a composite metal or a multilayer structure composed of any combination of Al, Cu, Ti, Mo, etc.

[0079] Each scanning line G extends along the first direction, and a plurality of scanning lines G are arranged at intervals along the second direction. Each scanning line G is located at the junction of two adjacent pixel regions M. The material of the scanning line G includes but is not limited to a single metal such as Al, Cu, Ti, Mo, and a composite metal or a multilayer structure composed of any combination of Al, Cu, Ti, Mo, etc.

[0080] It should be noted that, in other embodiments, multiple data lines D and multiple scan lines G may also be arranged in the same layer; multiple data lines D and multiple scan lines G may also be arranged in other layer structures. Exemplarily, multiple data lines D and multiple scan lines G are all arranged on the first surface 11 of the first substrate 10.

[0081] In addition, when the pixel unit 20 provided in the present embodiment is applied to a display panel in an RGB (Red, Green, Blue) mode, among the multiple pixel units 20, one third of the pixel units 20 are R (Red) pixel units 20, and the R pixel units 20 display red when displayed, one third of the pixel units 20 are G (Green) pixel units 20, and the G pixel units 20 display green when displayed, and one third of the pixel units 20 are B (Blue) pixel units 20, and the B pixel units 20 display blue when displayed. One R pixel unit 20, one G pixel unit 20, and one B pixel unit 20 together constitute a color display unit. In each color display unit, the arrangement of the R pixel unit 20, the G pixel unit 20, and the B pixel unit 20 can be set according to actual needs. For example, the R pixel unit 20, the G pixel unit 20, and the B pixel unit 20 can be arranged sequentially along the first direction (row direction).

[0082] Please continue reading Figures 3 to 6 In this embodiment, the first electrode layer 80 is deposited on the surface of the plurality of pixel units 20 facing away from the first substrate 10. Specifically, the first electrode layer 80 is stacked on the surface of the gate insulating layer 44 of the plurality of pixel units 20 facing away from the second passivation layer 35, and the first electrode layer 80 covers the gates 45 and the gate insulating layer 44 of the plurality of pixel units 20. The material of the first electrode layer 80 includes but is not limited to transparent conductive materials such as ITO.

[0083] In this embodiment, the first substrate 100 further includes a first alignment layer 90. The first alignment layer 90 is stacked on the surface of the first electrode layer 80 away from the first substrate 10. The material of the first alignment layer 90 includes but is not limited to polyimide (PI) material. The first alignment layer 90 is formed on the first electrode layer 80 by coating.

[0084] It can be understood that in this embodiment, the color filter layer 30 of multiple pixel units 20 is in the same layer and connected to each other to form the color filter layer 30 of the first substrate 100. The thin film transistors 40 of multiple pixel units 20 are in the same layer and spaced apart to form a thin film transistor array of the first substrate 100. Specifically, the black matrix layers 31 of the color filter layers 30 of the multiple pixel units 20 are in the same layer and are interconnected to form the black matrix layer 31 of the first substrate 100; the color resist layer units 32 of the color filter layers 30 of the multiple pixel units 20 are in the same layer and are interconnected to form the color resist layer of the first substrate 100 (including multiple color resist layer units 32 of different colors); the first passivation layers 33 of the color filter layers 30 of the multiple pixel units 20 are in the same layer and are interconnected to form the first passivation layer 33 of the first substrate 100; the second electrode layers 34 of the color filter layers 30 of the multiple pixel units 20 are in the same layer to form the second electrode layer 34 of the first substrate 100; the second passivation layers 35 of the color filter layers 30 of the multiple pixel units 20 are in the same layer and are interconnected to form the second passivation layer 35 of the first substrate 100. The first electrodes 41 and the second electrodes 42 of the thin film transistors 40 of the multiple pixel units 20 are in the same layer; the active layers 43 of the thin film transistors 40 of the multiple pixel units 20 are in the same layer; the gate insulating layers 44 of the thin film transistors 40 of the multiple pixel units 20 are in the same layer; and the gates 45 of the thin film transistors 40 of the multiple pixel units 20 are in the same layer.

[0085] In this embodiment, the second substrate 200 includes a second substrate 210 and a second alignment layer 220. The second substrate 210 includes a second surface 212 and a fourth surface 214, and the second surface 212 and the fourth surface 214 are arranged in opposite directions along the thickness direction of the second substrate 210. The second surface 212 and the fourth surface 214 are both planes and parallel to each other (a certain process tolerance is allowed). The material of the second substrate 210 includes but is not limited to transparent materials such as glass and plastic.

[0086] The second alignment layer 220 is stacked on the second surface 212 of the second substrate 210. The material of the second alignment layer 220 includes but is not limited to polyimide (PI) material. The second alignment layer 220 is formed on the second surface 212 of the second substrate 210 by coating. In this embodiment, the first substrate 100 and the second substrate 200 are arranged opposite to each other, and the liquid crystal layer 400 is filled between the first substrate 100 and the second substrate 200. Specifically, the first surface 11 of the first substrate 100 and the second surface 212 of the second substrate 200 are arranged opposite to each other along the thickness direction of the liquid crystal display panel 1000. After the multiple pixel units 20 of the first substrate 100 are powered on, the multiple liquid crystal molecules in the liquid crystal layer 400 can be driven to rotate to control the light flux of the backlight of the backlight module through the liquid crystal layer 400 to the outside of the liquid crystal display panel 1000.

[0087] In this embodiment, the liquid crystal display panel 1000 further includes a plurality of support columns 700. The shape of the support columns 700 includes, but is not limited to, columnar structures such as quadrilateral columns and trapezoidal columns. The plurality of support columns 700 are disposed between the first substrate 100 and the second substrate 200 to support the first substrate 100 and the second substrate 200. Specifically, along the thickness direction of the liquid crystal display panel 1000, the opposite ends of the plurality of support columns 700 are supported on the first alignment layer 90 and the second alignment layer 220, respectively. Along the thickness direction of the liquid crystal display panel 1000, the orthographic projection of each support column 700 on the first surface 11 of the first substrate 10 is located within the orthographic projection of the black matrix layer 31 on the first surface 11 of the first substrate 10.

[0088] It can be understood that, in this embodiment, the first substrate 100 includes a color filter layer 30 and a thin film transistor 40. Among them, the color filter layer 30 includes a black matrix layer 31. The black matrix layer 31 is used to shield the thin film transistor 40, the scan line G and the data line D. By arranging the black matrix layer 31, the plurality of thin film transistors 40, the scan line G and the data line D on the first substrate 100, during the vacuum box-matching process between the first substrate 100 and the second substrate 200, the displacement of the black matrix layer 31 and the thin film transistor 40, the scan line G and the data line D can be avoided, thereby avoiding the backlight emitted by the backlight module from passing through the thin film transistor 40, the scan line G or the data line D and entering the liquid crystal display panel 1000, thereby avoiding the light leakage phenomenon of the liquid crystal display panel 1000, and improving the display quality of the liquid crystal display panel 1000.

[0089] Compared with the prior art, the black matrix layer 31 and the color-blocking layer unit 32 are arranged on the first substrate 100, and the plurality of thin film transistors 40 are arranged on the second substrate 200, and then the first substrate 100 and the second substrate 200 are vacuum-aligned, thereby improving the alignment accuracy of the first substrate 100 and the second substrate 200. Compared with the prior art, the width of the black matrix layer 31 is increased to ensure the shielding effect of the black matrix layer 31 on the thin film transistor 40, the present application arranges the black matrix layer 31, the color-blocking layer unit 32 and the thin film transistor 40 on the first substrate 100, and on the basis of ensuring the alignment accuracy of the first substrate 100 and the second substrate 200, there is no need to increase the width of the black matrix layer 31, thereby ensuring the light flux of the backlight module passing through the liquid crystal display panel 1000, and avoiding the appearance of the mass shadow phenomenon on the display screen of the liquid crystal display panel 1000.

[0090] In the present application, along the thickness direction of the liquid crystal display panel 1000, the black matrix layer 31, the color-blocking layer unit 32 and the thin film transistor 40 are sequentially arranged on the first substrate 10. In the structure of the entire first substrate 100, only the second passivation layer 35 needs to be arranged between the color-blocking layer unit 32 and the second electrode layer 34, and between the second electrode layer 34 and the thin film transistor 40. Therefore, the film structure of the first substrate 100 is relatively simple, and the production process of the first substrate 100 is relatively simple. In addition, the thickness of the color-blocking layer unit 32 and the first passivation layer 33 is relatively thick, and the second electrode layer 34 and the first electrode layer 80 are both located on the side of the color-blocking layer unit 32 and the first passivation layer 33 facing away from the first substrate 10. Therefore, along the thickness direction of the liquid crystal display panel 1000, the spacing between the second electrode layer 34 and the first electrode layer 80 is relatively small. When a certain voltage is applied between the second electrode layer 34 and the first electrode layer 80 , a larger electric field can be formed between the second electrode layer 34 and the first electrode layer 80 , thereby increasing the driving force of the electric field between the second electrode layer 34 and the first electrode layer 80 on the liquid crystal molecules.

[0091] A plurality of support pillars 700 are located on a side of the first substrate 100 close to the backlight module, and the orthographic projection of each support pillar 700 on the first surface 11 of the first substrate 10 is located within the orthographic projection of the black matrix layer 31 on the first surface 11 of the first substrate 10. This can prevent the liquid crystal molecules near the plurality of support pillars 700 from being disordered, causing the light of the backlight module to pass through the liquid crystal molecules near the plurality of support pillars 700 and be emitted from the liquid crystal display panel 1000.

[0092] See also Figure 7 , Figure 7 yes Figure 1 The manufacturing process flow chart of the liquid crystal display panel shown in FIG. The manufacturing method of the liquid crystal display panel 1000 provided in the present application comprises the following steps:

[0093] Step 701: providing a first substrate 100, wherein the first substrate 100 comprises a first substrate 10, wherein the first substrate 10 has a first surface 11, and a plurality of pixel units 20 are formed on the first surface 11, wherein the plurality of pixel units 20 are arranged in a matrix, and each of the pixel units 20 comprises a color filter layer 30 and a thin film transistor 40, wherein the color filter layer 30 has a light-transmitting area and a non-light-transmitting area, wherein the non-light-transmitting area surrounds the light-transmitting area, and along the thickness direction of the liquid crystal display panel 1000, the orthographic projection of the thin film transistor 40 on the color filter layer 30 is located in the non-light-transmitting area;

[0094] Step 702: forming a first electrode layer 80 on the surface of the plurality of pixel units 20 facing away from the first substrate 10;

[0095] Step 703: forming a first alignment layer 90 on a surface of the first electrode layer 80 facing away from the first substrate 10;

[0096] Step 704: providing a second substrate 200 , wherein the second substrate 200 comprises a second substrate 210 , wherein the second substrate 210 has a second surface 212 , and a second alignment layer 220 is formed on the second surface 212 ;

[0097] Step 705: Align the first substrate 100 and the second substrate 200, fill a plurality of liquid crystal molecules and a plurality of support pillars 700 between the first alignment layer 90 and the second alignment layer 220, and bond the first substrate 100 and the second substrate 200 by means of sealant.

[0098] It should be noted that when the liquid crystal display panel 1000 is a curved display, before step 705, the following steps are also included:

[0099] A stress is applied to the first substrate 100 to bend the first substrate 100 ; a stress is applied to the second substrate 200 to bend the second substrate 200 .

[0100] It can be understood that, compared with the prior art in which the first substrate 100 and the second substrate 200 are vacuum-fitted and then liquid crystal molecules are filled between the first substrate 100 and the second substrate 200, in the present application, the first substrate 100 and the second substrate 200 are bent and then liquid crystal molecules are filled between the first substrate 100 and the second substrate 200 to form a liquid crystal layer 400. This can avoid disordered arrangement of the liquid crystal molecules, and further avoid amplification of the birefringence of the liquid crystal molecules, which would cause a phase difference in the light entering the liquid crystal display panel 1000 and affect the display quality of the liquid crystal display panel 1000.

[0101] See also Figure 8-1 to Figure 8-6 , Figure 8-1 to Figure 8-6 yes Figure 1 The structural schematic diagram of the steps of the manufacturing process of the first substrate of the liquid crystal display panel is shown. The manufacturing method of the liquid crystal display panel 1000 provided in the present application includes the following steps:

[0102] Step S801: forming a black matrix layer 31 and a color resist layer unit 32 on the first surface 11 of the first substrate 10;

[0103] Specifically, a black matrix base layer is formed on the surface of the first substrate 10, and the black matrix base layer is patterned to form a black matrix layer 31, so that the black matrix layer 31 has openings. A color-resistance layer unit 32 is formed on the surface of the black matrix layer 31 facing away from the first substrate 10, so that the color-resistance layer unit 32 fills the opening of the black matrix layer 31 and covers the surface of the black matrix layer 31 facing away from the first substrate 10.

[0104] Step S802: forming a first passivation layer 33 and a second electrode layer 34 on the surface of the color resist layer unit 32;

[0105] Specifically, a first passivation base layer is formed on the surface of the color resist layer unit 32 facing away from the first substrate 10. The first passivation base layer is patterned to form a first passivation layer 33 having a first bump 333 and a second bump 334. A second electrode layer 34 is deposited on the surface of the first passivation layer 33 facing away from the first substrate 10, so that the second electrode layer 34 covers the first passivation layer 33.

[0106] Step S803: forming a second passivation layer 35 on the surface of the second electrode layer 34;

[0107] Specifically, a second passivation base layer is deposited on the surface of the second electrode layer 34 facing away from the first substrate 10. The second passivation base layer is patterned to form a second passivation layer 35 having a first deposition groove 353 and a second deposition groove 354. The first deposition groove 353 includes a first sub-groove 3531, a second sub-groove 3532 and a third sub-groove 3533, wherein the first sub-groove 3531 and the second sub-groove 3532 are respectively located at opposite sides of the third sub-groove 3533, and the first sub-groove 3531 and the second sub-groove 3532 are both connected to the third sub-groove 3533;

[0108] Step S804: forming a data line D in the data line groove formed by the second deposition groove 354 of the pixel unit 20 in the same column;

[0109] Step S805: forming a plurality of thin film transistors 40 on the surface of the second passivation layer 35;

[0110] Specifically, the first electrode 41 and the second electrode 42 of the thin film transistor 40 are deposited in the first sub-groove 3531 and the second sub-groove 3532 of the first deposition groove 353 of the second passivation layer 35, respectively; the active layer 43 of the thin film transistor 40 is deposited in the third sub-groove 3533 of the first deposition groove 353; an insulating base layer is deposited on the surface of the second passivation layer 35, and the insulating base layer is patterned to form a gate insulating layer 44 having a first receiving groove 441 and a second receiving groove; and the gate 45 of the thin film transistor 40 is deposited in the first receiving groove 441.

[0111] It should be noted that in the process of forming the first electrode 41, the second electrode 42 and the active layer 43, a half-tone mask can be used, which can save a patterning process and a mask, thereby saving time and material costs.

[0112] Step S806: forming a scan line G in the scan line groove formed by the second receiving groove of the pixel units 20 in the same row, forming a first electrode layer 80 on the surface of the plurality of pixel units 20 facing away from the first substrate 10, and forming a first alignment layer 90 on the surface of the first electrode layer 80 facing away from the first substrate 10.

[0113] The embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A liquid crystal display panel, characterized in that: The liquid crystal display panel comprises a first substrate, a second substrate arranged opposite to the first substrate, and a liquid crystal layer sandwiched between the first substrate and the second substrate, and along the light emitting direction of the liquid crystal display panel, the second substrate and the first substrate are arranged in sequence; The first substrate comprises a first substrate and a plurality of pixel units, the first substrate has a first surface, the plurality of pixel units are arranged in a matrix along a first direction and a second direction, each of the pixel units comprises a color filter layer and a thin film transistor, the color filter layer is stacked on the first surface, the color filter layer has a light-transmitting area and a non-light-transmitting area, the non-light-transmitting area surrounds the light-transmitting area, and the first direction and the second direction are perpendicular to each other; The thin film transistor covers the surface of the color filter layer facing away from the first substrate. Along the thickness direction of the liquid crystal display panel, the orthographic projection of the thin film transistor on the color filter layer is located in the non-light-transmitting area.

2. The liquid crystal display panel according to claim 1, characterized in that: The color filter layer includes a first passivation layer, the first passivation layer has a first surface, the first passivation layer has a first bump and a second bump, the first bump and the second bump are arranged in parallel, the first bump and the second bump are both convexly arranged on the first surface, and the first bump and the second bump are located in the non-light-transmitting area; The first substrate further includes a first electrode layer, and the first electrode layer is stacked on a surface of the plurality of pixel units facing away from the first substrate; The color filter layer further includes a second electrode layer, which is stacked on the first surface and covers the first bump and the second bump.

3. The liquid crystal display panel according to claim 2, characterized in that: The color filter layer further includes a second passivation layer, the second passivation layer covers the surface of the second electrode layer facing away from the first substrate, the second passivation layer is provided with a first deposition groove, the first deposition groove is located in the non-light-transmitting area, the first deposition groove includes a first sub-groove, a second sub-groove and a third sub-groove, the first sub-groove and the second sub-groove are respectively located on opposite sides of the third sub-groove, and the first sub-groove and the second sub-groove are both connected to the third sub-groove, the first convex block is embedded in the second passivation layer, along the thickness direction of the liquid crystal display panel, the orthographic projection of the first sub-groove on the first surface is at least partially overlapped with the orthographic projection of the first convex block on the first surface, and the first sub-groove extends to the second electrode layer; The thin film transistor comprises a first electrode, a second electrode and an active layer, the first electrode and the second electrode of the thin film transistor are respectively filled in the first sub-groove and the second sub-groove, and the active layer is filled in the third sub-groove; The second electrode layer is electrically connected to the first electrode of the thin film transistor.

4. The liquid crystal display panel according to claim 3, characterized in that: The thin film transistor comprises a gate and a gate insulating layer, the gate insulating layer is stacked on the surface of the second passivation layer facing away from the first substrate and covers the first electrode, the second electrode and the active layer, the gate insulating layer is provided with a first receiving groove, the second bump is embedded in the gate insulating layer, along the thickness direction of the liquid crystal display panel, the orthographic projection of the second bump on the first surface is located within the orthographic projection of the first receiving groove on the first surface, and the first receiving groove extends to the second electrode layer; The gate is received in the first receiving groove, and the gate is electrically connected to the second electrode layer.

5. The liquid crystal display panel according to claim 4, characterized in that: The color filter layer also includes a black matrix layer and a color resist layer unit, the black matrix layer is stacked on the first surface, the black matrix layer has an opening, the opening is located in the light-transmitting area, the color resist layer unit fills the opening and covers the surface of the black matrix layer facing away from the first substrate, and the first passivation layer is stacked on the surface of the color resist layer unit facing away from the first substrate.

6. The liquid crystal display panel according to claim 5, characterized in that: The first substrate further includes a plurality of scan lines and a plurality of data lines; The second passivation layer is provided with a second deposition groove, the second deposition groove extends along the second direction, the second deposition groove is located in the non-light-transmitting area, the second deposition grooves of the pixel units in the same column are interconnected to form a data line groove, and each of the data line grooves accommodates one data line; The gate insulating layer is provided with a second accommodating groove, the second accommodating groove extends along the first direction, the orthographic projection of the second accommodating groove on the color filter layer is located in the non-light-transmitting area, the second accommodating grooves of the pixel units in the same row are interconnected to form scan line grooves, and each of the scan line grooves accommodates one scan line; The plurality of scanning lines and the plurality of data lines cross to form a plurality of pixel regions, and the plurality of pixel units correspond to the plurality of pixel regions one by one.

7. The liquid crystal display panel according to claim 6, characterized in that: The first substrate comprises a first alignment layer, and the first alignment layer covers a surface of the first electrode layer facing away from the first substrate; The second substrate comprises a second substrate and a second alignment layer, the second substrate has a second surface, and the second alignment layer covers the second surface; The liquid crystal display panel also includes a plurality of support columns, which are supported between the first alignment layer and the second alignment layer. Along the thickness direction of the liquid crystal display panel, the orthographic projection of each support column on the color filter layer is located in the non-light-transmitting area.

8. A display device, characterized in that: It comprises a backlight module and a liquid crystal display panel as claimed in any one of claims 1 to 7, wherein along the thickness direction of the display device, the backlight module is located on a side of the second substrate facing away from the first substrate.

9. A method for preparing a liquid crystal display panel, characterized in that: The steps include: A first substrate is provided, wherein the first substrate comprises a first substrate, the first substrate has a first surface, a plurality of pixel units are formed on the first surface, the plurality of pixel units are arranged in a matrix, each of the pixel units comprises a color filter layer and a thin film transistor, the color filter layer has a light-transmitting area and a non-light-transmitting area, the non-light-transmitting area surrounds the light-transmitting area, and along the thickness direction of the liquid crystal display panel, the orthographic projection of the thin film transistor on the color filter layer is located in the non-light-transmitting area; forming a first electrode layer on a surface of the plurality of pixel units facing away from the first substrate; forming a first alignment layer on a surface of the first electrode layer facing away from the first substrate; Providing a second substrate, wherein the second substrate comprises a second substrate, the second substrate has a second surface, and a second alignment layer is formed on the second surface; The first substrate and the second substrate are aligned, a plurality of liquid crystal molecules and a plurality of support pillars are filled between the first alignment layer and the second alignment layer, and the first substrate and the second substrate are bonded together by using a sealant.

10. The method for preparing a liquid crystal display panel according to claim 9, characterized in that: The step of "providing a first substrate, the first substrate comprising a first substrate, the first substrate having a first surface, forming a plurality of pixel units on the first surface, the plurality of pixel units being arranged in a matrix, each of the pixel units comprising a color filter layer and a thin film transistor, the color filter layer having a light-transmitting area and a non-light-transmitting area, the non-light-transmitting area surrounding the light-transmitting area, and along the thickness direction of the liquid crystal display panel, the orthographic projection of the thin film transistor on the color filter layer is located in the non-light-transmitting area" comprises: forming a black matrix base layer on the first surface, and patterning the black matrix base layer to form a black matrix layer, wherein the black matrix layer has an opening; forming a color-resistance layer unit on a surface of the black matrix layer facing away from the first substrate, wherein the color-resistance layer unit fills the opening and covers the black matrix layer; forming a first passivation base layer on a surface of the color-resistance layer unit facing away from the first substrate, patterning the first passivation base layer to form a first passivation layer, wherein the first passivation layer has a first bump and a second bump; Forming a first electrode layer on a surface of the first passivation layer facing away from the first substrate, wherein the first electrode layer covers the first bump and the second bump; A second passivation base layer is formed on a surface of the first electrode layer facing away from the first substrate, and the second passivation base layer is patterned to form a second passivation layer, wherein the second passivation layer has a first deposition groove, wherein the first deposition groove comprises a first sub-groove, a second sub-groove and a third sub-groove, wherein the first sub-groove and the second sub-groove are respectively located at two opposite sides of the third sub-groove, and both the first sub-groove and the second sub-groove are connected to the third sub-groove; A thin film transistor is formed on the surface of the second passivation layer facing away from the first substrate, the thin film transistor includes a first electrode, a second electrode, an active layer, a gate insulating layer and a gate, the first electrode is accommodated in the first sub-groove, the second sub-groove is accommodated in the second sub-groove, the active layer is accommodated in the third sub-groove, a gate insulating layer is formed on the surface of the second passivation layer facing away from the first substrate, the gate insulating layer is patterned to form a first accommodating groove, and the gate is accommodated in the first accommodating groove.

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