Instruction execution method of digital signal processor and digital signal processor

Abstract

The present invention discloses an instruction execution method of a digital signal processor and a digital signal processor, the instruction execution method includes: obtaining a target instruction and a peripheral clock enable signal of a corresponding peripheral unit; determining the instruction type of the target instruction through the instruction structure of the target instruction and a preset instruction setting condition; determining the signal state of the peripheral clock enable signal; executing a priority processing strategy when the instruction type is a priority instruction and the signal state is an enable state, the priority processing strategy includes: sending a companion core start signal to a priority processing unit, and sending a main core start signal to a main processing unit to start the priority processing unit to load and process the target instruction, and the main processing unit simultaneously processes the remaining instructions in the instruction set through a multi-stage pipeline sequence. The instruction execution method of the embodiment of the present invention can improve the instruction priority, accelerate the operation and processing of proprietary instructions, thereby improving the response speed and the processing capacity of the digital signal processor.

Description

Technical Field

[0001] The present invention relates to the technical field of electronics, and in particular to an instruction execution method of a digital signal processor and a digital signal processor. Background Art

[0002] At present, the chips used in new energy vehicles have an increasing demand for high-speed processing of sampled data, especially for driving safety, which requires extremely high response time for high-speed signal acquisition operations. However, the existing DSP (digital signal processor) with instruction sets still uses standard multi-stage pipeline sequential execution when executing corresponding instructions. When processing special instructions that need to be responded to quickly, it is impossible to dynamically adjust the execution priority of the instruction set according to the current state of the chip, especially when it is necessary to efficiently prioritize the processing of real-time sampled signal data and corresponding data. It is impossible to respond to the execution of instructions efficiently. The action of the central processing unit (CPU) in processing key instructions is triggered based on an event. The event contains multiple instructions to complete this event action. If the CPU detects an event that needs to be executed first, it still executes the event sequentially by the CPU, and it needs to wait for the CPU to execute the previous instructions and load the event instructions. If the event executed at this time also needs to call related data, it is necessary to wait for the CPU to complete the data instruction before completing all events, and its execution efficiency is greatly reduced. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes an instruction execution method for a digital signal processor, which can improve the instruction priority, accelerate the operation and processing of proprietary instructions, thereby improving the response speed and the processing capability of the digital signal processor.

[0004] The invention also provides a digital signal processor, a control device and a computer-readable storage medium.

[0005] According to the instruction execution method of the digital signal processor of the first aspect of the present invention, the digital signal processor includes a main processing unit, a priority processing unit, a plurality of peripheral units, and an instruction storage unit, each of the peripheral units is connected to the instruction storage unit, the main processing unit and the priority processing unit, the instruction storage unit is connected to the main processing unit and the priority processing unit respectively, the main processing unit is used to sequentially process the instruction sets of the plurality of peripheral units through a multi-stage pipeline, and the instruction storage unit is used to store the instruction sets;

[0006] The instruction execution method of the digital signal processor comprises the following steps:

[0007] Acquire a target instruction and a peripheral clock enable signal of the peripheral unit corresponding to the target instruction, wherein the target instruction is one of the instruction sets;

[0008] Determining the instruction type of the target instruction through the instruction structure of the target instruction and the preset instruction setting condition, wherein the instruction type includes a common instruction and a priority instruction;

[0009] Determine a signal state of the peripheral clock enable signal, wherein the signal state includes an enabled state and a disabled state;

[0010] Determining an execution priority state of the target instruction according to the instruction type and the signal state, the execution priority state including a priority execution state and a normal execution state, and when the instruction type is the priority instruction and the signal state is an enabled state, the execution priority state is the priority execution state;

[0011] An instruction processing strategy is executed according to the execution priority state, the instruction processing strategy includes a priority processing strategy, and the priority processing strategy is executed when the execution priority state is the priority execution state. The priority processing strategy includes: sending a companion core start signal to the priority processing unit, and sending a main core start signal to the main processing unit to start the priority processing unit to load and process the target instruction, and the main processing unit simultaneously processes the remaining instructions in the instruction set in sequence through a multi-stage pipeline.

[0012] The instruction execution method of the digital signal processor according to the embodiment of the present invention has at least the following beneficial effects:

[0013] The existing digital signal processors with instruction sets still use standard multi-stage pipeline sequence execution when executing corresponding instructions. When processing special instructions that need to be responded to quickly, it is impossible to dynamically adjust the execution priority of the instruction set according to the current state of the chip. The instruction execution method of the embodiment of the present invention sets two independent processing units, and solidifies the instruction type through the instruction structure, divides the instructions into ordinary instructions and priority instructions, and determines whether to use the priority processing unit to prioritize the target instruction by determining the instruction type of the target instruction and the signal state of the peripheral clock enable signal of the peripheral unit corresponding to the target instruction. Therefore, when the digital signal processor processes instructions that need to respond quickly, the priority processing unit can be started for priority processing, the instruction priority can be improved, and the operation and processing of proprietary instructions can be accelerated, thereby improving the response speed and the processing capacity of the digital signal processor.

[0014] According to some embodiments of the present invention, determining the instruction type of the target instruction by using the instruction structure of the target instruction and a preset instruction setting condition comprises the following steps:

[0015] Reading the instruction flag of the target instruction and decoding it to obtain a decoding result, wherein the instruction structure of the target instruction includes the instruction flag and instruction data bits;

[0016] The decoding result is compared with the preset instruction setting condition. If the decoding result is the same as the preset instruction setting condition, the instruction type of the target instruction is confirmed as the priority instruction. If the decoding result is different from the preset instruction setting condition, the instruction type of the target instruction is confirmed as the ordinary instruction.

[0017] According to some embodiments of the present invention, the instruction flag bits are the first three bits of the instruction structure of the target instruction.

[0018] According to some embodiments of the present invention, the peripheral unit has an enable register and a clock enable register; the peripheral clock enable signal is obtained by the following steps:

[0019] Reading a peripheral enable signal and a clock enable signal of the peripheral unit corresponding to the target instruction, wherein the peripheral enable signal indicates a first operating state of the enable register, and the clock enable signal indicates a second operating state of the clock enable register;

[0020] The peripheral clock enable signal is determined according to the peripheral enable signal and the clock enable signal.

[0021] According to some embodiments of the present invention, the determining the signal state of the peripheral clock enable signal comprises the following steps:

[0022] Determining the first operating state of the peripheral enable signal and the second operating state of the clock enable signal;

[0023] If both the first operating state and the second operating state are enabled states, confirming the signal state of the peripheral clock enable signal as the enabled state;

[0024] If any one of the first operating state and the second operating state is a disabled state, the signal state of the peripheral clock enable signal is confirmed as a disabled state.

[0025] According to some embodiments of the present invention, the instruction processing strategy also includes a normal processing strategy, which is executed when the execution priority state is the normal execution state, and the normal processing strategy includes: sending the main core start signal to the main processing unit so that the main processing unit sequentially processes the instruction set through a multi-stage pipeline, and the instruction set includes the target instruction.

[0026] According to some embodiments of the present invention, when the common processing strategy is executed, the priority processing unit is in a disabled state.

[0027] A digital signal processor according to an embodiment of the second aspect of the present invention comprises:

[0028] Multiple peripheral units;

[0029] A main processing unit connected to each of the peripheral units, the main processing unit being used to sequentially process instruction sets of the plurality of peripheral units through a multi-stage pipeline;

[0030] A priority processing unit connected to each of the peripheral units, the priority processing unit being used to independently process instructions;

[0031] an instruction storage unit, connected to each of the peripheral units, the main processing unit and the priority processing unit, respectively, and the instruction storage unit is used to store the instruction set;

[0032] The detection unit is connected to each of the peripheral units, the main processing unit, the priority processing unit, and the instruction storage unit respectively, and the detection unit is used to execute the instruction execution method of the digital signal processor as described in the first aspect embodiment above.

[0033] The digital signal processor according to the embodiment of the present invention has at least the following beneficial effects:

[0034] The existing digital signal processors with instruction sets still use standard multi-stage pipeline sequence execution when executing corresponding instructions. When processing special instructions that need to be responded to quickly, it is impossible to dynamically adjust the execution priority of the instruction set according to the current state of the chip. The digital signal processor of the embodiment of the present invention sets two independent processing units, solidifies the instruction type through the instruction structure, divides the instructions into ordinary instructions and priority instructions, and determines the instruction type of the target instruction and the signal state of the peripheral clock enable signal of the peripheral unit corresponding to the target instruction through the detection unit to determine whether to use the priority processing unit to prioritize the target instruction, so that when the digital signal processor processes instructions that need to respond quickly, the priority processing unit can be started for priority processing, the instruction priority can be improved, and the operation and processing of proprietary instructions can be accelerated, thereby improving the response speed and the processing capacity of the digital signal processor.

[0035] According to the third aspect of the present invention, the control device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, and the processor implements the instruction execution method of the digital signal processor as described in the first aspect of the embodiment when executing the computer program. Since the control device adopts all the technical solutions of the instruction execution method of the digital signal processor of the above embodiment, it has at least all the beneficial effects brought by the technical solutions of the above embodiment.

[0036] According to the computer-readable storage medium of the fourth aspect embodiment of the present invention, computer-executable instructions are stored, and the computer-executable instructions are used to execute the instruction execution method of the digital signal processor as described in the first aspect embodiment. Since the computer-readable storage medium adopts all the technical solutions of the instruction execution method of the digital signal processor of the above embodiment, it at least has all the beneficial effects brought by the technical solutions of the above embodiment.

[0037] Other features and advantages of the present invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0039] Figure 1 is a partial system block diagram of a digital signal processor according to an embodiment of the present invention;

[0040] Figure 2 is a partial system block diagram of a digital signal processor according to another embodiment of the present invention;

[0041] Figure 3 is a schematic diagram of an instruction structure of an embodiment of the present invention;

[0042] Figure 4 The invention is a flowchart of an instruction execution method of a digital signal processor according to an embodiment of the present invention.

[0043] Reference numerals:

[0044] Main processing unit 100;

[0045] Priority processing unit 200;

[0046] Peripheral unit 300, ADC sampling unit 310, analog input multiplexer 311, analog-to-digital converter 312, enhanced peripheral 321, first 32-bit peripheral bus 322, serial communication peripheral 331, second 32-bit peripheral bus 332, port multiplexer 340;

[0047] Memory 400, instruction storage unit 410, key operation function storage unit 420;

[0048] Detection unit 500. DETAILED DESCRIPTION

[0049] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0050] In the description of the present invention, if there is a description of first, second, etc., it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0051] In the description of the present invention, it should be understood that descriptions involving orientation, such as orientation or positional relationship indicated as up, down, etc., are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0052] In the description of the present invention, it should be noted that, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific content of the technical solution.

[0053] The following will be combined Figures 1 to 4 The instruction execution method of the digital signal processor according to the embodiment of the present invention is described clearly and completely. Obviously, the embodiment described below is only a part of the embodiments of the present invention, not all the embodiments.

[0054] According to the instruction execution method of the digital signal processor of the first aspect of the present invention, the digital signal processor includes a main processing unit 100, a priority processing unit 200, a plurality of peripheral units 300, and an instruction storage unit 410, each peripheral unit 300 is connected to the instruction storage unit 410, the main processing unit 100 and the priority processing unit 200, the instruction storage unit 410 is connected to the main processing unit 100 and the priority processing unit 200, respectively, the main processing unit 100 is used to sequentially process the instruction sets of the plurality of peripheral units 300 through a multi-stage pipeline, and the instruction storage unit 410 is used to store the instruction set;

[0055] The instruction execution method of the digital signal processor comprises the following steps:

[0056] Acquire a target instruction and a peripheral clock enable signal of the peripheral unit 300 corresponding to the target instruction, the target instruction being one of the instruction sets;

[0057] Determining the instruction type of the target instruction through the instruction structure of the target instruction and the preset instruction setting condition, the instruction type includes a common instruction and a priority instruction;

[0058] Determine a signal state of a peripheral clock enable signal, the signal state including an enabled state and a disabled state;

[0059] Determine the execution priority state of the target instruction according to the instruction type and the signal state, the execution priority state includes a priority execution state and a normal execution state, and when the instruction type is a priority instruction and the signal state is an enabled state, the execution priority state is a priority execution state;

[0060] The instruction processing strategy is executed according to the execution priority state. The instruction processing strategy includes a priority processing strategy. The priority processing strategy is executed when the execution priority state is the priority execution state. The priority processing strategy includes: sending a companion core start signal to the priority processing unit 200, and sending a main core start signal to the main processing unit 100 to start the priority processing unit 200 to load and process the target instruction, and the main processing unit 100 simultaneously processes the remaining instructions in the instruction set in sequence through a multi-stage pipeline.

[0061] The peripheral unit 300 includes two types of instructions that need to be processed first and instructions that do not need to be processed first. The type of the current execution event can be determined by loading the execution program through the built-in register. The priority processing unit 200 is essentially triggered based on the event. In some embodiments, for applications in the field of new energy vehicles, the chip has a relatively high demand for high-speed processing of sampled data, especially for driving safety. The high-speed acquisition operation response time requirement is extremely high, such as throttle sampling, brake sampling and other data monitoring instructions. The instruction flag bit in the instruction structure of such instructions can be pre-set as the instruction type identifier of the priority instruction. Specifically, the peripheral unit 300 that needs to process the instruction first includes but is not limited to an ADC sampling unit 310, an enhanced peripheral 321 and a serial communication peripheral 331, wherein the ADC sampling unit 310 includes an analog input multiplexer 311 and an analog-to-digital converter 312, and the analog-to-digital converter 312 is connected to the priority processing unit 200. The enhanced peripheral 321 is connected to the priority processing unit 200 via a first 32-bit peripheral bus 322. The serial communication peripheral 331 is connected to the main processing unit 100 via a second 32-bit peripheral bus 332. The enhanced peripheral 321 and the serial communication peripheral 331 are connected to the external device through the port multiplexer 340. It should be noted that the specific circuit structure and working principle of the ADC sampling unit 310, the enhanced peripheral 321 and the serial communication peripheral 331 are prior arts known to those skilled in the art and will not be described in detail here.

[0062] In the embodiment of the present invention, the instruction structure of the target instruction includes an instruction flag bit and an instruction data bit, wherein the instruction flag bit is used to determine the instruction type of the target instruction, and the instruction flag bits of different instructions are solidified when setting the instruction structure, and the instruction flag bits of the instructions that need to be processed first are set according to the preset instruction setting conditions, so as to distinguish the instructions into two instruction types: ordinary instructions and priority instructions. After reading the instruction flag bit of the target instruction, the decoding circuit is used to decode to obtain the decoding result, and the decoding result is compared with the preset instruction setting conditions. If the decoding result is the same as the preset instruction setting conditions, the instruction type of the target instruction is confirmed as the priority instruction, and if the decoding result is different from the preset instruction setting conditions, the instruction type of the target instruction is confirmed as the ordinary instruction. In some embodiments, the instruction structure is a 32-bit instruction, and the first three bits can be used as the instruction flag bit, and the latter can be used as the instruction data bit. When determining the instruction type of the target instruction, only the first three bits of the target instruction need to be read to confirm, and the response time is fast.

[0063] The existing digital signal processor uses a Harvard bus-based architecture to implement instruction execution and signal acquisition. It has a proprietary instruction bus to obtain instructions. The core (central processing unit CPU + floating point unit FPU) obtains instructions from the memory 400 through the instruction bus, loads them into the multi-stage pipeline, and performs actions such as instruction acquisition, decoding, storage and execution. Each instruction needs to run the entire process of the pipeline before it can be executed, and it is impossible to implement high-priority instructions with priority execution. In the embodiment of the present invention, an independent priority processing unit 200 is added on the basis of the original main processing unit 100. The priority processing unit 200 has a clock system, an instruction set acquisition pipeline and a proprietary register independent of the main processing unit 100, and can independently execute a proprietary instruction set: the instruction set is acquired, decoded, stored, executed and written into the result register, and the instructions that need to be processed first will be pre-stored in the proprietary execution ROM of the priority processing unit 200, and the corresponding execution instructions can be efficiently retrieved. After startup, the priority processing unit 200 is not controlled by the main processing unit 100, but directly obtains the target instruction through the instruction bus and loads the target instruction into the priority processing unit 200. The main processing unit 100 and the priority processing unit 200 are synchronous and independent, and can execute instructions synchronously. It should be noted that if there are multiple instructions that need to be executed preferentially, the priority processing unit 200 also loads the corresponding instructions through the pipeline.

[0064] The priority processing unit 200 is essentially triggered based on an event. Only when the digital signal processor executes an event that needs to be processed with priority (i.e., the clock of the relevant peripheral unit 300 is started, the corresponding operation is performed, and the key peripheral unit 300 is detected to be executed), the main processing unit 100 detects the target instruction corresponding to the corresponding event and starts the priority processing unit 200 after arbitration. The priority processing unit 200 directly obtains the target instruction through the instruction bus, loads the target instruction into the instruction set acquisition pipeline of the priority processing unit 200, performs instruction acquisition, decoding, storage, execution and writing, and controls the corresponding peripheral unit 300 to realize the priority execution of special instructions. At the same time, the main processing unit 100 synchronously loads the next instruction, and can synchronously execute subsequent instructions.

[0065] The execution priority state of the target instruction is finally determined by determining the instruction type of the target instruction and the signal state of the peripheral clock enable signal of the peripheral unit 300 corresponding to the target instruction. When the instruction type is a priority instruction and the signal state is an enable state, the execution priority state of the target instruction is a priority execution state, otherwise the execution priority state of the target instruction is a normal execution state. By analyzing the instruction type of the instruction and the signal state of the peripheral clock enable signal of the peripheral unit 300 corresponding to the instruction, the priority of the instruction is improved, and the priority processing unit 200 will load the instruction that needs to be executed first to perform the corresponding operation. After completing the instruction, the result and execution data will be written into the proprietary memory of the priority processing unit 200, and the main processing unit 100 will continue to process the remaining instructions in the instruction set normally through the multi-stage pipeline sequence, so that when the digital signal processor processes the instruction that needs a fast response, the priority processing unit 200 can be started for priority processing, the instruction priority can be improved, and the operation and processing of the proprietary instruction can be accelerated, thereby improving the response speed and the processing capacity of the digital signal processor.

[0066] According to the instruction execution method of the digital signal processor of the embodiment of the present invention, the existing digital signal processor with an instruction set still uses the standard multi-stage pipeline sequence execution when executing the corresponding instructions. When processing special instructions that need to be responded to and executed quickly, it is impossible to dynamically adjust the execution priority of the instruction set according to the current state of the chip. The instruction execution method of the embodiment of the present invention sets two independent processing units, and solidifies the instruction type through the instruction structure, divides the instructions into ordinary instructions and priority instructions, and determines whether to use the priority processing unit 200 to prioritize the target instruction by determining the instruction type of the target instruction and the signal state of the peripheral clock enable signal of the peripheral unit 300 corresponding to the target instruction, so that when the digital signal processor processes instructions that need to respond quickly, the priority processing unit 200 can be started for priority processing, the instruction priority can be improved, and the operation and processing of proprietary instructions can be accelerated, thereby improving the response speed and the processing capacity of the digital signal processor.

[0067] In some embodiments of the present invention, reference Figure 3 , determining the instruction type of the target instruction through the instruction structure of the target instruction and the preset instruction setting condition, including the following steps:

[0068] Reading the instruction flag of the target instruction and decoding it to obtain a decoding result, the instruction structure of the target instruction includes an instruction flag and an instruction data bit;

[0069] Compare the decoding result with the preset instruction setting condition. If the decoding result is the same as the preset instruction setting condition, the instruction type of the target instruction is confirmed as a priority instruction. If the decoding result is different from the preset instruction setting condition, the instruction type of the target instruction is confirmed as a common instruction.

[0070] like Figure 3 As shown, the target instruction is a 32-bit instruction, the first three bits are instruction flag bits, and the rest are instruction data bits. Priority instructions and ordinary instructions are distinguished by presetting instruction flag bits. In some embodiments, priority instructions include but are not limited to operation instructions and configuration instructions. Specifically, the instruction flag bit of the operation instruction can be set to 101, and the instruction flag bit of the configuration instruction can be set to 110. The preset instruction setting condition can be determined according to different priority instruction types, not just one. As long as it is detected that the instruction flag bit meets one of the preset instruction setting conditions, the instruction type of the target instruction can be confirmed as a priority instruction.

[0071] It should be noted that the specific value of the above instruction flag is only an embodiment and can be changed according to actual conditions, and cannot be regarded as a limitation of the present invention.

[0072] In some embodiments of the present invention, reference Figure 3 , the instruction flag is the first three bits of the instruction structure of the target instruction. In some embodiments, the instruction structure is a 32-bit instruction, and after reading the instruction flag of the target instruction, the instruction is decoded by a decoding circuit to obtain a decoding result, and then the decoding result is compared with the preset instruction setting conditions. When determining the instruction type of the target instruction, only the first three bits of the target instruction need to be read to confirm, and the response time is fast. It should be noted that the specific position and specific number of bits of the instruction flag can be changed according to actual conditions, and cannot be regarded as a limitation of the present invention.

[0073] In some embodiments of the present invention, reference Figure 2 , the peripheral unit 300 has an enable register and a clock enable register; the peripheral clock enable signal is obtained by the following steps:

[0074] Reading a peripheral enable signal and a clock enable signal of the peripheral unit 300 corresponding to the target instruction, wherein the peripheral enable signal indicates a first operating state of the enable register, and the clock enable signal indicates a second operating state of the clock enable register;

[0075] A peripheral clock enable signal is determined according to the peripheral enable signal and the clock enable signal.

[0076] Each peripheral unit 300 is configured with an enable register and a clock enable register. When the peripheral unit 300 is enabled and the clock of the peripheral unit 300 is enabled, it indicates that the peripheral unit 300 is operating normally. In the embodiment of the present invention, the normal operation of the peripheral unit 300 is used as one of the conditions for determining the execution priority state of the target instruction, that is, the signal state of the peripheral clock enable signal is an enabled state.

[0077] By reading the peripheral enable signal corresponding to the enable register and the clock enable signal corresponding to the clock enable register, the operation status of the enable register and the clock enable register is confirmed. If both the peripheral enable signal and the clock enable signal are in the enabled state, the peripheral clock enable signal of the peripheral unit 300 is in the enabled state, otherwise it is in the disabled state. Specifically, the enable register / clock enable register outputs 1 (i.e., the peripheral enable signal / clock enable signal is 1) to indicate the enabled state, and the enable register / clock enable register outputs 0 (i.e., the peripheral enable signal / clock enable signal is 0) to indicate the disabled state. If both the peripheral enable signal and the clock enable signal are 1, the signal state of the peripheral clock enable signal is the enabled state; if either the peripheral enable signal or the clock enable signal is 0, the signal state of the peripheral clock enable signal is the disabled state.

[0078] In some embodiments of the present invention, determining the signal state of a peripheral clock enable signal comprises the following steps:

[0079] Determining a first operating state of a peripheral enable signal and a second operating state of a clock enable signal;

[0080] If both the first operating state and the second operating state are enabled states, confirming the signal state of the peripheral clock enable signal as the enabled state;

[0081] If any one of the first operating state and the second operating state is a disabled state, the signal state of the peripheral clock enable signal is confirmed as a disabled state.

[0082] When the peripheral unit 300 is enabled and the clock of the peripheral unit 300 is enabled, it indicates that the peripheral unit 300 is operating normally. In the embodiment of the present invention, the normal operation of the peripheral unit 300 is used as one of the conditions for determining the execution priority state of the target instruction, that is, the signal state of the peripheral clock enable signal is the enabled state. Specifically, the enable register / clock enable register outputs 1 (that is, the peripheral enable signal / clock enable signal is 1) to indicate the enabled state, and the enable register / clock enable register outputs 0 (that is, the peripheral enable signal / clock enable signal is 0) to indicate the disabled state. If both the peripheral enable signal and the clock enable signal are 1, the signal state of the peripheral clock enable signal is the enabled state; if either the peripheral enable signal or the clock enable signal is 0, the signal state of the peripheral clock enable signal is the disabled state.

[0083] After confirming the instruction type of the target instruction in the above steps, an instruction enable signal is generated. The instruction enable signal is 1, indicating that the instruction type of the target instruction is a priority instruction, and the instruction enable signal is 0, indicating that the instruction type of the target instruction is a normal instruction. Specifically, the signal state of the peripheral clock enable signal and the execution priority state of the target instruction can be confirmed by an AND gate. The first input of the AND gate is used to input the instruction enable signal, the second input is connected to the enable register, and the third input is connected to the clock enable register. If the first input, the second input, and the third input are all input 1, the output of the AND gate outputs 1 (that is, the execution priority state of the target instruction is the priority execution state), and if any one of the first input, the second input, and the third input is 0, the output of the AND gate outputs 0 (that is, the execution priority state of the target instruction is the normal execution state).

[0084] In some embodiments of the present invention, reference Figure 1 , the instruction processing strategy also includes a normal processing strategy. When the execution priority state is the normal execution state, the normal processing strategy is executed. The normal processing strategy includes: sending a main core start signal to the main processing unit 100, so that the main processing unit 100 sequentially processes the instruction set through a multi-stage pipeline, and the instruction set includes the target instruction. When the execution priority state of the target instruction is the normal execution state, it means that the target instruction does not need to be processed in priority. The instruction set including the target instruction is still processed in the original order through the main processing unit 100 through the multi-stage pipeline. The priority processing unit 200 is only used to process instructions with an execution priority state of the priority execution state. When the instruction needs to be processed in priority, it is loaded into the priority processing unit 200 for priority processing. When the instruction does not need to be processed in priority, the normal processing process of the instruction set can also be guaranteed.

[0085] In some embodiments of the present invention, reference Figure 1 When executing the normal processing strategy, the priority processing unit 200 is in a disabled state. When executing the normal processing strategy, the priority processing unit 200 is in a disabled state, that is, a standby state, and is only started when a priority processing instruction is required, which can reduce power consumption.

[0086] In order to better demonstrate the advantages of the instruction execution method of the digital signal processor according to the embodiment of the present invention, a specific embodiment is described in detail below.

[0087] The instruction execution method of the embodiment of the present invention is executed by the detection unit 500, and the types of target instructions include but are not limited to operation instructions and configuration instructions, wherein the operation instruction is to accelerate the operation by directly calling the operation function in the key operation function storage unit 420; the configuration instruction is that the priority processing unit 200 directly loads the configuration instruction, and outputs the storage data by loading, acquiring, decoding and executing the configuration instruction. It should be noted that the specific type of the target instruction needs to be determined according to the actual situation, and the types of target instructions corresponding to different peripheral units 300 may be the same or different, which cannot be regarded as a limitation of the present invention, and the operation instruction and the configuration instruction are two independent instructions. The processing order of these two instructions is determined according to the order of the pipeline of the priority processing unit 200, and whichever is loaded first will be executed first.

[0088] Taking the ADC sampling unit 310 for sampling relevant data as an example, the ADC sampling unit 310 is a peripheral unit 300 that needs to be processed preferentially. When the ADC sampling unit 310 performs relevant data sampling, it is necessary to configure the ADC clock and enable the ADC clock. At this time, the detection unit 500 obtains the sampling instruction and sampling window configuration instruction of the ADC sampling unit 310 and the peripheral clock enable signal of the ADC sampling unit 310, and reads the instruction flag bits of the sampling instruction and the sampling window configuration instruction and decodes them to obtain the decoding result. If the decoding result is the same as the preset instruction setting condition, and the peripheral clock enable signal of the ADC sampling unit 310 is in the enabled state, a companion core start signal is sent to the priority processing unit 200, and a main core start signal is sent to the main processing unit 100, so as to start the priority processing unit 200 to load and process the sampling instruction and the sampling window configuration instruction, and the main processing unit 100 simultaneously processes the remaining instructions in the instruction set through a multi-stage pipeline sequence.

[0089] Since the ADC sampling unit 310 needs to be configured before sampling, the sampling window configuration instruction belongs to the configuration instruction, and the sampling instruction belongs to the operation instruction. The process of the priority processing unit 200 loading and processing the sampling instruction and the sampling window configuration instruction includes: the priority processing unit 200 first loads the sampling window configuration instruction, and outputs the sampling window configuration instruction to the sampling window configuration register of the ADC sampling unit 310 after instruction decoding to configure the sampling window of the ADC sampling unit 310. After completing the configuration of the sampling window, the sampling instruction is loaded, and the operation function in the key operation function storage unit 420 is called to accelerate the operation to obtain the operation result.

[0090] It should be noted that the above is only one embodiment of the ADC sampling unit 310. The basic principles and working processes of the enhanced peripherals 321 and the serial communication peripherals 331 mentioned in the embodiments of the present invention are prior arts known to those skilled in the art. The process of instruction execution can refer to the embodiment of the ADC sampling unit 310 and will not be repeated here.

[0091] The digital signal processor according to the second embodiment of the present invention includes a plurality of peripheral units 300 , a main processing unit 100 , a priority processing unit 200 , an instruction storage unit 410 , and a detection unit 500 .

[0092] A plurality of peripheral units 300;

[0093] A main processing unit 100 is connected to each peripheral unit 300, and the main processing unit 100 is used to sequentially process instruction sets of multiple peripheral units 300 through a multi-stage pipeline;

[0094] A priority processing unit 200 is connected to each peripheral unit 300, and the priority processing unit 200 is used to independently process instructions;

[0095] An instruction storage unit 410, connected to each peripheral unit 300, the main processing unit 100 and the priority processing unit 200, respectively, and the instruction storage unit 410 is used to store an instruction set;

[0096] The detection unit 500 is respectively connected to each peripheral unit 300, the main processing unit 100, the priority processing unit 200, and the instruction storage unit 410. The detection unit 500 is used to execute the instruction execution method of the digital signal processor of the first embodiment mentioned above.

[0097] The peripheral unit 300 includes two types of instructions that need to be processed first and instructions that do not need to be processed first. In some embodiments, for applications in the field of new energy vehicles, the chip has a relatively high demand for high-speed processing of sampled data, especially for driving safety. The high-speed acquisition operation response time requirements are extremely high, such as instructions for data monitoring such as throttle sampling and brake sampling. The instruction flag bit in the instruction structure of such instructions can be pre-set as an instruction type identifier for priority instructions. Specifically, the peripheral unit 300 that needs to process instructions first includes but is not limited to an ADC sampling unit 310, an enhanced peripheral 321, and a serial communication peripheral 331, wherein the ADC sampling unit 310 includes an analog input multiplexer 311 and an analog-to-digital converter 312, and the analog-to-digital converter 312 is connected to the priority processing unit 200. The enhanced peripheral 321 is connected to the priority processing unit 200 via a first 32-bit peripheral bus 322. The serial communication peripheral 331 is connected to the main processing unit 100 via a second 32-bit peripheral bus 332. The enhanced peripheral 321 and the serial communication peripheral 331 are connected to the external device through the port multiplexer 340. It should be noted that the specific circuit structure and working principle of the ADC sampling unit 310, the enhanced peripheral 321 and the serial communication peripheral 331 are prior arts known to those skilled in the art and will not be described in detail here.

[0098] Each peripheral unit 300 is configured with an enable register and a clock enable register. When the peripheral unit 300 is enabled and the clock of the peripheral unit 300 is enabled, it indicates that the peripheral unit 300 is operating normally. In the embodiment of the present invention, the normal operation of the peripheral unit 300 is used as one of the conditions for determining the execution priority status of the target instruction, that is, the enable register and the clock enable register are both in the enabled state.

[0099] In the embodiment of the present invention, the instruction structure of the target instruction includes an instruction flag bit and an instruction data bit, wherein the instruction flag bit is used to determine the instruction type of the target instruction, and the instruction flag bits of different instructions are solidified when setting the instruction structure, and the instruction flag bits of the instructions that need to be processed first are set according to the preset instruction setting conditions, so as to distinguish the instructions into two instruction types: ordinary instructions and priority instructions. After reading the instruction flag bit of the target instruction, the decoding circuit is used to decode to obtain the decoding result, and the decoding result is compared with the preset instruction setting conditions. If the decoding result is the same as the preset instruction setting conditions, the instruction type of the target instruction is confirmed as the priority instruction, and if the decoding result is different from the preset instruction setting conditions, the instruction type of the target instruction is confirmed as the ordinary instruction. In some embodiments, the instruction structure is a 32-bit instruction, and the first three bits can be used as the instruction flag bit, and the latter can be used as the instruction data bit. When determining the instruction type of the target instruction, only the first three bits of the target instruction need to be read to confirm, and the response time is fast.

[0100] The types of target instructions include but are not limited to operation instructions and configuration instructions, wherein the operation instruction is to accelerate the operation by directly calling the operation function in the key operation function storage unit 420; the configuration instruction is to directly load the configuration instruction by the priority processing unit 200, and output the storage data by loading, acquiring, decoding and executing the configuration instruction. Figure 1 The memory 400 of the embodiment of the present invention includes an instruction storage unit 410 and a key operation function storage unit 420.

[0101] The existing digital signal processor uses an architecture based on the improved Harvard bus to implement instruction execution and signal acquisition. The core (central processing unit CPU + floating point unit FPU) obtains instructions from the memory 400, loads them into the multi-stage pipeline, and performs actions such as instruction acquisition, decoding, storage and execution. Each instruction needs to run the entire process of the pipeline before it can be executed, and it is impossible to implement high-priority instructions with priority execution. In the embodiment of the present invention, an independent priority processing unit 200 is added on the basis of the original main processing unit 100. The priority processing unit 200 has a clock system, an instruction set acquisition pipeline and a proprietary register independent of the main processing unit 100, and can independently execute a proprietary instruction set: the instruction set is acquired, decoded, stored, executed and written into the result register, and the instructions that need to be processed first will be pre-stored in the proprietary execution ROM of the priority processing unit 200, and the corresponding execution instructions can be efficiently retrieved. The main processing unit 100 and the priority processing unit 200 are synchronous and independent, and can execute instructions synchronously. It should be noted that if there are multiple instructions that need to be executed first, the priority processing unit 200 also loads the corresponding instructions through the pipeline.

[0102] The execution priority state of the target instruction is finally determined by determining the instruction type of the target instruction and the signal state of the peripheral clock enable signal of the peripheral unit 300 corresponding to the target instruction. When the instruction type is a priority instruction and the signal state is an enable state, the execution priority state of the target instruction is a priority execution state, otherwise the execution priority state of the target instruction is a normal execution state. By analyzing the instruction type of the instruction and the signal state of the peripheral clock enable signal of the peripheral unit 300 corresponding to the instruction, the priority of the instruction is improved, and the priority processing unit 200 will load the instruction that needs to be executed first to perform the corresponding operation. After completing the instruction, the result and execution data will be written into the proprietary memory of the priority processing unit 200, and the main processing unit 100 will continue to process the remaining instructions in the instruction set normally through the multi-stage pipeline sequence, so that when the digital signal processor processes the instruction that needs a fast response, the priority processing unit 200 can be started for priority processing, the instruction priority can be improved, and the operation and processing of the proprietary instruction can be accelerated, thereby improving the response speed and the processing capacity of the digital signal processor.

[0103] According to the digital signal processor of the embodiment of the present invention, the existing digital signal processor with an instruction set still uses a standard multi-stage pipeline sequence to execute the corresponding instructions. When processing special instructions that need to be responded to quickly, it is impossible to dynamically adjust the execution priority of the instruction set according to the current state of the chip. The digital signal processor of the embodiment of the present invention sets two independent processing units, solidifies the instruction type through the instruction structure, divides the instructions into ordinary instructions and priority instructions, and determines the instruction type of the target instruction and the signal state of the peripheral clock enable signal of the peripheral unit 300 corresponding to the target instruction through the detection unit 500 to determine whether to use the priority processing unit 200 to prioritize the target instruction, so that when the digital signal processor processes instructions that need to respond quickly, the priority processing unit 200 can be started for priority processing, improve the instruction priority, and accelerate the operation and processing of proprietary instructions, thereby improving the response speed and the processing capacity of the digital signal processor.

[0104] In addition, the third aspect of the present invention also provides a control device, which includes: a memory, a processor, and a computer program stored in the memory and executable on the processor. The processor and the memory may be connected via a bus or other means.

[0105] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0106] The non-transitory software program and instructions required to implement the instruction execution method of the digital signal processor in the above embodiment are stored in the memory, and when executed by the processor, the instruction execution method of the digital signal processor in the above embodiment is executed.

[0107] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0108] In addition, the fourth aspect embodiment of the present invention also provides a computer-readable storage medium, which stores computer-executable instructions, and the computer-executable instructions are executed by a processor or controller, for example, by a processor of the above-mentioned control device, so that the above-mentioned processor can execute the instruction execution method of the digital signal processor in the above-mentioned embodiment.

[0109] It will be appreciated by those skilled in the art that all or some of the steps and systems in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0110] The embodiments of the present invention are described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present invention.

Claims

1. A method for executing instructions of a digital signal processor, characterized in that: The digital signal processor comprises a main processing unit, a priority processing unit, a plurality of peripheral units, and an instruction storage unit, each of the peripheral units is connected to the instruction storage unit, the main processing unit and the priority processing unit, the instruction storage unit is connected to the main processing unit and the priority processing unit respectively, the main processing unit is used to sequentially process the instruction sets of the plurality of peripheral units through a multi-stage pipeline, and the instruction storage unit is used to store the instruction sets; The instruction execution method of the digital signal processor comprises the following steps: Acquire a target instruction and a peripheral clock enable signal of the peripheral unit corresponding to the target instruction, wherein the target instruction is one of the instruction sets, and the instruction structure of the target instruction includes an instruction flag bit and an instruction data bit; The instruction type of the target instruction is determined by the instruction structure of the target instruction and the preset instruction setting condition, and the instruction type includes a common instruction and a priority instruction; the instruction type of the target instruction is determined by the instruction structure of the target instruction and the preset instruction setting condition, including the following steps: reading the instruction flag of the target instruction and decoding it to obtain a decoding result; comparing the decoding result with the preset instruction setting condition, if the decoding result is the same as the preset instruction setting condition, confirming the instruction type of the target instruction as the priority instruction, if the decoding result is different from the preset instruction setting condition, confirming the instruction type of the target instruction as the common instruction; Determine a signal state of the peripheral clock enable signal, wherein the signal state includes an enabled state and a disabled state; Determine the execution priority state of the target instruction according to the instruction type and the signal state, the execution priority state includes a priority execution state and a normal execution state, when the instruction type is the priority instruction and the signal state is an enabled state, the execution priority state is the priority execution state, otherwise, the execution priority state is the normal execution state; An instruction processing strategy is executed according to the execution priority state, and the instruction processing strategy includes a priority processing strategy and a normal processing strategy. The priority processing strategy is executed when the execution priority state is the priority execution state, and the priority processing strategy includes: sending a companion core startup signal to the priority processing unit, and sending a main core startup signal to the main processing unit, so as to start the priority processing unit to load and process the target instruction, and the main processing unit simultaneously processes the remaining instructions in the instruction set through a multi-stage pipeline sequence; the normal processing strategy is executed when the execution priority state is the normal execution state, and the normal processing strategy includes: sending the main core startup signal to the main processing unit, so that the main processing unit processes the instruction set through a multi-stage pipeline sequence, and the instruction set contains the target instruction.

2. The instruction execution method of a digital signal processor according to claim 1, characterized in that: The instruction flag bits are the first three bits of the instruction structure of the target instruction.

3. The instruction execution method of a digital signal processor according to claim 1, characterized in that: The peripheral unit has an enable register and a clock enable register; the peripheral clock enable signal is obtained by the following steps: Reading a peripheral enable signal and a clock enable signal of the peripheral unit corresponding to the target instruction, wherein the peripheral enable signal indicates a first operating state of the enable register, and the clock enable signal indicates a second operating state of the clock enable register; The peripheral clock enable signal is determined according to the peripheral enable signal and the clock enable signal.

4. The instruction execution method of a digital signal processor according to claim 3, characterized in that: Determining the signal state of the peripheral clock enable signal comprises the following steps: Determining the first operating state of the peripheral enable signal and the second operating state of the clock enable signal; If both the first operating state and the second operating state are enabled states, confirming the signal state of the peripheral clock enable signal as the enabled state; If any one of the first operating state and the second operating state is a disabled state, the signal state of the peripheral clock enable signal is confirmed as a disabled state.

5. The instruction execution method of a digital signal processor according to claim 1, characterized in that: When the common processing strategy is executed, the priority processing unit is in a disabled state.

6. A digital signal processor, characterized in that: include: Multiple peripheral units; A main processing unit connected to each of the peripheral units, the main processing unit being used to sequentially process instruction sets of the plurality of peripheral units through a multi-stage pipeline; A priority processing unit connected to each of the peripheral units, the priority processing unit being used to independently process instructions; an instruction storage unit, connected to each of the peripheral units, the main processing unit and the priority processing unit, respectively, and the instruction storage unit is used to store the instruction set; A detection unit is connected to each of the peripheral units, the main processing unit, the priority processing unit, and the instruction storage unit respectively, and the detection unit is used to execute the instruction execution method of the digital signal processor as described in any one of claims 1 to 5.

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