Method and system for injecting and writing data

Abstract

The invention provides a method and system for injecting and writing data, and relates to the technical field of injected and written data caching, and the method for injecting and writing data comprises the steps that when an input / output block receives at least one instruction sent by an input / output device and / or a processing unit, the at least one instruction is sent to the input / output device and / or the processing unit; temporarily storing the instruction in a queue unit of a buffer; and an arbiter in the input / output block calls an instruction from the queue unit, judges the attribute of the instruction, and executes cache processing according to the attribute of the instruction. Moreover, the system for injecting and writing data comprises an input / output block, at least two processing units, a system memory, a network interface and an input / output device, each processor and the peripheral device are enabled to jointly communicate with a specific input / output block, and the efficiency of the system for improving the asymmetry of the peripheral speed is achieved.

Description

Technical Field

[0001] The present invention provides a method and system for injecting and writing data, and relates to the technical field of injecting and writing data, and in particular to the technical field of injecting and writing data high-speed cache. Background Art

[0002] Caches increase system performance because when a processor accesses a data element at a specific address, it has a high probability of accessing a data element at a neighboring address. Caches usually follow certain rules when storing or invalidating data. For example, many processors follow an allocate-on-write rule, which indicates that cache lines corresponding to memory locations written by the processor will be stored in the cache. A common coherence protocol is the MOESI (Modified Owned Exclusive Shared Invalid) protocol. According to this protocol, each cache line includes a status bit to indicate the MOESI state of the cache line. These states include indicating that the cache line is modified (Modified; M), the cache line is exclusive (Exclusive; E) or shared (Shared; S), or the cache line is invalid (Invalid; I). The Owned (Owned; O) state indicates that the cache line in the cache has been modified, the cache can share a copy with other caches, and the data in memory is stale. However, the processor operation process needs to constantly change the state of the cache row, which obviously reduces the performance of the processor. Therefore, a method and processor that can reduce the main memory access demand to improve system performance are necessary means to solve the known shortcomings. Summary of the invention

[0003] The present invention provides a method and system for injecting write data to solve the problem that the processor operation process needs to constantly change the state of the cache column, which obviously reduces the performance of the processor.

[0004] The present invention proposes a method and system for injecting and writing data, wherein the system for injecting and writing data includes an input / output block, at least two processing units, a system memory, a network interface, and an input / output device; wherein the at least two processing units are electrically coupled to the input / output block; and the system memory, the network interface, and the input / output device are electrically coupled to the input / output block, respectively.

[0005] Furthermore, the processing unit includes a core unit and a cache unit; wherein the core unit and the cache unit are electrically coupled to each other.

[0006] Furthermore, the input / output block includes a memory controller, a network controller, an input / output controller and a buffer; wherein the memory controller, the network controller, and the input / output controller are electrically coupled to the buffer respectively; the buffer is electrically coupled to the processing unit; the network controller is electrically coupled to the system memory; and the input / output controller is electrically coupled to the input / output device.

[0007] Furthermore, the cache includes an arbitrator and a queue unit; wherein the arbitrator and the queue unit are electrically coupled; the queue unit is electrically coupled to the network controller; and the arbitrator and the memory controller are electrically coupled.

[0008] Furthermore, the input / output block is also configured with a tasker, and the tasker is used to connect different components inside the input / output block and / or to link components inside the input / output block with external components.

[0009] Furthermore, the at least two processing units are linked via a tasker and a buffer configured in the input / output block.

[0010] Furthermore, the method for injecting and writing data includes:

[0011] When the input / output block receives at least one instruction sent by the input / output device and / or the processing unit, the instruction is temporarily stored in a queue unit of a buffer;

[0012] The arbiter inside the input / output block retrieves instructions from the queue unit, determines the attributes of the instructions, and performs cache processing according to the attributes of the instructions.

[0013] Furthermore, the arbiter inside the input / output block retrieves instructions from the queue unit, determines the attributes of the instructions, and performs cache processing according to the attributes of the instructions, including:

[0014] The arbiter inside the input / output block retrieves an instruction from the queue unit, and determines whether the instruction is a write-required instruction or a read-required instruction;

[0015] When the instruction is a write request instruction, the input / output block writes data to the cache corresponding to the designated processing unit;

[0016] When the instruction is a read request instruction, the instruction is placed in the queue unit, and the arbiter reads and executes the instructions one by one to obtain read data, and the input / output block does not cache the read data to the designated processing unit.

[0017] Furthermore, when the instruction is a write request instruction, the input / output block writes data to a cache corresponding to a designated processing unit, including:

[0018] When the instruction is a write request instruction, the input / output block retrieves data to be written into the processing unit and the designated processing unit corresponding to the write data from the system memory;

[0019] The input / output block detects whether the designated processing unit is in a cache state;

[0020] When the designated processing unit is in a cache state, i.e., a cache hit occurs, the input / output block caches the write data to the processing unit;

[0021] When the designated processing unit is not in a cache state, that is, a cache miss, the input / output block determines the operation quality state of the designated processing unit according to the historical cache record data of the designated processing unit;

[0022] When the operation quality status of the designated processing unit is in a good state, the swap block is loaded into the designated processing unit, and the write data is cached in the processing unit;

[0023] When the operation quality status of the designated processing unit is in a non-good state, any processing unit whose operation quality status is in a good state is selected from the processing units and is used to replace the designated processing unit for data caching.

[0024] Furthermore, the input / output block determines the operation quality status of the designated processing unit according to the historical cache record data of the designated processing unit, including:

[0025] When the designated processing unit is not in a cache state, that is, a cache miss occurs, the input / output block retrieves the historical cache record data of the designated processing unit;

[0026] Retrieving the cache hit rate, cache data volume and cache delay in the historical cache record data;

[0027] The first evaluation factor is obtained by using the cache hit rate in the historical cache record data; wherein the first evaluation factor is obtained by the following formula:

[0028]

[0029] Among them, P 1yz is the first evaluation factor of the specified processing unit, h is the historical cache times of the specified processing unit, v gsiz is the actual cache rate of the specified processing unit in the history of the i-th cache, w max is the preset cache status upper limit, that is, the maximum allowed cache rate, w min is the preset cache state lower limit, that is, the minimum allowed cache rate, C mziz is the number of cache hits in the history of the i-th cache of the specified processing unit, Q ziz The total number of requests for the i-th cache in the history of the specified processing unit;

[0030] The second evaluation factor is obtained by using the cache data volume and cache delay; wherein the second evaluation factor is obtained by the following formula:

[0031]

[0032] Among them, P 2yz is the second evaluation factor of the specified processing unit, C lz is the cache data volume of the specified processing unit, d is the total number of processing units, C la is the cache data volume of the ath processing unit, Y la is the cache delay time of the ath processing unit, Y lz The cache delay time for the specified processing unit;

[0033] Extracting the hit time data information of the designated processing unit from the historical cache record data;

[0034] The first evaluation factor and the second evaluation factor are combined with the hit time data information to obtain a cache operation evaluation parameter of the designated processing unit, wherein the cache operation evaluation parameter is obtained by the following formula:

[0035]

[0036] Among them, X yp Run the evaluation parameters for the cache of the specified processing unit, M sz is the hit time data of the specified processing unit, M la is the hit time data of the ath processing unit;

[0037] When the cache operation evaluation parameter of the processing unit is lower than a preset evaluation parameter threshold, it is determined that the operation quality state of the designated processing unit is in a non-good state.

[0038] Beneficial effects of the present invention: Through the coordinated work of the memory controller, the network controller and the input / output controller, the system can process data and communicate with external devices more efficiently. The use of the buffer reduces the number of accesses to the main memory, and improves the data access speed and system responsiveness. The electrical coupling connection ensures stable communication and data transmission between components, and reduces the failure rate. At the same time, the use of the buffer reduces the risk of data loss and damage. The system can further improve data processing capabilities and performance by adding processing units or expanding memory. In addition, the use of the network controller enables the system to easily support more network devices and services. The integrated design of the memory controller, the network controller and the input / output controller simplifies the management and maintenance of the system. The administrator can more conveniently monitor and manage the operating status of the system, and promptly discover and solve problems. By configuring different input / output devices and network interfaces, the system can adapt to different application scenarios and needs, and provide users with flexible and diverse solutions. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A method for injecting written data;

[0040] Figure 2 A schematic diagram of the system architecture disclosed in an embodiment of the present invention;

[0041] Figure 3 A schematic diagram of an input / output block architecture disclosed in an embodiment of the present invention;

[0042] Figure 4 A block diagram of the steps of writing data disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0043] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0044] One embodiment of the present invention provides a method and system for injecting write data, wherein the system for injecting write data includes an input / output block, at least two processing units, a system memory, a network interface, and an input / output device; wherein the at least two processing units are electrically coupled to the input / output block; the system memory, the network interface, and the input / output device are electrically coupled to the input / output block, respectively. The processing unit includes a core unit and a cache unit; wherein the core unit and the cache unit are electrically coupled.

[0045] The working principle of the above technical solution is as follows: the input / output block serves as a bridge for data exchange between the system and the outside, and is responsible for receiving external input data and outputting the internally processed data to the outside. The system includes at least two processing units, which are electrically coupled to the input / output block and can process data in parallel to improve system performance. Each processing unit includes a core unit and a cache unit, which are electrically coupled to each other. The core unit is responsible for performing the main computing tasks. The cache unit serves as a cache for the core unit and stores the data that has been recently used or is about to be used to speed up data processing. The system memory is electrically coupled to the input / output block and is used to store the data and programs required for the system to run. The network interface is electrically coupled to the input / output block and is responsible for data exchange between the system and the external network, such as receiving network requests, sending network responses, etc. The input / output device is electrically coupled to the input / output block, including various input devices (such as keyboards, mice, touch screens, etc.) and output devices (such as displays, printers, etc.) for user interaction with the system. Data enters the input / output block from the input / output device or the network interface. The input / output block distributes data to the corresponding processing unit according to the data type and destination. The processing unit uses the core unit to perform computing tasks and accelerates data processing through the cache unit. The processed data is returned to the input / output block and then output to external devices or storage media as needed.

[0046] like Figure 2 As shown, the present invention proposes a specific embodiment of a processing system, providing an input / output block (I / Oblock) 100 coupled to at least two processing units 110, 120. The processing units 110, 120 each have a core 111, 120 connected to a cache 112, 122. Secondly, the input / output block 100 is also connected to a system memory 130, a network interface 140 and an input / output device 150. The cache 112, 122 is at least a first-level cache; the system memory 130 is a dynamic random access memory (DRAM) or other memory of similar nature; the input / output device 150.

[0047] like Figure 3As shown, a feasible embodiment of an input / output block 100 is shown in the figure. The input / output block 100 includes a buffer 101 connected to a memory controller 102, an input / output controller 103 and a network controller 104. Furthermore, the composition of the buffer 101 includes a queue unit 105 connected to an arbiter 106. Secondly, an appropriate number of multiplexers (not shown) can be configured in the input / output block 100, and the multiplexers can be used to connect different components inside the input / output block 100, or to link components inside the input / output block 100 with external components.

[0048] like Figure 2 and 3 As shown, according to the above description, the processing units 110 and 120 can be linked to the register 101 through an appropriate multiplexer; the register 101 and the input / output controller 103 can be connected to the multiplexer, and the multiplexer is connected to the memory controller 102. The memory controller 102 is connected to the system memory 130. The input / output controller 103 is connected to the input / output device 150, wherein the input / output device 150 can be a graphics adapter, a display, a keyboard, etc. The network controller 104 is connected to the network interface 140.

[0049] The architecture shown above is a centralized system architecture that can be applied to a multi-core computer system or server. Specifically, since the processing units 110 and 120 are connected to other devices or peripherals, such as the system memory 130, the network interface 140, and the input / output device 150 are all connected to the input / output block 100, the processing units 110 and 120 communicate with other devices or peripherals through the input / output block, and the input / output block 100 uniformly issues input / output control to the processing units 110 and 120. It is worth noting that each input / output control only performs one access action.

[0050] like Figure 4 As shown, the architecture shown in the present invention, a method for injecting write data, includes:

[0051] Block 201 represents command reception. The I / O block receives at least one command and temporarily stores it in the queue unit of the buffer; the command can come from the I / O device or the processing unit; secondly, the arbiter can obtain the command from the queue unit;

[0052] Block 202 indicates determining the instruction request. Here, the instruction obtained by the arbitrator is determined to be a write request instruction or a read request instruction;

[0053] Block 203 performs actions based on whether the instruction is a write request. When the instruction is a write request, the input / output block writes data to the cache of the designated processing unit;

[0054] Block 204 represents the action taken when the instruction is a read request. If the instruction is a read, the instruction is placed in the queue unit, and the arbiter performs accesses one by one without injecting data into the cache of the processing unit.

[0055] The method shown in this embodiment obviously only performs an access to a single cache. As in the prior art, multiple cache states will be changed at the same time. Therefore, a simpler cache column state can be provided to improve the disadvantage of frequent cache column state changes. The system and method provided by the present invention enable each processor and peripheral device to communicate with a specific input / output block together, thereby improving the system efficiency of the asymmetric speed of each peripheral.

[0056] The effect of the above technical solution is: through the parallel processing of at least two processing units, the system can process multiple tasks at the same time, significantly improving the data processing capability. The cache unit is used to store the data that has been recently used or will be used soon, which reduces the number of times the system memory is accessed and improves the data processing speed and efficiency. The system supports a variety of input / output devices and network interfaces, and can adapt to different application scenarios and requirements. By adding processing units or expanding the system memory, the data processing capability and performance of the system can be further improved. The electrical coupling connection ensures stable communication and data transmission between the components within the system, and improves the stability and reliability of the system.

[0057] In one embodiment of the present invention, the input / output block includes a memory controller, a network controller, an input / output controller and a buffer; wherein the memory controller, the network controller, and the input / output controller are electrically coupled to the buffer respectively; the buffer is electrically coupled to the processing unit; the network controller is electrically coupled to the system memory; and the input / output controller is electrically coupled to the input / output device.

[0058] The working principle of the above technical solution is as follows: The memory controller is responsible for processing the data interaction between the CPU and the memory. It performs tasks such as address translation, data caching and timing control to ensure that the data is read or written to the memory at the right time. The memory controller is electrically coupled to the cache to quickly access the cached data. The network controller is the basis for software-defined network (SDN) management, providing a centralized programmable automation point for managing, configuring, monitoring and troubleshooting virtual network infrastructure. It communicates with network devices and services through network controller APIs (such as Southbound API and Northbound API). The network controller is electrically coupled to the cache to ensure fast caching and access of network data. In addition, it is also electrically coupled to the system memory to support higher-level data processing and storage. The input / output controller manages data transmission between the computer and external devices. It is responsible for receiving signals from input devices (such as keyboard keys, mouse movements, etc.) and sending processed data to output devices (such as displays, printers, etc.). The input / output controller is electrically coupled to the cache to provide cache support during data transmission. At the same time, it is electrically coupled to the input / output device to ensure accurate data transmission. The cache is located inside the input / output block and is used to temporarily store data that needs to be accessed frequently. It reduces the number of accesses to the main memory, improves data access speed and system performance. The cache is electrically coupled to the memory controller, network controller, input / output controller, and processing unit to quickly transfer data between these components. The processing unit is the computing core of the system, responsible for executing program instructions and processing data. It is connected to the cache through an electrically coupled connection to quickly access data in the cache. The processing unit receives data from the input / output block, performs computing tasks, and sends the results back to the input / output block for further processing or output.

[0059] The effect of the above technical solution is: through the collaborative work of the memory controller, the network controller and the input / output controller, the system can process data and communicate with external devices more efficiently. The use of the buffer reduces the number of accesses to the main memory, improves the data access speed and system responsiveness. The electrical coupling connection ensures stable communication and data transmission between components, reducing the failure rate. At the same time, the use of the buffer reduces the risk of data loss and damage. The system can further improve data processing capabilities and performance by adding processing units or expanding memory. In addition, the use of the network controller enables the system to easily support more network devices and services. The integrated design of the memory controller, the network controller and the input / output controller simplifies the management and maintenance of the system. The administrator can more conveniently monitor and manage the operating status of the system, and promptly discover and solve problems. By configuring different input / output devices and network interfaces, the system can adapt to different application scenarios and needs, providing users with flexible and diverse solutions.

[0060] In one embodiment of the present invention, the cache includes an arbitrator and a queue unit; wherein the arbitrator and the queue unit are electrically coupled; the queue unit is electrically coupled to the network controller; and the arbitrator and the memory controller are electrically coupled.

[0061] The working principle of the above technical solution is as follows: the main function of the arbitrator is to coordinate and manage the access to the data in the cache. In the case of concurrent access, the arbitrator will decide which request can have priority access to the data in the cache to ensure data consistency and access fairness. The arbitrator is electrically coupled to the memory controller, which means that it can receive data requests from the memory controller and decide whether to allow the request to access the cache data based on the current cache status and access policy. The queue unit is a data structure that follows the first-in-first-out (FIFO) principle and is used to store data requests waiting to access the cache. When multiple requests arrive at the cache at the same time, they are placed in a queue and wait for processing by the arbitrator in the order of arrival. The queue unit is electrically coupled to the network controller, so it can receive data requests from the network controller and put them in a queue for processing. When the arbitrator decides to allow a request to access the cache data, it notifies the queue unit to remove the request from the queue and send its data to the corresponding processing unit or output device. When a data request arrives, it is first sent to the queue unit of the cache. The queue unit puts the request in the queue and notifies the arbitrator that there is a new request waiting to be processed. The arbitrator decides whether to allow the request to access the cache data based on the current cache status and access policy. If access is allowed, the arbitrator notifies the queue unit to remove the request from the queue and send its data to the corresponding processing unit or output device. If access is not allowed (for example, the required data does not exist in the cache), the arbitrator may forward the request to the memory controller or other data source for further processing.

[0062] The effect of the above technical solution is: through the collaborative work of the arbitrator and the queue unit, the cache can efficiently process concurrent data requests and reduce the delay and conflict of data access. The use of the queue unit ensures the orderly processing of data requests and avoids the performance degradation caused by disordered competition. The use of the arbitrator ensures the consistency and fairness of cache data access and avoids data conflicts and inconsistencies. In the case of concurrent access, the arbitrator can intelligently allocate cache resources to ensure that each request can be responded to in a timely manner. Through the integrated design of the arbitrator and the queue unit, the management of the cache becomes simpler and more intuitive. The administrator can easily monitor and manage the status of the cache and the processing of data requests. The design of the arbitrator and the queue unit can support a large number of concurrent data requests and complex cache strategies. As the system scale expands and the demand increases, the cache can expand its processing capacity by increasing the number of arbitrators and queue units. Since the queue unit is electrically coupled to the network controller, the cache can directly receive and process data requests from the network. This reduces the delay and intermediate links of data transmission and improves the overall performance of the network.

[0063] In one embodiment of the present invention, the input / output block is further configured with a tasker, and the tasker is used to connect different components within the input / output block and / or to link components within the input / output block with external components.

[0064] The working principle of the above technical solution is as follows: the tasker connects the memory controller, network controller, input / output controller and buffer (including arbiter and queue unit) in the input / output block through electrical coupling. It ensures that the data communication and control signals between these components can be transmitted efficiently and accurately. When a component needs to interact with other components, the tasker will be responsible for establishing a communication channel and managing the data transmission process. In addition to connecting internal components, the tasker is also responsible for linking the input / output block with external components (such as processing units, system memory, input / output devices, etc.). Through appropriate interfaces and protocols, it is ensured that the data exchange and control signal transmission between internal and external components can proceed smoothly. The tasker will dynamically adjust the connection relationship between internal and external components according to the needs and configuration of the system to achieve the best performance and efficiency. The tasker is also responsible for managing and controlling the data transmission process inside and outside the input / output block. According to the type, priority and destination of the data, the appropriate transmission path and method are selected to ensure that the data can reach the target component quickly. At the same time, the tasker will also perform necessary processing on the data, such as data verification, format conversion, etc., to ensure the integrity and correctness of the data.

[0065] The effect of the above technical solution is that the tasker significantly improves the overall performance of the system by optimizing the connection relationship and data transmission path between internal and external components. The delay and bottleneck of data transmission are reduced, so that the system can respond to and process external requests more quickly. The tasker enhances the reliability of the system by ensuring the integrity and correctness of data during transmission, and can promptly detect and handle errors and anomalies in data transmission to avoid data loss or damage. The introduction of the tasker makes the management of input / output blocks simpler and more convenient. Administrators can monitor and manage the status and performance of internal and external components through the tasker, and promptly detect and solve problems. The design of the tasker makes the input / output block have good scalability. As the scale of the system expands and the demand increases, the processing capacity of the system can be expanded by increasing the number or function of the tasker. The tasker can dynamically adjust the connection relationship and data transmission path between internal and external components according to the actual needs of the system to achieve optimal configuration and efficient utilization of resources. This helps to reduce the energy consumption and cost of the system and improve the overall efficiency of the system.

[0066] According to an embodiment of the present invention, the at least two processing units are linked via a tasker and a buffer configured in the input / output block.

[0067] The working principle of the above technical solution is as follows: the tasker acts as a bridge connecting the processing unit and the buffer, and is responsible for data communication and control signal transmission between the processing unit and the buffer. When the processing unit needs to access the data in the buffer, it sends a request to the tasker. After receiving the request, the tasker will decide whether to allow the processing unit to access the buffer based on factors such as the status of the buffer and the priority of the processing unit. If access is allowed, the tasker will establish a communication channel between the processing unit and the buffer and manage the data transmission process. This includes reading data from the buffer to the processing unit, or writing data generated by the processing unit to the buffer. The processing unit interacts with the buffer through the tasker to realize data reading and writing operations. When the processing unit needs to read data, it sends a read request to the tasker and specifies the data address to be read. The tasker checks whether there is data at the address in the buffer. If it exists, it directly sends the data to the processing unit; if it does not exist, it may need to load data from the main memory or other data sources to the buffer, and then send it to the processing unit. When the processing unit needs to write data, it sends a write request to the tasker and specifies the data address and data content to be written. The tasker manages the write operation of the cache to ensure the correctness and consistency of the data. When multiple processing units access the cache at the same time, the tasker will perform concurrent processing. It uses appropriate scheduling algorithms such as polling and priority queues based on factors such as the priority of each processing unit and the urgency of the data request to ensure that each processing unit can access the cache fairly and efficiently.

[0068] The effect of the above technical solution is: by optimizing the connection and data transmission between the processing unit and the buffer through the tasker, the system can respond and process data requests more quickly, thereby improving the overall performance. The concurrent processing capability enables multiple processing units to access the buffer at the same time, improving the throughput and response speed of the system. The tasker ensures the integrity and correctness of the data during the transmission process, reducing the risk of data errors and damage. The use of the buffer reduces the frequent access of the processing unit to the main memory, reducing the possibility of system crashes and performance degradation. Through the centralized management of the tasker, the connection and data transmission process between the processing unit and the buffer is simplified, reducing the complexity and management difficulty of the system. The administrator can quickly locate and solve potential problems by monitoring the status and performance of the tasker. The architecture supports the expansion of processing units and buffers. As the system scale expands and the demand increases, more processing units and buffers can be easily added to meet higher performance requirements. The tasker dynamically adjusts the connection and data transmission mode between the processing unit and the buffer according to the actual needs of the system, realizing the optimal configuration and efficient use of resources. This helps to reduce the energy consumption and cost of the system and improve the overall efficiency of the system.

[0069] In one embodiment of the present invention, the method for injecting and writing data includes:

[0070] When the input / output block receives at least one instruction sent by the input / output device and / or the processing unit, the instruction is temporarily stored in a queue unit of a buffer;

[0071] The arbiter inside the input / output block retrieves instructions from the queue unit, determines the attributes of the instructions, and performs cache processing according to the attributes of the instructions.

[0072] The working principle of the above technical solution is as follows: after the input / output block receives the instruction, it will first temporarily store the instruction in the queue unit of the cache. The queue unit follows the first-in-first-out (FIFO) principle to ensure that the instructions are queued for processing in the order in which they are received. The arbitrator inside the cache will call the instruction from the queue unit regularly or according to preset conditions. The arbitrator is responsible for managing and coordinating the resource access in the cache to ensure that the instruction can be processed in time according to the priority and strategy. After calling the instruction, the arbitrator will determine the attributes of the instruction. The attributes of the instruction may include data type, access type (read / write), target address, priority, etc. These attributes determine how the instruction is processed in the cache. According to the attributes of the instruction, the arbitrator will perform corresponding cache processing. For example, if the instruction is a read instruction, the arbitrator will check whether the required data already exists in the cache. If it exists, the data is directly read from the cache and returned to the requester; if it does not exist, it may be necessary to load the data from the main memory or other data sources into the cache and then return it to the requester. If the instruction is a write instruction, the arbitrator will manage the write operation of the cache to ensure the correctness and consistency of the data.

[0073] The effect of the above technical solution is: by temporarily storing the instructions in the queue unit of the buffer, conflicts and delays that may be caused by direct processing of the instructions are avoided. The existence of the queue unit enables the instructions to wait for processing in an orderly manner, thereby improving the throughput and response speed of the system. The arbitrator performs cache processing according to the attributes of the instructions, and can manage the resources in the buffer more intelligently. The data reading and writing strategies can be dynamically adjusted according to actual needs to ensure that the data in the buffer is always kept in the best state, thereby improving the utilization of resources. The use of the buffer reduces the frequent access of the processing unit and the input / output device to the main memory, reducing the risk of system crash and performance degradation. At the same time, the existence of the arbitrator ensures the orderly processing of instructions and the reasonable allocation of resources, further enhancing the reliability of the system. By integrating the processes of temporary storage, retrieval, attribute judgment and processing of instructions in the input / output block, the management of the system is simplified. The administrator can more conveniently monitor and manage the status and performance of the buffer, and timely discover and solve problems. The method supports multiple instructions to be simultaneously in the queue unit waiting for processing, thereby realizing the ability of concurrent processing. This enables the system to process multiple instructions from different input / output devices or processing units at the same time, improving the throughput and response speed of the system.

[0074] In one embodiment of the present invention, the arbiter inside the input / output block retrieves instructions from the queue unit, determines the attributes of the instructions, and performs cache processing according to the attributes of the instructions, including:

[0075] The arbiter inside the input / output block retrieves an instruction from the queue unit, and determines whether the instruction is a write-required instruction or a read-required instruction;

[0076] When the instruction is a write request instruction, the input / output block writes data to the cache corresponding to the designated processing unit;

[0077] When the instruction is a read request instruction, the instruction is placed in the queue unit, and the arbiter reads and executes the instructions one by one to obtain read data, and the input / output block does not cache the read data to the designated processing unit.

[0078] The working principle of the above technical solution is as follows: the arbitrator retrieves instructions from the queue unit of the cache. The queue unit may contain multiple instructions waiting to be processed at the same time. The arbitrator analyzes the retrieved instructions and determines their attributes. Specifically, it determines whether the instruction is a request to write data to a certain cache (write-required instruction) or a request to read data from a certain cache (read-required instruction). If the instruction is a write-required instruction, the arbitrator will instruct the input / output block to write data to the cache corresponding to the specified processing unit. This usually involves transferring data from the input / output block or system memory to the target cache, and may include some error checking and data integrity maintenance steps. If the instruction is a read-required instruction, the arbitrator will put the instruction back into the queue unit and wait for the right time to read and execute. When it is the turn of the instruction to be executed, the arbitrator will instruct the input / output block to read data from the specified cache. This process may involve data verification, format conversion, etc. The read data will be directly returned to the processing unit or input / output device that requested the data, and will not be written to the cache of the processing unit through the input / output block. This means that read operations are directly from the target cache and no additional cache write step is required.

[0079] The effect of the above technical solution is that by distinguishing between read and write instructions, the system can use cache resources more effectively. The write operation ensures that the data is correctly written to the target cache, while the read operation reads the data directly from the target cache, avoiding unnecessary cache writes and possible data conflicts. The read operation obtains data directly from the target cache, reducing the data transmission delay, thereby improving the response speed of the system. This is particularly important for application scenarios that require fast response. By processing read and write operations separately, the management and scheduling of the cache are simplified. The arbitrator can focus more on the characteristics and requirements of each operation, optimize the processing flow, and improve system performance. This method allows the system to flexibly process read and write operations according to the attributes of the instructions. The system can dynamically adjust the read and write strategies according to actual conditions and needs to adapt to different application scenarios and load conditions. For read operations, data is read directly from the target cache without going through additional cache write steps, reducing unnecessary redundant operations and data transmission, and improving the overall efficiency of the system.

[0080] In one embodiment of the present invention, when the instruction is a write request instruction, the input / output block writes data to a cache corresponding to a designated processing unit, including:

[0081] When the instruction is a write request instruction, the input / output block retrieves data to be written into the processing unit and the designated processing unit corresponding to the write data from the system memory;

[0082] The input / output block detects whether the designated processing unit is in a cache state;

[0083] When the designated processing unit is in a cache state, i.e., a cache hit occurs, the input / output block caches the write data to the processing unit;

[0084] When the designated processing unit is not in a cache state, that is, a cache miss, the input / output block determines the operation quality state of the designated processing unit according to the historical cache record data of the designated processing unit;

[0085] When the operation quality status of the designated processing unit is in a good state, the swap block is retrieved and loaded into the designated processing unit, and the write data is cached in the processing unit;

[0086] When the operation quality status of the designated processing unit is in a non-good state, any processing unit whose operation quality status is in a good state is selected from the processing units and is used to replace the designated processing unit for data caching.

[0087] The working principle of the above technical solution is as follows: the input / output block first retrieves the data to be written and the designated processing unit corresponding to these data from the system memory. The input / output block detects whether the designated processing unit is in the cache state. This usually involves checking whether the cache of the processing unit already contains data that is the same as or related to the written data. If the designated processing unit is in the cache state (i.e., cache hit), the input / output block directly caches the written data to the processing unit. This means that the data write operation can be completed directly in the cache without accessing the main memory, thereby increasing the write speed. If the designated processing unit is not in the cache state (i.e., cache miss), the input / output block further analyzes the operating status of the processing unit. The input / output block determines the operating quality status of the processing unit based on the historical cache record data of the designated processing unit. These historical records may include indicators such as cache hit rate, processing speed, and error rate. If the running quality status of the designated processing unit is in a good state, the input / output block will call the swap block (i.e., the cache block used to replace old data) to load it into the processing unit, and cache the written data to the processing unit. In this way, the new data will be stored in the cache for subsequent quick access. If the running quality status of the designated processing unit is in a bad state, the input / output block will filter out any processing unit in the system whose running quality status is in a good state, and replace the designated processing unit for data caching. This ensures that even if a processing unit fails or its performance degrades, the system can continue to operate through other healthy processing units, ensuring the stability and reliability of the system.

[0088] The effect of the above technical solution is: by means of cache hits and direct writing to the cache, the number of accesses to the main memory is reduced, thereby improving the performance of data writing. When a processing unit fails or its performance degrades, the system can automatically switch to other healthy processing units for data caching, thereby ensuring the stability and reliability of the system. By dynamically scheduling according to the operating quality status of the processing unit, the system can more efficiently utilize cache and processing unit resources, avoiding resource waste and performance bottlenecks. The automated processing flow reduces the need for manual intervention and reduces the complexity and cost of system management. By improving system performance and stability, user waiting time and the possibility of system crashes are reduced, thereby improving user experience.

[0089] In one embodiment of the present invention, the input / output block determines the operation quality status of the designated processing unit according to the historical cache record data of the designated processing unit, including:

[0090] When the designated processing unit is not in a cache state, that is, a cache miss occurs, the input / output block retrieves the historical cache record data of the designated processing unit;

[0091] Retrieving the cache hit rate, cache data volume and cache delay in the historical cache record data;

[0092] The first evaluation factor is obtained by using the cache hit rate in the historical cache record data; wherein the first evaluation factor is obtained by the following formula:

[0093]

[0094] Among them, P 1yz is the first evaluation factor of the specified processing unit, h is the historical cache times of the specified processing unit, v gsiz is the actual cache rate of the specified processing unit in the history of the i-th cache, w max is the preset cache status upper limit, that is, the maximum allowed cache rate, w min is the preset cache state lower limit, that is, the minimum allowed cache rate, C mziz is the number of cache hits in the history of the i-th cache of the specified processing unit, Q ziz The total number of requests for the i-th cache in the history of the specified processing unit;

[0095] When v gsiz -w max or v gsiz -w min When it is zero, set it to 1. When it is a positive number, it indicates that the actual cache rate is not within the preset cache status range. is a negative number, the first evaluation factor is relatively small. When it is a negative number, it indicates that the actual cache rate is within the preset cache status range. If it is a positive number, the first evaluation factor is relatively large. Relatively speaking, the larger the Cmziz, the larger the Qziz, and the greater the cache hit rate, the larger the first evaluation factor.

[0096] The second evaluation factor is obtained by using the cache data volume and cache delay; wherein the second evaluation factor is obtained by the following formula:

[0097]

[0098] Among them, P 2yz is the second evaluation factor of the specified processing unit, C lz is the cache data volume of the specified processing unit, d is the total number of processing units, C lais the cache data volume of the ath processing unit, Y la is the cache delay time of the ath processing unit, Y lz The cache delay time for the specified processing unit;

[0099] Relatively speaking, when C lz The larger the value, the more data and instructions stored in the cache, thereby improving the cache hit rate. The second evaluation factor increases accordingly. lz The larger the Y la -Y lz The smaller, The smaller it is, the smaller the second evaluation factor is.

[0100] Extracting the hit time data information of the designated processing unit from the historical cache record data;

[0101] The first evaluation factor and the second evaluation factor are combined with the hit time data information to obtain a cache operation evaluation parameter of the designated processing unit, wherein the cache operation evaluation parameter is obtained by the following formula:

[0102]

[0103] Among them, X yp Run the evaluation parameters for the cache of the specified processing unit, M sz is the hit time data of the specified processing unit, M la is the hit time data of the ath processing unit;

[0104] Relatively speaking, M sz The larger the The smaller, The smaller the value is, the smaller the cache operation evaluation parameter is, and vice versa.

[0105] When the cache operation evaluation parameter of the processing unit is lower than a preset evaluation parameter threshold, it is determined that the operation quality state of the designated processing unit is in a non-good state.

[0106] The working principle of the above technical solution is as follows: the input / output block first retrieves the historical cache record data of the specified processing unit. These data contain the past cache performance information of the processing unit. From the historical cache record data, the input / output block extracts three key indicators: cache hit rate, cache data volume, and cache delay. The cache hit rate is used to calculate the first evaluation factor. This evaluation factor is based on the historical cache times of the processing unit, the actual cache rate, the cache hit times, the total number of requests, and the preset upper and lower limits of the cache state. When the actual cache rate exceeds or falls below the preset range, it will affect the calculation of the evaluation factor. The higher the cache hit rate, the larger the first evaluation factor. The second evaluation factor is calculated based on the cache data volume and cache delay. The larger the cache data volume, the higher the cache hit rate, so the second evaluation factor will increase accordingly. The longer the cache delay time, the smaller the second evaluation factor. In addition to the above two evaluation factors, the input / output block also extracts the hit time data information of the processing unit from the historical cache record data. This information reflects the time performance of the processing unit when the cache hits. Combining the first evaluation factor, the second evaluation factor and the hit time data information, the input / output block will calculate a cache operation evaluation parameter. This parameter comprehensively considers the cache hit rate, data volume, latency and hit time of the processing unit. Finally, the calculated cache operation evaluation parameter is compared with the preset evaluation parameter threshold. If the evaluation parameter is lower than the threshold, it is determined that the operation quality status of the specified processing unit is in a non-good state.

[0107] The effect of the above technical solution is: through the formula of the first evaluation factor It can be determined whether the actual cache rate is within the preset cache status range by The positive or negative state of the calculation result can directly or indirectly determine the relative size of the first evaluation factor, and then evaluate the cache hit rate in the historical cache record data. Evaluate the cache data volume of the specified processing unit by Evaluate the cache delay time of the specified processing unit. lz The larger the value, the more data and instructions stored in the cache, thereby improving the cache hit rate. The second evaluation factor increases accordingly. lz The larger the Y la -Y lz The smaller, The smaller the value, the smaller the second evaluation factor. The calculation formula of the evaluation parameter is run by cache. The comprehensive evaluation coefficient of the first evaluation factor and the second evaluation factor on the cache operation evaluation parameter can be calculated. The evaluation coefficient of the hit time data of the specified processing unit on the cache operation evaluation parameter can be calculated. Relatively speaking, M sz The larger the The smaller, The smaller the cache operation evaluation parameter is, the smaller the cache operation evaluation parameter is, and vice versa. By comprehensively considering multiple cache performance indicators and hit time data information, the operating quality status of the processing unit can be evaluated more accurately. According to the evaluation results, the system can dynamically adjust the use strategy of the processing unit, such as selecting other processing units with better operating quality for cache operations, thereby ensuring the overall performance and stability of the system. By avoiding the use of processing units with poor operating quality for cache operations, resource waste can be reduced and the efficiency of cache resource utilization can be improved. When a processing unit fails or its performance degrades, the system can detect and handle it in a timely manner, thereby enhancing the reliability and availability of the system. The automated evaluation and adjustment process reduces the need for manual intervention and reduces the complexity and cost of system management.

[0108] The above are preferred embodiments and drawings of the present invention, which are merely illustrative and are not intended to limit the protection scope of the present invention. Equivalent technical means, or implementation within the scope of rights covered by the claims, do not depart from the scope of the present invention and are the applicant's scope of rights.

[0109] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A system for injecting and writing data, characterized in that: The system for injecting write data includes an input / output block, at least two processing units, a system memory, a network interface and an input / output device; wherein the at least two processing units are electrically coupled to the input / output block; and the system memory, the network interface and the input / output device are electrically coupled to the input / output block respectively.

2. The system for injecting and writing data according to claim 1, characterized in that: The processing unit includes a core unit and a cache unit; wherein the core unit and the cache unit are electrically coupled.

3. The system for injecting and writing data according to claim 1, characterized in that: The input / output block includes a memory controller, a network controller, an input / output controller and a buffer; wherein the memory controller, the network controller, and the input / output controller are electrically coupled to the buffer respectively; the buffer is electrically coupled to the processing unit; the network controller is electrically coupled to the system memory; and the input / output controller is electrically coupled to the input / output device.

4. The system for injecting and writing data according to claim 3, characterized in that: The buffer includes an arbitrator and a queue unit; wherein the arbitrator and the queue unit are electrically coupled; the queue unit is electrically coupled to the network controller; and the arbitrator and the memory controller are electrically coupled to each other.

5. The system for injecting and writing data according to claim 1, characterized in that: The input / output block is also configured with a tasker, and the tasker is used to connect different components inside the input / output block and / or to link components inside the input / output block with external components.

6. The system for injecting and writing data according to claim 1, characterized in that: The at least two processing units are linked via a tasker and a buffer configured in the input / output block.

7. A method for injecting and writing data corresponding to the system for injecting and writing data as claimed in any one of claims 1 to 6, characterized in that: The method for injecting and writing data comprises: When the input / output block receives at least one instruction sent by the input / output device and / or the processing unit, the instruction is temporarily stored in a queue unit of a buffer; The arbiter inside the input / output block retrieves instructions from the queue unit, determines the attributes of the instructions, and performs cache processing according to the attributes of the instructions.

8. The method for injecting and writing data according to claim 7, characterized in that: The arbiter inside the input / output block retrieves instructions from the queue unit, determines the attributes of the instructions, and performs cache processing according to the attributes of the instructions, including: The arbiter inside the input / output block retrieves an instruction from the queue unit, and determines whether the instruction is a write-required instruction or a read-required instruction; When the instruction is a write request instruction, the input / output block writes data to the cache corresponding to the designated processing unit; When the instruction is a read request instruction, the instruction is placed in the queue unit, and the arbiter reads and executes the instructions one by one to obtain read data, and the input / output block does not cache the read data to the designated processing unit.

9. The method for injecting and writing data according to claim 8, characterized in that: When the instruction is a write request instruction, the input / output block writes data to the cache corresponding to the designated processing unit, including: When the instruction is a write request instruction, the input / output block retrieves data to be written into the processing unit and the designated processing unit corresponding to the write data from the system memory; The input / output block detects whether the designated processing unit is in a cache state; When the designated processing unit is in a cache state, i.e., a cache hit occurs, the input / output block caches the write data to the processing unit; When the designated processing unit is not in a cache state, that is, a cache miss, the input / output block determines the operation quality state of the designated processing unit according to the historical cache record data of the designated processing unit; When the operation quality status of the designated processing unit is in a good state, the swap block is loaded into the designated processing unit, and the write data is cached in the processing unit; When the operation quality status of the designated processing unit is in a non-good state, any processing unit whose operation quality status is in a good state is selected from the processing units and is used to replace the designated processing unit for data caching.

10. The method for injecting and writing data according to claim 9, characterized in that: The input / output block determines the operation quality status of the designated processing unit according to the historical cache record data of the designated processing unit, including: When the designated processing unit is not in a cache state, that is, a cache miss occurs, the input / output block retrieves the historical cache record data of the designated processing unit; Retrieving the cache hit rate, cache data volume and cache delay in the historical cache record data; The first evaluation factor is obtained by using the cache hit rate in the historical cache record data; wherein the first evaluation factor is obtained by the following formula: Among them, P 1yz is the first evaluation factor of the specified processing unit, h is the historical cache times of the specified processing unit, v gsi is the actual cache rate of the specified processing unit in the history of the i-th cache, w max is the preset cache status upper limit, that is, the maximum allowed cache rate, w min is the preset cache state lower limit, that is, the minimum allowed cache rate, C mziz is the number of cache hits in the history of the i-th cache of the specified processing unit, Q ziz The total number of requests for the i-th cache in the history of the specified processing unit; The second evaluation factor is obtained by using the cache data volume and cache delay; wherein the second evaluation factor is obtained by the following formula: Among them, P 2yz is the second evaluation factor of the specified processing unit, C lz is the cache data volume of the specified processing unit, d is the total number of processing units, C la is the cache data volume of the ath processing unit, Y la is the cache delay time of the ath processing unit, Y lz The cache delay time for the specified processing unit; Extracting the hit time data information of the designated processing unit from the historical cache record data; The first evaluation factor and the second evaluation factor are combined with the hit time data information to obtain a cache operation evaluation parameter of the designated processing unit, wherein the cache operation evaluation parameter is obtained by the following formula: Among them, X yp Run the evaluation parameters for the cache of the specified processing unit, M sz is the hit time data of the specified processing unit, M la is the hit time data of the ath processing unit; When the cache operation evaluation parameter of the processing unit is lower than a preset evaluation parameter threshold, it is determined that the operation quality state of the designated processing unit is in a non-good state.

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