Flash memory interface circuit, flash memory control method, electronic device and storage medium

Abstract

The present application discloses a flash memory interface circuit, a flash memory control method, an electronic device and a storage medium. The flash memory interface circuit is used to connect a CPU and a flash memory. The flash memory includes at least one first flash memory group and at least one second flash memory group. The first flash memory group stores an erasure program code and / or a programming program code. The flash memory interface circuit includes: a timing generation unit, at least one first control register and at least one second control register. The first control register corresponds to the first flash memory group, and the first control register is connected to the CPU; the second control register corresponds to the second flash memory group, and the second control register is connected to the CPU; the first control register, the second control register, the first flash memory group and the second flash memory group are all connected to the timing generation unit.

Description

Technical Field

[0001] The present application relates to the field of flash memory technology, and in particular to a flash memory interface circuit, a flash memory control method, an electronic device and a storage medium. Background Art

[0002] In embedded systems, flash memory is a non-volatile memory. The data stored in it will not be lost due to power failure. It can be erased and programmed multiple times. It is usually used to store program code, system management parameters and user data. However, for flash memory, data cannot be read while erasing or programming. Therefore, it is impossible to use the erase or programming application programming interface stored in the flash memory to erase and program the flash memory itself.

[0003] In the related art, before performing an erase or program operation on a flash memory, the relevant flash memory application programming interface program code stored in the flash memory is first copied to a memory, and then the central processing unit (CPU) reads the relevant flash memory application programming interface program code from the memory to execute the erase or program instruction, thereby performing an erase or program operation on the flash memory. However, copying the relevant flash memory application programming interface program code from the flash memory to the memory often consumes part of the program execution time, and the efficiency of performing an erase or program operation on the flash memory is not high. Summary of the invention

[0004] The present application aims to provide a flash memory interface circuit, a flash memory control method, an electronic device and a storage medium, which can solve the problem of low efficiency in performing erase or programming operations on flash memory.

[0005] In a first aspect, an embodiment of the present application provides a flash memory interface circuit for connecting a CPU and a flash memory, wherein the flash memory includes at least one first flash memory group and at least one second flash memory group, wherein the first flash memory group stores an erasure program code and / or a programming program code, and the flash memory interface circuit includes:

[0006] at least one first control register, the first control register corresponding to the first flash memory group, and the first control register connected to the CPU;

[0007] at least one second control register, the second control register corresponding to the second flash memory group, and the second control register connected to the CPU;

[0008] A timing generation unit, the first control register, the second control register, the first flash memory group and the second flash memory group are all connected to the timing generation unit;

[0009] The first control register is used to receive a first instruction, and the first instruction is used to configure the first control register so that the first control register generates and outputs a first timing signal to the first flash memory group through the timing generation unit, so as to read the erase program code or the programming program code stored in the first flash memory group, and the first timing signal is a timing signal for controlling a read operation, and the read operation is used to read the erase program code and / or the programming program code stored in the first flash memory group;

[0010] The second control register is used to receive a second instruction, and the second instruction is obtained based on the erase program code or the programming program code. The second instruction is used to configure the second control register so that the second control register generates and outputs a second timing signal or a third timing signal to the second flash memory group through the timing generation unit, thereby performing an erase operation or a programming operation on the second flash memory group. The second timing signal is a timing signal for controlling the erase operation, and the third timing signal is a timing signal for controlling the programming operation.

[0011] According to some embodiments of the present application, the timing generation unit includes:

[0012] A state machine, wherein the first control register and the second control register are both connected to the state machine;

[0013] A timing generator, the state machine is connected to the timing generator, and the first flash memory group and the second flash memory group are both connected to the timing generator.

[0014] According to some embodiments of the present application, it further includes:

[0015] At least one first status register, the first status register corresponds to the first flash memory group, and the CPU and the timing generation unit are both connected to the first status register.

[0016] According to some embodiments of the present application, it further includes:

[0017] At least one second status register, the second status register corresponds to the second flash memory group, and the CPU and the timing generation unit are both connected to the second status register.

[0018] In a second aspect, an embodiment of the present application provides a flash memory control method, which is applied to the flash memory interface circuit as described above, and the method includes:

[0019] Sending a first instruction to a first control register, wherein the first instruction is used to configure the first control register so that the first control register generates and outputs a first timing signal to the first flash memory group through a timing generation unit, thereby reading an erase program code or a programming program code stored in the first flash memory group, wherein the first timing signal is a timing signal for controlling a read operation, and the read operation is used to read the erase program code and / or the programming program code stored in the first flash memory group;

[0020] Based on the erase program code or the programming program code, a second instruction is sent to a second control register, and the second instruction is used to configure the second control register so that the second control register generates and outputs a second timing signal or a third timing signal to the second flash memory group through the timing generation unit, thereby performing an erase operation or a programming operation on the second flash memory group, and the second timing signal is a timing signal for controlling the erase operation, and the third timing signal is a timing signal for controlling the programming operation.

[0021] According to some embodiments of the present application, the timing generation unit includes a state machine and a timing generator, the first control register and the second control register are both connected to the state machine, the state machine is connected to the timing generator, and the first flash memory group and the second flash memory group are both connected to the timing generator; based on the erasure program code or the programming program code, sending a second instruction to the second control register, the second instruction is used to configure the second control register, so that the second control register generates a second timing signal or a third timing signal through the timing generation unit, and outputs it to the second flash memory group, including:

[0022] A second instruction is sent to the second control register, wherein the second instruction is used to configure the second control register so that the second control register controls the state machine to enter an erase state or a programming state, and the state machine controls the timing generator to generate and output the second timing signal to the second flash memory group in the erase state, and the state machine controls the timing generator to generate and output the third timing signal to the second flash memory group in the programming state.

[0023] According to some embodiments of the present application, the flash memory interface circuit further includes at least one first status register, the first status register corresponds to the first flash memory group, the CPU and the timing generation unit are both connected to the first status register, and the method further includes:

[0024] The first status data of the first status register is read, and the status of the first flash memory group is confirmed according to the first status data, where the first status data is obtained by feedback from the timing generation unit.

[0025] According to some embodiments of the present application, the flash memory interface circuit further includes at least one second status register, the second status register corresponds to the second flash memory group, the CPU and the timing generation unit are both connected to the second status register, and the method further includes:

[0026] The second state data of the second state register is read, and the state of the second flash memory group is confirmed according to the second state data, where the second state data is obtained by feedback from the timing generation unit.

[0027] In a third aspect, an embodiment of the present application provides an electronic device, including:

[0028] at least one processor;

[0029] at least one memory for storing at least one program;

[0030] When at least one of the programs is executed by at least one of the processors, the flash memory control method as described above is implemented.

[0031] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a program executable by a processor, and the program executable by the processor is used to implement the flash memory control method as described above when executed by the processor.

[0032] In the embodiment of the present application, since the first flash memory group is provided with a first control register correspondingly, and the second flash memory group is provided with a second control register correspondingly, the erasure program code or programming program code stored in the first flash memory group can be directly called through the first control register and the timing generation unit, and based on the erasure program code or the programming program code, the second flash memory group is erased or programmed through the second control register and the timing generation unit. Compared with the traditional flash memory technology, the erasure program code or programming program code stored in the flash memory can be directly called without copying the erasure program code or the programming program code to the memory, and the flash memory itself can be erased or programmed, thereby improving efficiency.

[0033] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The present application is further described below with reference to the accompanying drawings and embodiments, wherein:

[0035] Figure 1 A functional block diagram of an embodiment of a flash memory interface circuit provided by the present application;

[0036] Figure 2A flowchart of an embodiment of a flash memory control method provided by the present application;

[0037] Figure 3 A schematic diagram of the structure of an embodiment of the electronic device provided in this application.

[0038] Reference numerals:

[0039] CPU 100 , flash memory interface circuit 110 , register unit 111 , state machine 112 , timing generator 113 , first flash memory group 120 , second flash memory group 130 , electronic device 200 , processor 210 , memory 220 . DETAILED DESCRIPTION

[0040] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0041] In the description of the present application, it should be understood that the descriptions involving orientation, such as the orientation or positional relationship indicated as up, down, etc., are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0042] In the description of this application, "a plurality" means more than two. If there is a description of "first" or "second", it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0043] In the description of this application, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in this application based on the specific content of the technical solution.

[0044] Refer to the following Figures 1 to 3 A flash memory interface circuit 110, an electronic device 200, and a storage medium according to an embodiment of the present application are described.

[0045] The embodiment of the present application provides a flash memory interface circuit 110, which is used to connect a CPU 100 and a flash memory, wherein the flash memory includes at least one first flash memory group 120 and at least one second flash memory group 130, wherein the first flash memory group 120 stores an erasing program code and / or a programming program code, and the flash memory interface circuit 110 includes:

[0046] A register unit 111, the register unit 111 includes at least one first control register and at least one second control register, the first control register corresponds to the first flash memory group 120, the first control register is connected to the CPU 100, the second control register corresponds to the second flash memory group 130, and the second control register is connected to the CPU 100;

[0047] A timing generation unit, the first control register, the second control register, the first flash memory group 120 and the second flash memory group 130 are all connected to the timing generation unit;

[0048] The first control register is used to receive a first instruction, and the first instruction is used to configure the first control register, so that the first control register generates and outputs a first timing signal to the first flash memory group 120 through the timing generation unit, so as to read the erase program code or the programming program code stored in the first flash memory group 120, and the first timing signal is a timing signal for controlling a read operation, and the read operation is used to read the erase program code and / or the programming program code stored in the first flash memory group 120;

[0049] The second control register is used to receive a second instruction, and the second instruction is obtained based on the erase program code or the programming program code. The second instruction is used to configure the second control register so that the second control register generates and outputs a second timing signal or a third timing signal to the second flash memory group 130 through the timing generation unit, thereby performing an erase operation or a programming operation on the second flash memory group 130. The second timing signal is a timing signal for controlling the erase operation, and the third timing signal is a timing signal for controlling the programming operation.

[0050] In the embodiment of the present application, since the first flash memory group 120 is provided with a first control register correspondingly, and the second flash memory group 130 is provided with a second control register correspondingly, the erasure program code or programming program code stored in the first flash memory group 120 can be directly called through the first control register and the timing generation unit, and based on the erasure program code or the programming program code, the second flash memory group 130 is erased or programmed through the second control register and the timing generation unit. Compared with the traditional flash memory technology, without copying the erasure program code or the programming program code to the memory, the erasure program code or the programming program code stored in the flash memory can be directly called to perform the erasure operation or programming operation on the flash memory itself, thereby improving efficiency.

[0051] like Figure 1 As shown, in some embodiments of the present application, when there are multiple first flash memory groups 120 and multiple first control registers, the multiple first flash memory groups 120 correspond to the multiple first control registers. When there are multiple second flash memory groups 130 and multiple second control registers, the multiple second flash memory groups 130 correspond to the multiple second control registers.

[0052] In some embodiments of the present application, since the first flash memory group 120 and the second flash memory group 130 are respectively provided with independent first control registers and second control registers, each first flash memory group 120 and each second flash memory group 130 can independently perform read operations, erase operations and programming operations.

[0053] In some implementations of the present application, the CPU 100 provides a clock signal for the flash memory interface circuit 110 .

[0054] In some implementations of the present application, the CPU 100 is connected to the flash memory interface circuit 110 via a first bus, and the flash memory interface circuit 110 is connected to the first flash memory group 120 and the second flash memory group 130 via a second bus. The first control register and the second control register are both connected to the timing generation unit via a third bus. The second bus is a bus that can perform a read operation on the first flash memory group 120 and an erase operation or a program operation on the second flash memory group 130 at the same time.

[0055] In one embodiment of the present application, Figure 1 As shown, the timing generation unit includes:

[0056] The state machine 112, the first control register and the second control register are both connected to the state machine 112;

[0057] The state machine 112 is connected to the timing generator 113 , and the first flash memory group 120 and the second flash memory group 130 are both connected to the timing generator 113 .

[0058] In this embodiment, the first control register is connected to the state machine 112 through the third bus, the state machine 112 is connected to the timing generator 113 through the third bus, and the timing generator 113 is respectively connected to the first flash memory group 120 and the second flash memory group 130 through the second bus. The CPU 100 configures the first control register so that the first control register controls the state machine 112 to the read state, and the timing generator 113 generates a fourth timing signal according to the read state of the first control register, and outputs the fourth timing signal to the first flash memory group 120, so as to read the erase program code or the programming program code in the first flash memory group 120. The fourth timing signal is used to read the erase program code or the programming program code in the first flash memory group 120. The CPU 100 configures the second control register so that the second control register controls the state machine 112 to the erase or programming state. In the erase state, the state machine 112 controls the timing generator 113 to generate and output the second timing signal to the second flash memory group 130, so as to perform an erase operation on the second flash memory group 130. The state machine 112 controls the timing generator 113 to generate and output the third timing signal to the second flash memory group 130 in the programming state, so as to perform a programming operation on the second flash memory group 130 .

[0059] In some embodiments of the present application, when the state machine 112 is in the erase state, the second flash memory group 130 will be subjected to a pre-erase read operation, an erase operation, and a post-erase read verification operation. Before the erase operation is performed, the second flash memory group 130 is read to confirm whether it needs to be erased, and the erase operation is performed on the second flash memory group 130 that is not empty, otherwise the erase operation is terminated directly. After completing an erase operation, a post-erase read verification operation is performed, and the data read out of the second flash memory group 130 is all "1", that is, the verification is passed, indicating that the erase is successful, and the erase operation is terminated; if the verification fails, the erase operation is performed again. If the content in the second flash memory group 130 is not successfully erased within the configured number of erase times, the state jumps to the erase error state and generates the corresponding status bit, and the erase operation is terminated.

[0060] When the state machine 112 is in the programming state, the target address of the second flash memory group 130 will be subjected to a pre-programming read operation, a programming operation, and a post-programming read verification operation. Flash memory programming can only be programmed from "1" to "0". Before executing the programming operation, the data of the second flash memory group 130 is read and compared with the target data. When a programming operation from "0" to "1" occurs, the programming operation can be directly terminated, and the corresponding error status is fed back to the second state register. After completing a programming operation, a post-programming read verification operation is performed. If the read data is the target data, the verification is passed, indicating that the programming is successful and the programming operation is terminated; if the verification fails, the programming operation is re-executed. If the programming is not successful within the configured programming times, it jumps to the programming error state and generates the corresponding status bit, and the programming operation is terminated.

[0061] In some embodiments of the present application, the timing generator 113 includes multiple timing counters. When performing an erase operation or a programming operation, the corresponding count value is loaded into the relevant timing counter according to the erase state or the programming state of the state machine 112, thereby outputting the corresponding second timing signal or the third timing signal to the second flash memory group 130.

[0062] In one embodiment of the present application, Figure 1 As shown, the register unit 111 also includes:

[0063] At least one first status register, the first status register corresponds to the first flash memory group 120, and the CPU 100 and the timing generation unit are both connected to the first status register.

[0064] In this embodiment, the CPU 100 reads the first status data of the first status register and confirms the status of the first flash group 120 according to the first status data. In other words, the CPU 100 can confirm the execution status of the read operation of the first flash group 120 through the first status data, for example, confirm whether the read operation of the first flash group 120 is completed.

[0065] In some implementations of the present application, the first status register is connected to the state machine 112 in the timing generation unit via the third bus, and the state machine 112 feeds back the state of the first flash memory group 120 to the first status register.

[0066] In one embodiment of the present application, Figure 1 As shown, the register unit 111 also includes:

[0067] At least one second status register, the second status register corresponds to the second flash memory group 130, and the CPU 100 and the timing generation unit are both connected to the second status register.

[0068] In this embodiment, the CPU 100 reads the second state data of the second state register, and confirms the state of the second flash memory group 130 according to the second state data. In other words, the CPU 100 can confirm the execution state of the erase operation or programming operation of the second flash memory group 130 through the second state data, for example, confirming that the second flash memory group 130 is being programmed, programming error, being erased, or erasure error.

[0069] In some implementations of the present application, the second status register is connected to the state machine 112 in the timing generation unit via a third bus, and the state machine 112 feeds back the state of the second flash memory group 130 to the second status register.

[0070] In addition, the present application embodiment provides a flash memory control method, which is applied to the flash memory interface circuit 110 as described above. Figure 2 As shown, the method includes:

[0071] Step S100: Sending a first instruction to the first control register, the first instruction is used to configure the first control register, so that the first control register generates and outputs a first timing signal to the first flash memory group 120 through the timing generation unit, so as to read the erase program code or the programming program code stored in the first flash memory group 120, the first timing signal is a timing signal for controlling a read operation, and the read operation is used to read the erase program code and / or the programming program code stored in the first flash memory group 120;

[0072] Step S200: Based on the erase program code or the programming program code, send a second instruction to the second control register, the second instruction is used to configure the second control register, so that the second control register generates and outputs a second timing signal or a third timing signal to the second flash memory group 130 through the timing generation unit, thereby performing an erase operation or a programming operation on the second flash memory group 130, the second timing signal is a timing signal for controlling the erase operation, and the third timing signal is a timing signal for controlling the programming operation.

[0073] In this embodiment, the CPU 100 sends a first instruction to the first control register, so that the first control register generates and outputs a first timing signal to the first flash memory group 120 through the timing generation unit, thereby reading the erase program code or the programming program code stored in the first flash memory group 120. Based on the erase program code or the programming program code, the CPU 100 sends a second instruction to the second control register, so that the second control register generates and outputs a second timing signal or a third timing signal to the second flash memory group 130 through the timing generation unit, thereby performing an erase operation or a programming operation on the second flash memory group 130.

[0074] In one embodiment of the present application, the timing generation unit includes a state machine 112 and a timing generator 113, the first control register and the second control register are both connected to the state machine 112, the state machine 112 is connected to the timing generator 113, and the first flash memory group 120 and the second flash memory group 130 are both connected to the timing generator 113;

[0075] Further explanation of "sending a second instruction to a second control register based on the erasing program code or the programming program code, the second instruction being used to configure the second control register so that the second control register generates a second timing signal or a third timing signal through a timing generation unit and outputs the second timing signal to the second flash memory group 130" in step S200 includes:

[0076] Step S210: Send a second instruction to the second control register, the second instruction is used to configure the second control register, so that the second control register controls the state machine 112 to enter the erase state or the programming state, the state machine 112 controls the timing generator 113 to generate and output a second timing signal to the second flash memory group 130 in the erase state, and the state machine 112 controls the timing generator 113 to generate and output a third timing signal to the second flash memory group 130 in the programming state.

[0077] In this embodiment, the CPU 100 sends a second instruction to the second control register, and configures the second control register through the second instruction, so that the second control register controls the state machine 112 to enter the erase state or the programming state.

[0078] In one embodiment of the present application, the flash memory interface circuit 110 further includes at least one first state register, the first state register corresponds to the first flash memory group 120, the CPU 100 and the timing generation unit are both connected to the first state register, and the method further includes:

[0079] Step S300: reading first state data of a first state register, and confirming the state of the first flash memory group 120 according to the first state data, wherein the first state data is obtained by feedback from a timing generation unit.

[0080] In this embodiment, the CPU 100 reads the first status data of the first status register, and the CPU 100 can confirm the status of the first flash memory group 120 according to the first status data.

[0081] In one embodiment of the present application, the flash memory interface circuit 110 further includes at least one second state register, the second state register corresponds to the second flash memory group 130, the CPU 100 and the timing generation unit are both connected to the second state register, and the method further includes:

[0082] Step S400: Read the second state data of the second state register, and confirm the state of the second flash memory group 130 according to the second state data, wherein the second state data is obtained by feedback from the timing generation unit.

[0083] In this embodiment, the CPU 100 reads the second status data of the second status register, and the CPU 100 can confirm the status of the second flash memory group 130 according to the second status data.

[0084] In addition, an embodiment of the present application further discloses an electronic device 200, such as Figure 3 As shown, including:

[0085] at least one processor 210;

[0086] At least one memory 220, used to store at least one program;

[0087] When at least one program is executed by at least one processor 210 , the flash memory control method as described above is implemented.

[0088] The electronic device 200 provided in the embodiment of the present application can implement each process implemented in the above method embodiment and achieve the same beneficial effects. To avoid repetition, it will not be described again here.

[0089] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a program executable by a processor, and the program executable by the processor is used to implement the flash memory control method as described above when executed by the processor.

[0090] The computer-readable storage medium provided in the embodiment of the present application can implement each process implemented in the above method embodiment and achieve the same beneficial effects. To avoid repetition, it will not be described here.

[0091] It will be appreciated by those skilled in the art that all or some of the steps and systems in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0092] The embodiments of the present application are described in detail above in conjunction with the accompanying drawings, but the present application is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present application.

Claims

1. A flash memory interface circuit, characterized in that: Used to connect a central processing unit and a flash memory, the flash memory includes at least one first flash memory group and at least one second flash memory group, the first flash memory group stores an erasing program code and / or a programming program code, and the flash memory interface circuit includes: at least one first control register, the first control register corresponding to the first flash memory group, the first control register connected to the central processing unit; at least one second control register, the second control register corresponding to the second flash memory group, the second control register being connected to the central processing unit; A timing generation unit, the first control register, the second control register, the first flash memory group and the second flash memory group are all connected to the timing generation unit; The first control register is used to receive a first instruction, and the first instruction is used to configure the first control register so that the first control register generates and outputs a first timing signal to the first flash memory group through the timing generation unit, so as to read the erase program code or the programming program code stored in the first flash memory group, and the first timing signal is a timing signal for controlling a read operation, and the read operation is used to read the erase program code and / or the programming program code stored in the first flash memory group; The second control register is used to receive a second instruction, the second instruction is obtained based on the erase program code or the programming program code, the second instruction is used to configure the second control register, so that the second control register generates and outputs a second timing signal or a third timing signal to the second flash memory group through the timing generation unit, thereby performing an erase operation or a programming operation on the second flash memory group, the second timing signal is a timing signal for controlling the erase operation, and the third timing signal is a timing signal for controlling the programming operation; At least one first status register, the first status register corresponds to the first flash memory group, and the central processing unit and the timing generation unit are both connected to the first status register; At least one second status register, the second status register corresponds to the second flash memory group, and the central processing unit and the timing generation unit are both connected to the second status register.

2. The flash memory interface circuit according to claim 1, characterized in that: The timing generation unit comprises: A state machine, wherein the first control register and the second control register are both connected to the state machine; A timing generator, the state machine is connected to the timing generator, and the first flash memory group and the second flash memory group are both connected to the timing generator.

3. A flash memory control method, characterized in that: Applied to the flash memory interface circuit as claimed in claim 1, the method comprising: Sending a first instruction to a first control register, wherein the first instruction is used to configure the first control register so that the first control register generates and outputs a first timing signal to the first flash memory group through a timing generation unit, thereby reading an erase program code or a programming program code stored in the first flash memory group, wherein the first timing signal is a timing signal for controlling a read operation, and the read operation is used to read the erase program code and / or the programming program code stored in the first flash memory group; Based on the erase program code or the programming program code, a second instruction is sent to a second control register, and the second instruction is used to configure the second control register so that the second control register generates and outputs a second timing signal or a third timing signal to the second flash memory group through the timing generation unit, thereby performing an erase operation or a programming operation on the second flash memory group, and the second timing signal is a timing signal for controlling the erase operation, and the third timing signal is a timing signal for controlling the programming operation.

4. The flash memory control method according to claim 3, characterized in that: The timing generation unit includes a state machine and a timing generator, the first control register and the second control register are both connected to the state machine, the state machine is connected to the timing generator, and the first flash memory group and the second flash memory group are both connected to the timing generator; based on the erasure program code or the programming program code, sending a second instruction to the second control register, the second instruction is used to configure the second control register, so that the second control register generates a second timing signal or a third timing signal through the timing generation unit, and outputs it to the second flash memory group, including: A second instruction is sent to the second control register, wherein the second instruction is used to configure the second control register so that the second control register controls the state machine to enter an erase state or a programming state, and the state machine controls the timing generator to generate and output the second timing signal to the second flash memory group in the erase state, and the state machine controls the timing generator to generate and output the third timing signal to the second flash memory group in the programming state.

5. The flash memory control method according to claim 3, characterized in that: The flash memory interface circuit further includes at least one first status register, the first status register corresponds to the first flash memory group, the central processing unit and the timing generation unit are both connected to the first status register, and the method further includes: The first status data of the first status register is read, and the status of the first flash memory group is confirmed according to the first status data, where the first status data is obtained by feedback from the timing generation unit.

6. The flash memory control method according to claim 3, characterized in that: The flash memory interface circuit further includes at least one second status register, the second status register corresponds to the second flash memory group, the central processing unit and the timing generation unit are both connected to the second status register, and the method further includes: The second state data of the second state register is read, and the state of the second flash memory group is confirmed according to the second state data, where the second state data is obtained by feedback from the timing generation unit.

7. An electronic device, characterized in that: include: at least one processor; at least one memory for storing at least one program; When at least one of the programs is executed by at least one of the processors, the flash memory control method according to any one of claims 3 to 6 is implemented.

8. A computer-readable storage medium, characterized in that: A processor-executable program is stored therein, and when the processor-executable program is executed by the processor, it is used to implement the flash memory control method as described in any one of claims 3 to 6.

Images