DMA controller applied to audio data handling, control method and I2S system

Abstract

According to the DMA controller applied to audio data carrying, the control method and the I2S system provided by the invention, the bottleneck that multi-channel audio data and 24-bit audio data cannot be transmitted through general DMA is effectively solved by introducing the DMA controller special for audio. The method supports various audio data formats, and can intelligently and automatically select the optimal DMA data transmission strategy according to specific configuration information such as the number of sound channels, the width of the audio data and the width of a groove. According to the innovation, the audio data transmission efficiency and flexibility are remarkably improved, the burden of a CPU in the data carrying process is greatly relieved, the CPU can process more complex tasks in a centralized computing power mode, and therefore the overall system performance is improved.

Description

Technical Field

[0001] The present application relates to the field of digital audio signal processing, and in particular to a DMA controller, a control method and an I2S system for audio data transfer. Background Art

[0002] Microcontrollers (MCUs) are usually equipped with I2S (Inter-IC Sound Bus) peripherals, which is a synchronous serial communication protocol designed for audio data transmission between digital audio devices. During audio playback, audio data needs to be written from memory to the send data register inside I2S. I2S transmits the data to the audio codec chip (Codec) through the I2S bus according to the relevant transmission protocol standard (such as Philips standard, left-aligned (MSB) standard, right-aligned (LSB) standard or PCM standard) to drive the speaker to play the decoded audio. For mono or dual-channel 16-bit or 32-bit audio data, the data exchange between memory and I2S peripherals can be completed through the CPU or general DMA. Using DMA for data transmission significantly improves system performance: during the data transfer process, the CPU does not need to participate, freeing up its resources to handle other complex computing tasks, thereby achieving more efficient CPU resource utilization.

[0003] The features of general DMA include support for 8-bit (byte), 16-bit (half-word) and 32-bit (word) width data transfer, as well as self-increment, self-decrement or fixed address modes. For example, when playing dual-channel 32-bit audio data, the source address can be set to the memory address where the audio data is stored and the self-increment mode can be selected, while the destination address is specified as the address of the I2S transmit register and set to fixed mode. At this time, the data width of the source address and the destination address are both 32 bits. In this way, DMA can self-incrementally traverse the audio data in the memory and transfer it to the I2S transmit register, thereby realizing audio playback.

[0004] However, for multi-channel audio data such as four-channel, six-channel, and eight-channel, in non-TDM mode (Time Division Multiplexed, time division multiplexing mode), more than one I2S transmit register is required, which makes it impossible to set the destination address to fixed or self-incrementing, thereby limiting the application of general DMA in the data handling process. In addition, for 24-bit audio data, the storage format is 3 consecutive bytes corresponding to 1 channel of audio data, so 3 bytes need to be transported to the I2S transmit register each time. However, since the data width of general DMA does not support 24 bits, it is also impossible to use general DMA to transport this type of audio data. Therefore, these technical limitations affect the efficiency of DMA in processing multi-channel and specific bit-width audio data. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a DMA controller, a control method and an I2S system for audio data transfer, so as to solve the problem of application limitations of general DMA in the prior art when processing multi-channel and 24-bit audio data.

[0006] To achieve the above-mentioned purpose and other related purposes, the first aspect of the present application provides a method for a DMA controller for audio data transfer, comprising: a parameter configuration unit: the parameter configuration unit is communicatively connected to the control interface; the parameter configuration unit is used to receive a source address, a target address and configuration parameters through the control interface, perform parameter configuration operations on a data processing unit based on the configuration parameters, and send the source address, the target address and the configuration parameters to the data processing unit; a data processing unit: the data processing unit includes a data acquisition module, a format matching module and a data transfer module; the data acquisition module is communicatively connected to the parameter configuration unit and the format matching module to acquire audio data from a main memory or an audio input device according to the source address; the format matching module is communicatively connected to the data acquisition module and the data transfer module to perform a format matching operation on the audio data according to the configuration parameters; the data transfer module is communicatively connected to the format matching module to perform a data transfer operation on the format-matched audio data according to the target address, and transfer the format-matched audio data to the main memory or the audio output device.

[0007] In some embodiments of the first aspect of the present application, the DMA controller also includes: a first channel, the first channel reads the audio data from the main memory through a data acquisition module, and stores the audio data in a multi-channel output register, and the data acquisition module sends the audio data to the audio output device; a second channel, the second channel receives the audio data sent by the audio input device through a data acquisition module, and stores the audio data in a multi-channel input register, and the data transfer module transfers the audio data to the main memory.

[0008] In some embodiments of the first aspect of the present application, it includes: the multiple input registers are connected to the data handling module, each input register contains a receive FIFO buffer area with a depth of 16 words and a width of 32 bits, corresponding to two channels of audio data of an audio input device; the input process of each frame of audio data includes taking 2 words of audio data from each input register respectively; the multiple output registers are connected to the data handling module, each output register contains a send FIFO buffer area with a depth of 16 words and a width of 32 bits, corresponding to two channels of audio data of an audio output device; the output process of each frame of audio data includes filling 2 words of audio data into each output register respectively.

[0009] In some embodiments of the first aspect of the present application, the process of performing data transfer operations on audio data after format matching includes: after starting the first channel transmission, in response to the data amount of audio data stored in each output register being less than or equal to the output gate threshold, a DMA event is triggered, and the audio data in the main memory is transferred to each output register until each output register is filled; after starting the second channel transmission, in response to the data amount of audio data stored in each input register being greater than or equal to the input gate threshold, a DMA event is triggered, and the audio data in each input register is transferred to the main memory until each input register is cleared.

[0010] In some embodiments of the first aspect of the present application, the process of performing data transfer operations on format-matched audio data also includes an index increment operation, which includes: in response to successfully executing an operation of reading a frame of data from a source address, the source address index increases by a preset read byte amount so that the source address index points to the starting position of the next frame of data; and / or, in response to successfully executing an operation of writing a frame of data to a target address, the target address index increases by a preset write byte amount so that the target address index points to the data storage location to be written next time.

[0011] In some embodiments of the first aspect of the present application, performing a data transfer operation on format-matched audio data also includes an index reset operation, wherein the index reset operation includes: in response to all output registers being filled with a frame of data, resetting the target address index back to the first address of multiple output registers to wait for the next frame of data to be filled; and / or, in response to all input registers being filled with a frame of data, resetting the source address index back to the first address of multiple input registers to wait for the next frame of data to be read.

[0012] In some embodiments of the first aspect of the present application, the process of performing a format configuration operation on the received audio data includes: in response to the data width of the audio data being smaller than the slot width of the target address, performing a data shift operation of a preset number of bits on the audio data.

[0013] In some embodiments of the first aspect of the present application, the configuration parameters include: one or more of the number of audio channels, data width, data slot width, and the number of audio data frames.

[0014] To achieve the above-mentioned purpose and other related purposes, the second aspect of the present application provides a DMA control method for audio data transfer, which is applied to a DMA controller, and the method includes: receiving a source address, a target address and configuration parameters, and performing parameter configuration operations based on the configuration parameters; obtaining audio data from a main memory or an audio input device according to the source address; performing a format matching operation on the audio data according to the configuration parameters; performing a data transfer operation on the format-matched audio data according to the target address, and transferring the format-matched audio data to the main memory or an audio output device.

[0015] To achieve the above-mentioned object and other related objects, the third aspect of the present application provides an I2S system, which includes: a DMA controller applied to audio data transfer as described in any one of claims 1 to 8.

[0016] As described above, the DMA controller, control method and I2S system for audio data transfer of the present application have the following beneficial effects: the problem that multi-channel audio data and 24-bit audio data cannot be transferred through general DMA is solved. The present invention supports multiple audio data formats and automatically selects the most suitable DMA data transfer strategy according to configuration information such as the number of channels, audio data width, slot width, etc. This improvement greatly reduces the burden on the CPU, allowing it to get rid of cumbersome data transfer tasks, thereby using more computing resources to process other complex computing tasks. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A structural schematic diagram of an embodiment of a DMA controller used for audio data transfer according to the present application is shown.

[0018] Figure 2 A system block diagram of an I2S where a DMA controller is located in an embodiment of a DMA controller of the present application applied to audio data transfer is shown.

[0019] Figure 3 The waveform diagram of a frame of data signal of eight-channel audio input / output in one embodiment of the DMA controller of the present application applied to audio data transfer is shown.

[0020] Figure 4 A schematic diagram showing 8-channel / 32-bit audio data / 32-bit slot width output audio data transport in an embodiment of a DMA controller of the present application applied to audio data transport is shown.

[0021] Figure 5 A schematic diagram showing 8-channel / 32-bit audio data / 32-bit slot width input audio data transfer in an embodiment of a DMA controller of the present application applied to audio data transfer is shown.

[0022] Figure 6 A schematic diagram showing 8-channel / 24-bit audio data / 32-bit slot width output audio data transport in an embodiment of a DMA controller of the present application applied to audio data transport is shown.

[0023] Figure 7 A structural schematic diagram of an embodiment of a DMA controller device of the present application for audio data transfer is shown.

[0024] Figure 8 A structural schematic diagram of an embodiment of a DMA controller terminal used for audio data transfer according to the present application is shown.

[0025] Fig. 9 A schematic diagram of 8-channel / 16-bit audio data / 32-bit slot width input audio data transfer in an embodiment of a DMA controller of the present application applied to audio data transfer is shown.

[0026] Fig.10 A schematic diagram showing 8-channel / 32-bit audio data / 16-bit slot width output audio data transport in an embodiment of a DMA controller of the present application applied to audio data transport is shown.

[0027] Fig.11 A schematic diagram of 8-channel / 32-bit audio data / 16-bit slot width input audio data transfer in an embodiment of a DMA controller of the present application applied to audio data transfer is shown.

[0028] Fig.12 A flow chart of an embodiment of a DMA control method of the present application applied to audio data transfer is shown. DETAILED DESCRIPTION

[0029] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0030] Before further describing the present invention in detail, the nouns and terms involved in the embodiments of the present invention are explained. The nouns and terms involved in the embodiments of the present invention are applicable to the following interpretations:

[0031] <1> DMA controller: A hardware component that manages the transfer and storage of data within a computer without the direct involvement of the central processing unit (CPU).

[0032] <2> I2S: A protocol for audio data transmission used to connect audio devices such as audio codecs and audio processors.

[0033] <3> FIFO: A data storage structure that stores and reads data according to the first-in, first-out principle. It is used to temporarily store data to ensure the order and timing of the data.

[0034] <4> SDOUTFIFO: In the I2S system, the FIFO buffer area at the sending end is used to temporarily store audio data that needs to be sent to the sound output device (such as a speaker).

[0035] <5> SDIN FIFO: In an I2S system, a FIFO buffer at the receiving end that is used to temporarily store audio data received from a sound input device (such as a microphone).

[0036] <6> Register: A register is a hardware component used to temporarily store data in a computer. It consists of a register file, and each register stores a data value with a fixed bit width. Registers can be divided into general registers and special registers, the latter of which are used to store specific data or control information.

[0037] <7> Channel: A channel refers to a single channel of an audio signal, such as left and right channels, front and rear channels, etc., which are responsible for processing different parts of the audio signal. The number and type of channels depend on the specific design of the audio system, such as stereo (left and right channels), 5.1 channels (front, rear, left, right and center channels), etc.

[0038] <8> Data slot width: Data slot width refers to the bit width used for data transmission, that is, the number of data bits that can be accommodated in each data slot. Common data slot widths include 8 bits (byte), 16 bits (half word), 24 bits, 32 bits (whole word) and 64 bits. Different data slot widths determine the efficiency and accuracy of data transmission.

[0039] <9> Audio data cache: A buffer area used to store audio data, which is used to temporarily store audio data for easy access by an audio processor or other device.

[0040] <10> Address increment: When accessing data, the address in the base register is incremented to facilitate access to the next data location.

[0041] <11> Index auto-increment: When accessing data, the value in the index register is incremented to facilitate access to the next data location.

[0042] <12> Data shift operation: An operation that shifts data, such as shifting it left or right, to align it or perform other operations.

[0043] <13> Word: In computers, a word usually refers to a unit consisting of multiple bytes, usually 16 bits, 32 bits, or 64 bits. A word is a basic storage unit in a computer and is used to represent an integer value.

[0044] <14> Byte: In computers, a byte is a unit consisting of 8 bits, which is the smallest storage unit in computers. A word usually consists of multiple bytes.

[0045] Figure 1 is a schematic block diagram of a DMA controller for audio data transfer provided by an embodiment of the present application. Figure 1 As shown, the DMA controller includes a parameter configuration unit 101 and a data processing unit 102 .

[0046] Parameter configuration unit 101: the parameter configuration unit is communicatively connected to the control interface; the parameter configuration unit is used to receive a source address, a target address and configuration parameters through the control interface, perform parameter configuration operations on the data processing unit based on the configuration parameters, and send the source address, the target address and the configuration parameters to the data processing unit;

[0047] Data processing unit 102: The data processing unit includes a data acquisition module, a format matching module and a data handling module; the data acquisition module is communicatively connected to the parameter configuration unit and the format matching module, so as to acquire audio data from the main memory or the audio input device according to the source address; the format matching module is communicatively connected to the data acquisition module and the data handling module, so as to perform a format matching operation on the audio data according to the configuration parameters; the data handling module is communicatively connected to the format matching module, so as to perform a data handling operation on the format-matched audio data according to the target address, and to handle the format-matched audio data to the main memory or the audio output device.

[0048] Figure 2The system block diagram of the DMA (Direct Memory Access) controller described in one embodiment of the present invention applied to I2S (Inter-IC Sound) is shown. In this embodiment, four transmit data lines SDOUT[0:3] (Serial Data Output) and four receive data lines SDIN[0:3] (Serial Data Input) are included. Each transmit line SDOUT is equipped with a 16-word deep, 32-bit wide transmit FIFO buffer (First In, First Out); each receive line SDIN also has a 16-word deep, 32-bit wide receive FIFO buffer. The address and space of each FIFO are independent, and one word consists of four bytes.

[0049] In this embodiment, a serial-to-parallel conversion protocol is used between the transmit FIFO (first-in-first-out buffer) and SDOUT (transmit data output), and a serial-to-parallel conversion protocol is used between the receive FIFO (first-in-first-out buffer) and SDIN (transmit data input). The serial-to-parallel conversion protocol control is used to effectively convert between serial data and parallel data, ensuring that the data format sent through SDOUT and the data format received by SDIN are accurate and can be efficiently transmitted to the receiving end and the transmitting end.

[0050] Furthermore, in the system block diagram of I2S shown in this embodiment, MCLK (Main Clock) represents the main clock signal, which provides a driving clock for the audio codec (Codec); LRCLK (Left Right Clock) represents the frame control clock signal, which is used to identify the start of the frame and control the data of the left and right channels, that is, each data line corresponds to the audio data of the two channels; BCLK (Bit Clock) represents the bit clock signal, which is used to identify the input and output of the driving data bit. At the same time, a control register is used to configure and manage the operating status of the I2S system, and the clock control information sent by the control interface is used to set the register that generates the clock signal to flexibly adjust the clock frequency and data transmission mode. In addition, the audio-specific DMA belongs to the I2S system and is responsible for carrying audio data in the memory and I2S FIFO data.

[0051] In one embodiment of the present invention, the DMA controller also includes: a first channel, the first channel reads the audio data from the main memory through a data acquisition module, and stores the audio data in a multi-channel output register, and the data acquisition module sends the audio data to the audio output device; a second channel, the second channel receives the audio data sent by the audio input device through the data acquisition module, and stores the audio data in a multi-channel input register, and the data transfer module transfers the audio data to the main memory.

[0052] In this embodiment, the first channel and the second channel both represent data transmission paths in the DMA controller. The first channel is used to read audio data from the main memory to transfer the audio content stored in the memory to an audio output device (such as a speaker or a sound card). The second channel is used to receive audio data sent by an audio input device (such as a microphone, a musical instrument, etc.) to convert the sound signal generated in real time into digital data and transfer it to the DMA controller, and then save it in the main memory. Through this two-way data stream, the system can realize the recording and playback functions of audio.

[0053] In this embodiment, the multi-channel output register and the multi-channel input register together constitute a temporary storage unit for data in the audio system. The multi-channel output register is used to store audio data that has been read from the main memory so that it can be quickly delivered to the audio output device for playback; while the multi-channel input register is responsible for receiving audio signals from multiple input sources (such as microphones and musical instruments) and temporarily saving these signals for subsequent processing. These two registers can implement functions similar to SDOUT (serial data output) and SDIN (serial data input), where SDOUT sends processed audio data from the system to an external device, and SDIN receives audio data from the input device. With this combination, audio signals can flow seamlessly between input and output. Exemplarily, SDOUT can merge and output data from multiple audio channels into an output buffer, while SDIN receives data from different audio sources into separate input buffers, thereby ensuring efficient flow of audio data.

[0054] In one embodiment of the present invention, the multiple input registers are connected to the data handling module, each input register includes a receiving FIFO buffer area with a depth of 16 words and a width of 32 bits, corresponding to two channels of audio data of an audio input device; the input process of each frame of audio data includes taking 2 words of audio data from each input register respectively; the multiple output registers are connected to the data handling module, each output register includes a sending FIFO buffer area with a depth of 16 words and a width of 32 bits, corresponding to two channels of audio data of an audio output device; the output process of each frame of audio data includes filling 2 words of audio data into each output register respectively.

[0055] In one embodiment of the present invention, the I2S system where the DMA controller is located supports 16-bit, 24-bit and 32-bit audio data, and the configurable data slot width is 16-bit and 32-bit. Therefore, the combinations of audio data and data slot width that can be supported for transport are: encapsulating 16-bit audio data into a 16-bit data slot; encapsulating 16-bit audio data into a 32-bit data slot; encapsulating 24-bit audio data into a 32-bit data slot; encapsulating 32-bit audio data into a 32-bit data slot.

[0056] In this embodiment, I2S supports the Philips standard, the left-aligned (MSB) standard, the right-aligned (LSB) standard or the PCM standard protocol. Taking the left-aligned (MSB) standard as an example, in the non-TDM mode, a waveform of a frame of data signal of eight-channel audio input / output (data slot width is 32 bits) is shown in the figure. Figure 3 As shown in the figure, one LRCLK cycle represents one frame of audio data. Each SDOUT and SDIN channel corresponds to two channels of audio data of the speaker (SPEAKER) and microphone (MIC). Therefore, four SDOUT channels and four SDIN channels correspond to eight channels of audio data of the speaker and microphone, respectively.

[0057] Furthermore, during the output of a frame of audio data, SPEAKER needs to fill two words of audio data into each SDOUTFIFO; correspondingly, during the input of a frame of audio data, MIC needs to take out two words of audio data from each SDINFIFO. These data will interact with the memory with the help of the audio-specific DMA of the present invention. The audio-specific DMA includes two channels: channel 0 is used for SPEAKER, which is responsible for transferring the audio data (source address) in the memory to the FIFO (destination address) of each SDOUT of I2S; channel 1 is used for MIC, which is responsible for moving the data in the FIFO (source address) of each SDIN of I2S to the memory (destination address).

[0058] It can be understood that the number of transmission data lines SDOUT[0:3] and the number of reception data lines SDIN[0:3] used are determined by the number of channels and can be expressed by the following formula:

[0059] Number of SDOUT / SDIN = Number of channels / 2 (Formula 1)

[0060] Furthermore, when the slot width is 32 bits, the two-channel corresponds to SDOUT0 / SDIN0 (1 SDOUT and 1 SDIN), the four-channel corresponds to SDOUT0 / SDIN0, SDOUT1 / SDIN1 (2 SDOUT and 2 SDIN), the six-channel corresponds to SDOUT0 / SDIN0, SDOUT1 / SDIN1, SDOUT2 / SDIN2 (3 SDOUT and 3 SDIN), and the eight-channel corresponds to SDOUT0 / SDIN0, SDOUT1 / SDIN1, SDOUT2 / SDIN2, SDOUT3 / SDIN3 (4 SDOUT and 4 SDIN); when the slot width is 16 bits, the four-channel corresponds to SDOUT0 / SDIN0 (1 SDOUT and 1 SDIN), and the eight-channel corresponds to SDOUT0 / SDIN0, SDOUT1 / SDIN1 (2 SDOUT and 2 SDIN).

[0061] In an embodiment of the present invention, the configuration parameters include: one or more of the number of audio channels, data width, data slot width, and the number of audio data frames.

[0062] The parameters that can be configured for the audio-specific DMA proposed in the present invention include: the number of audio channels, audio data width, data slot width, audio data address, and the number of audio data frames. The supported number of audio channels includes 2, 4, 6, and 8 channel configurations to meet the needs of different audio applications. Secondly, the audio data width supports 16 bits, 24 bits, and 32 bits to ensure high-fidelity transmission of audio signals. The data slot width supports 16 bits and 32 bits. The configurable audio data address points to the memory address. Exemplarily, the audio data address pointed to by the first channel is the source address, and the audio data address pointed to by the second channel is the target address. The number of audio data frames refers to the amount of audio data carried by the audio-specific DMA controller proposed in the present invention. Among them, the minimum unit of data carried by the audio-specific DMA each time is a frame of audio data, and the number of bytes occupied by a frame of audio data is shown in Formula 2. Exemplarily, for 8-channel 32-bit audio data, one frame has 8*4=32 bytes of data.

[0063] The number of bytes of audio data in one frame = the number of audio channels * the width of audio data (bytes) (Formula 2)

[0064] In one embodiment of the present invention, the process of performing data transfer operations on audio data after format matching includes: after starting the first channel transmission, in response to the data amount of audio data stored in each output register being less than or equal to the output gate threshold, a DMA event is triggered, and the audio data in the main memory is transferred to each output register until each output register is filled; after starting the second channel transmission, in response to the data amount of audio data stored in each input register being greater than or equal to the input gate threshold, a DMA event is triggered, and the audio data in each input register is transferred to the main memory until each input register is cleared.

[0065] In this embodiment, the transport mechanism of the audio-specific DMA triggers a data transmission event (DMA event) by setting the FIFO threshold value. When the DMA channel 0 of the I2S system is started for audio data transmission, if the amount of data in each SDOUT FIFO is less than or equal to the threshold value of the SDOUT FIFO, the system will generate a DMA event. In this case, DMA will automatically transport the audio data from the memory to each SDOUT FIFO until the FIFO is filled. If the audio data transported for the last time is not enough to fill each FIFO, DMA will automatically stop the transmission after completing the configured number of audio data frames. Similarly, when the I2SDMA channel 1 is started for data reception, if the amount of data in each SDIN FIFO is greater than or equal to the threshold value of the SDIN FIFO, a DMA event will also be generated. At this time, DMA will transport the data in the SDIN FIFO to the memory, which is equivalent to clearing each SDIN FIFO, and will automatically stop after the configured number of audio data frames has been moved.

[0066] Furthermore, the DMA event triggering mechanism in this embodiment automatically generates an interrupt signal after the transmission of the DMA channel is completed, providing an efficient feedback mechanism. When the data transfer is completed (the configured number of audio data frames are moved), the system immediately triggers the DMA interrupt, and the user can quickly reconfigure the DMA and start a new data transfer within the DMA interrupt processing function. This optimization not only improves the efficiency of audio data transfer, but also enables the system to flexibly respond to different audio application requirements, thereby providing higher adaptability and responsiveness for various application scenarios.

[0067] In one embodiment of the present invention, the process of performing data transfer operations on format-matched audio data also includes an index increment operation, and the index increment operation includes: in response to successfully executing an operation of reading a frame of data from a source address, the source address index increases by a preset read byte amount so that the source address index points to the starting position of the next frame of data; and / or, in response to successfully executing an operation of writing a frame of data to a target address, the target address index increases by a preset write byte amount so that the target address index points to the data storage location to be written next time.

[0068] In one embodiment of the present invention, performing a data transfer operation on the format-matched audio data also includes an index reset operation, wherein the index reset operation includes: in response to all output registers being filled with a frame of data, resetting the target address index back to the first address of multiple output registers to wait for the next frame of data to be filled; and / or, in response to all input registers being filled with a frame of data, resetting the source address index back to the first address of multiple input registers to wait for the next frame of data to be read.

[0069] In one embodiment of the present invention, Figure 4 The following diagram shows the DMA data transfer from the main memory (audio data buffer) to the speaker (SD OUT FIFO) when the configuration parameters are 8 channels, 32-bit audio data, and 32-bit slot width. Figure 4 As shown in the figure, 32-bit 8-channel audio data is stored continuously in the memory. When the I2S interface and internal dedicated DMA channel 0 are enabled, the DMA will extract 8 words (32 bytes) of data from the source address of the audio data, and fill these data into each of the 4 SDOUTFIFOs in turn, filling 2 words into each channel to complete the filling of one frame of data. Subsequently, the source address data index (Index) inside the DMA will increase by 32 bytes to point to the source address of the next frame of audio data to be read.

[0070] In this embodiment, in view of the fact that the source address and destination address of DMA are constantly changing, but the change mode of the destination address is different from the address self-increment mode of the general DMA. The present invention sets up a unique index self-increment operation to properly handle the SDOUT FIFO address. Specifically, the index self-increment operation includes: during the data transmission process, each SDOUT FIFO is first filled with 2 words of data, and then an SDOUT FIFO address is incremented. Therefore, it can be understood that during the DMA operation, the 2 words (a total of 8 bytes) in a data frame will first be written to the first SDOUT FIFO. Only when the first SDOUT FIFO successfully receives the 2 words of data, will the DMA move the destination address to the second SDOUT FIFO, and then fill in the 2 words of data in turn. This process will be repeated until all SDOUT FIFOs are filled.

[0071] Furthermore, the index reset operation process includes: after completing the filling of a frame of data, the destination address of DMA will automatically return to the first address of SDOUT0 FIFO and prepare for new data filling. Since each SDOUT FIFO has a depth of 16 words, each FIFO will be filled when DMA moves 8 frames of data. When the data in the FIFO is "consumed" by the I2S interface and sent to the output device, if the filling amount of valid data in the FIFO is lower than the set threshold, DMA will automatically start and continue to move the next audio data in the memory to each SDOUT FIFO until the number of audio data frames set by DMA is moved.

[0072] In this embodiment, Figure 5 The diagram shows the DMA data transfer from the microphone (SD IN FIFO) to the main memory (audio data buffer) when the configuration parameters are 8 channels, 32-bit audio data, and 32-bit slot width. When the I2S and the second channel in the DMA controller are enabled, the DMA will extract two words of data from the four SDIN FIFOs (source address) in turn and fill them into the audio data address (destination address), thus completing the acquisition of one frame of data. At this time, the destination address data index (Index) inside the DMA will increase by 32 bytes to point to the destination address to be written to the next frame of audio data.

[0073] Furthermore, similarly, the source address and destination address of DMA will change continuously, but the change of the source address is significantly different from the traditional general DMA address self-increment mode. In this embodiment, the index self-increment operation includes: the source address SDIN FIFO will only increment an SDIN FIFO address after successfully reading two words of data; and after reading all the data of SDIN FIFO, the source address will be reset to SDIN0 FIFO address. At the same time, the data generated by I2S will be filled into SDIN FIFO.

[0074] In particular, when the amount of valid data in the FIFO exceeds the preset threshold, the DMA system will automatically start to transfer the data in each SDIN FIFO to the audio data buffer in the memory until the number of audio data frames set by the DMA is reached. If the transfer completion interrupt of the DMA channel is enabled, the system will generate a DMA interrupt signal after the data transfer is completed. After receiving the interrupt, the user can reconfigure the DMA in the DMA interrupt processing function, illustratively, by setting a new audio data address and length, and restarting the data transfer to complete the reconfiguration of the DMA controller.

[0075] Furthermore, if the transfer completion interrupt of the DMA channel is enabled, the DMA will generate an interrupt signal after the transfer is completed, prompting the user to perform subsequent operations. In the DMA interrupt processing function, the user can reconfigure the DMA, set the new audio data address and length, and restart the data transfer to ensure smooth audio playback and data processing. This design effectively utilizes the automation capability of DMA, thereby improving the efficiency and real-time performance of audio data transmission.

[0076] In one embodiment of the present invention, the process of performing a format configuration operation on the received audio data includes: in response to the data width of the audio data being smaller than the slot width of the target address, performing a data shift operation of a preset number of bits on the audio data.

[0077] Figure 6 The schematic diagram of moving data to an external device using 8 channels, 24-bit audio data, and 32-bit slot width is shown in one embodiment of the present invention. Figure 6 As shown, 24-bit 8-channel audio data is continuously stored in the memory, that is, the data width of the source address is 3 bytes, but the data width of the destination address SDOUT FIFO is 4 bytes. At this time, the data width of the audio data is less than the slot width of the target address, and a data shift operation of a preset number of bits is performed on the audio data. Specifically, the I2S audio data uses 24 bits of valid data in a 32-bit wide slot, sets the upper 24 bits (MSB) as valid bits, and forces the lower 8 bits (LSB) to be written to zero.

[0078] Furthermore, the data shift operation includes: when I2S and internal dedicated DMA channel 0 are started, DMA takes out 3 bytes of data from the audio data address each time and shifts it left by 8 bits to form a 32-bit data, which is then filled into the SDOUTFIFO. The DMA operation is performed 8 times, and the 4-channel SDOUT FIFO is filled with 8 DMA newly formed 32-bit audio data in turn (each channel is filled 2 times), and the filling of one frame of data is completed. Then, the index self-increment operation is performed, that is, the source address data index Index inside the DMA is added by 24 bytes. At this time, the preset write byte amount is 24 bytes, and it points to the source address of the next frame of audio data to be read.

[0079] Figure 7 The schematic diagram of DMA acquiring a frame of 8-channel 24-bit audio data from SDIN FIFO in one embodiment of the present invention is shown, wherein the slot width is 32 bits. The data width of the source address SDIN FIFO is 4 bytes, but the audio storage (destination address) data is 3 bytes, so only the upper 24 bits (MSB) of the SDIN FIFO data need to be stored in the memory. When I2S and internal dedicated DMA channel 1 are started, DMA takes out 2 words of data from 4-way SDIN FIFO (source address) in turn, and only fills the upper 24 bits into the audio data address (destination address), thus completing the acquisition of a frame of data. Then, the destination address data index Index inside DMA is added with 24 bytes, and the preset read byte amount is 24 bytes at this time, pointing to the destination address to be written to the next frame of audio data. Since the source address and destination address of DMA are both variable, and the source address and destination address data bit widths are different. This requires that the audio-specific DMA must not only handle the self-increment mode of the SDIN FIFO address, but also support 24-bit data width reading / writing. Therefore, this embodiment uses the data shift operation to right-shift the 32-bit number by 8 bits to convert it into 24-bit data writing. At this time, the preset number of bits is 8 bits. The data "produced" by I2S will be filled into the SDIN FIFO. When the FIFO valid data filling amount is higher than the set FIFO threshold value, DMA will automatically start to move the data of each SDIN FIFO to the memory audio data Buffer until the number of audio data frames set by DMA is moved. If the transmission completion interrupt of the DMA channel is enabled, a DMA interrupt will be generated after the transfer is completed. The user can reconfigure the DMA in the DMA interrupt processing function, such as setting a new audio data address and length, and restarting the transmission.

[0080] Figure 8The schematic diagram of DMA filling a frame of 8-channel 16-bit audio data into SDOUT FIFO in one embodiment of the present invention is shown, wherein the slot width is 32 bits. The 16-bit 8-channel audio data is stored continuously in the memory, that is, the data width of the source address is 2 bytes, but the data width of the destination address SDOUT FIFO is 4 bytes. That is, 16 bits of valid data are used in the 32-bit wide slot of I2S audio data, the upper 16 bits (MSB) are valid bits, and the lower 16 bits (LSB) are forced to write zero. When I2S and internal dedicated DMA channel 0 are started, DMA takes out 2 bytes of data from the audio data address each time and shifts it left by 16 bits to form a 32-bit data, which is then filled into the SDOUT FIFO. The DMA operates 8 times, and fills the 4 SDOUT FIFOs with 8 newly constructed 32-bit audio data in turn (each channel is filled twice), thus completing the filling of one frame of data. Then the source address data index Index inside the DMA is increased by 16 bytes. At this time, the preset write byte amount is 16 bytes, pointing to the source address of the next frame of audio data to be read.

[0081] like Figure 8 As shown, the source address and destination address of DMA are both changed, but the destination address is different from the change of the general DMA address self-increment mode, and the data bit width of the source address and the destination address are also different. This requires that the audio-specific DMA must not only handle the self-increment mode of the SDOUT FIFO address. In this embodiment, the process of the data shift operation includes: performing a data shift operation on the 16-bit data width read data to convert the 16-bit data into 32-bit data, and then carrying the data. Specifically, the 16-bit data is shifted left by 16 bits to obtain a 32-bit value, the upper 16 bits are the original 16-bit data, and the lower 16 bits are zero. At this time, the preset number of bits is 16 bits.

[0082] Furthermore, since each SDOUT FIFO has a 16-word depth, the DMA will be filled after transferring 8 frames of data. When the data in the FIFO is "consumed" by I2S and the amount of valid data in the FIFO is lower than the set FIFO threshold, the DMA will automatically start to move the audio data in the memory to each SDOUT FIFO until the number of audio data frames set by the DMA is moved. If the transfer completion interrupt of the DMA channel is enabled, a DMA interrupt will be generated after the transfer is completed. The user can reconfigure the DMA in the DMA interrupt processing function, such as setting a new audio data address and length, and restarting the transfer.

[0083] Correspondingly, Fig. 9The schematic diagram of DMA acquiring a frame of 8-channel 16-bit audio data from SDIN FIFO in this embodiment is shown, wherein the slot width is 32 bits. The data width of the source address SDIN FIFO is 4 bytes, but the audio storage (destination address) data is 2 bytes, so only the upper 16 bits (MSB) of the SDIN FIFO data need to be stored in the memory. When I2S and internal dedicated DMA channel 1 are started, DMA takes out 2 words of data from the 4-way SDIN FIFO (source address) in turn, and only fills the upper 16 bits into the audio data address (destination address), completing the acquisition of a frame of data, and then the destination address data index Index inside DMA is added by 16 bytes. At this time, the preset read byte amount is 16 bytes, pointing to the destination address to be written to the next frame of audio data. And the 32-bit number is converted into 16-bit data for writing. The data "produced" by I2S will be filled into the SDIN FIFO. When the amount of valid data in the FIFO is higher than the set FIFO threshold, DMA will automatically start to move the data of each SDIN FIFO to the memory audio data buffer until the number of audio data frames set by DMA is moved. If the transfer completion interrupt of the DMA channel is enabled, a DMA interrupt will be generated after the transfer is completed. The user can reconfigure DMA in the DMA interrupt processing function, such as setting a new audio data address and length, and restarting the transfer.

[0084] Fig.10 The following is a schematic diagram showing how DMA fills a frame of 8-channel 16-bit audio data into SDOUTFIFO when there are 8 channels, 16-bit audio data, and 16-bit slot width in one embodiment of the present invention (slot width 16 bits). In this embodiment, 16-bit audio data is encapsulated in a 16-bit slot channel. Since both SDOUT / SDIN FIFOs are 32 bits, data of 2 slot channels will be stored in a word-deep FIFO. With one LRCLK, each SDOUT / SDIN will consume / generate 2 word-deep data. Therefore, corresponding to four-channel data, 2 SDOUT / SDIN channels can achieve eight channels.

[0085] like Fig.10As shown in the figure, 6-bit 8-channel audio data is stored continuously in the memory, that is, the data width of the source address is 2 bytes and the slot width is also 2 bytes, but the data width of the destination address SDOUT FIFO is 4 bytes, so the data of the two slot channels constitute 4 bytes and can be directly written into the SDOUT FIFO. When I2S and internal dedicated DMA channel 0 are started, DMA takes out 4 words (16 bytes) of data from the audio data address (source address), and fills 4 words of data into the two SDOUT FIFOs in turn (each channel is filled twice), thus completing the filling of one frame of data. Then the source address data index Index inside DMA is added by 16 bytes, and the preset write byte amount is 16 bytes at this time, pointing to the source address of the next frame of audio data to be read. I2S only has 2 SDOUT signals, corresponding to the use of 2 FIFOs. The source address and destination address of DMA are both variable, but the data bit width of the source address and destination address is the same. The audio-specific DMA performs index increment operation based on the SDOUT FIFO address. Since each SDOUT FIFO has a 16-word depth, the DMA will be filled after transferring 8 frames of data. When the data in the FIFO is "consumed" by I2S and the amount of valid data in the FIFO is lower than the set FIFO threshold, the DMA will automatically start to move the audio data in the memory to each SDOUTFIFO until the number of audio data frames set by the DMA is moved. If the transfer completion interrupt of the DMA channel is enabled, a DMA interrupt will be generated after the transfer is completed. The user can reconfigure the DMA in the DMA interrupt processing function, such as setting a new audio data address and length, and restarting the transfer.

[0086] Correspondingly, Fig.11The schematic diagram of DMA acquiring a frame of 8-channel 16-bit audio data from SDIN FIFO (slot width 16 bits) in one embodiment of the present invention is shown. The data width of the source address SDIN FIFO is 4 bytes and contains data of 2 slot channels. The audio storage (destination address) data is 2 bytes, so it is only necessary to store the SDIN FIFO data in units of 4 bytes into the memory. When I2S and internal dedicated DMA channel 1 are started, DMA sequentially takes out 2 words of data from 2-way SDIN FIFO (source address) and fills them into the audio data address (destination address), thus completing the acquisition of a frame of data. Then the destination address data index Index inside DMA is added by 16 bytes. At this time, the preset read byte amount is 16 bytes, pointing to the destination address to be written to the next frame of audio data. The source address and destination address of DMA are both variable, but the data bit width of the source address and destination address are the same. The audio-dedicated DMA only needs to handle the self-increment mode of the SDOUT FIFO address. The data "produced" by I2S will be filled into the SDIN FIFO. When the amount of valid data in the FIFO is higher than the set FIFO threshold, DMA will automatically start to move the data of each SDIN FIFO to the memory audio data buffer until the number of audio data frames set by DMA is moved. If the transfer completion interrupt of the DMA channel is enabled, a DMA interrupt will be generated after the transfer is completed. The user can reconfigure DMA in the DMA interrupt processing function, such as setting a new audio data address and length, and restarting the transfer.

[0087] The above embodiments demonstrate the flexibility and adaptability of the I2S interface in processing audio data of different bit widths, including multiple ways of encapsulating 16-bit audio data into 16-bit and 32-bit slots, 24-bit data into 32-bit slots, and 32-bit data into 32-bit slots, thereby ensuring efficient data transmission and compatibility.

[0088] It should be noted that the above examples are all eight-channel audio data. For other numbers of channels, such as dual-channel, four-channel, and six-channel, the difference is that the data amount of the SDOUT and SDIN signals used is different, and the data amount of one frame of audio data is different. Exemplarily, when the slot width is 32 bits, the dual-channel corresponds to SDOUT0 / SDIN0, the four-channel corresponds to SDOUT0 / SDIN0, SDOUT1 / SDIN1, the six-channel corresponds to SDOUT0 / SDIN0, SDOUT1 / SDIN1, SDOUT2 / SDIN2, and the eight-channel corresponds to SDOUT0 / SDIN0, SDOUT1 / SDIN1, SDOUT2 / SDIN2, and SDOUT3 / SDIN3; when the slot width is 16 bits, the four-channel corresponds to SDOUT0 / SDIN0, and the eight-channel corresponds to SDOUT0 / SDIN0, SDOUT1 / SDIN1.

[0089] Through the audio-specific DMA controller and the corresponding control method proposed by the present invention, the address and quantity of SDOUT FIFO and SDIN FIFO can be automatically adjusted according to the channel number parameter configuration. According to the above embodiment, the working conditions of the audio-specific DMA for other channels can be inferred by the same logic. It should be noted that the embodiments given in the present invention are only used for explanation and are not used to limit the scope of application of the present invention. In fact, the present invention can also be applied to other channel configurations, and has adaptive capabilities, and can flexibly adjust the addresses and quantities of SDOUT FIFO and SDIN FIFO to meet different application requirements.

[0090] To facilitate understanding of the embodiments of the present application, first Fig.12 Detailed description. Fig.12 The flowchart of a DMA control method for audio data transfer in an embodiment of the present invention is shown. The DMA control method for audio data transfer in this embodiment mainly includes the following steps:

[0091] Step S121: receiving a source address, a target address, and configuration parameters, and performing a parameter configuration operation based on the configuration parameters;

[0092] Step S122: Acquire audio data from the main memory or the audio input device according to the source address;

[0093] Step S123: performing a format matching operation on the audio data according to the configuration parameters;

[0094] Step S124: performing a data transfer operation on the format-matched audio data according to the target address, and transferring the format-matched audio data to the main memory or the audio output device.

[0095] It should be understood that the specific process of each module executing the above corresponding steps has been described in detail in the above method embodiment, and for the sake of brevity, it will not be repeated here.

[0096] It should also be understood that the division of modules in the embodiments of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation. In addition, each functional module in each embodiment of the present application may be integrated into a processor, or may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated modules may be implemented in the form of hardware or in the form of software functional modules.

[0097] In the embodiments of the present application, words such as "first" and "second" are used to distinguish the same or similar items with substantially the same functions and effects. For example, the first channel and the second channel are only used to distinguish different channels, and do not limit their order. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit them to be different.

[0098] It should be noted that in the embodiments of the present application, words such as "exemplary" or "for example" represent examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0099] In the embodiments of the present application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, ab, ac, bc or abc, where a, b, c can be single or multiple.

[0100] Those of ordinary skill in the art will appreciate that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0101] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, DMA controller and unit can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0102] In the several embodiments provided in the present application, it should be understood that the disclosed system, DMA controller and method can be implemented in other ways. For example, the DMA controller embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the DMA controller or unit can be electrical, mechanical or other forms.

[0103] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0104] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0105] In the above embodiments, the functions of each functional unit can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When loading and executing computer program instructions (programs) on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (Digital Subscriber Line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server, data center, etc. that contains one or more available media integrated. Available media may be magnetic media (e.g., floppy disks, hard disks, tapes), optical media (e.g., high-density digital video discs (DVDs), or semiconductor media (e.g., solid state disks (SSDs)).

[0106] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0107] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0108] In summary, the present application provides a DMA controller, a control method and an I2S system for audio data transfer. The present invention provides a method for improving the flexibility of the DMA controller and the efficiency of audio data transmission. By introducing an audio-specific DMA controller, the bottleneck that multi-channel audio data and 24-bit audio data cannot be transmitted through general DMA is effectively solved. The present invention supports a variety of audio data formats and can intelligently and automatically select the best DMA data transmission strategy based on specific configuration information such as the number of channels, audio data width and slot width. This innovation not only significantly improves the efficiency and flexibility of audio data transmission, but also greatly reduces the burden on the CPU during data transfer, allowing it to concentrate computing power to process more complex tasks, thereby improving overall system performance. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0109] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A DMA controller for audio data transfer, characterized in that: include: Parameter configuration unit: the parameter configuration unit is communicatively connected to the control interface; the parameter configuration unit is used to receive the source address, the target address and the configuration parameters through the control interface, perform parameter configuration operations on the data processing unit based on the configuration parameters, and send the source address, the target address and the configuration parameters to the data processing unit; Data processing unit: The data processing unit includes a data acquisition module, a format matching module and a data handling module; the data acquisition module is communicatively connected to the parameter configuration unit and the format matching module, so as to acquire audio data from the main memory or the audio input device according to the source address; the format matching module is communicatively connected to the data acquisition module and the data handling module, so as to perform a format matching operation on the audio data according to the configuration parameters; the data handling module is communicatively connected to the format matching module, so as to perform a data handling operation on the format-matched audio data according to the target address, and to handle the format-matched audio data to the main memory or the audio output device.

2. The DMA controller for audio data transfer according to claim 1, characterized in that: The DMA controller further includes: A first channel, wherein the first channel reads the audio data from the main memory through a data acquisition module and stores the audio data in a multi-channel output register, and the data acquisition module sends the audio data to the audio output device; The second channel receives the audio data sent by the audio input device through the data acquisition module and stores the audio data in the multi-channel input register, and the data transport module transports the audio data to the main memory.

3. The DMA controller for audio data transfer according to claim 2, characterized in that: include: The multi-channel input register is connected to the data handling module, and each input register includes a receiving FIFO buffer area with a depth of 16 words and a width of 32 bits, corresponding to two channels of audio data of an audio input device; The input process of each frame of audio data includes taking 2 words of audio data from each input register; The multi-channel output register is connected to the data handling module, and each output register includes a 16-word-deep and 32-bit-wide transmit FIFO buffer corresponding to two-channel audio data of an audio output device; The output process of each frame of audio data includes filling 2 words of audio data into each output register.

4. The DMA controller for audio data transfer according to claim 2, characterized in that: The process of performing data handling operations on the audio data after format matching includes: After the first channel transmission is started, a DMA event is triggered in response to the data amount of the audio data stored in each output register being less than or equal to the output gate threshold, and the audio data in the main memory is moved to each output register until each output register is filled; After the second channel transmission is started, a DMA event is triggered in response to the amount of audio data stored in each input register being greater than or equal to the input gate threshold, and the audio data in each input register is moved to the main memory until each input register is cleared.

5. The DMA controller for audio data transfer according to claim 4, characterized in that: The process of performing data handling operations on the audio data after format matching also includes an index increment operation, and the index increment operation includes: In response to successfully executing the operation of reading a frame of data from the source address, the source address index is increased by a preset read byte amount so that the source address index points to the starting position of the next frame of data; And / or, in response to successfully executing the operation of writing a frame of data to the target address, the target address index is increased by a preset write byte amount so that the target address index points to a data storage location to be written next time.

6. The DMA controller for audio data transfer according to claim 4, characterized in that: The data handling operation performed on the audio data after the format is matched also includes an index reset operation, and the index reset operation includes: In response to all output registers being filled with one frame of data, resetting the target address index back to the first address of the plurality of output registers to wait for the filling of the next frame of data; And / or, in response to all input registers being filled with a frame of data, the source address index is reset back to the first address of the plurality of input registers, waiting for the reading of the next frame of data.

7. The DMA controller for audio data transfer according to claim 2, characterized in that: The process of performing a format configuration operation on the received audio data includes: in response to a data width of the audio data being smaller than a slot width of a target address, performing a data shift operation of a preset number of bits on the audio data.

8. The DMA controller for audio data transfer according to claim 1, characterized in that: The configuration parameters include: one or more of the number of audio channels, data width, data slot width, and the number of audio data frames.

9. A DMA control method for audio data transfer, characterized in that: The method is applied to a DMA controller, and the method comprises: Receiving a source address, a target address, and configuration parameters, and performing a parameter configuration operation based on the configuration parameters; Acquire audio data from a main memory or an audio input device according to the source address; Performing a format matching operation on the audio data according to the configuration parameters; A data transfer operation is performed on the audio data after the format is matched according to the target address, and the audio data after the format is matched is transferred to the main memory or the audio output device.

10. An I2S system, characterized in that: The system comprises: a DMA controller for audio data transfer according to any one of claims 1 to 8.

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