Butterfly operation unit and butterfly operation unit array

Abstract

The invention provides a butterfly operation unit and a butterfly operation unit array. The butterfly operation unit comprises a modular multiplication operation module, a modular subtraction operation module and a modular addition operation module, in the first operation mode, the modular multiplication operation module performs modular subtraction on the first coefficient and the second coefficient, performs modular multiplication on a modular multiplication 1 / 2 result of a modular subtraction result and a twiddle factor, and outputs a second modular multiplication operation result; the modular addition operation module performs modular addition on the first coefficient and the second coefficient to obtain a second modular addition operation result and outputs a modular multiplication 1 / 2 result of the second modular addition operation result; in the second operation mode, the modular multiplication operation module performs modular multiplication on the second coefficient and the twiddle factor to output a first modular multiplication operation result, and the modular subtraction operation module performs modular subtraction on the first coefficient and the first modular multiplication operation result to output a first modular subtraction operation result; and the modular addition operation module performs modular addition on the first coefficient and the first modular multiplication operation result and outputs a first modular addition operation result. The butterfly operation unit can improve the calculation speed of polynomial matrix-vector multiplication operation.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a butterfly operation unit and a butterfly operation unit array. Background Art

[0002] Public key cryptography has gradually become the underlying supporting technology of the modern information society, providing security for systems and their data. However, the widely used public key cryptographic protocols will become insecure due to the rise of quantum computers. In response, the industry has launched the Post-quantum Cryptography (PQC) standardization process to establish quantum-safe public key cryptographic standards for the next generation of cryptographic systems.

[0003] Among them, the two lattice-based algorithms, Kyber key encapsulation mechanism and Dilithium digital signature scheme, are used as quantum-safe public key cryptography standards. The security foundations of Kyber and Dilithium are both based on the Modular Learning-With-Error (MLWE) problem, so both algorithms involve polynomial matrix-vector multiplication operations, which contain a large number of polynomial multiplication operations and polynomial accumulation operations on polynomial rings, where the point-by-point addition, subtraction, and multiplication operations of polynomial coefficients are defined on finite fields. As the main standards for post-quantum cryptographic algorithms, the common performance bottleneck of Kyber and Dilithium is the computational speed bottleneck when executing polynomial matrix-vector multiplication operations through computer CPUs. Summary of the invention

[0004] In view of the above technical status, the present application proposes a butterfly operation unit and a butterfly operation unit array, which can improve the calculation speed of polynomial matrix-vector multiplication operations.

[0005] In a first aspect, the present application provides a butterfly operation unit, comprising:

[0006] A modular multiplication operation module, a modular subtraction operation module and a modular addition operation module;

[0007] Wherein, in the first operation mode, the modular multiplication operation module performs a modular subtraction operation on the received first coefficient and the second coefficient to obtain a modular subtraction result, performs a modular multiplication operation on a modular multiplication 1 / 2 result of the modular subtraction result and a rotation factor to output a second modular multiplication operation result, the modular subtraction operation module receives the second modular multiplication operation result and outputs the second modular multiplication operation result, the modular addition operation module performs a modular addition operation on the received first coefficient and the second coefficient to obtain a second modular addition operation result, and outputs a modular multiplication 1 / 2 result of the second modular addition operation result;

[0008] or,

[0009] In the second operation mode, the modular multiplication operation module performs a modular multiplication operation on the received second coefficient and the rotation factor and outputs a first modular multiplication operation result, the modular subtraction operation module performs a modular subtraction operation on the received first coefficient and the first modular multiplication operation result and outputs a first modular subtraction operation result, and the modular addition operation module performs a modular addition operation on the received first coefficient and the first modular multiplication operation result and outputs a first modular addition operation result.

[0010] In some implementations, the modular multiplication operation module includes:

[0011] A first modular subtractor, a first modular multiplier 1 / 2, and a modular multiplier;

[0012] The first modular subtractor performs a modular subtraction operation on the received first coefficient and the second coefficient and outputs a modular subtraction result, and the first modular multiplier 1 / 2 operates on the modular subtraction result and outputs a modular multiplication 1 / 2 result of the modular subtraction result;

[0013] The modular multiplier performs a modular multiplication operation on the received second coefficient and the rotation factor to output a first modular multiplication operation result, or performs a modular multiplication operation on a 1 / 2 result of the modular subtraction result and the rotation factor to output a second modular multiplication operation result.

[0014] In some implementations, the modular multiplication operation module further includes a first multiplexer;

[0015] The first input end of the first multiplexer is connected to the output end of the first modular multiplier 1 / 2, the second input end of the first multiplexer is connected to the input end of the second coefficient, and the output end of the first multiplexer is connected to the input end of the modular multiplier;

[0016] The control port of the first multiplexer is connected to the input terminal of the selection control signal. In the first operation mode, the control port of the first multiplexer receives the first selection control signal, and the first input terminal of the first multiplexer is connected to the output terminal of the first multiplexer; in the second operation mode, the control port of the first multiplexer receives the second selection control signal, and the second input terminal of the first multiplexer is connected to the output terminal of the first multiplexer.

[0017] In some implementations, the modular addition operation module includes:

[0018] A modular adder and a second modular multiplier 1 / 2;

[0019] The modular adder performs a modular addition operation on the received first coefficient and the first modular multiplication operation result to output a first modular addition operation result, or performs a modular addition operation on the received first coefficient and the second coefficient to obtain a second modular addition operation result;

[0020] The second modular multiplier 1 / 2 performs a modular multiplication 1 / 2 operation on the modular addition operation result output by the modular adder and outputs a modular multiplication 1 / 2 result of the modular addition operation result.

[0021] In some implementations, the modular addition operation module further includes:

[0022] a second multiplexer and a third multiplexer;

[0023] The first input end of the second multiplexer is connected to the input end of the second coefficient, the second input end of the second multiplexer is connected to the output end of the modular multiplication operation module, and the output end of the second multiplexer is connected to the input end of the modular adder;

[0024] The first input end of the third multiplexer is connected to the output end of the second modular multiplier 1 / 2, and the second input end of the third multiplexer is connected to the output end of the modular adder;

[0025] The control port of the second multiplexer and the control port of the third multiplexer are respectively connected to the gating control signal input terminal;

[0026] In the first operation mode, the control port of the second multiplexer and the control port of the third multiplexer respectively receive the first selection control signal, the first input end of the second multiplexer is connected to the output end of the second multiplexer, and the first input end of the third multiplexer is connected to the output end of the third multiplexer;

[0027] In the second operation mode, the control port of the second multiplexer and the control port of the third multiplexer respectively receive a second selection control signal, the second input end of the second multiplexer is connected to the output end of the second multiplexer, and the second input end of the third multiplexer is connected to the output end of the third multiplexer.

[0028] In some implementations, the modular subtraction operation module includes:

[0029] A second modular subtractor, configured to perform a modular subtraction operation on the received first coefficient and the first modular multiplication operation result to output a first modular subtraction operation result;

[0030] The control port of the second modulus subtractor is connected to the subtraction control signal input terminal;

[0031] In the second operation mode, the control port of the second modular subtractor receives a first subtraction control signal, and the subtractor calculates the difference between the first coefficient and the first modular multiplication result to obtain a first modular subtraction result.

[0032] In some implementations, the modular subtraction operation module further includes a fourth multiplexer;

[0033] The first input end of the fourth multiplexer is connected to the output end of the modular multiplication operation module, and the second input end of the fourth multiplexer is connected to the output end of the second modular subtraction device;

[0034] The control port of the fourth multiplexer is connected to the gating control signal input terminal;

[0035] In the first operation mode, the control port of the fourth multiplexer receives a first selection control signal, and the first input terminal of the fourth multiplexer is connected to the output terminal of the fourth multiplexer;

[0036] In the second operation mode, the control port of the fourth multiplexer receives a second selection control signal, and the second input terminal of the fourth multiplexer is connected to the output terminal of the fourth multiplexer.

[0037] In some implementations, the method further includes:

[0038] A first register and a second register;

[0039] The input end of the first register is connected to the output end of the analog addition operation module, and is used to optimize the timing of the output signal of the analog addition operation module;

[0040] The input end of the second register is connected to the output end of the analog subtraction operation module, and is used to optimize the timing of the output signal of the analog subtraction operation module.

[0041] A second aspect of the present application provides a butterfly operation unit array, comprising:

[0042] A first multiplexer component, a second multiplexer component, a first butterfly operation unit and a second butterfly operation unit, wherein the first butterfly operation unit and the second butterfly operation unit both adopt the structure of the above-mentioned butterfly operation unit; the first multiplexer component and the second multiplexer component respectively include a plurality of cascaded multiplexers;

[0043] The first multiplexer component is connected to the first butterfly operation unit, and the second multiplexer component is connected to the second butterfly operation unit;

[0044] When the first butterfly operation unit and the second butterfly operation unit are in the second operation mode, the first multiplexer component inputs the i-th first coefficient and the i-th second coefficient into the first butterfly operation unit, and the first butterfly operation unit performs at least one of modular addition, modular subtraction and modular multiplication on the i-th first coefficient and the i-th second coefficient; the second multiplexer component inputs the i+1-th first coefficient and the i+1-th second coefficient into the second butterfly operation unit, and the second butterfly operation unit performs at least one of modular addition, modular subtraction and modular multiplication on the i+1-th first coefficient and the i+1-th second coefficient; i is a positive integer.

[0045] In some implementations, the butterfly operation unit array further includes:

[0046] Alternatively, when the first butterfly operation unit and the second butterfly operation unit are in the second operation mode, the first multiplexer component inputs the accumulated sum of the i-th first coefficient, the i-th second coefficient and the first i-th first coefficient and the second coefficient into the first butterfly operation unit, and the first butterfly operation unit performs a modular multiplication and accumulation operation on the accumulated sum of the i-th first coefficient, the i-th second coefficient and the first i-th first coefficient and the second coefficient; the second multiplexer component inputs the accumulated sum of the i+1-th first coefficient, the i+1-th second coefficient and the first i+1-th first coefficient and the second coefficient into the second butterfly operation unit, and the second butterfly operation unit performs a modular multiplication and accumulation operation on the accumulated sum of the i+1-th first coefficient, the i+1-th second coefficient and the first i+1-th first coefficient and the second coefficient.

[0047] In some implementations, the butterfly operation unit array further includes:

[0048] a third butterfly operation unit, a fourth butterfly operation unit, a fifth butterfly operation unit and a sixth butterfly operation unit; the third butterfly operation unit, the fourth butterfly operation unit, the fifth butterfly operation unit and the sixth butterfly operation unit all adopt the structure of the above-mentioned butterfly operation unit;

[0049] The first coefficient input terminal of the third butterfly operation unit is connected to the output terminal of the modular subtraction operation module of the first butterfly operation unit, and the second coefficient input terminal of the third butterfly operation unit is connected to the output terminal of the modular subtraction operation module of the second butterfly operation unit;

[0050] The first coefficient input terminal of the fourth butterfly operation unit is connected to the output terminal of the modular subtraction operation module of the first butterfly operation unit and the output terminal of the modular subtraction operation module of the second butterfly operation unit, and the second coefficient input terminal of the fourth butterfly operation unit is connected to the output terminal of the modular addition operation module of the second butterfly operation unit;

[0051] The first coefficient input terminal of the fifth butterfly operation unit is connected to the output terminal of the modular addition operation module of the third butterfly operation unit;

[0052] The first coefficient input terminal of the sixth butterfly operation unit is connected to the output terminal of the modular subtraction operation module of the fourth butterfly operation unit;

[0053] When the first butterfly operation unit and the second butterfly operation unit are in the third operation mode and the control ports of the modulo subtractors of the third butterfly operation unit and the fourth butterfly operation unit receive a second subtraction control signal, the first multiplexer component inputs the 2i-th first coefficient, the 2i-th second coefficient and the 2i+1-th first coefficient into the first butterfly operation unit, and the second multiplexer component inputs the 2i-th second coefficient, the 2i+1-th first coefficient and the 2i+1-th second coefficient into the second butterfly operation unit, and the butterfly operation unit array performs a fundamental modulo multiplication and accumulation operation on the first coefficient and the second coefficient.

[0054] In some implementations, the first multiple selector component includes:

[0055] The fifth multiplexer, the sixth multiplexer, the seventh multiplexer, the eighth multiplexer, the ninth multiplexer, and the tenth multiplexer;

[0056] The first input end of the fifth multiplexer is connected to the cumulative sum signal input end of the first i first coefficients and the second coefficients, the second input end of the fifth multiplexer is connected to the 0 signal input end, and the output end of the fifth multiplexer is connected to the first input end of the sixth multiplexer;

[0057] The output end of the sixth multiple selector is connected to the first coefficient input end of the first butterfly operation unit, and the second input end of the sixth multiple selector is connected to the output end of the seventh multiple selector;

[0058] The first input end of the seventh multiple selector is connected to the input end of the i-th first coefficient, and the second input end of the seventh multiple selector is connected to the input end of the 2i+1-th first coefficient;

[0059] The first input terminal of the eighth multiplexer is connected to the 1 signal input terminal, the second input terminal of the eighth multiplexer is connected to the input terminal of the 2i-th second coefficient, and the output terminal of the eighth multiplexer is connected to the second input terminal of the ninth multiplexer;

[0060] The first input end of the ninth multiplexer is connected to the input end of the i-th first coefficient, and the output end of the ninth multiplexer is connected to the rotation factor input end of the first butterfly operation unit;

[0061] The first input end of the tenth multiple selector is connected to the input end of the i-th second coefficient, the second input end of the tenth multiple selector is connected to the input end of the 2i-th first coefficient, and the output end of the tenth multiple selector is connected to the input end of the second coefficient of the first butterfly operation unit;

[0062] When the control ports of the fifth multiplexer, the sixth multiplexer, the seventh multiplexer, the eighth multiplexer, the ninth multiplexer and the tenth multiplexer receive the first selection control signal, the second input terminals of the control ports are connected to their output terminals; when the control ports of the fifth multiplexer, the sixth multiplexer, the seventh multiplexer, the eighth multiplexer, the ninth multiplexer and the tenth multiplexer receive the second selection control signal, the first input terminals of the control ports are connected to their output terminals.

[0063] In some implementations, the second multiplexer component includes:

[0064] The eleventh multiplexer, the twelfth multiplexer, the thirteenth multiplexer, the fourteenth multiplexer, the fifteenth multiplexer, and the sixteenth multiplexer;

[0065] The first input end of the eleventh multiple selector is connected to the cumulative sum signal input end of the first i+1 first coefficients and the second coefficients, the second input end of the eleventh multiple selector is connected to the 0 signal input end, and the output end of the eleventh multiple selector is connected to the first input end of the twelfth multiple selector;

[0066] The output end of the twelfth multiple selector is connected to the first coefficient input end of the second butterfly operation unit, and the second input end of the twelfth multiple selector is connected to the output end of the thirteenth multiple selector;

[0067] The first input end of the thirteenth multiple selector is connected to the input end of the (i+1)th first coefficient, and the second input end of the thirteenth multiple selector is connected to the input end of the (2i)th second coefficient;

[0068] The first input end of the fourteenth multiplexer is connected to the 1 signal input end, the second input end of the fourteenth multiplexer is connected to the input end of the 2i+1th first coefficient, and the output end of the fourteenth multiplexer is connected to the second input end of the fifteenth multiplexer;

[0069] The first input end of the fifteenth multiple selector is connected to the input end of the (i+1)th first coefficient, and the output end of the fifteenth multiple selector is connected to the rotation factor input end of the second butterfly operation unit;

[0070] The first input end of the sixteenth multiple selector is connected to the input end of the i+1th second coefficient, the second input end of the sixteenth multiple selector is connected to the input end of the 2i+1th second coefficient, and the output end of the sixteenth multiple selector is connected to the input end of the second coefficient of the second butterfly operation unit;

[0071] When the control ports of the eleventh multiplexer, the twelfth multiplexer, the thirteenth multiplexer, the fourteenth multiplexer, the fifteenth multiplexer and the sixteenth multiplexer receive the first selection control signal, the second input end and the output end thereof are connected; when the control ports of the eleventh multiplexer, the twelfth multiplexer, the thirteenth multiplexer, the fourteenth multiplexer, the fifteenth multiplexer and the sixteenth multiplexer receive the second selection control signal, the first input end and the output end thereof are connected.

[0072] In some implementations, the butterfly operation unit array further includes an independent modular adder,

[0073] The first coefficient input terminal of the fourth butterfly operation unit is connected to the output terminal of the modular subtraction operation module of the first butterfly operation unit and the output terminal of the modular subtraction operation module of the second butterfly operation unit, including:

[0074] The output end of the modular subtraction module of the first butterfly operation unit and the output end of the modular subtraction module of the second butterfly operation unit are connected to the input end of the independent modular adder, and the output end of the independent modular adder is connected to the first coefficient input end of the fourth butterfly operation unit.

[0075] In some implementations, further comprising a seventeenth multiplexer, an eighteenth multiplexer, a nineteenth multiplexer, and a twentieth multiplexer;

[0076] The first input end of the seventeenth multiple selector is connected to the input end of the cumulative sum signal of the first 2i first coefficients and the second coefficients, and the second input end of the seventeenth multiple selector is connected to the input end of the 0 signal;

[0077] The first input end of the eighteenth multiplexer is connected to the input end of the cumulative sum signal of the first 2i+1 first coefficients and the second coefficients, and the second input end of the seventeenth multiplexer is connected to the input end of the 0 signal;

[0078] The first input end of the nineteenth multiplexer is connected to the output end of the modular addition operation module of the first butterfly operation unit, the second input end of the nineteenth multiplexer is connected to the output end of the modular subtraction operation module of the first butterfly operation unit, and the third input end of the nineteenth multiplexer is connected to the output end of the modular addition operation module of the fifth butterfly operation unit;

[0079] The first input end of the 20th multiple selector is connected to the output end of the modular addition operation module of the second butterfly operation unit, the second input end of the 20th multiple selector is connected to the output end of the modular subtraction operation module of the second butterfly operation unit, and the third input end of the 20th multiple selector is connected to the output end of the modular addition operation module of the sixth butterfly operation unit;

[0080] When the control ports of the seventeenth multiple selector and the eighteenth multiple selector receive the first selection control signal, the second input end thereof is connected to the output end thereof; when the control ports of the seventeenth multiple selector and the eighteenth multiple selector receive the second selection control signal, the first input end thereof is connected to the output end thereof;

[0081] When the control ports of the nineteenth multiplexer and the twenty-third multiplexer receive the first selection control signal, the second input terminal and the output terminal thereof are connected; when the control ports of the nineteenth multiplexer and the twenty-third multiplexer receive the second selection control signal, the first input terminal and the output terminal thereof are connected; when the control ports of the nineteenth multiplexer and the twenty-third multiplexer receive the third selection control signal, the third input terminal and the output terminal thereof are connected.

[0082] The butterfly operation unit proposed in this application can realize the operation of the NTT algorithm, specifically, it can realize the CT butterfly operation of NWC-NTT, and it can also realize the GS butterfly operation of NWC-inverse NTT. Therefore, using the butterfly operation unit to perform polynomial matrix-vector multiplication operations can reduce the computational complexity, realize hardware acceleration of NTT operations, and improve the computational speed of polynomial matrix-vector multiplication operations.

[0083] In addition, the present application cascades multiple of the above-mentioned butterfly operation units to form a butterfly operation unit array. Under the control after control absorption, the butterfly operation unit array can perform polynomial operations on a finite field used in various lattice post-quantum cryptography, including modular addition, modular subtraction, modular multiplication, and complex BMA operations, thereby further improving the utilization rate of computing resources in the butterfly operation unit and expanding the application scope of the butterfly operation unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0084] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0085] Figure 1 A schematic diagram of the structure of a butterfly operation unit provided in an embodiment of the present application.

[0086] Figure 2 A schematic diagram of the structure of another butterfly operation unit provided in an embodiment of the present application.

[0087] Figure 3 A schematic diagram of the structure of a butterfly operation unit array provided in an embodiment of the present application.

[0088] Figure 4 The BMA2 operation data flow diagram provided for the embodiment of the present application. DETAILED DESCRIPTION

[0089] Public key cryptography has gradually become the underlying supporting technology of the modern information society, providing security for systems and their data. However, the widely used public key cryptographic protocols will become insecure due to the rise of quantum computers. In response, the industry has launched the Post-quantum Cryptography (PQC) standardization process to establish quantum-safe public key cryptographic standards for the next generation of cryptographic systems.

[0090] Among them, the two lattice-based algorithms, Kyber key encapsulation mechanism and Dilithium digital signature scheme, are used as quantum-safe public key cryptography standards. The security foundations of Kyber and Dilithium are both based on the Modular Learning-With-Error (MLWE) problem, so both algorithms involve polynomial matrix-vector multiplication operations, which contain a large number of polynomial multiplication operations and polynomial accumulation operations on polynomial rings, where the point-by-point addition, subtraction, and multiplication operations of polynomial coefficients are defined on finite fields. As the main standards for post-quantum cryptographic algorithms, the common performance bottleneck of Kyber and Dilithium is the computational speed bottleneck when executing polynomial matrix-vector multiplication operations through computer CPUs.

[0091] Polynomial multiplication on a ring usually uses the Number Theoretic Transform (NTT) algorithm to reduce computational complexity. The NTT calculation can further apply the Negative Wrapped Convolution (NWC) optimization strategy to cancel the zero-padding operation. The NWC-NTT algorithm can perform fast calculations through multiple rounds of butterfly operations. Therefore, designing a dedicated butterfly operation unit can achieve hardware acceleration of the NTT operation.

[0092] Compared with executing polynomial matrix-vector multiplication operations through the CPU, executing the NTT algorithm through a dedicated butterfly operation unit can reduce the computational complexity. At the same time, the polynomial matrix-vector multiplication operations are implemented through this dedicated hardware operation unit, and the calculation speed is faster than that of implementing the polynomial matrix-vector multiplication operations through the CPU.

[0093] Based on the above improvement ideas, the embodiment of the present application proposes a butterfly operation unit that can support the execution of NWC-NTT operations, thereby improving the operation speed when executing polynomial matrix-vector multiplication operations.

[0094] Furthermore, the embodiment of the present application also proposes a butterfly operation unit array based on the above-mentioned butterfly operation unit, which supports finite field operations such as modular addition, modular subtraction, modular multiplication and base modular multiplication and accumulation (BMA) operations widely used in lattice post-quantum cryptography algorithms, thereby improving the utilization rate of computing resources in the butterfly operation unit.

[0095] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0096] The present application embodiment first proposes a butterfly operation unit, see Figure 1 As shown, the butterfly operation unit includes:

[0097] Modular multiplication operation module, modular subtraction operation module and modular addition operation module.

[0098] In the above-mentioned modular multiplication operation module, modular subtraction operation module and modular addition operation module, a data input port, a control signal input port, a clock signal port, a reset signal port and the like are respectively provided.

[0099] The above-mentioned data input port is used to receive coefficient input, such as receiving the first coefficient in1 or the second coefficient in2, the rotation factor ω N ,wait.

[0100] The control signal input port is used to receive control signals, such as a selection control signal sels of a multiplexer, a subtraction control signal subctr of a subtractor, and the like.

[0101] The above-mentioned clock signal port and reset signal port are used to receive clock signals and reset signals.

[0102] Since these ports belong to the normal structure of the operation module, they are no longer passed Figure 1 The detailed display and description only show relevant signals or data inputs by way of example.

[0103] The modular multiplication operation module, modular subtraction operation module and modular addition operation module cooperate with each other to realize CT (Cooley-Tukey, Cooley-Tukey Fast Fourier Transform) butterfly operation and GS (Gentleman-Sande algorithm) butterfly operation.

[0104] Among them, when the modular multiplication operation module, the modular subtraction operation module and the modular addition operation module are in the first operation mode, they can cooperate to implement the GS butterfly operation of NWC-inverse NTT.

[0105] In this operation mode, the modular multiplication operation module performs a modular subtraction operation on the received first coefficient in1 and the second coefficient in2 to obtain a modular subtraction result in1-in2, and performs a modular multiplication of the modular subtraction result by 1 / 2. and the rotation factor ω N Perform modular multiplication and output the second modular multiplication result out2 = v·ω N modq.

[0106] The modular subtraction operation module receives the second modular multiplication operation result and outputs the second modular multiplication operation result out2, the modular addition operation module performs a modular addition operation on the first coefficient in1 and the second coefficient in2 to obtain a second modular addition operation result, and outputs a modular multiplication 1 / 2 result of the second modular addition operation result

[0107] When the modular multiplication operation module, the modular subtraction operation module and the modular addition operation module are in the second operation mode, they can cooperate to implement the CT butterfly operation of NWC-NTT.

[0108] In this operation mode, the modular multiplication operation module receives the second coefficient in2 and the rotation factor ω N Perform modular multiplication and output the first modular multiplication result in2·ω N The modular subtraction operation module receives the first coefficient in1 and the first modular multiplication operation result in2·ω N Perform modular subtraction operation to output the first modular subtraction operation result out2 = (in1-in2·ω N )modq, the modular addition operation module receives the first coefficient in1 and the first modular multiplication operation result in2·ω N Perform a modular addition operation and output the first modular addition operation result out1 = (in1 + in2·ω N )modq.

[0109] In the above operation, represents the modulus of the modulus operation unit, which is configured by an external control status register.

[0110] Figure 2 The specific structure of the above-mentioned butterfly operation unit is shown.

[0111] See also Figure 2 As shown, in the above-mentioned butterfly operation unit, the modular multiplication operation module includes a first modular subtractor, a first modular multiplier 1 / 2, and a modular multiplier.

[0112] The above modular multiplier 1 / 2 is used to perform a logical shift operation. For even inputs, the logical shift is 1 bit right; for odd inputs, the logical shift is 1 bit right and added.

[0113] The first modular subtractor is connected to the input end of the first coefficient in1 and the input end of the second coefficient in2, the first modular multiplier 1 / 2 is connected in series with the first modular subtractor, the first modular subtractor performs a modular subtraction operation on the received first coefficient in1 and the second coefficient in2, and outputs the modular subtraction result in1-in2, the first modular multiplier 1 / 2 performs a 1 / 2 modular multiplication operation on the modular subtraction result in1-in2, and outputs the modular multiplication 1 / 2 result of the modular subtraction result

[0114]

[0115] The modular multiplier receives the second coefficient in2 and the rotation factor ω N Perform modular multiplication and output the first modular multiplication result in2·ω N , or, the modular multiplication result of the above modular reduction result by 1 / 2 and the rotation factor ω N Perform modular multiplication and output the second modular multiplication result v·ω N modq.

[0116] In order to make the modular multiplier perform different operations in different computing scenarios, see Figure 2 As shown, the modular multiplication operation module also includes a first multiplexer, which is a two-to-one multiplexer.

[0117] like Figure 2 As shown, the first input end of the first multiplexer is connected to the output end of the first modular multiplier 1 / 2, the second input end of the first multiplexer is connected to the input end of the second coefficient in2, and the output end of the first multiplexer is connected to the input end of the modular multiplier.

[0118] At the same time, the control port of the first multiplexer is connected to the input end of the selection control signal sels.

[0119] Based on the above hardware structure, in the first operation mode, the selection control signal sels is set to the first selection control signal. In this embodiment, the first selection control signal is 1. At this time, the control port of the first multiplexer receives the first selection control signal, so that the first input end of the first multiplexer is connected to the output end of the first multiplexer. At this time, the analog multiplier can receive the signal output by the first analog multiplier 1 / 2 Thus executing and the rotation factor ω N The modular multiplication operation outputs the second modular multiplication operation result v·ω N modq.

[0120] In the second operation mode, the selection control signal sels is set to the second selection control signal. In this embodiment, the second selection control signal is 0. At this time, the control port of the first multiplexer receives the second selection control signal, so that the second input end of the first multiplexer is connected to the output end of the first multiplexer. At this time, the modular multiplier can receive the second coefficient in2, thereby performing the second coefficient in2 and the rotation factor ω N The modular multiplication operation outputs the first modular multiplication result in2·ω N .

[0121] In the above-mentioned butterfly operation unit, the modular addition operation module includes a modular adder and a second modular multiplier 1 / 2.

[0122] The modular adder can be used to receive the first coefficient in1 and the first modular multiplication result in2·ω output by the modular multiplication operation module. N Perform a modular addition operation and output the first modular addition operation result (in1+in2·ω N )modq, or, it can also be used to perform a modular addition operation on the received first coefficient in1 and the second coefficient in2 to obtain a second modular addition operation result (in1+in2)modq.

[0123] The input end of the second modular multiplier 1 / 2 is connected to the output end of the modular adder, and can be used to perform modular multiplication 1 / 2 on the modular addition operation result output by the modular adder and output the modular multiplication 1 / 2 result of the modular addition operation result.

[0124] In order to enable the modular adder and the modular addition operation module including the modular adder to perform different operations in different operation scenarios, see Figure 2 As shown, the analog addition operation module also includes a second multiplexer and a third multiplexer, and the second multiplexer and the third multiplexer are both two-to-one multiplexers.

[0125] like Figure 2As shown, the first input end of the second multiplexer is connected to the input end of the second coefficient in2, the second input end of the second multiplexer is connected to the output end of the modular multiplication operation module, specifically to the output end of the modular multiplier, and the output end of the second multiplexer is connected to the input end of the modular adder.

[0126] The first input end of the third multiplexer is connected to the output end of the second modular multiplier 1 / 2, and the second input end of the third multiplexer is connected to the output end of the modular adder.

[0127] The control ports of the second multiplexer and the third multiplexer are respectively connected to the input terminals of the selection control signal sels.

[0128] In the first operation mode, the selection control signal sels is set to the first selection control signal, and in this embodiment, the first selection control signal is 1. At this time, the control port of the second multiplexer and the control port of the third multiplexer respectively receive the first selection control signal, so that the first input end of the second multiplexer is connected to the output end of the second multiplexer, and the first input end of the third multiplexer is connected to the output end of the third multiplexer.

[0129] At the same time, in the first operation mode, the first multiplexer in the modular multiplication operation module also receives the first selection control signal. At this time, the modular multiplier of the modular multiplication operation module can receive the signal output by the first modular multiplier 1 / 2 device. Thus executing and the rotation factor ω N The modular multiplication operation outputs the second modular multiplication operation result v·ω N Then, the modulo adder in the modulo addition operation module can receive the first coefficient in1 and the second coefficient in2, and then the modulo adder can perform the modulo addition operation on the first coefficient in1 and the second coefficient in2, and output the modulo addition result (in1+in2)modq. Since the first input terminal and the output terminal of the third multiplexer are connected at this time, the modulo addition result enters the second modulo multiplier 1 / 2 to perform the modulo multiplication 1 / 2 operation, and the modulo multiplication 1 / 2 result of the modulo addition operation result is obtained and output.

[0130] In the second operation mode, the selection control signal sels is set to the second selection control signal, and in this embodiment, the second selection control signal is 0. At this time, the control ports of the second multiplexer and the third multiplexer respectively receive the second selection control signal, so that the second input end of the second multiplexer is connected to the output end of the second multiplexer, and the second input end of the third multiplexer is connected to the output end of the third multiplexer.

[0131] At the same time, in the above-mentioned second operation mode, the first multiplexer in the modular multiplication operation module also receives the above-mentioned second selection control signal. At this time, the modular multiplier in the modular multiplication operation module can receive the second coefficient in2, thereby performing the second coefficient in2 and the rotation factor ω N The modular multiplication operation outputs the first modular multiplication result in2·ω N Then, the modular adder in the modular addition operation module can receive the first modular multiplication operation result in2·ω output by the modular multiplier. N and the first coefficient in1, the modular adder can now perform the first modular multiplication result in2·ω N The modular addition operation is performed on the first coefficient in1, and the modular addition result (in1+in2·ω) is output. N )modq. Since the second input terminal and the output terminal of the third multiplexer are connected at this time, the above-mentioned modular addition result is output through the third multiplexer, and the output out1 = (in1 + in2·ω N )modq.

[0132] In the above-mentioned butterfly operation unit, the modular subtraction operation module includes a second modular subtractor, and the input end of the modular subtractor is respectively connected to the input end of the first coefficient in1 and the output end of the modular multiplier in the modular multiplication operation module.

[0133] The second modular subtractor is used to perform a modular subtraction operation on the received first coefficient in1 and the modular multiplication operation result output by the modular multiplication operation module, and output a first modular subtraction operation result.

[0134] At the same time, the control port of the second modulus subtractor is connected to the input terminal of the subtraction control signal subctr, and the subtraction control signal is used to control the subtraction operation direction of the second modulus subtractor. Figure 2 For the input signals op1 and op2 of the subtractor shown in FIG. 1 , when the subtraction control signal subctr=0, the second modulo subtractor performs the operation of res=(op1-op2)modq; when the subtraction control signal subctr=1, the second modulo subtractor performs the operation of res=(op2-op1)modq.

[0135] In the first operation mode, the subtraction control signal subctr takes the first subtraction control signal, that is, subctr = 0. At this time, the second modular subtractor calculates the first coefficient in1 minus the first modular multiplication result in2·ω. N The difference between in1 and in2 is obtained as the first modular subtraction result out2 = (in1-in2·ω N )modq.

[0136] The above-mentioned modular subtraction operation module also includes a fourth multiplexer, a first input end of the fourth multiplexer is connected to the output end of the modular multiplication operation module, that is, connected to the output end of the modular multiplier in the modular multiplication operation module, and a second input end of the fourth multiplexer is connected to the output end of the second modular subtractor in the modular subtraction operation module.

[0137] At the same time, the control port of the fourth multiplexer is connected to the input terminal of the selection control signal sels.

[0138] In the first operation mode, the selection control signal sels is set to the first selection control signal, and in this embodiment, the first selection control signal is 1. At this time, the control port of the fourth multiplexer receives the first selection control signal, so that the first input end of the fourth multiplexer is connected to the output end of the fourth multiplexer.

[0139] At the same time, in the first operation mode, the first multiplexer in the modular multiplication operation module also receives the first selection control signal. At this time, the modular multiplier of the modular multiplication operation module can receive the signal output by the first modular multiplier 1 / 2 device. Thus executing and the rotation factor ω N The modular multiplication operation outputs the second modular multiplication operation result v·ω N modq.

[0140] Since the first input terminal and the output terminal of the fourth multiplexer are connected at this time, the fourth multiplexer outputs the second modular multiplication result, that is, out2 = v·ω N modq.

[0141] In the second operation mode, the selection control signal sels is set to the second selection control signal, and in this embodiment, the second selection control signal is 0. At this time, the control port of the fourth multiplexer receives the second selection control signal, so that the second input end of the fourth multiplexer is connected to the output end of the fourth multiplexer.

[0142] At the same time, in the above-mentioned second operation mode, the first multiplexer in the modular multiplication operation module also receives the above-mentioned second selection control signal. At this time, the modular multiplier in the modular multiplication operation module can receive the second coefficient in2, thereby performing the second coefficient in2 and the rotation factor ω N The modular multiplication operation outputs the first modular multiplication result in2·ω N .

[0143] In the second operation mode, the subtraction control signal is set to the first subtraction control signal, that is, subctr=0. At this time, the second modular subtractor in the modular subtraction operation module receives the first modular multiplication operation result in2·ω output by the modular multiplier. Nand the first coefficient in1, the second modular subtraction device can now perform the first modular multiplication operation result in2·ω N The modular subtraction operation is performed on the first coefficient in1, and the modular subtraction result (in1-in2·ω) is output. N )modq. Since the second input terminal and the output terminal of the fourth multiplexer are connected at this time, the above-mentioned modular subtraction result is output through the fourth multiplexer, and the output out2=(in1-in2·ω N )modq.

[0144] Continuing with reference to FIG. 2 , the butterfly operation unit further includes a first register and a second register.

[0145] The input end of the first register is connected to the output end of the analog addition operation module, that is, connected to the output end of the third multiplexer in the analog subtraction operation module, for optimizing the timing of the output signal of the analog addition operation module;

[0146] The input end of the second register is connected to the output end of the modular subtraction operation module, that is, connected to the output end of the fourth multiplexer in the modular subtraction operation module, and is used to optimize the timing of the output signal of the modular subtraction operation module.

[0147] The first register and the second register mentioned above can be used to beat the output signal, thereby cutting off the critical path and optimizing the timing of the output signal.

[0148] Based on the above introduction to the butterfly operation unit, combined with Figure 2 As shown, the butterfly operation unit proposed in the embodiment of the present application retains the selection control signal sels, the subtraction control signal subctr, the first coefficient in1, the second coefficient in2, the rotation factor ω N These input ports also retain two output ports, out1 and out2. The names and functions of each signal are shown in Table 1.

[0149] Table 1

[0150]

[0151] The butterfly operation unit described above can implement the following different NTT operations under the control of different control signals:

[0152] When sels=4′b0000,subctr=1′b0, the butterfly operation unit performs CT butterfly calculation, which is suitable for NWC-NTT calculation:

[0153] out1=(in1+in2·ω N )modq

[0154] out2=(in1-in2·ωN )modq

[0155] When sels=4′b1111,subctr=1′b0, the butterfly unit performs GS butterfly calculation, which is suitable for NWC-inverse NTT calculation: first calculate the intermediate signals u and v, and further calculate the output signal

[0156]

[0157] out1=u,out2=v·ω N modq

[0158] Based on the above-mentioned butterfly operation unit, another embodiment of the present application further proposes a butterfly operation unit array, which is composed of a plurality of the above-mentioned butterfly operation units cascaded together. That is to say, each butterfly operation unit in the butterfly operation unit array adopts the structure of the butterfly operation unit introduced in the above-mentioned embodiment.

[0159] See also Figure 3 As shown, the butterfly operation unit array proposed in the embodiment of the present application includes a first multiplexer component, a second multiplexer component, a first butterfly operation unit and a second butterfly operation unit.

[0160] The first multiplexer assembly and the second multiplexer assembly are respectively composed of a plurality of multiplexers cascaded.

[0161] The first multiplexer component is connected to the first butterfly operation unit and is used to control the input signal of the first butterfly operation unit; the second multiplexer component is connected to the second butterfly operation unit and is used to control the input signal of the second butterfly operation unit.

[0162] When the first butterfly operation unit and the second butterfly operation unit are in the second operation mode, that is, when sels=4′b0000, the first multiplexer component selects the i-th first coefficient and the i-th second coefficient The first butterfly operation unit is input, and the first butterfly operation unit performs the operation on the i-th first coefficient and the i-th second coefficient Perform at least one of modular addition, modular subtraction and modular multiplication to obtain a modular addition result. Modulo subtraction result And modular multiplication result at least one of .

[0163] In the second operation mode, the second multiplexer component selects the i+1th first coefficient and the i+1th second coefficient The second butterfly operation unit is input, and the second butterfly operation unit performs the operation on the i+1th first coefficient and the second coefficient of the i+1th grid Perform at least one of modular addition, modular subtraction and modular multiplication to obtain a modular addition result. Modulo subtraction result And modular multiplication result at least one of .

[0164] Alternatively, when the first butterfly operation unit and the second butterfly operation unit are in the second operation mode, the first multiplexer component selects the i-th first coefficient The i-th second coefficient and the cumulative sum of the first and second coefficients of the first i i The first butterfly operation unit is input, and the first butterfly operation unit performs the operation on the i-th first coefficient The i-th second coefficient And the cumulative sum acc of the first i first coefficients and the second coefficients i Perform BMA1 operation, that is, perform point-by-point modular multiplication and accumulation operation of polynomial coefficients with lower complexity used in Dilithium algorithm to obtain the operation result Among them, sel3 is acc i The selection signal of the signal, when sel3 = 0, acc i The signal is input into the first butterfly operation unit.

[0165] The second multiplexer component inputs the accumulated sum of the i+1th first coefficient, the i+1th second coefficient, and the first i+1th first coefficient and the second coefficient to the second butterfly operation unit, and the second butterfly operation unit performs the operation on the i+1th first coefficient. The i+1th second coefficient And the cumulative sum of the first i+1 first coefficients and the second coefficients acc i+1 Perform BMA1 operation, that is, perform point-by-point modular multiplication and accumulation operation of polynomial coefficients with lower complexity used in Dilithium algorithm to obtain the operation result Among them, sel3 is acc i+1 The selection signal of the signal, when sel3 = 0, acc i+1 The signal is input into the second butterfly operation unit.

[0166] like Figure 3 As shown, in the above-mentioned butterfly operation unit array, a third butterfly operation unit, a fourth butterfly operation unit, a fifth butterfly operation unit and a sixth butterfly operation unit are also included.

[0167] The first coefficient input terminal in1 of the third butterfly operation unit is connected to the output terminal out2 of the modular subtraction operation module of the first butterfly operation unit, and the second coefficient input terminal in2 of the third butterfly operation unit is connected to the output terminal out2 of the modular subtraction operation module of the second butterfly operation unit; the rotation factor input terminal of the third butterfly operation unit is used to receive the rotation factor ω N Signal.

[0168] The first coefficient input terminal in1 of the fourth butterfly operation unit is connected to the output terminal out2 of the modular subtraction operation module of the first butterfly operation unit and the output terminal out2 of the modular subtraction operation module of the second butterfly operation unit. Figure 3 As shown in, the output end out2 of the modular subtraction module of the first butterfly operation unit and the output end out2 of the modular subtraction module of the second butterfly operation unit are connected to the input end of the independent modular adder, and the output end of the independent modular adder is connected to the first coefficient input end in1 of the fourth butterfly operation unit.

[0169] The second coefficient input terminal in2 of the fourth butterfly operation unit is connected to the output terminal out1 of the analog addition operation module of the second butterfly operation unit; the rotation factor input terminal of the fourth butterfly operation unit is connected to the output terminal out1 of the analog addition operation module of the first butterfly operation unit.

[0170] The first coefficient input terminal in1 of the fifth butterfly operation unit is connected to the output terminal out1 of the modular addition operation module of the third butterfly operation unit; the rotation factor input terminal of the fifth butterfly operation unit is used to receive ω N =1 signal; the second coefficient input terminal in2 of the fifth butterfly operation unit is used to receive the cumulative sum acc of the first 2i first coefficients and the second coefficients 2i or 0 signal.

[0171] The first coefficient input terminal in1 of the sixth butterfly operation unit is connected to the output terminal out2 of the modular subtraction operation module of the fourth butterfly operation unit; the rotation factor input terminal of the sixth butterfly operation unit is used to receive the rotation factor signal; the second coefficient input terminal in2 of the sixth butterfly operation unit is used to receive the cumulative sum acc of the first 2i+1 first coefficients and the second coefficients 2i+1 or 0 signal.

[0172] When the first butterfly operation unit and the second butterfly operation unit are in the third operation mode, i.e., sels=4′b1010, and the control ports of the modular subtractors of the third butterfly operation unit and the fourth butterfly operation unit receive the second subtraction control signal (subctr=1′b1), the first multiplexer component selects the 2ith first coefficient 2i second coefficient and the 2i+1th first coefficient The first butterfly operation unit is input, and the second multiplexer component converts the 2ith second coefficient 2i+1th first coefficient and the 2i+1th second coefficient The second butterfly operation unit is input, and the butterfly operation unit array performs a BMA2 operation on the first coefficient and the second coefficient, which is a high-complexity basic modular multiplication and accumulation operation used in the Kyber algorithm:

[0173]

[0174]

[0175] In the above-mentioned BMA1 and BMA2 operations, the value of the signal changes with the calculation process. When the BMA operation is performed for the first time, sel3=0, and when the BMA operation is performed after the first time, sel3=1.

[0176] In order to enable the butterfly operation unit array to perform different types of operations, the embodiment of the present application controls the array input through the first multiplexer component and the second multiplexer component, thereby realizing input signal adjustment in different operation scenarios.

[0177] See also Figure 3 As shown, the first multiple selector component comprises:

[0178] The fifth multiplexer, the sixth multiplexer, the seventh multiplexer, the eighth multiplexer, the ninth multiplexer, and the tenth multiplexer, the fifth to tenth multiplexers are all two-to-one multiplexers.

[0179] The first input terminal of the fifth multiplexer is connected to the cumulative sum acc of the first i first coefficients and the second coefficients. i The first input terminal of the fifth multiplexer is connected to the first input terminal of the sixth multiplexer; the second input terminal of the fifth multiplexer is connected to the 0 signal input terminal; and the output terminal of the fifth multiplexer is connected to the first input terminal of the sixth multiplexer;

[0180] The output end of the sixth multiple selector is connected to the first coefficient input end in1 of the first butterfly operation unit, and the second input end of the sixth multiple selector is connected to the output end of the seventh multiple selector;

[0181] The first input terminal of the seventh multiple selector is connected to the i-th first coefficient The second input end of the seventh multiplexer is connected to the 2i+1th first coefficient The input terminal is connected to

[0182] The first input terminal of the eighth multiplexer is connected to the 1 signal input terminal, and the second input terminal of the eighth multiplexer is connected to the 2i second coefficient The output end of the eighth multiple selector is connected to the second input end of the ninth multiple selector;

[0183] The first input terminal of the ninth multiple selector is connected to the i-th first coefficient The output end of the ninth multiplexer is connected to the rotation factor ω of the first butterfly operation unit. N The input terminal is connected to

[0184] The first input terminal of the tenth multiple selector is connected to the i-th second coefficient The second input end of the tenth multiplexer is connected to the 2i-th first coefficient The output end of the tenth multiplexer is connected to the input end of the second coefficient in2 of the first butterfly operation unit;

[0185] See also Figure 3 As shown, the control port of the fifth multiplexer is connected to the input end of the sel3 selection control signal for receiving the sel3 selection control signal; the control ports of the sixth multiplexer and the ninth multiplexer are connected to the input end of the sel1 selection control signal for receiving the sel1 selection control signal; the control ports of the seventh multiplexer, the eighth multiplexer and the tenth multiplexer are connected to the input end of the sel0 selection control signal for receiving the sel0 selection control signal.

[0186] When the control ports of the fifth multiplexer, the sixth multiplexer, the seventh multiplexer, the eighth multiplexer, the ninth multiplexer and the tenth multiplexer receive the first selection control signal (i.e., the value of the selection control signal is equal to 1), the second input end and the output end thereof are connected; when the control ports of the fifth multiplexer, the sixth multiplexer, the seventh multiplexer, the eighth multiplexer, the ninth multiplexer and the tenth multiplexer receive the second selection control signal (i.e., the value of the selection control signal is equal to 0), the first input end and the output end thereof are connected.

[0187] The first multiple selector component mentioned above comprises:

[0188] The eleventh multiplexer, the twelfth multiplexer, the thirteenth multiplexer, the fourteenth multiplexer, the fifteenth multiplexer, and the sixteenth multiplexer, the eleventh to sixteenth multiplexers are all two-to-one multiplexers.

[0189] The first input terminal of the eleventh multiplexer is combined with the cumulative sum acc of the first i+1 first coefficients and the second coefficients i+1The output end of the eleventh multiple selector is connected to the first input end of the twelfth multiple selector; the second input end of the eleventh multiple selector is connected to the 0 signal input end; and the output end of the eleventh multiple selector is connected to the first input end of the twelfth multiple selector;

[0190] The output end of the twelfth multiple selector is connected to the first coefficient input end in1 of the second butterfly operation unit, and the second input end of the twelfth multiple selector is connected to the output end of the thirteenth multiple selector;

[0191] The first input terminal of the thirteenth multiple selector is connected to the (i+1)th first coefficient The second input end of the thirteenth multiplexer is connected to the 2i-th second coefficient The input terminal is connected to

[0192] The first input terminal of the fourteenth multiplexer is connected to the 1 signal input terminal, and the second input terminal of the fourteenth multiplexer is connected to the 2i+1th first coefficient The output end of the fourteenth multiple selector is connected to the second input end of the fifteenth multiple selector;

[0193] The first input terminal of the fifteenth multiple selector is connected to the (i+1)th first coefficient The output end of the fifteenth multiplexer is connected to the rotation factor ω of the second butterfly operation unit. N The input terminal is connected to

[0194] The first input terminal of the sixteenth multiple selector is connected to the (i+1)th second coefficient The second input end of the sixteenth multiplexer is connected to the 2i+1th second coefficient The output end of the sixteenth multiplexer is connected to the input end in2 of the second coefficient of the second butterfly operation unit;

[0195] See also Figure 3 As shown, the control port of the eleventh multiplexer is connected to the input end of the sel3 selection control signal for receiving the sel3 selection control signal; the control ports of the twelfth multiplexer and the fifteenth multiplexer are connected to the input end of the sel1 selection control signal for receiving the sel1 selection control signal; the control ports of the thirteenth multiplexer, the fourteenth multiplexer and the sixteenth multiplexer are connected to the input end of the sel0 selection control signal for receiving the sel0 selection control signal.

[0196] When the control ports of the eleventh multiple selector, the twelfth multiple selector, the thirteenth multiple selector, the fourteenth multiple selector, the fifteenth multiple selector and the sixteenth multiple selector receive the first selection control signal (i.e., the value of the selection control signal is equal to 1), the second input end and the output end thereof are connected; when the control ports of the eleventh multiple selector, the twelfth multiple selector, the thirteenth multiple selector, the fourteenth multiple selector, the fifteenth multiple selector and the sixteenth multiple selector receive the second selection control signal (i.e., the value of the selection control signal is equal to 0), the first input end and the output end thereof are connected.

[0197] Continue to see Figure 3 As shown, in the above butterfly operation unit array, there are also a seventeenth multiplexer, an eighteenth multiplexer, a nineteenth multiplexer and a twentieth multiplexer. Among them, the seventeenth multiplexer and the eighteenth multiplexer are two-to-one multiplexers, and the nineteenth multiplexer and the twentieth multiplexer are three-to-one multiplexers.

[0198] The first input terminal of the seventeenth multiplexer is connected to the cumulative sum signal acc of the first 2i first coefficients and the second coefficients. 2i The input end of the seventeenth multiplexer is connected to the input end of the 0 signal;

[0199] The first input terminal of the eighteenth multiplexer is connected to the cumulative sum signal acc of the first 2i+1 first coefficients and the second coefficients. 2i+1 The input end of the seventeenth multiplexer is connected to the input end of the 0 signal;

[0200] The first input end of the nineteenth multiplexer is connected to the output end out1 of the analog addition operation module of the first butterfly operation unit, the second input end of the nineteenth multiplexer is connected to the output end out2 of the analog subtraction operation module of the first butterfly operation unit, and the third input end of the nineteenth multiplexer is connected to the output end out1 of the analog addition operation module of the fifth butterfly operation unit;

[0201] The first input end of the 20th multiple selector is connected to the output end out1 of the modular addition operation module of the second butterfly operation unit, the second input end of the 20th multiple selector is connected to the output end out2 of the modular subtraction operation module of the second butterfly operation unit, and the third input end of the 20th multiple selector is connected to the output end out1 of the modular addition operation module of the sixth butterfly operation unit;

[0202] The control ports of the seventeenth multiplexer and the eighteenth multiplexer are connected to the input end of the sel3 selection control signal and are used to receive the sel3 selection control signal.

[0203] When the control ports of the seventeenth multiple selector and the eighteenth multiple selector receive the first gating control signal (i.e., the value of the gating control signal is equal to 1), the second input end and the output end thereof are connected; when the control ports of the seventeenth multiple selector and the eighteenth multiple selector receive the second gating control signal (i.e., the value of the gating control signal is equal to 0), the first input end and the output end thereof are connected.

[0204] The control ports of the nineteenth multiplexer and the twenty-first multiplexer are connected to the input end of the sel2 selection control signal and are used to receive the sel2 selection control signal.

[0205] When the control ports of the nineteenth multiplexer and the twenty-third multiplexer receive the first selection control signal (i.e., the value of the selection control signal is equal to 1), the second input terminal and the output terminal thereof are connected; when the control ports of the nineteenth multiplexer and the twenty-third multiplexer receive the second selection control signal (i.e., the value of the selection control signal is equal to 0), the first input terminal and the output terminal thereof are connected; when the control ports of the nineteenth multiplexer and the twenty-third multiplexer receive the third selection control signal (i.e., the value of the selection control signal is equal to 2), the third input terminal and the output terminal thereof are connected.

[0206] Based on the above-mentioned embodiments, the butterfly operation unit array proposed in the present application reserves the signal ports shown in Table 2 for external use. The signal name, signal bit width, signal function, etc. received by each signal port can be seen in Table 2.

[0207] Table 2

[0208]

[0209] Based on the above signal ports, under different data input and different control signal input conditions, the above butterfly operation unit array can realize different operation functions, as shown in Table 3.

[0210] Table 3

[0211]

[0212] Among them, for the BMA2 operation, the butterfly operation unit array proposed in the embodiment of the present application introduces the Karatsuba algorithm to split the operation (excluding accumulation) into two parts, such as Figure 4 In the BMA2 operation data flow diagram shown, the first column of butterfly operation units Cycle1 and the second column of butterfly operation units Cycle2 are responsible for the complex calculation of BMA2 respectively. After the complex calculation is completed, the third column of butterfly operation units Cycle3 is responsible for the accumulation of the calculation results.

[0213] in, Figure 4 The first column of butterfly cells in Cycle1 corresponds to Figure 3 The first butterfly operation unit and the second butterfly operation unit in the butterfly operation unit array shown, Figure 4 The second column of butterfly units in Figure 3 The third butterfly operation unit and the fourth butterfly operation unit in the butterfly operation unit array shown, Figure 4 The third column of butterfly units in Figure 3 The fifth butterfly operation unit and the sixth butterfly operation unit in the butterfly operation unit array are shown.

[0214] From the introduction of the above embodiments, it can be seen that the butterfly operation unit proposed in this application can realize the operation of the NTT algorithm, specifically, it can realize the CT butterfly operation of NWC-NTT, and can also realize the GS butterfly operation of NWC-inverse NTT. Therefore, using the butterfly operation unit to perform polynomial matrix-vector multiplication operations can reduce the computational complexity, realize hardware acceleration of NTT operations, and improve the computational speed of polynomial matrix-vector multiplication operations.

[0215] In addition, the present application cascades multiple of the above-mentioned butterfly operation units to form a butterfly operation unit array. Under the control after control absorption, the butterfly operation unit array can perform polynomial operations on a finite field used in various lattice post-quantum cryptography, including modular addition, modular subtraction, modular multiplication, and complex BMA operations, thereby further improving the utilization rate of computing resources in the butterfly operation unit and expanding the application scope of the butterfly operation unit.

[0216] For the aforementioned method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the order of the actions described, because according to the present application, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0217] It should be noted that each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0218] The steps in the methods of each embodiment of the present application can be adjusted in order, combined and deleted according to actual needs, and the technical features recorded in each embodiment can be replaced or combined.

[0219] The modules and sub-modules in the devices and terminals of the various embodiments of the present application can be combined, divided and deleted according to actual needs.

[0220] In the several embodiments provided in the present application, it should be understood that the disclosed terminals, devices and methods can be implemented in other ways. For example, the terminal embodiments described above are only schematic, for example, the division of modules or submodules is only a logical function division, and there may be other division methods in actual implementation, for example, multiple submodules or modules can be combined or integrated into another module, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, which can be electrical, mechanical or other forms.

[0221] The modules or submodules described as separate components may or may not be physically separated, and the components of the modules or submodules may or may not be physical modules or submodules, that is, they may be located in one place, or they may be distributed on multiple network modules or submodules. Some or all of the modules or submodules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0222] In addition, each functional module or submodule in each embodiment of the present application may be integrated into one processing module, or each module or submodule may exist physically separately, or two or more modules or submodules may be integrated into one module. The above-mentioned integrated modules or submodules may be implemented in the form of hardware or in the form of software functional modules or submodules.

[0223] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0224] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly by hardware, software units executed by a processor, or a combination of the two. The software units may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0225] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0226] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A butterfly computing unit, characterized in that: include: A modular multiplication operation module, a modular subtraction operation module and a modular addition operation module; Wherein, in the first operation mode, the modular multiplication operation module performs a modular subtraction operation on the received first coefficient and the second coefficient to obtain a modular subtraction result, performs a modular multiplication operation on a modular multiplication 1 / 2 result of the modular subtraction result and a rotation factor to output a second modular multiplication operation result, the modular subtraction operation module receives the second modular multiplication operation result and outputs the second modular multiplication operation result, the modular addition operation module performs a modular addition operation on the received first coefficient and the second coefficient to obtain a second modular addition operation result, and outputs a modular multiplication 1 / 2 result of the second modular addition operation result; or, In the second operation mode, the modular multiplication operation module performs a modular multiplication operation on the received second coefficient and the rotation factor and outputs a first modular multiplication operation result, the modular subtraction operation module performs a modular subtraction operation on the received first coefficient and the first modular multiplication operation result and outputs a first modular subtraction operation result, and the modular addition operation module performs a modular addition operation on the received first coefficient and the first modular multiplication operation result and outputs a first modular addition operation result.

2. The butterfly operation unit according to claim 1, characterized in that: The modular multiplication operation module comprises: A first modular subtractor, a first modular multiplier 1 / 2, and a modular multiplier; The first modular subtractor performs a modular subtraction operation on the received first coefficient and the second coefficient and outputs a modular subtraction result, and the first modular multiplier 1 / 2 operates on the modular subtraction result and outputs a modular multiplication 1 / 2 result of the modular subtraction result; The modular multiplier performs a modular multiplication operation on the received second coefficient and the rotation factor to output a first modular multiplication operation result, or performs a modular multiplication operation on a 1 / 2 result of the modular subtraction result and the rotation factor to output a second modular multiplication operation result.

3. The butterfly operation unit according to claim 2, characterized in that: The modular multiplication operation module also includes a first multiplexer; The first input end of the first multiplexer is connected to the output end of the first modular multiplier 1 / 2, the second input end of the first multiplexer is connected to the input end of the second coefficient, and the output end of the first multiplexer is connected to the input end of the modular multiplier; The control port of the first multiplexer is connected to the input terminal of the selection control signal. In the first operation mode, the control port of the first multiplexer receives the first selection control signal, and the first input terminal of the first multiplexer is connected to the output terminal of the first multiplexer; in the second operation mode, the control port of the first multiplexer receives the second selection control signal, and the second input terminal of the first multiplexer is connected to the output terminal of the first multiplexer.

4. The butterfly operation unit according to claim 1, characterized in that: The modular addition operation module comprises: A modular adder and a second modular multiplier 1 / 2; The modular adder performs a modular addition operation on the received first coefficient and the first modular multiplication operation result to output a first modular addition operation result, or performs a modular addition operation on the received first coefficient and the second coefficient to obtain a second modular addition operation result; The second modular multiplier 1 / 2 performs a modular multiplication 1 / 2 operation on the modular addition operation result output by the modular adder and outputs a modular multiplication 1 / 2 result of the modular addition operation result.

5. The butterfly operation unit according to claim 4, characterized in that: The modular addition operation module further includes: a second multiplexer and a third multiplexer; The first input end of the second multiplexer is connected to the input end of the second coefficient, the second input end of the second multiplexer is connected to the output end of the modular multiplication operation module, and the output end of the second multiplexer is connected to the input end of the modular adder; The first input end of the third multiplexer is connected to the output end of the second modular multiplier 1 / 2, and the second input end of the third multiplexer is connected to the output end of the modular adder; The control port of the second multiplexer and the control port of the third multiplexer are respectively connected to the gating control signal input terminal; In the first operation mode, the control port of the second multiplexer and the control port of the third multiplexer respectively receive the first selection control signal, the first input end of the second multiplexer is connected to the output end of the second multiplexer, and the first input end of the third multiplexer is connected to the output end of the third multiplexer; In the second operation mode, the control port of the second multiplexer and the control port of the third multiplexer respectively receive a second selection control signal, the second input end of the second multiplexer is connected to the output end of the second multiplexer, and the second input end of the third multiplexer is connected to the output end of the third multiplexer.

6. The butterfly operation unit according to claim 1, characterized in that: The modular subtraction operation module comprises: A second modular subtractor, configured to perform a modular subtraction operation on the received first coefficient and the first modular multiplication operation result to output a first modular subtraction operation result; The control port of the second modulus subtractor is connected to the subtraction control signal input terminal; In the second operation mode, the control port of the second modular subtractor receives a first subtraction control signal, and the second modular subtractor calculates the difference between the first coefficient and the first modular multiplication operation result to obtain a first modular subtraction operation result.

7. The butterfly operation unit according to claim 6, characterized in that: The modular subtraction operation module also includes a fourth multiplexer; The first input end of the fourth multiplexer is connected to the output end of the modular multiplication operation module, and the second input end of the fourth multiplexer is connected to the output end of the second modular subtraction device; The control port of the fourth multiplexer is connected to the gating control signal input terminal; In the first operation mode, the control port of the fourth multiplexer receives a first selection control signal, and the first input terminal of the fourth multiplexer is connected to the output terminal of the fourth multiplexer; In the second operation mode, the control port of the fourth multiplexer receives a second selection control signal, and the second input terminal of the fourth multiplexer is connected to the output terminal of the fourth multiplexer.

8. The butterfly operation unit according to any one of claims 1 to 7, characterized in that: Also includes: A first register and a second register; The input end of the first register is connected to the output end of the analog addition operation module, and is used to optimize the timing of the output signal of the analog addition operation module; The input end of the second register is connected to the output end of the analog subtraction operation module, and is used to optimize the timing of the output signal of the analog subtraction operation module.

9. A butterfly computing unit array, characterized in that: include: a first multiplexer component, a second multiplexer component, a first butterfly operation unit and a second butterfly operation unit, wherein the first butterfly operation unit and the second butterfly operation unit both adopt the structure of the butterfly operation unit according to any one of claims 1 to 8; the first multiplexer component and the second multiplexer component respectively include a plurality of cascaded multiplexers; The first multiplexer component is connected to the first butterfly operation unit, and the second multiplexer component is connected to the second butterfly operation unit; When the first butterfly operation unit and the second butterfly operation unit are in the second operation mode, the first multiplexer component inputs the i-th first coefficient and the i-th second coefficient into the first butterfly operation unit, and the first butterfly operation unit performs at least one of modular addition, modular subtraction and modular multiplication on the i-th first coefficient and the i-th second coefficient; the second multiplexer component inputs the i+1-th first coefficient and the i+1-th second coefficient into the second butterfly operation unit, and the second butterfly operation unit performs at least one of modular addition, modular subtraction and modular multiplication on the i+1-th first coefficient and the i+1-th second coefficient; i is a positive integer.

10. The butterfly operation unit array according to claim 9, characterized in that: Also includes: Alternatively, when the first butterfly operation unit and the second butterfly operation unit are in the second operation mode, the first multiplexer component inputs the accumulated sum of the i-th first coefficient, the i-th second coefficient and the first i-th first coefficient and the second coefficient into the first butterfly operation unit, and the first butterfly operation unit performs a modular multiplication and accumulation operation on the accumulated sum of the i-th first coefficient, the i-th second coefficient and the first i-th first coefficient and the second coefficient; the second multiplexer component inputs the accumulated sum of the i+1-th first coefficient, the i+1-th second coefficient and the first i+1-th first coefficient and the second coefficient into the second butterfly operation unit, and the second butterfly operation unit performs a modular multiplication and accumulation operation on the accumulated sum of the i+1-th first coefficient, the i+1-th second coefficient and the first i+1-th first coefficient and the second coefficient.

11. The butterfly operation unit array according to claim 9, characterized in that: Also includes: a third butterfly operation unit, a fourth butterfly operation unit, a fifth butterfly operation unit and a sixth butterfly operation unit; the third butterfly operation unit, the fourth butterfly operation unit, the fifth butterfly operation unit and the sixth butterfly operation unit all adopt the structure of the butterfly operation unit according to any one of claims 1 to 8; The first coefficient input terminal of the third butterfly operation unit is connected to the output terminal of the modular subtraction operation module of the first butterfly operation unit, and the second coefficient input terminal of the third butterfly operation unit is connected to the output terminal of the modular subtraction operation module of the second butterfly operation unit; The first coefficient input terminal of the fourth butterfly operation unit is connected to the output terminal of the modular subtraction operation module of the first butterfly operation unit and the output terminal of the modular subtraction operation module of the second butterfly operation unit, and the second coefficient input terminal of the fourth butterfly operation unit is connected to the output terminal of the modular addition operation module of the second butterfly operation unit; The first coefficient input terminal of the fifth butterfly operation unit is connected to the output terminal of the modular addition operation module of the third butterfly operation unit; The first coefficient input terminal of the sixth butterfly operation unit is connected to the output terminal of the modular subtraction operation module of the fourth butterfly operation unit; When the first butterfly operation unit and the second butterfly operation unit are in the third operation mode and the control ports of the modulo subtractors of the third butterfly operation unit and the fourth butterfly operation unit receive a second subtraction control signal, the first multiplexer component inputs the 2i-th first coefficient, the 2i-th second coefficient and the 2i+1-th first coefficient into the first butterfly operation unit, and the second multiplexer component inputs the 2i-th second coefficient, the 2i+1-th first coefficient and the 2i+1-th second coefficient into the second butterfly operation unit, and the butterfly operation unit array performs a fundamental modulo multiplication and accumulation operation on the first coefficient and the second coefficient.

12. The butterfly operation unit array according to any one of claims 9 to 11, characterized in that: The first multiple selector component comprises: The fifth multiplexer, the sixth multiplexer, the seventh multiplexer, the eighth multiplexer, the ninth multiplexer, and the tenth multiplexer; The first input end of the fifth multiplexer is connected to the cumulative sum signal input end of the first i first coefficients and the second coefficients, the second input end of the fifth multiplexer is connected to the 0 signal input end, and the output end of the fifth multiplexer is connected to the first input end of the sixth multiplexer; The output end of the sixth multiple selector is connected to the first coefficient input end of the first butterfly operation unit, and the second input end of the sixth multiple selector is connected to the output end of the seventh multiple selector; The first input end of the seventh multiple selector is connected to the input end of the i-th first coefficient, and the second input end of the seventh multiple selector is connected to the input end of the 2i+1-th first coefficient; The first input terminal of the eighth multiplexer is connected to the 1 signal input terminal, the second input terminal of the eighth multiplexer is connected to the input terminal of the 2i-th second coefficient, and the output terminal of the eighth multiplexer is connected to the second input terminal of the ninth multiplexer; The first input end of the ninth multiplexer is connected to the input end of the i-th first coefficient, and the output end of the ninth multiplexer is connected to the rotation factor input end of the first butterfly operation unit; The first input end of the tenth multiple selector is connected to the input end of the i-th second coefficient, the second input end of the tenth multiple selector is connected to the input end of the 2i-th first coefficient, and the output end of the tenth multiple selector is connected to the input end of the second coefficient of the first butterfly operation unit; When the control ports of the fifth multiplexer, the sixth multiplexer, the seventh multiplexer, the eighth multiplexer, the ninth multiplexer and the tenth multiplexer receive the first selection control signal, the second input end and the output end thereof are connected; when the control ports of the fifth multiplexer, the sixth multiplexer, the seventh multiplexer, the eighth multiplexer, the ninth multiplexer and the tenth multiplexer receive the second selection control signal, the first input end and the output end thereof are connected.

13. The butterfly operation unit array according to any one of claims 9 to 11, characterized in that: The second multiplexer component comprises: The eleventh multiplexer, the twelfth multiplexer, the thirteenth multiplexer, the fourteenth multiplexer, the fifteenth multiplexer, and the sixteenth multiplexer; The first input end of the eleventh multiple selector is connected to the cumulative sum signal input end of the first i+1 first coefficients and the second coefficients, the second input end of the eleventh multiple selector is connected to the 0 signal input end, and the output end of the eleventh multiple selector is connected to the first input end of the twelfth multiple selector; The output end of the twelfth multiple selector is connected to the first coefficient input end of the second butterfly operation unit, and the second input end of the twelfth multiple selector is connected to the output end of the thirteenth multiple selector; The first input end of the thirteenth multiple selector is connected to the input end of the (i+1)th first coefficient, and the second input end of the thirteenth multiple selector is connected to the input end of the (2i)th second coefficient; The first input end of the fourteenth multiplexer is connected to the 1 signal input end, the second input end of the fourteenth multiplexer is connected to the input end of the 2i+1th first coefficient, and the output end of the fourteenth multiplexer is connected to the second input end of the fifteenth multiplexer; The first input end of the fifteenth multiple selector is connected to the input end of the (i+1)th first coefficient, and the output end of the fifteenth multiple selector is connected to the rotation factor input end of the second butterfly operation unit; The first input end of the sixteenth multiple selector is connected to the input end of the i+1th second coefficient, the second input end of the sixteenth multiple selector is connected to the input end of the 2i+1th second coefficient, and the output end of the sixteenth multiple selector is connected to the input end of the second coefficient of the second butterfly operation unit; When the control ports of the eleventh multiplexer, the twelfth multiplexer, the thirteenth multiplexer, the fourteenth multiplexer, the fifteenth multiplexer and the sixteenth multiplexer receive the first selection control signal, the second input end and the output end thereof are connected; when the control ports of the eleventh multiplexer, the twelfth multiplexer, the thirteenth multiplexer, the fourteenth multiplexer, the fifteenth multiplexer and the sixteenth multiplexer receive the second selection control signal, the first input end and the output end thereof are connected.

14. The butterfly operation unit array according to claim 11, characterized in that: Also includes a standalone module adder, The first coefficient input terminal of the fourth butterfly operation unit is connected to the output terminal of the modular subtraction operation module of the first butterfly operation unit and the output terminal of the modular subtraction operation module of the second butterfly operation unit, including: The output end of the modular subtraction module of the first butterfly operation unit and the output end of the modular subtraction module of the second butterfly operation unit are connected to the input end of the independent modular adder, and the output end of the independent modular adder is connected to the first coefficient input end of the fourth butterfly operation unit.

15. The butterfly operation unit array according to claim 11, characterized in that: Also included are a seventeenth multiplexer, an eighteenth multiplexer, a nineteenth multiplexer, and a twentieth multiplexer; The first input end of the seventeenth multiple selector is connected to the input end of the cumulative sum signal of the first 2i first coefficients and the second coefficients, and the second input end of the seventeenth multiple selector is connected to the input end of the 0 signal; The first input end of the eighteenth multiplexer is connected to the input end of the cumulative sum signal of the first 2i+1 first coefficients and the second coefficients, and the second input end of the seventeenth multiplexer is connected to the input end of the 0 signal; The first input end of the nineteenth multiplexer is connected to the output end of the modular addition operation module of the first butterfly operation unit, the second input end of the nineteenth multiplexer is connected to the output end of the modular subtraction operation module of the first butterfly operation unit, and the third input end of the nineteenth multiplexer is connected to the output end of the modular addition operation module of the fifth butterfly operation unit; The first input end of the 20th multiple selector is connected to the output end of the modular addition operation module of the second butterfly operation unit, the second input end of the 20th multiple selector is connected to the output end of the modular subtraction operation module of the second butterfly operation unit, and the third input end of the 20th multiple selector is connected to the output end of the modular addition operation module of the sixth butterfly operation unit; When the control ports of the seventeenth multiple selector and the eighteenth multiple selector receive the first selection control signal, the second input end thereof is connected to the output end thereof; when the control ports of the seventeenth multiple selector and the eighteenth multiple selector receive the second selection control signal, the first input end thereof is connected to the output end thereof; When the control ports of the nineteenth multiplexer and the twenty-third multiplexer receive the first selection control signal, the second input terminal and the output terminal thereof are connected; when the control ports of the nineteenth multiplexer and the twenty-third multiplexer receive the second selection control signal, the first input terminal and the output terminal thereof are connected; when the control ports of the nineteenth multiplexer and the twenty-third multiplexer receive the third selection control signal, the third input terminal and the output terminal thereof are connected.

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