Layout design method for common centroid matching of multiple transistor devices
By using the method of co-centricity matching of multiple transistor devices in the analog layout design, it is divided into inter-index and distributed uniformly, the problem of decreasing current matching accuracy under the influence of nonlinear gradients is solved, and the precise current matching and high performance of 13 transistor devices is achieved Accurate current replication.
Patent Information
- Application Number
- CN202411265368.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-10
- Publication Date
- 2024-12-13
AI Technical Summary
In analog layout design, when the number of transistors to match reaches more than 5, the nonlinear gradient has a great impact, resulting in a decrease in current matching accuracy, making it difficult for existing methods to achieve accurate matching.
Using the layout design method of matching the centroid of multiple transistor devices, the device is divided into intervening indexes to form reusable units, evenly distributed in an array of 16 rows and 9 columns, and a P-type substrate ring is inserted between every two columns, with edges Add virtual devices to ensure that the centroid of each device is at the origin, forming a tight layout to reduce the impact of nonlinear gradients.
Through this method, accurate current matching of 13 transistor devices is achieved, mismatch caused by nonlinear gradients is reduced, replication accuracy of gate voltage and source and drain currents is improved, and a higher current matching accuracy is achieved.
Smart Images
Figure CN119129511A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of analog integrated circuit layout, and in particular to a layout design method for matching the common centroid of multiple transistor devices. Background Art
[0002] In traditional analog layout design, when the number of transistors that need to be matched is 2 or 4, it is easier to use the common centroid matching method. When the number of matches reaches 5 or more, a layout method of side-by-side cross-value arrangement and close to each other will be used. This method is greatly affected by nonlinear gradients. For precisely matched currents, this design method will reduce the current matching accuracy.
[0003] The purpose of the present invention is to propose a layout design method for matching the common centroids of multiple transistor devices. When the number of transistors that need to be matched reaches 13, the layout area is compact and the common centroids are all at the origin. By reducing the distance between the centroids of the matching transistors, the mismatch caused by the gradient can be reduced, making each device less susceptible to the influence of nonlinear gradients, improving the replication of gate voltage and source-drain current, and achieving more accurate current matching. Summary of the invention
[0004] The present invention provides a layout design method for common centroid matching of multiple transistor devices, which can at least solve one of the technical problems in the background technology.
[0005] To achieve the above object, the present invention adopts the following technical solutions:
[0006] A layout design method for common centroid matching of multiple transistor devices includes generating layout devices, designing layout layout, designing layout wiring, physical verification, and post-simulation verification. The common centroid matching method of multiple transistor devices in the layout layout has the following specific steps:
[0007] Step 1: Divide multiple devices into N cross indices;
[0008] Step 2: Combining two cross-index devices into a reusable unit;
[0009] Step 3: Distribute multiple reusable units evenly on the layout;
[0010] Step 4: Distribute all devices evenly into 16 rows and 9 columns.
[0011] Furthermore, the matching method of the present invention adopts common centroid matching of 13 transistors.
[0012] Furthermore, in step 4 of the present invention, a P-type substrate ring is inserted between every two columns of devices to prevent latching.
[0013] Furthermore, in step 4 of the present invention, N14 devices are added as virtual devices at the edge of the device array to reduce the gate error in the process.
[0014] Furthermore, in the layout design of the present invention, 13 precisely matched currents and 13 transistor devices are evenly distributed around the layout, and the common centroid of each device is at the origin to form a layout structure with common centroid matching.
[0015] It can be seen from the above technical scheme that the layout design method for common centroid matching of multiple transistor devices of the present invention proposes a method for 13 precise current matching. The 13 transistor devices in this method adopt a layout structure with common centroid matching, including 13 devices N1-N13, each device is divided into N cross indexes of equal size, and all devices are evenly distributed in an array of 16 rows and 9 columns to the greatest extent. The centroid of each device coincides with the origin of the X-axis and the Y-axis to form a common centroid layout structure. The corresponding lines are symmetrical in equal length to achieve current matching, and the N14 device is added as a virtual device to reduce the production error of the device in the process. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 It is a flow chart of the layout design of common centroid matching of multiple transistor devices of the present invention;
[0017] Figure 2 It is a schematic diagram of step 2 of the present invention;
[0018] Figure 3 It is a schematic diagram of step three of the present invention;
[0019] Figure 4 It is a schematic diagram of step four of the present invention. DETAILED DESCRIPTION
[0020] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments.
[0021] like Figure 1 As shown, the layout design method described in this embodiment, in order to achieve the above-mentioned purpose, the present invention proposes the following technical solutions:
[0022] S1, generate layout devices of design units;
[0023] Using the Virtuoso tool, based on the process library information, all layout devices are generated according to the circuit of the design unit, and the layout area of the design unit is preliminarily confirmed.
[0024] S2, design unit layout;
[0025] The Nmos layout devices that need to be matched in the design unit are evenly arranged into 16 rows and 9 columns according to the method of matching the common centroid of multiple transistor devices, and a P-type substrate ring is inserted between the devices in every two columns to prevent latching. N14 devices are added as dummy devices at the edge of the array to reduce the gate error in the process.
[0026] Among them, the method of matching the common centroid of multiple transistor devices, such as Figure 1 As shown, the specific steps are as follows:
[0027] Step 1: Divide multiple devices into N cross indices;
[0028] N1 is 1 cross index, N2 is 1 cross index, N3 is 2 cross indexes, N4 is 4 cross indexes, N5 is 8 cross indexes, and N6-N13 are 16 cross indexes respectively. The current of the device increases in the same proportion as the cross index.
[0029] Step 2: Combine the two cross index devices into a reusable unit;
[0030] like Figure 2 As shown, N6 and N7 constitute unit A; N8 and N9 constitute unit B; and N10 and N11 constitute unit C.
[0031] Step 3: Distribute the reusable units evenly on the layout;
[0032] like Figure 3 As shown, in the four quadrants divided by the X-axis and the Y-axis, there are 2 units A, 2 units B, and 2 units C. The centroid formed by the line connecting the unit A in the first quadrant and the unit A in the third quadrant is at the origin, and the centroid formed by the line connecting the unit A in the second quadrant and the unit A in the fourth quadrant is at the origin. The centroid of unit A is at the origin, that is, the common centroid of devices N6 and N7 is at the origin.
[0033] Similarly, the centroid formed by the connecting lines of unit B is at the origin, that is, the common centroid of devices N8 and N9 is at the origin.
[0034] Similarly, the centroid formed by the connecting line of unit C is at the origin, that is, the common centroid of devices N10 and N11 is at the origin.
[0035] Step 4: Distribute all devices evenly into 16 rows and 9 columns
[0036] like Figure 4 As shown, N1 and N2 are distributed in the upper half of the Y axis.
[0037] N3, N4, and N5 are symmetrical about the X-axis and are respectively distributed on the center line of the Y-axis, so the common centroid of the devices of N3, N4, and N5 is at the origin.
[0038] N12 and N13 are symmetrical about the X-axis and Y-axis respectively. N12 is distributed near the X-axis, and N13 is distributed on the edge of the Y-axis. Then, the device centroids of N12 and N13 are at the origin.
[0039] The above 13 precisely matched currents, the number of 13 transistor devices are evenly distributed around the layout, the common centroid of each device is at the origin and forms a layout structure with common centroid matching. All devices are consistent in length and width and close to each other, forming a compact layout, which improves the accuracy of the current.
[0040] S3, layout and routing of design units;
[0041] Use metal wires to connect the signal lines between each device. In order to ensure that the parasitic resistance and capacitance in the connection of each device are as consistent as possible, equal length and spacing must also be considered in the wiring.
[0042] S4. Physically verify the designed layout;
[0043] Using the calibre tool, the geometric design rule DRC check is performed on the layout of the unit based on the DRC RULE provided by the process factory. The circuit is compared and the circuit consistency LVS check is performed on the layout of the unit.
[0044] S5, extracting post-simulation parameters and post-simulation verification;
[0045] After completing the physical verification, the parasitic parameters of the unit layout are extracted and simulated.
[0046] The present invention proposes a method for 13-way accurate current matching. The 13 transistor devices in the design adopt a common centroid matching layout structure, including 13 devices N1-N13, each device is divided into N cross indexes of equal size, and all devices are evenly distributed in an array of 16 rows and 9 columns to the greatest extent. The centroid of each device coincides with the origin of the X-axis and the Y-axis to form a common centroid layout structure. The corresponding lines are symmetrical in length to achieve current matching, and the N14 device is added as a virtual device to reduce the production error of the device in the process.
[0047] Through the layout structure of multi-transistor common centroid matching in step S2 of this solution, 13 devices are evenly distributed into 16 rows and 9 columns to achieve common centroid matching to reduce stress-induced mismatch.
[0048] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0049] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.
[0050] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A layout design method for matching the common centroid of multiple transistor devices, including generating layout devices, designing layout layout, designing layout wiring, physical verification, and post-simulation verification, characterized in that: The design layout includes a multi-transistor device common centroid matching method, and the specific steps are as follows: Step 1: Divide multiple devices into N cross indices; Step 2: Combining two cross-index devices into a reusable unit; Step 3: Distribute multiple reusable units evenly on the layout; Step 4: Distribute all devices evenly into 16 rows and 9 columns.
2. The layout design method for common centroid matching of multiple transistor devices according to claim 1, characterized in that: The method for common centroid matching of a multi-transistor device also includes matching the common centroid of 13 transistors.
3. The layout design method for common centroid matching of multiple transistor devices according to claim 2, characterized in that: The step four also includes inserting a P-type substrate ring between every two columns of devices to prevent latching.
4. The layout design method for common centroid matching of multiple transistor devices according to claim 3, characterized in that: In the step 4, N14 devices are added as virtual devices at the edge of the device array to reduce the gate error in the process.
5. The layout design method for common centroid matching of multiple transistor devices according to claim 1, characterized in that: The design layout also includes 13 precisely matched currents, and the number of 13 transistor devices is evenly distributed around the layout, and the common centroid of each device is at the origin to form a layout structure with common centroid matching.