Method for reducing height of step at bottom of Schottky groove

Abstract

The invention provides a method for reducing the height of a Schottky trench bottom step. The method comprises the following steps: providing a substrate, forming an N-type epitaxial layer on the substrate, forming a plurality of first trench gates in the N-type epitaxial layer, forming an etching stop layer to cover the N-type epitaxial layer and the first trench gates, and forming an interlayer dielectric layer covering the etching stop layer; a groove serving as a Schottky junction window is formed in an interlayer dielectric layer, and the method comprises the following steps that a Schottky groove forming area is defined through photoetching; performing first dry etching to form a first opening; performing wet etching to completely remove the interlayer dielectric layer reserved below the bottom surface of the first opening to the etching stop layer; and carrying out second dry etching, opening the exposed etching stop layer, forming a second opening as a Schottky groove, and enabling the top of the exposed Schottky groove to be relatively flat. According to the invention, the Schottky barrier metal layer at the undercut notch is formed relatively flat, and the final morphology is significantly improved.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, in particular to a method for reducing the step height of a Schottky groove bottom. Background Art

[0002] Schottky diodes have the advantages of low forward voltage drop and high switching frequency, and are widely used in power device fields such as switching power supplies and drive circuits.

[0003] However, the traditional Schottky diode has large reverse leakage, which makes the device prone to soft breakdown and reduces the breakdown voltage. In order to solve this problem, the industry has developed TMBS devices.

[0004] like Figure 1 , which is a schematic diagram of the structure of an existing TMBS device; an N-type epitaxial layer 202 is formed on the surface of an N-type semiconductor substrate 201, and a trench gate structure is formed in the N-type epitaxial layer 202, including a trench and a gate dielectric layer 204 formed on the inner surface of the trench and a polysilicon gate 203 filled in the trench. The trench gate structure is a MOS structure.

[0005] A Schottky barrier metal layer covers the surface of the N-type epitaxial layer 202 outside the trench gate structure, that is, outside the trench, and the Schottky barrier metal layer includes a Ti layer 205 and a TiN layer 206. The Schottky barrier metal layer and the N-type epitaxial layer 202 form a Schottky contact.

[0006] A front metal layer 208 needs to be formed on the top of the Schottky barrier metal layer. The front metal layer 208 leads to the anode of the TMBS device. The regional position of the anode is defined by the passivation layer 207 .

[0007] A back metal layer 209 is formed on the back side of the N-type semiconductor substrate 201 , and the back metal layer 209 leads out a cathode.

[0008] Working principle of TMBS device: Under normal bias, the Schottky junction is turned on, the turn-on voltage is small, and the forward conduction characteristics of the Schottky diode are retained; under reverse bias, the MOS structure depletes the N-type epitaxial layer 202 between the trenches, reduces the surface electric field, thereby reducing the leakage current and increasing the device breakdown voltage.

[0009] TMBS devices are usually integrated into power devices such as power MOSFETs. Figure 2 , which is a circuit diagram of a conventional power device integrated with a TMBS device; Figure 2 In the embodiment, the power device includes a parallel structure formed by connecting multiple MOSFET units in parallel and a TMBS device. The TMBS device adopts Figure 1 The structure shown.

[0010] The gates G of the MOSFET units are connected together, the sources S are connected together, and the drains D are connected together. The anode of the TMBS device is connected to the source S, and the cathode is connected to the drain D.

[0011] In shielded gate trench (SGT) power devices, the trench gate structure also includes an SGT structure. The SGT process flow of integrated Schottky diodes is to insert a Schottky process loop between the contact hole (CT) process loop and the barrier metal of conventional products. The overall process flow is expressed as:

[0012] Trench->Poly->body->IMP->Source->IMP->CT->Schottky(PH+ETCH+IMP)->barrier->WEB->TM->PV / PI.

[0013] Among them, Trench represents the process of forming the gate trench, Poly represents the process of forming the polysilicon gate, body IMP represents the body ion implantation, Source IMP represents the source ion implantation, CT represents the process of forming the contact hole opening, Schottky represents the Schottky process ring, (PH+ETCH+IMP) in Schottky represents the three sub-steps of Schottky, PH represents the lithography definition of the Schottky trench, ETCH represents the etching of the Schottky trench, and IMP represents the Schottky ion implantation. Barrier represents the process of forming the barrier metal, W EB represents the tungsten filling and etching back process of the contact hole, and TM represents the process of forming the front metal layer. PV / PI represents the process of forming the passivation layer and the pad window.

[0014] The existing Schottky trench etching process uses a two-step process of dry etching and wet etching, wherein the wet process requires an over-etching amount of more than 50%, and the undercut formed is easily too large, thus causing problems in the formation of barrier metal (blocking layer).

[0015] The sidewalls of the Schottky trench at the undercut position formed by the existing baseline process after wet etching are relatively straight and the step height is greater than the top tip of the mesa between the gate trenches. This is not conducive to the formation of a barrier metal layer during the subsequent sputtering process of Schottky metals such as Ti and TiN.

[0016] like Figure 3, is an electron microscope photograph of the device after the wet etching of the Schottky trench is completed in the existing TMBS device manufacturing method; the step height between the undercut and the platform area reaches 714 angstroms.

[0017] like Figure 4 , is an electron microscope photograph of the device after the Schottky barrier metal layer formation process is completed in the existing TMBS device manufacturing method.

[0018] like Figure 5 The figure shows an electron microscope photo of a device after the metal layer of the contact hole is etched back in the existing TMBS device manufacturing method; metal residues are easily formed on the side of the Schottky trench, usually tungsten residues. Figure 6 As shown, in the circled area, the Schottky barrier metal layer has a weak point, that is, the thickness is thinned or disconnected, so tungsten penetration is likely to occur, that is, the tungsten residue directly contacts the N-type epitaxial layer, which affects the performance of the device, such as the increase of zero gate voltage drain current (IDSS), the decrease of source-drain breakdown voltage (BVDSS), and finally the reduction of product yield.

[0019] In order to solve the above problems, it is necessary to propose a new method to reduce the step height of the Schottky groove bottom. Summary of the invention

[0020] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for reducing the step height of the Schottky trench bottom, so as to solve the problem of adverse effects caused by the undercut opening formed by over-etching of the interlayer dielectric layer at the bottom of the Schottky trench in the prior art.

[0021] To achieve the above-mentioned object and other related objects, the present invention provides a method for reducing the step height of the Schottky groove bottom, comprising:

[0022] Step 1, providing a substrate, on which an N-type epitaxial layer is formed, in which a plurality of first trench gates are formed, forming an etch stop layer to cover the N-type epitaxial layer and the first trench gates, and forming an interlayer dielectric layer covering the etch stop layer;

[0023] Step 2: forming a trench as a Schottky junction window in the interlayer dielectric layer, comprising the following sub-steps:

[0024] Step 21, photolithography defines the Schottky trench formation area;

[0025] Step 22, performing a first dry etching, wherein the first dry etching removes the interlayer dielectric layer within an etching depth range and forms a first opening, wherein a portion of the thickness of the interlayer dielectric layer is retained below a bottom surface of the first opening;

[0026] Step 23, performing wet etching to completely remove the interlayer dielectric layer retained below the bottom surface of the first opening to the etching stop layer;

[0027] The etching amount of the wet etching has an over-etching amount to ensure that the interlayer dielectric layer retained below the bottom surface of the first opening is completely removed;

[0028] Step 24, perform a second dry etching to open the exposed etch stop layer, form a second opening as a Schottky trench, make the top of the exposed Schottky trench flatter, and reduce the undercut notch formed at the bottom edge of the first opening by the over-etching amount of the wet etching.

[0029] Preferably, the first trench gate formed by the Schottky junction window in step 1 includes: a first gate trench, a first gate dielectric layer formed on the first gate trench, and a first gate conductive material layer filling the remaining first trench gate.

[0030] Preferably, the material of the etch stop layer in step one is silicon nitride.

[0031] Preferably, the thickness of the etch stop layer in step 1 is 50 to 70 angstroms.

[0032] Preferably, the second dry etching in step 24 uses CF4 and CHF3 as etching gases, and the gas ratio of CF4 to CHF3 is 5:9 to 7:9.

[0033] Preferably, the RF power of the second dry etching in step 24 is 380 to 420 W, and there is only one etching step.

[0034] Preferably, the undercut recess in step 24 is of inclined shape, and the step height of the undercut recess is less than 500 angstroms.

[0035] Preferably, the method also includes: step three, forming a Schottky barrier metal layer; at the bottom of the Schottky trench, making the Schottky barrier metal layer have a flat surface; the Schottky barrier metal layer and the epitaxial layer between the first trench gate are in contact to form a Schottky diode; step four, forming a front metal layer, the front metal layer and the Schottky barrier metal layer are in contact and serve as the anode of the Schottky diode.

[0036] Preferably, the Schottky barrier metal layer in step three comprises a Ti layer and a TiN layer stacked in sequence.

[0037] Preferably, a trench gate power device is also formed on the substrate.

[0038] Preferably, in step 1, a P-type well and a plurality of second trench gates are formed in the trench gate power device formation region;

[0039] The second trench gate comprises a second gate trench, a second gate dielectric layer and a second gate conductive material layer;

[0040] The second gate trenches are formed in the first epitaxial layer and each of the second gate trenches vertically passes through the P-type well, the second gate dielectric layer covers the inner surface of the second gate trench, and the second gate conductive material layer is filled in the second gate trench formed with the second gate dielectric layer;

[0041] An N+ doped source region is formed on the surface of the P-type well and the source region is self-aligned with the side surface of the second trench gate.

[0042] Preferably, before step three, before step two or after step two, it also includes: photolithography to define the contact hole formation area; etching to form a contact hole opening passing through the interlayer dielectric layer and the etch stop layer, and corresponding contact hole openings are formed on the top of the second gate conductive material layer and the top of the source region respectively; after step three and before step four, it also includes: depositing a first metal layer, the first metal layer completely fills the contact hole opening and forms the contact hole; etching back the first metal layer to completely remove the first metal layer on the surface of the interlayer dielectric layer outside the contact hole opening, and there is metal residue on the side of the Schottky trench, and at the bottom cut notch on the side of the Schottky trench, the flat structure of the Schottky barrier metal layer prevents the metal residue from causing metal puncture; in step four, after the front metal layer is patterned, a source and a gate are also formed at the same time, the top of the second gate conductive material layer is connected to the gate through the corresponding contact hole, and the top of the source region is connected to the source through the corresponding contact hole; the source and the anode are shared.

[0043] Preferably, the material of the first metal layer includes tungsten.

[0044] Preferably, the trench gate power device includes a trench gate power device with SGT; the second trench gate also includes an SGT structure, and the SGT structure includes a shielding conductive material layer, a shielding dielectric layer and an inter-gate dielectric layer; in each of the second gate trenches, each of the shielding dielectric layers is located on the inner surface of the second gate trench at the bottom of the second gate dielectric layer; the shielding conductive material layer and the second gate trench are isolated by the shielding dielectric layer; the shielding conductive material layer and the second gate conductive material layer are isolated by the inter-gate dielectric layer.

[0045] Preferably, after the front process is completed, the following back process is also included: thinning the substrate; forming an N+ doped drain region; the substrate is N+ doped, and the thinned semiconductor substrate acts as the drain region; or, performing N+ back ion implantation on the thinned substrate to form the drain region; forming a back metal layer, and the back metal layer constitutes the drain of the trench gate power device and also serves as the cathode of the Schottky diode.

[0046] Preferably, in step 2, after step 24 is completed, the method further includes: step 25, performing Schottky ion implantation.

[0047] As described above, the method of reducing the step height of the Schottky groove bottom of the present invention has the following beneficial effects:

[0048] The Schottky barrier metal layer at the bottom cut notch position of the present invention is formed relatively flat, and the final morphology is significantly improved; the present invention significantly improves the convergence of IDSS leakage, and also effectively reduces the probability of low yield in actual production. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 It is a schematic diagram of the structure of an existing TMBS device;

[0050] Figure 2 It is a circuit diagram of an existing power device integrated with a TMBS device;

[0051] Figure 3 This is an electron microscope photograph of the device after the wet etching of the Schottky trench is completed in the existing TMBS device manufacturing method;

[0052] Figure 4 It is an electron microscope photograph of the device after the Schottky barrier metal layer formation process is completed in the existing TMBS device manufacturing method;

[0053] Figure 5 This is an electron microscope photograph of the device after the metal layer of the contact hole is etched back in the existing TMBS device manufacturing method;

[0054] Figure 6 This is an electron microscope photo of tungsten penetration in an existing TMBS device;

[0055] Figure 7 Shown is a schematic diagram of the process flow of the present invention;

[0056] Figure 8 It is a schematic diagram showing the Schottky trench formation area defined by photolithography according to the present invention;

[0057] Fig. 9 It is a schematic diagram showing the formation of a first opening according to the present invention;

[0058] Fig.10Shown is a schematic diagram of the device structure after wet etching of the present invention;

[0059] Fig.11 It is a schematic diagram of etching back the first metal layer of the present invention;

[0060] Fig.12 This is an electron microscope photograph of the device after the metal layer of the contact hole is etched back in the manufacturing method of the TMBS device. DETAILED DESCRIPTION

[0061] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0062] See also Figure 7 The present invention provides a method for reducing the step height of the bottom of a Schottky groove, comprising:

[0063] Step 1, providing a substrate 101, on which an N-type epitaxial layer 102 is formed, in which a plurality of first trench gates are formed, forming an etch stop layer 110 to cover the N-type epitaxial layer 102 and the first trench gates, and forming an interlayer dielectric layer 111 covering the etch stop layer 110;

[0064] In some embodiments, the first trench gate formed by the Schottky junction window in step 1 includes: a first gate trench, a first gate dielectric layer 103 formed on the first gate trench, and a first gate conductive material layer 104 filling the remaining first trench gate.

[0065] In some embodiments, the material of the etch stop layer 110 in step 1 is silicon nitride.

[0066] In some embodiments, the thickness of the etch stop layer 110 in step 1 is 50 to 70 angstroms.

[0067] Step 2: forming a trench as a Schottky junction window in the interlayer dielectric layer 111, including the following steps:

[0068] Step 21, photolithography defines the Schottky trench formation area, forming Figure 8 Specifically, a photoresist layer 113 is formed on the interlayer dielectric layer 111, and then the photoresist layer 113 is opened by photolithography to define a Schottky trench formation area;

[0069] Step 22, performing a first dry etching, wherein the first dry etching removes the interlayer dielectric layer 111 within the etching depth range and forms a first opening, wherein a portion of the thickness of the interlayer dielectric layer 111 is retained below the bottom surface of the first opening, forming a Fig. 9 The structure shown;

[0070] Step 23, performing wet etching to completely remove the interlayer dielectric layer 111 retained below the bottom surface of the first opening to the etching stop layer 110;

[0071] The etching amount of the wet etching has an over-etching amount to ensure that the interlayer dielectric layer 111 retained below the bottom surface of the first opening is completely removed;

[0072] Step 24: Perform a second dry etching to open the exposed etching stop layer 110 and form a second opening as a Schottky trench. Fig.10 In the structure shown, since the wet etching of the bottom of the first opening stays on the etching stop layer 110, only the bottom of the second opening sidewall is etched to form an undercut notch, the top of the exposed Schottky trench can be flattened, and the undercut notch formed at the bottom edge of the first opening due to the over-etching amount of the wet etching can be reduced. After the wet etching, a dry etching step with a smaller etching amount is added, which significantly reduces the undercut notch caused by the etching amount of the wet etching. The step height of the undercut notch can be controlled to be less than 500 angstroms and the angle is relatively inclined, which is beneficial to the subsequent formation of the Schottky barrier metal layer 114;

[0073] In some embodiments, the second dry etching in step 24 uses CF4 and CHF3 as etching gases, and the gas ratio of CF4 to CHF3 is 5:9 to 7:9, for example, the gas ratio of CF4 to CHF3 is 5:9, 6:9 or 7:9.

[0074] In some embodiments, the RF power of the second dry etching in step 24 is 380 to 420 W, and there is only one step of etching, such as 380 W, 400 W or 420 W. A high proportion of CF4 gas can reduce the polymer of the etching reaction, which is beneficial to controlling the morphology. The RF power is 380 to 420 W and there is only one step of etching, which can effectively control the etching amount.

[0075] In some embodiments, in step 2, after step 24 is completed, the following further includes: step 25, performing Schottky ion implantation.

[0076] In some embodiments, the method further includes: step three, forming a Schottky barrier metal layer 114; at the bottom of the Schottky trench, making the Schottky barrier metal layer 114 have a flat surface; the Schottky barrier metal layer 114 and the epitaxial layer 102 between the first trench gate are in contact to form a Schottky diode; step four, forming a front metal layer, the front metal layer and the Schottky barrier metal layer 114 are in contact and serve as the anode of the Schottky diode.

[0077] In some embodiments, the Schottky barrier metal layer 114 in step three includes a Ti layer and a TiN layer stacked in sequence.

[0078] In some embodiments, a trench gate power device is also formed on the substrate 101 .

[0079] In some embodiments, in step 1, a P-type well and a plurality of second trench gates are formed in the trench gate power device formation region;

[0080] The second trench gate includes a second gate trench, a second gate dielectric layer 109 and a second gate conductive material layer 108;

[0081] The second gate trenches are formed in the first epitaxial layer 102 and each second gate trench passes through the P-type well vertically, the second gate dielectric layer 109 covers the inner surface of the second gate trench, and the second gate conductive material layer 108 is filled in the second gate trench formed with the second gate dielectric layer 109;

[0082] An N+ doped source region 112 is formed on the surface of the P-type well and the source region 112 is self-aligned with the side surface of the second trench gate.

[0083] In some embodiments, before step three, before step two or after step two, it also includes: photolithography to define the contact hole formation area; etching to form a contact hole opening through the interlayer dielectric layer 111 and the etch stop layer 110, and corresponding contact hole openings are formed on the top of the second gate conductive material layer 108 and the top of the source region 112 respectively; after step three and before step four, it also includes: depositing a first metal layer 115, the first metal layer 115 completely fills the contact hole opening and forms a contact hole; etching back the first metal layer 115 to completely remove the first metal layer 115 on the surface of the interlayer dielectric layer 111 outside the contact hole opening, and there is a metal residue 115a on the side of the Schottky trench, forming a Fig.11 In the structure shown, at the bottom cut notch on the side of the Schottky trench, the flat structure of the Schottky barrier metal layer 114 prevents metal residue from causing metal puncture; in step four, after the front metal layer is patterned, the source and gate are also formed at the same time, the top of the second gate conductive material layer 108 is connected to the gate through the corresponding contact hole, and the top of the source region 112 is connected to the source through the corresponding contact hole; the source and anode are shared.

[0084] In some embodiments, the material of the first metal layer 115 includes tungsten.

[0085] In some embodiments, the trench gate power device includes a trench gate power device with SGT; the second trench gate also includes an SGT structure, the SGT structure includes a shielding conductive material layer 106, a shielding dielectric layer 105 and an inter-gate dielectric layer 107; in each second gate trench, each shielding dielectric layer 105 is located on the inner surface of the second gate trench at the bottom of the second gate dielectric layer 109; the shielding conductive material layer 106 and the second gate trench are isolated by the shielding dielectric layer 105; the shielding conductive material layer 106 and the second gate conductive material layer 108 are isolated by the inter-gate dielectric layer 107.

[0086] In some embodiments, after the front process is completed, the following back process is also included: thinning the substrate 101; forming an N+ doped drain region; the substrate 101 is N+ doped, and the thinned semiconductor substrate 101 acts as the drain region; or, performing N+ back ion implantation on the thinned substrate 101 to form a drain region; forming a back metal layer, the back metal layer constitutes the drain of the trench gate power device and also serves as the cathode of the Schottky diode.

[0087] See also Fig.12 The Schottky barrier metal layer 114 at the undercut notch of the present invention is formed relatively flat, and the final morphology is relatively similar to Figure 5 The morphology of the prior art shown is significantly improved; the present invention significantly improves the convergence of IDSS leakage and effectively reduces the probability of low yield in actual production.

[0088] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0089] In summary, the Schottky barrier metal layer at the undercut notch position of the present invention is relatively flat, and the final morphology is significantly improved; the present invention significantly improves the convergence of IDSS leakage, and effectively reduces the probability of low yield in actual production. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0090] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for reducing the step height of a Schottky groove bottom, characterized in that: At least: Step 1, providing a substrate, on which an N-type epitaxial layer is formed, in which a plurality of first trench gates are formed, forming an etch stop layer to cover the N-type epitaxial layer and the first trench gates, and forming an interlayer dielectric layer covering the etch stop layer; Step 2: forming a trench as a Schottky junction window in the interlayer dielectric layer, comprising the following sub-steps: Step 21, photolithography defines the Schottky trench formation area; Step 22, performing a first dry etching, wherein the first dry etching removes the interlayer dielectric layer within an etching depth range and forms a first opening, wherein a portion of the thickness of the interlayer dielectric layer is retained below a bottom surface of the first opening; Step 23, performing wet etching to completely remove the interlayer dielectric layer retained below the bottom surface of the first opening to the etching stop layer; The etching amount of the wet etching has an over-etching amount to ensure that the interlayer dielectric layer retained below the bottom surface of the first opening is completely removed; Step 24, perform a second dry etching to open the exposed etch stop layer, form a second opening as a Schottky trench, make the exposed top of the Schottky trench more flat, and reduce the undercut notch formed at the bottom edge of the Schottky trench by the over-etching amount of the wet etching.

2. The method for reducing the step height of the Schottky groove bottom according to claim 1, characterized in that: The first trench gate formed by the Schottky junction window in step 1 includes: a first gate trench, a first gate dielectric layer formed on the first gate trench, and a first gate conductive material layer filling the remaining first trench gate.

3. The method for reducing the step height of the Schottky groove bottom according to claim 1, characterized in that: The material of the etching stop layer in step 1 is silicon nitride.

4. The method for reducing the step height of the Schottky groove bottom according to claim 1, characterized in that: The thickness of the etching stop layer in step 1 is 50 to 70 angstroms.

5. The method for reducing the step height of the Schottky groove bottom according to claim 1, characterized in that: The second dry etching in step 24 uses CF4 and CHF3 as etching gases, and the gas ratio of CF4 to CHF3 is 5:9 to 7:

9.

6. The method for reducing the step height of the Schottky groove bottom according to claim 1, characterized in that: The radio frequency power of the second dry etching in step 24 is 380 to 420 W, and there is only one step of etching.

7. The method for reducing the step height of the Schottky groove bottom according to claim 1, characterized in that: The undercut recess in step 24 has an inclined morphology, and a step height of the undercut recess is less than 500 angstroms.

8. The method for reducing the step height of the Schottky groove bottom according to claim 1, characterized in that: The method also includes: step 3, forming a Schottky barrier metal layer; at the bottom of the Schottky trench, the Schottky barrier metal layer has a flat surface; The Schottky barrier metal layer and the epitaxial layer between the first trench gate are in contact with each other to form a Schottky diode; Step 4: forming a front metal layer, wherein the front metal layer and the Schottky barrier metal layer are in contact with each other and serve as the anode of the Schottky diode.

9. The method for reducing the step height of the Schottky groove bottom according to claim 8, characterized in that: The Schottky barrier metal layer in step three includes a Ti layer and a TiN layer stacked in sequence.

10. The method for reducing the step height of the Schottky groove bottom according to claim 1, characterized in that: A trench gate power device is also formed on the substrate.

11. The method for reducing the step height of the Schottky groove bottom according to claim 10, characterized in that: In step 1, a P-type well and a plurality of second trench gates are formed in the trench gate power device forming region; The second trench gate comprises a second gate trench, a second gate dielectric layer and a second gate conductive material layer; The second gate trenches are formed in the first epitaxial layer and each of the second gate trenches vertically passes through the P-type well, the second gate dielectric layer covers the inner surface of the second gate trench, and the second gate conductive material layer is filled in the second gate trench formed with the second gate dielectric layer; An N+ doped source region is formed on the surface of the P-type well and the source region is self-aligned with the side surface of the second trench gate.

12. The method for reducing the step height of the Schottky groove bottom according to claim 8, characterized in that: Before step three, before step two or after step two, it also includes: photolithography to define the contact hole formation area; etching to form a contact hole opening passing through the interlayer dielectric layer and the etch stop layer, and corresponding contact hole openings are formed on the top of the second gate conductive material layer and the top of the source region respectively; after step three and before step four, it also includes: depositing a first metal layer, the first metal layer completely fills the contact hole opening and forms the contact hole; etching back the first metal layer to completely remove the first metal layer on the surface of the interlayer dielectric layer outside the contact hole opening, and there is metal residue on the side of the Schottky trench, and at the bottom cut notch on the side of the Schottky trench, the flat structure of the Schottky barrier metal layer prevents the metal residue from causing metal puncture; in step four, after the front metal layer is patterned, a source and a gate are also formed at the same time, the top of the second gate conductive material layer is connected to the gate through the corresponding contact hole, and the top of the source region is connected to the source through the corresponding contact hole; the source and the anode are shared.

13. The method for reducing the step height of the Schottky groove bottom according to claim 12, characterized in that: The material of the first metal layer includes tungsten.

14. The method for reducing the step height of the Schottky groove bottom according to claim 10, characterized in that: The trench gate power device includes a trench gate power device with SGT; the second trench gate also includes an SGT structure, and the SGT structure includes a shielding conductive material layer, a shielding dielectric layer and an inter-gate dielectric layer; in each of the second gate trenches, each of the shielding dielectric layers is located on the inner side surface of the second gate trench at the bottom of the second gate dielectric layer; the shielding conductive material layer and the second gate trench are isolated by the shielding dielectric layer; The shielding conductive material layer and the second gate conductive material layer are isolated from each other by the inter-gate dielectric layer.

15. The method for reducing the step height of the Schottky groove bottom according to claim 1, characterized in that: After the front process is completed, the following back process is also included: thinning the substrate; forming an N+ doped drain region; the substrate is N+ doped, and the thinned semiconductor substrate acts on the drain region; Alternatively, N+ back ion implantation is performed on the thinned substrate to form the drain region; A back metal layer is formed, which constitutes the drain of the trench gate power device and also serves as the cathode of the Schottky diode.

16. The method for manufacturing a TMBS device according to claim 1, wherein: In step 2, after step 24 is completed, the following further includes: step 25, performing Schottky ion implantation.

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