MOSFET device manufacturing method and device

Abstract

The invention discloses a manufacturing method of an MOSFET (metal-oxide-semiconductor field effect transistor) device. The method comprises the following steps: providing an MOSFET device semi-finished product; the MOSFET device semi-finished product comprises two grid electrodes and a source electrode contact hole; the source electrode contact hole is arranged between the two grid electrodes; forming a first gap layer, a second gap layer and a third gap layer on the MOSFET device semi-finished product; the third gap layer is arranged on the source electrode contact hole; the first gap layer is arranged on the second gap layer and the two grids; the second gap layer is arranged on the side walls of the two grid electrodes and is arranged between the source electrode contact hole and the grid electrodes; and removing the first gap layer and the third gap layer, and forming an ILD dielectric layer on the second gap layer and the two gates to obtain a target MOSFET device. The method can improve the precision problem of the source electrode contact hole and improve the miniaturization process of the device. The method can be widely applied to the technical field of semiconductors.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for manufacturing a MOSFET device and a device. Background Art

[0002] In the related art, the conventional process source contact hole (Source hole) of SiC planar MOSFET is formed by photolithography and etching process. Due to the accuracy of photolithography and etching, a certain safety distance needs to be maintained between the Source hole and the gate polycrystalline. Usually, a safety distance of about 0.8-1.2um is required between the Source hole and the gate polycrystalline, which easily limits the further reduction of the cell size of SiC planar MOSFET. Therefore, there are still technical problems that need to be solved in the related art. Summary of the invention

[0003] The purpose of this application is to solve one of the technical problems existing in the prior art to at least a certain extent.

[0004] To this end, an object of an embodiment of the present application is to provide a method for manufacturing a MOSFET device and a device, which can improve the accuracy problem of the source contact hole and improve the miniaturization process of the device.

[0005] In order to achieve the above technical objectives, the technical solution adopted in the embodiment of the present application includes: a MOSFET device manufacturing method, including: providing a semi-finished MOSFET device; the semi-finished MOSFET device includes two gates and a source contact hole; the source contact hole is arranged between the two gates; a first gap layer, a second gap layer and a third gap layer are formed on the semi-finished MOSFET device; the third gap layer is arranged on the source contact hole; the first gap layer is arranged on the second gap layer and the two gates; the second gap layer is arranged on the side walls of the two gates and between the source contact hole and the gate; the first gap layer and the third gap layer are removed, and an ILD dielectric layer is formed on the second gap layer and the two gates to obtain a target MOSFET device.

[0006] In addition, a method for manufacturing a MOSFET device according to the above embodiment of the present invention may also have the following additional technical features: Further, in an embodiment of the present application, forming a first gap layer, a second gap layer and a third gap layer on the semi-finished MOSFET device specifically includes: A silicon nitride layer with a thickness of 3000 angstroms to 5000 angstroms is deposited on the semi-finished MOSFET device by a CVD process to obtain a first gap layer, a second gap layer and a third gap layer.

[0007] Further, in an embodiment of the present application, removing the first gap layer and the third gap layer, and forming an ILD dielectric layer on the second gap layer and the two gates to obtain a target MOSFET device specifically includes: removing the first gap layer and the third gap layer by anisotropic dry etching; An ILD dielectric layer is formed on the gate by a thermal oxidation process to obtain a target MOSFET device.

[0008] Furthermore, in the embodiment of the present application, the thickness of the ILD dielectric layer is 5000 angstroms to 8000 angstroms.

[0009] Furthermore, in an embodiment of the present application, the semi-finished MOSFET device is obtained by the following steps: providing a substrate layer; forming an epitaxial layer on the substrate layer; forming a P-well on the substrate layer; forming an N-type heavily doped region and a P-type heavily doped region on the P-well; forming two gates on the substrate layer and forming a source contact hole between the two gates; the source contact hole is arranged on the N-type heavily doped region and the P-type heavily doped region.

[0010] Furthermore, in an embodiment of the present application, the forming of two gates on the substrate layer and the forming of a source contact hole between the two gates specifically includes: forming an oxide layer on the substrate layer; depositing a polysilicon layer on the oxide layer; removing the oxide layer and the polysilicon layer located on the N-type heavily doped region and the P-type heavily doped region to obtain two gates and form a source contact hole between the two gates.

[0011] Furthermore, in an embodiment of the present application, the thickness of the oxide layer is one tenth of the thickness of the polysilicon layer.

[0012] Furthermore, in an embodiment of the present application, the thickness of the second gap layer is less than or equal to 0.5 um.

[0013] In addition, the present application also provides a MOSFET device, which is manufactured by any of the MOSFET device manufacturing methods described above.

[0014] The advantages and benefits of the present application will be partially given in the following description, and partially become apparent from the following description, or be understood through the practice of the present application: The present application can form a first gap layer, a second gap layer and a third gap layer on a semi-finished MOSFET device with two gates and a source contact hole; the third gap layer is arranged on the source contact hole; the first gap layer is arranged on the second gap layer and the two gates; the second gap layer is arranged on the side walls of the two gates and between the source contact hole and the gates; the first gap layer and the third gap layer are removed, and an ILD dielectric layer is formed on the second gap layer and the two gates to obtain a target MOSFET device. The present application does not require a photolithography process to form a gap layer on the side walls of the two gates and between the source contact hole and the gate. The present application can improve the accuracy problem of the source contact hole in the traditional process and improve the miniaturization process of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a structural schematic diagram of a MOSFET device in the related art; Figure 2 A schematic diagram of the steps of a method for manufacturing a MOSFET device in a specific embodiment of the present invention; Figure 3 A schematic diagram of structural changes of a method for manufacturing a MOSFET device in a specific embodiment of the present invention; Figure 4 It is a schematic structural diagram of a MOSFET device in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0016] The embodiments of the present invention are described in detail below in conjunction with the accompanying drawings to illustrate the MOSFET device manufacturing method and the principle and process of the MOSFET device in the embodiments of the present invention.

[0017] First, refer to Figure 1 , explain the technical problems existing in the relevant technology: exist Figure 1In the figure, 1 is a silicon carbide substrate, 2 is a silicon carbide epitaxial layer, 3 is a P-type well, 4 is a P-type heavily doped layer, 5 is an N-type heavily doped layer, 6 is a gate oxide layer, 7 is a gate polycrystalline layer, 8 is a source contact hole (Source hole), 9 is an ILD dielectric layer, 10 is a drain, and 11 is the distance between the source contact hole and the gate polycrystalline diameter. In the traditional process, when removing the ILD dielectric layer, there is a photolithography offset error accuracy affecting the photolithography offset of about 0.1-0.3um. When etching the Source contact hole, there is a dielectric layer etching lateral erosion effect. Depending on the thickness of the dielectric layer and the etching process, the lateral erosion is about 0.1-0.2um. In this way, the total maximum error of photolithography and etching is about 0.5um. It is necessary to leave a safety margin spacing of more than 0.5um between the Source hole and the gate polycrystalline to avoid the short circuit between the Gate and Source poles, but this limits the further reduction of the cell design size. Therefore, there are still technical problems that need to be solved in the relevant technology.

[0018] Reference Figure 2 The present application provides a method for manufacturing a MOSFET device, comprising the following steps S101 to S103.

[0019] S101, providing a semi-finished MOSFET device; the semi-finished MOSFET device includes two gates and a source contact hole; the source contact hole is arranged between the two gates.

[0020] S102, forming a first gap layer, a second gap layer and a third gap layer on the semi-finished MOSFET device; the third gap layer is arranged on the source contact hole; the first gap layer is arranged on the second gap layer and the two gates; the second gap layer is arranged on the side walls of the two gates and is arranged between the source contact hole and the gate.

[0021] S103 , removing the first gap layer and the third gap layer, and forming an ILD dielectric layer on the second gap layer and the two gates to obtain a target MOSFET device.

[0022] Further, in some embodiments of the present application, the step of forming a first gap layer, a second gap layer, and a third gap layer on the semi-finished MOSFET device may specifically include: A silicon nitride layer with a thickness of 3000 angstroms to 5000 angstroms is deposited on the semi-finished MOSFET device by a CVD process to obtain a first gap layer, a second gap layer and a third gap layer.

[0023] Furthermore, in some embodiments of the present application, the step of removing the first gap layer and the third gap layer, and forming an ILD dielectric layer on the second gap layer and the two gates to obtain the target MOSFET device may specifically include steps S201 and S202.

[0024] S201 , removing the first gap layer and the third gap layer by anisotropic dry etching.

[0025] S202 , forming an ILD dielectric layer on the gate by a thermal oxidation process to obtain a target MOSFET device.

[0026] Furthermore, in some embodiments of the present application, the thickness of the ILD dielectric layer is 5000 angstroms to 8000 angstroms.

[0027] Furthermore, in some embodiments of the present application, a semi-finished MOSFET device is obtained through steps S301 to S305.

[0028] S301, providing a substrate layer.

[0029] S302, forming an epitaxial layer on the substrate layer.

[0030] S303 , forming a P well on the substrate layer.

[0031] S304 , forming an N-type heavily doped region and a P-type heavily doped region on the P well.

[0032] S305, forming two gates on the substrate layer and forming a source contact hole between the two gates; the source contact hole is arranged on the N-type heavily doped region and the P-type heavily doped region.

[0033] Furthermore, in some embodiments of the present application, the step of forming two gates on the substrate layer and forming a source contact hole between the two gates may specifically include steps S401 to S403.

[0034] S401, forming an oxide layer on the substrate layer.

[0035] S402 , depositing a polysilicon layer on the oxide layer.

[0036] S403 , removing the oxide layer and the polysilicon layer on the N-type heavily doped region and the P-type heavily doped region to obtain two gates and forming a source contact hole between the two gates.

[0037] Furthermore, in some embodiments of the present application, the thickness of the oxide layer is one tenth of the thickness of the polysilicon layer.

[0038] Furthermore, in some embodiments of the present application, the thickness of the oxide layer is 400-600 angstroms.

[0039] Furthermore, in some embodiments of the present application, the thickness of the second gap layer is less than or equal to 0.5 um.

[0040] Reference Figure 3 as well as Figure 4 The specific process steps of the Source hole self-alignment process of this application are: 1. The first step is to prepare a silicon carbide wafer material sheet, which is usually 100mm, 150mm or 200mm in diameter (i.e. 4 inches, 6 inches or 8 inches). 1 is a silicon carbide substrate, which corresponds to an N-channel MOSFET substrate doped with N-type, generally doped with nitrogen impurities, and the resistivity of the silicon carbide substrate is generally 0.01-0.02 Ω·cm, with a thickness of 250-350um. 2 is a silicon carbide epitaxial layer, which is generally 0.5-100um thick and is selected according to the breakdown voltage of the product. The thickness is also generally selected according to the breakdown voltage of the actual product.

[0041] 2. The second step is the formation of the P-well. According to the design of the mask pattern, P-type impurities are doped into the silicon carbide wafer through a high-temperature ion implantation process through photolithography and etching processes to form a P-well structure.

[0042] 3. The third step is the formation of the N-type heavily doped region. According to the design of the mask pattern, a high concentration of N-type impurities is doped into the silicon carbide wafer through a high-temperature ion implantation process through photolithography and etching processes to form an N-type heavily doped region. The area between the N-type heavily doped region and the P-well boundary forms the channel region of the silicon carbide MOSFET.

[0043] 4. The fourth step is the formation of a P-type heavily doped region. According to the design of the mask pattern, a high concentration of P-type impurities is doped into the silicon carbide wafer through a high-temperature ion implantation process through photolithography and etching processes to form a P-type heavily doped region. The P-type heavily doped region is generally located in the middle of the P-well.

[0044] 5. The fifth step is the deposition of gate oxide and gate polycrystalline electrodes. A 400-600 angstrom oxide layer is formed on the surface of silicon carbide through a high-temperature oxidation process, and then a 4000-6000 angstrom in-situ doped polysilicon layer is deposited through a CVD process to form a gate electrode.

[0045] 6. The sixth step is the formation of the gate. According to the design of the mask pattern, the gate is formed on the silicon carbide wafer through lithography and etching processes.

[0046] 7. Deposition of contact hole spacer layer: deposit a silicon nitride layer or other dielectric layer that cannot be oxidized with a thickness of about 3000-5000 angstroms on the gate by CVD process. The specific thickness is set according to the required spacing between the source contact hole and the gate to obtain the required spacer width. The first gap layer, the second gap layer and the third gap layer can be formed at the same time. The first gap layer corresponds to the silicon nitride layer above the gate. The second gap layer corresponds to the silicon nitride layer on the side wall of the gate. The third silicon nitride layer corresponds to the silicon nitride layer above the P well.

[0047] 8. Formation of contact hole spacer: Part of the dielectric spacer layer on and between the gates is removed by anisotropic dry etching, and a dielectric spacer layer of a certain width is retained on both sides of the gate polycrystalline. The width of the dielectric spacer layer is controlled by the thickness of the deposited dielectric layer and the etching conditions. In this way, the spacing between the Source contact hole and the gate is accurately obtained, avoiding the fluctuation of the spacing between the Source contact hole and the gate caused by the Source hole photolithography overlay accuracy and etching deviation in conventional processes.

[0048] 9. Formation of ILD dielectric layer: A layer of ILD dielectric layer of about 5000 angstroms to 8000 angstroms is grown on the gate polycrystalline through a thermal oxidation process. Since the oxidation rate of silicon carbide is much lower than that of the polycrystalline silicon layer, and the dielectric spacer layer cannot produce a thermal oxidation layer, the ILD dielectric layer is basically grown only on the gate polycrystalline silicon, and the oxide layer grown at the position of the Source contact hole is very small, and the dielectric spacer layer remains unchanged. In this way, the Source contact hole can be formed by removing the oxide layer at the position of the Source contact hole through a relatively short wet etching process. The Source contact hole self-alignment process of this embodiment eliminates the need for Source contact hole photolithography and etching, and the formation of the Source contact hole can be completed, and the spacing between the Source contact hole and the gate can be accurately controlled by the spacer.

[0049] In this embodiment, a dielectric spacer structure is combined with a local polysilicon oxidation process to form a Source contact hole by self-alignment, so that the spacing between the Source contact hole and the gate can be reduced from about 0.8-1.2um to about 0.3um at the lowest, so that the cell size of the silicon carbide MOSFET can be reduced by 20%-30%, and the on-resistance is reduced by about 20%-25%, which greatly improves the power density of the silicon carbide MOSFET, reduces the size of the chip, and reduces one photolithography and etching, thereby saving the cost of process processing and reducing the cost of a single chip.

[0050] In addition, the present application also provides a MOSFET device, which is manufactured by any of the above MOSFET device manufacturing methods.

[0051] It should be noted that the contents of the above-mentioned MOSFET device manufacturing method embodiment are all applicable to the present MOSFET device embodiment, the functions specifically implemented by the present MOSFET device embodiment are the same as those of the above-mentioned MOSFET device manufacturing method embodiment, and the beneficial effects achieved are also the same as those achieved by the above-mentioned MOSFET device manufacturing method embodiment.

[0052] In some selectable embodiments, the function / operation mentioned in the block diagram may not occur in the order mentioned in the operation diagram. For example, depending on the function / operation involved, the two boxes shown in succession can actually be executed substantially simultaneously or the boxes can sometimes be executed in reverse order. In addition, the embodiment presented and described in the flow chart of the application is provided by way of example, for the purpose of providing a more comprehensive understanding of technology. The disclosed method is not limited to the operation and logic flow presented herein. Selectable embodiments are expected, wherein the order of various operations is changed and the sub-operation of a part described as a larger operation is performed independently.

[0053] In the above description of this specification, the description with reference to the terms "one embodiment / example", "another embodiment / example" or "certain embodiments / examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0054] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

[0055] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the described embodiments. Technical personnel familiar with the field may make various equivalent modifications or substitutions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A method for manufacturing a MOSFET device, characterized in that: include: Provide semi-finished products of MOSFET devices; The semi-finished MOSFET device includes two gate electrodes and a source contact hole; The source contact hole is arranged between the two gates; A first gap layer, a second gap layer and a third gap layer are formed on the semi-finished MOSFET device; the third gap layer is arranged on the source contact hole; the first gap layer is arranged on the second gap layer and the two gates; the second gap layer is arranged on the side walls of the two gates and between the source contact hole and the gate; The first gap layer and the third gap layer are removed, and an ILD dielectric layer is formed on the second gap layer and the two gates to obtain a target MOSFET device.

2. The method for manufacturing a MOSFET device according to claim 1, characterized in that: The forming of a first gap layer, a second gap layer and a third gap layer on the semi-finished MOSFET device specifically includes: A silicon nitride layer with a thickness of 3000 angstroms to 5000 angstroms is deposited on the semi-finished MOSFET device by a CVD process to obtain a first gap layer, a second gap layer and a third gap layer.

3. The method for manufacturing a MOSFET device according to claim 1, wherein: The removing of the first gap layer and the third gap layer, and forming an ILD dielectric layer on the second gap layer and the two gates to obtain a target MOSFET device specifically includes: removing the first gap layer and the third gap layer by anisotropic dry etching; An ILD dielectric layer is formed on the gate by a thermal oxidation process to obtain a target MOSFET device.

4. The method for manufacturing a MOSFET device according to claim 3, characterized in that: The thickness of the ILD dielectric layer is 5000 angstroms to 8000 angstroms.

5. The method for manufacturing a MOSFET device according to claim 1, characterized in that: The semi-finished MOSFET device is obtained by the following steps: providing a substrate layer; forming an epitaxial layer on the substrate layer; forming a P well on the substrate layer; forming an N-type heavily doped region and a P-type heavily doped region on the P-well; Two gates are formed on the substrate layer and a source contact hole is formed between the two gates; the source contact hole is arranged on the N-type heavily doped region and the P-type heavily doped region.

6. The method for manufacturing a MOSFET device according to claim 5, characterized in that: The step of forming two gates on the substrate layer and forming a source contact hole between the two gates specifically includes: forming an oxide layer on the substrate layer; depositing a polysilicon layer on the oxide layer; The oxide layer and the polysilicon layer located on the N-type heavily doped region and the P-type heavily doped region are removed to obtain two gates and form a source contact hole between the two gates.

7. The method for manufacturing a MOSFET device according to claim 6, characterized in that: The thickness of the oxide layer is one tenth of the thickness of the polysilicon layer.

8. The method for manufacturing a MOSFET device according to claim 6, characterized in that: The thickness of the oxide layer is 400-600 angstroms.

9. The method for manufacturing a MOSFET device according to claim 1, characterized in that: The thickness of the second gap layer is less than or equal to 0.5 um.

10. A MOSFET device, characterized in that: The MOSFET device is manufactured by the method for manufacturing the MOSFET device according to any one of claims 1 to 9.

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