Wafer chip partition grabbing method and device, computer equipment and storage medium

Abstract

The invention discloses a wafer chip partition grabbing method and device, computer equipment and a storage medium. The wafer chip partition grabbing method comprises the steps of obtaining wafer graphic data; performing region division on the wafer pattern region according to the wafer pattern data so as to form different division regions; and setting chip grabbing modes for the different divided areas, and grabbing the chips according to the set chip grabbing modes. According to the invention, the chips with different performances in the same BIN in the wafer are divided into different areas, and the grabbing modes are set for the different areas, so that the problem of grabbing errors caused by large movement span during traditional grabbing is avoided, and meanwhile, the working efficiency is also improved.

Description

Technical Field

[0001] The present invention relates to the field of chip packaging technology, and more specifically to a wafer chip partition grabbing method, device, computer equipment and storage medium. Background Art

[0002] In the existing packaging technology, the chip grabbing method is single. The server instructs the grabbing device to grab all the selected BIN chips in the wafer pattern through the wafer pattern data and the selected BIN information. Figure 1 The black arrow direction is the chip grabbing direction. Figure 1 In the figure, the area surrounded by the black circle is the wafer pattern area. The green square 2 in the wafer pattern area represents a good chip, the red square D represents a bad chip, and the white square represents that there is no chip at that position. The chip to be captured is a good chip. Figure 1 As shown, in the row where the black arrow is located, there are two green squares 2 near the left and right ends, and the middle is all white squares. After the second green square 2 near the left end is grasped, the grasping device needs to cross all the white squares in the middle to grasp the first green square 2 near the right. The span of the mobile grasping is large, and the situation indicated by the yellow arrow will appear, that is, there will be an upward, downward, leftward and rightward offset, resulting in the risk of chip grasping errors, and the efficiency is also relatively low. Summary of the invention

[0003] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a wafer chip partition capture method, device, computer equipment and storage medium, aiming to reduce the risk of chip capture errors and improve the capture efficiency.

[0004] To achieve the above object, the present invention adopts the following technical solutions:

[0005] In a first aspect, the present invention provides a wafer chip partition grabbing method, comprising:

[0006] Obtain wafer pattern data;

[0007] Dividing the wafer pattern area according to the wafer pattern data to form different divided areas;

[0008] Chip grabbing methods are set for different divided areas, and chips are grabbed according to the set chip grabbing methods.

[0009] Furthermore, the wafer pattern area is divided according to the wafer pattern data to form different divided areas, including:

[0010] Get wafer MAP data;

[0011] According to the wafer MAP data, the wafer graphic area is divided into an inner circle and an outer circle, where the inner circle and the outer circle are chips of the same BIN category but with different internal performance.

[0012] Furthermore, the step of dividing the wafer pattern area according to the wafer pattern data to form different divided areas includes:

[0013] The number of divided areas is set based on the center line of the wafer pattern area.

[0014] The wafer pattern area is divided according to a set number of areas to form a plurality of sector-shaped divided areas.

[0015] Furthermore, the step of dividing the wafer pattern area according to the wafer pattern data to form different divided areas includes:

[0016] Get wafer MAP data;

[0017] According to the wafer MAP data, the wafer graphic area is divided into an inner circle and an outer circle, where the inner circle and the outer circle are chips of the same BIN category but with different internal performance.

[0018] Use the center line of the inner circle as the division basis and set the number of divided areas;

[0019] The inner circle is divided according to the set number of regions to form multiple inner circle sector-shaped division regions.

[0020] Furthermore, the chip grabbing method is set for different divided areas, and the chip grabbing is performed according to the set chip grabbing method, including:

[0021] Get the BIN and other chip information that needs to be captured;

[0022] Shield the BIN chips that cannot be grabbed in the divided area;

[0023] According to the set chip grabbing method, grab the selected BIN other chips from the divided area.

[0024] Furthermore, the BIN chips that cannot be captured in the shielded area include:

[0025] Get the specified type of MASK;

[0026] Send MASK to the divided area to form an image mask for the BIN chips that cannot be captured.

[0027] Furthermore, the step of grabbing the selected BIN chips from the divided areas according to the set chip grabbing method includes:

[0028] Get the MAP information of the BIN chips to be captured in the divided area;

[0029] According to the MAP information of the BIN chip to be captured, capture it row by row from left to right or from right to left.

[0030] In a second aspect, the present invention further provides a wafer chip partition grabbing device, comprising:

[0031] An acquisition unit, used for acquiring wafer pattern data;

[0032] A region division unit, used for dividing the wafer pattern region according to the wafer pattern data to form different divided regions;

[0033] The grabbing unit is used to set chip grabbing methods for different divided areas and to grab chips according to the set chip grabbing methods.

[0034] In a third aspect, the present invention further provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the wafer chip partition capture method as described above when executing the computer program.

[0035] In a fourth aspect, the present invention further provides a computer-readable storage medium, wherein the storage medium stores a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by a processor, the processor executes the wafer chip partition capture method as described above.

[0036] Compared with the prior art, the present invention has the following beneficial effects: a wafer chip partition grabbing method, comprising: obtaining wafer graphic data; dividing the wafer graphic area according to the wafer graphic data to form different divided areas; setting chip grabbing methods for different divided areas, and performing chip grabbing according to the set chip grabbing methods. By dividing the chips with different performances of the same BIN in the wafer into different areas and setting grabbing methods for different areas, the problem of grabbing errors caused by large moving spans during traditional grabbing is avoided, and work efficiency is also improved.

[0037] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following preferred embodiments are specifically cited and described in detail as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying any creative work.

[0039] Figure 1 A schematic diagram of wafer chip grabbing in the prior art;

[0040] Figure 2 A flowchart of a wafer chip partition grabbing method provided by a specific embodiment of the present invention;

[0041] Figure 3 A schematic block diagram of a wafer chip partition grabbing device provided in a specific embodiment of the present invention;

[0042] Figure 4 A schematic block diagram of a computer device provided for a specific embodiment of the present invention;

[0043] Figure 5 A schematic diagram of dividing a wafer pattern area into an inner circle and an outer circle provided in a specific embodiment of the present invention;

[0044] Figure 6 A schematic diagram of dividing a wafer pattern area into four quadrants is provided for a specific embodiment of the present invention. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0046] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0047] It should also be understood that the terms used in the present specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the present specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0048] It should be further understood that the term "and / or" used in the present description and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0049] like Figure 2 As shown, an embodiment of the present invention provides a wafer chip partition grabbing method, including the following steps: S10-S30.

[0050] S10, obtaining wafer pattern data.

[0051] Wafer graphic data can be obtained through a scanning electron microscope (SEM), an optical microscope or other image acquisition equipment. The surface image data of the wafer is obtained through these devices, and then the graphic data of the wafer is generated. The purpose of obtaining wafer graphic data is to obtain detailed information about the wafer, including wafer MAP data, the location of each chip in the wafer, etc. Among them, wafer MAP data refers to the test results or classification of the chip. Chips with different BINs are usually used to indicate the quality, function, performance, etc. of the chip. For example: BIN1 represents a fully qualified chip, BIN2 represents a partially qualified chip with limited functions, and BIND or BIN X represents an unqualified chip.

[0052] S20, dividing the wafer pattern area according to the wafer pattern data to form different divided areas.

[0053] In one embodiment, step S20 specifically includes the following steps: S201 - S202 .

[0054] S201, obtaining wafer MAP data.

[0055] The wafer MAP data can be used to obtain the performance and distribution of other chips in the same BIN on the same wafer.

[0056] S202. Divide the wafer graphic area into an inner circle and an outer circle according to the wafer MAP data, wherein the inner circle and the outer circle are chips of the same BIN type but with different internal performances.

[0057] Divide BIN chips of the same performance into the same circle, that is, the inner circle or the outer circle.

[0058] like Figure 5 As shown, Figure 5 There are three types of BIN chips with different performances, one is the red block D, representing defective products, one is the green block 2, representing a good product category, and one is the blue block 1, representing another good product category. In this embodiment, the chips in the outer circle are set to the green block BIN2, and the chips in the inner circle are set to the blue block BIN1.

[0059] For steps S201-S202, the chips of the same BIN in the wafer are divided into areas according to different performances by means of circles, which is beneficial for subsequent capture.

[0060] In one embodiment, step S20 specifically includes the following steps: S201A-S202A.

[0061] S201A, using the center line of the wafer graphic area as the division reference, setting the number of divided areas.

[0062] S202A, dividing the wafer pattern area according to a set number of areas to form a plurality of sector-shaped divided areas.

[0063] For steps S201A-S202A, if Figure 6 As shown, there are two BIN chips in the wafer, blue square 1 and red square D. In this embodiment, four areas are divided, namely Figure 6 The four quadrants.

[0064] In one embodiment, step S20 specifically includes the following steps: S201B-S204B.

[0065] S201B, obtain wafer MAP data.

[0066] S202B, dividing the wafer pattern area into an inner circle and an outer circle according to the wafer MAP data, wherein the inner circle and the outer circle are chips of the same BIN type but with different internal performances.

[0067] S203B, using the center line of the inner circle as the division basis, set the number of divided areas.

[0068] S204B, dividing the inner circle according to the set number of regions to form a plurality of inner circle sector-shaped divided regions.

[0069] For steps S201B-S204B, the division method of inner and outer circles and center lines is combined, which is beneficial to subsequent grasping.

[0070] S30, setting chip grabbing methods for different divided areas, and performing chip grabbing according to the set chip grabbing methods.

[0071] In one embodiment, step S30 specifically includes the following steps: S301 - S303 .

[0072] S301, obtain the BIN and other chip information that needs to be captured.

[0073] According to production requirements, determine the target BIN type to be grabbed. For example, Figure 5 As shown, the green square 2 located in the outer circle is selected as the target to be grasped.

[0074] S302, shielding the BIN chips that cannot be captured in the divided area.

[0075] like Figure 5 As shown, the red square D in the outer circle is shielded, that is, the red square D is a BIN chip that cannot be captured.

[0076] In one embodiment, step S302 specifically includes the following steps: S3021 - S3022 .

[0077] S3021. Obtain a specified type of MASK.

[0078] S3022. Send a MASK to the divided area to form an image mask for the BIN chips that cannot be captured.

[0079] For steps S3021-S3022, a mask (MASK) is generated by analyzing the wafer MAP data to mark the locations of all ungraspable BIN chips. The mask is a two-dimensional matrix corresponding to the wafer MAP data, marking the locations of ungraspable chips. After obtaining the specified type of MASK, the MASK needs to be applied to the divided area to form an image mask to shield the ungraspable BIN chips. According to the results of the MASK application, the data of each sub-area is updated to ensure that only the information of the graspable chips is retained. After the update, there will be no ungraspable BIN chips.

[0080] S303, grab the selected BIN chips from the divided area according to the set chip grabbing method.

[0081] In one embodiment, step S303 specifically includes the following steps: S3031 - S3032 .

[0082] S3031. Obtain MAP information of other BIN chips to be captured in the divided area.

[0083] S3032. Capture row by row from left to right or from right to left according to the MAP information of other chips of the BIN to be captured.

[0084] For steps S3031-S3032, since the BIN chips that cannot be captured are shielded by image masking, the captured data can be captured row by row in a set manner. Figure 6As shown, first grab the top row of blue blocks 2 in the first quadrant from left to right one by one, after grabbing the top row, grab the blue blocks 2 from the next row from the top one by one from right to left, after grabbing this row, grab the blue blocks 2 from the next row from left to right one by one. After grabbing the blue blocks 2 in the first quadrant, grab them in another quadrant. This grabbing method can greatly reduce the moving span of the grabbing device.

[0085] The present invention divides chips with different performances in the same BIN in a wafer into different areas and sets grabbing methods for different areas, thereby avoiding the problem of grabbing errors caused by a large moving span during traditional grabbing and also improving work efficiency.

[0086] The embodiment of the present invention also provides a wafer chip partition grabbing device, which is used to perform the steps in any embodiment of the wafer chip partition grabbing method described above. Figure 3 , Figure 3 A schematic block diagram of a wafer chip partition grabbing device 100 provided in an embodiment of the present application is shown. The wafer chip partition grabbing device 100 specifically includes:

[0087] The acquisition unit 110 is used to acquire wafer graphic data; the area division unit 120 is used to divide the wafer graphic area according to the wafer graphic data to form different divided areas; the grasping unit 130 is used to set the chip grasping method for the different divided areas and grasp the chip according to the set chip grasping method.

[0088] In one embodiment, the area division unit 120 includes:

[0089] The first acquisition module is used to acquire wafer MAP data; the first setting module is used to divide the wafer graphic area into an inner circle and an outer circle according to the wafer MAP data, wherein the inner circle and the outer circle are chips of the same BIN type but with different internal performances.

[0090] In one embodiment, the area division unit 120 includes:

[0091] The first division module is used to set the number of divided areas based on the center line of the wafer graphic area as the division basis; the second setting module is used to divide the wafer graphic area according to the set number of areas to form a plurality of sector-shaped divided areas.

[0092] In one embodiment, the area division unit 120 includes:

[0093] The first acquisition module is used to acquire wafer MAP data; the first setting module is used to divide the wafer graphic area into an inner circle and an outer circle according to the wafer MAP data, wherein the inner circle and the outer circle are chips of the same BIN type but with different internal performances. The second setting module is used to set the number of divided areas based on the center line of the inner circle as the division reference; the second division module is used to divide the inner circle according to the set number of areas to form multiple inner circle fan-shaped division areas.

[0094] In one embodiment, the area division unit 130 includes:

[0095] The second acquisition module is used to obtain the BIN chip information that needs to be captured; the shielding module is used to shield the BIN chips that cannot be captured in the divided area; the first capture module is used to capture the selected BIN chips from the divided area according to the set chip capture method.

[0096] In one embodiment, the shielding module comprises:

[0097] The first acquisition submodule is used to acquire a specified type of MASK; the MASK sending module is used to send the MASK to the divided area to form an image mask for the BIN chips that cannot be captured.

[0098] In one embodiment, the crawling module includes:

[0099] The second acquisition submodule is used to acquire the MAP information of the BIN chips to be captured in the divided area; the second capture module is used to capture row by row from left to right or from right to left according to the MAP information of the BIN chips to be captured.

[0100] It should be noted that technicians in the relevant field can clearly understand that the specific implementation process of the above-mentioned wafer chip partitioning grasping device 100 and each unit can refer to the corresponding description in the aforementioned method embodiment, and for the convenience and brevity of description, it will not be repeated here.

[0101] The above-mentioned wafer chip partition grabbing device can be implemented in the form of a computer program, and the computer program can be used in Figure 4 Runs on the computer device shown.

[0102] See also Figure 4 , Figure 4 700 is a schematic block diagram of a computer device provided in an embodiment of the present application. The computer device 700 may be a server, wherein the server may be an independent server or a server cluster composed of multiple servers.

[0103] like Figure 4As shown, the computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the above-mentioned steps of the wafer chip partition grabbing method are implemented.

[0104] The computer device 700 may be a terminal or a server. The computer device 700 includes a processor 720 , a memory, and a network interface 750 connected via a system bus 710 , wherein the memory may include a non-volatile storage medium 730 and an internal memory 740 .

[0105] The non-volatile storage medium 730 may store an operating system 731 and a computer program 732. When the computer program 732 is executed, the processor 720 may execute a wafer chip partition grabbing method.

[0106] The processor 720 is used to provide computing and control capabilities and support the operation of the entire computer device 700.

[0107] The internal memory 740 provides an environment for the operation of the computer program 732 in the non-volatile storage medium 730. When the computer program 732 is executed by the processor 720, the processor 720 can execute the wafer chip partition capture method.

[0108] The network interface 750 is used for network communication, such as sending assigned tasks, etc. Those skilled in the art will appreciate that Figure 4 The structure shown in the figure is only a block diagram of a part of the structure related to the present application scheme, and does not constitute a limitation on the computer device 700 to which the present application scheme is applied. The specific computer device 700 may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components. The processor 720 is used to run the program code stored in the memory to implement the steps of the wafer chip partition grabbing method.

[0109] Those skilled in the art will understand that Figure 4 The embodiments of the computer device shown in the figure do not constitute a limitation on the specific composition of the computer device. In other embodiments, the computer device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently. For example, in some embodiments, the computer device may only include a memory and a processor. In such embodiments, the structure and function of the memory and the processor are the same as those of the embodiment of the present invention. Figure 4 The embodiments shown are consistent and will not be described again here.

[0110] It should be understood that in the embodiment of the present application, the processor 720 may be a central processing unit (CPU), and the processor 720 may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0111] In another embodiment of the present invention, a computer-readable storage medium is provided. The computer-readable storage medium may be a non-volatile computer-readable storage medium. The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the wafer chip partition grabbing method disclosed in the embodiment of the present invention is implemented.

[0112] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the above-described equipment, devices and units can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. Those of ordinary skill in the art can appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, computer software or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to the function. Whether these functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0113] In the several embodiments provided by the present invention, it should be understood that the disclosed equipment, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. Units with the same function may also be combined into one unit. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices or units, or may be electrical, mechanical or other forms of connection.

[0114] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiments of the present invention.

[0115] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0116] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), disk or optical disk and other media that can store program codes.

[0117] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A wafer chip partition grabbing method, characterized in that: include: Obtain wafer pattern data; Dividing the wafer pattern area according to the wafer pattern data to form different divided areas; Chip grabbing methods are set for different divided areas, and chips are grabbed according to the set chip grabbing methods.

2. The wafer chip partition grabbing method according to claim 1, characterized in that: The step of dividing the wafer pattern area according to the wafer pattern data to form different divided areas includes: Get wafer MAP data; According to the wafer MAP data, the wafer graphic area is divided into an inner circle and an outer circle, where the inner circle and the outer circle are chips of the same BIN category but with different internal performance.

3. The wafer chip partition grabbing method according to claim 1, characterized in that: The step of dividing the wafer pattern area according to the wafer pattern data to form different divided areas includes: The number of divided areas is set based on the center line of the wafer pattern area. The wafer pattern area is divided according to a set number of areas to form a plurality of sector-shaped divided areas.

4. The wafer chip partition grabbing method according to claim 1, characterized in that: The step of dividing the wafer pattern area according to the wafer pattern data to form different divided areas includes: Get wafer MAP data; According to the wafer MAP data, the wafer graphic area is divided into an inner circle and an outer circle, where the inner circle and the outer circle are chips of the same BIN category but with different internal performance. Take the center line of the inner circle as the division basis and set the number of divided areas; The inner circle is divided according to the set number of regions to form multiple inner circle sector-shaped division regions.

5. The wafer chip partition grabbing method according to claim 1, characterized in that: The chip grabbing method is set for different divided areas, and the chip is grabbed according to the set chip grabbing method, including: Get the BIN and other chip information that needs to be captured; Shield the BIN chips that cannot be grabbed in the divided area; According to the set chip grabbing method, grab the selected BIN other chips from the divided area.

6. The wafer chip partition grabbing method according to claim 5, characterized in that: The BIN chips that cannot be captured in the shielded area include: Get the specified type of MASK; Send MASK to the divided area to form an image mask for the BIN chips that cannot be captured.

7. The wafer chip partition grabbing method according to claim 5, characterized in that: The method of grabbing the selected BIN chip from the divided area according to the set chip grabbing method includes: Get the MAP information of the BIN chips to be captured in the divided area; According to the MAP information of the BIN chip to be captured, capture it row by row from left to right or from right to left.

8. Wafer chip partition grabbing device, characterized in that: include: An acquisition unit, used for acquiring wafer pattern data; A region division unit, used for dividing the wafer pattern region according to the wafer pattern data to form different divided regions; The grabbing unit is used to set chip grabbing methods for different divided areas and to grab chips according to the set chip grabbing methods.

9. A computer device, characterized in that: The method comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the wafer chip partition grabbing method as claimed in any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and the computer program includes program instructions. When the program instructions are executed by a processor, the processor executes the wafer chip partition grabbing method according to any one of claims 1 to 7.

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