Interconnection structure and manufacturing method thereof
By forming a second opening with a larger depth on the silicon wafer and removing the damaged layer using a high etching selection ratio pickling process, the problem of difficulty in removing the damaged layer caused by the larger size of the silicon wafer or insufficient cleaning uniformity is solved, and the device is improved TDDB performance.
Patent Information
- Application Number
- CN202411293972.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-14
- Publication Date
- 2024-12-13
AI Technical Summary
When the silicon wafer size becomes larger or the cleaning uniformity is insufficient, short-term pickling cannot effectively remove the damaged layer, affecting the TDDB characterization of the device.
By forming a second opening with a depth greater than the first opening in the second dielectric layer, extending to the dielectric barrier layer, and using a high etching selection ratio pickling solution in the pickling process, the damaged layer and the remaining dielectric barrier layer are removed, Extend cleaning time to ensure complete removal of the damaged layer.
Effectively remove the damaged layer, improve the TDDB performance of the metal interconnect layer, avoid the problems of pickling uniformity variation and insufficient large-size wafer process window, and avoid the oxidation and damage of the first dielectric layer during the etching process.
Smart Images
Figure CN119133097A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to an interconnection structure and a manufacturing method thereof. Background Art
[0002] MHM (metal-hard-mask) AIO (All-In-One) etching is one of the important processes for semiconductor back-end wire metallization. Etching byproducts will be produced during the etching process, and a damaged layer will be produced on the surface after the etching is terminated. These defects will affect the performance of the device TDDB. Specifically, in order to reduce RC delay, the back-end dielectric mostly uses porous ultra-low dielectric constant (ULK) materials. However, ultra-low dielectric constant materials have low mechanical strength and are porous and easy to absorb water. When AIO etching forms through holes and grooves, F-containing plasma will damage the ultra-low dielectric constant material, thereby producing a damaged layer on the surface of the through holes and grooves. In this case, even if the EKC solution is used for wet cleaning before copper filling, the damaged layer cannot be removed, resulting in poor TDDB of the interconnect metal layer. In the prior art, the TDDB of the metal interconnect layer is improved by removing the damaged layer with an acidic solution before filling the through holes and grooves with metal copper. However, insufficient pre-cleaning time will result in inadequate removal of the damaged layer, while too long a pre-cleaning time will result in undercutting at the bottom of the via, which will affect the reliability of EM (electron migration) and SM (stress migration). Moreover, when the size of the silicon wafer becomes larger or the cleaning uniformity is insufficient, a short pickling time may still result in the inability to remove the damaged layer, affecting the TDDB characterization. Summary of the invention
[0003] The object of the present invention is to provide an interconnect structure and a manufacturing method thereof, so as to solve the problem that when the size of silicon wafer becomes larger or the cleaning uniformity is insufficient, the damaged layer cannot be removed due to the short pickling time, thus affecting the TDDB characterization of the device.
[0004] In order to solve the above technical problems, the present invention provides a method for manufacturing an interconnect structure, comprising:
[0005] Providing a substrate, on which a first dielectric layer and a second dielectric layer and a dielectric barrier layer located between the first dielectric layer and the second dielectric layer are formed, and a first interconnection layer is formed in the first dielectric layer;
[0006] Performing an etching process to form a first opening and a second opening in the second dielectric layer, wherein a damaged layer is formed in the first opening and the second opening, the depth of the second opening is greater than the depth of the first opening, the second opening penetrates the second dielectric layer and extends into the dielectric barrier layer, and a predetermined thickness of the dielectric barrier layer remains at the second opening;
[0007] An acid pickling process is performed to remove the damaged layers in the first opening and the second opening and the dielectric barrier layer of a predetermined thickness remaining in the second opening, wherein the second opening extends to the surface of the first dielectric layer and exposes the first interconnection layer in the first dielectric layer.
[0008] Optionally, after performing the etching process, the remaining predetermined thickness of the dielectric barrier layer is 10 angstroms to 20 angstroms.
[0009] Optionally, an etching rate of the dielectric barrier layer in the pickling process is greater than 20 times an etching rate of the second dielectric layer.
[0010] Optionally, the pickling process has a process time of greater than 40 seconds.
[0011] Optionally, the material of the first dielectric layer and the material of the second dielectric layer are both porous ultra-low dielectric constant materials.
[0012] Optionally, the dielectric barrier layer is made of carbon-doped silicon nitride.
[0013] Optionally, the etching process includes a first etching process and a second etching process:
[0014] Etching the second dielectric layer using the first etching process to form a first opening and a second opening in the second dielectric layer, wherein the depth of the second opening is greater than the depth of the first opening, and the second opening penetrates the second dielectric layer to expose the surface of the dielectric barrier layer;
[0015] The second etching process is used to etch a portion of the thickness of the dielectric barrier layer, the second opening extends into the dielectric barrier layer, and a portion of the thickness of the dielectric barrier layer is retained at the second opening.
[0016] Optionally, the first etching process is an AIO etching process.
[0017] Optionally, the second etching process is a dry etching process.
[0018] Based on the same inventive concept, the present invention further provides an interconnection structure, which is manufactured using any of the above-mentioned methods for manufacturing the interconnection structure.
[0019] In an interconnect structure and a manufacturing method thereof provided by the present invention, an etching process is first performed to form a first opening and a second opening in a second dielectric layer, a damaged layer is formed in the first opening and the second opening, the depth of the second opening is greater than the depth of the first opening, the second opening penetrates the second dielectric layer and extends into the dielectric barrier layer, and a predetermined thickness of the dielectric barrier layer remains at the second opening; then an acid pickling process is performed to remove the damaged layer in the first opening and the second opening and the predetermined thickness of the dielectric barrier layer remaining at the second opening, the second opening extends to the surface of the first dielectric layer and exposes the first interconnect layer in the first dielectric layer. When etching the dielectric barrier layer, a predetermined thickness of the dielectric barrier layer is reserved, and finally the dielectric barrier layer is opened by a high etching selectivity acid pickling process, the time for cleaning the damaged layer can be greater than 40 seconds, and the problem of uniformity variation of the acid pickling process or insufficient process window for large-size wafers is avoided. And because the dielectric barrier layer is opened by the acid pickling process, oxidation and damage of the first interconnect layer in the first dielectric layer caused by the etching process is also avoided. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.
[0021] Figure 1 It is a flow chart of a method for manufacturing an interconnection structure according to an embodiment of the present invention.
[0022] Figure 2 It is a schematic structural diagram of the interconnect structure after the first etching process is performed according to an embodiment of the present invention.
[0023] Figure 3 It is a schematic structural diagram of the interconnect structure after the second etching process is performed according to an embodiment of the present invention.
[0024] Figure 4 It is a schematic structural diagram of the interconnect structure after the pickling process is performed according to an embodiment of the present invention.
[0025] Figure 5 It is a structural schematic diagram of an interconnection structure after forming a second interconnection layer and a metal plug in a second dielectric layer according to an embodiment of the present invention.
[0026] In the attached figure:
[0027] 10 - substrate; 11 - first dielectric layer; 11a - first interconnection layer; 12 - dielectric barrier layer; 13 - second dielectric layer; 13a - first opening; 13b - second opening; 13c - damaged layer; 13d - second interconnection layer; 13e - metal plug. DETAILED DESCRIPTION
[0028] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.
[0029] As used in the present invention, the singular forms "one", "an" and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second" and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second" and "third" can explicitly or implicitly include one or at least two of the features. In addition, as used in the present invention, an element is arranged on another element, which usually only indicates that there is a connection, coupling, matching or transmission relationship between the two elements, and the connection, coupling, matching or transmission between the two elements can be direct or indirect through an intermediate element, and cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, an element can be in any orientation such as inside, outside, above, below or on one side of another element, unless the content clearly indicates otherwise. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0030] Figure 1 FIG. 1 is a flow chart of a method for manufacturing an interconnect structure according to an embodiment of the present invention. Figure 1 As shown, this embodiment provides a method for manufacturing an interconnect structure, comprising:
[0031] Step S10, providing a substrate, on which a first dielectric layer and a second dielectric layer and a dielectric barrier layer located between the first dielectric layer and the second dielectric layer are formed, and a first interconnect layer is formed in the first dielectric layer;
[0032] Step S20, performing an etching process to form a first opening and a second opening in the second dielectric layer, wherein a damaged layer is formed in the first opening and the second opening, the depth of the second opening is greater than the depth of the first opening, the second opening penetrates the second dielectric layer and extends into the dielectric barrier layer, and a predetermined thickness of the dielectric barrier layer remains at the second opening;
[0033] Step S30, performing an acid pickling process to remove the damaged layers in the first opening and the second opening and the dielectric barrier layer of a predetermined thickness remaining in the second opening, wherein the second opening extends to the surface of the first dielectric layer and exposes the first interconnect layer in the first dielectric layer.
[0034] Figure 2 It is a schematic structural diagram of the interconnect structure after the first etching process is performed according to an embodiment of the present invention. Figure 3 It is a schematic structural diagram of the interconnect structure after the second etching process is performed according to an embodiment of the present invention. Figure 4 It is a schematic structural diagram of the interconnect structure after the pickling process is performed according to an embodiment of the present invention. Figure 5 1 is a schematic diagram of the structure of the interconnection structure after forming the second interconnection layer and the metal plug in the second dielectric layer according to an embodiment of the present invention. Figures 2 to 5 The specific embodiments of the present invention are described in detail.
[0035] like Figure 2 As shown, a substrate 10 is provided. In some embodiments, the substrate 10 may be a semiconductor substrate made of any semiconductor material suitable for a semiconductor device (such as Si, SiC, SiGe, etc.). In other embodiments, the substrate 10 may also be various composite substrates such as silicon on insulator (SOI) and silicon germanium on insulator. Those skilled in the art will understand that the substrate is not subject to any restrictions, but may be selected according to practical applications. Various device (not limited to semiconductor devices) components (not shown in the figure) may be formed in the substrate 10. The substrate 10 may also have other layers or components formed thereon, such as: a gate structure, a contact hole, a dielectric layer, a metal connection, a through hole, and the like.
[0036] Please continue to refer to Figure 2The substrate 10 is provided with a first dielectric layer 11 and a second dielectric layer 13 and a dielectric barrier layer 12 located between the first dielectric layer 11 and the second dielectric layer 13. The dielectric barrier layer 12 is located on the first dielectric layer 11 and covers the first dielectric layer 11, and the second dielectric layer 13 is located on the dielectric barrier layer 12 and covers the dielectric barrier layer. The material of the first dielectric layer 11 and the material of the second dielectric layer 13 are both porous ultra-low dielectric constant materials (Ultra Low-k, ULK), which is a special dielectric material used in integrated circuit manufacturing to reduce signal delay and improve chip performance. The main characteristics of this material are that its dielectric constant (k value) is less than 2.5, and it has high porosity and low hardness. The material of the first dielectric layer 11 and the second dielectric layer 13 is, for example, silicon oxide or SiCOH, and the first dielectric layer 11 and the second dielectric layer 13 are formed by chemical vapor deposition process or physical vapor deposition process. The material of the dielectric barrier layer 12 is carbon-doped silicon nitride. The dielectric barrier layer 12 is formed by an atomic layer deposition process or a chemical vapor deposition process. The dielectric barrier layer 12 is used to stop etching, that is, when carbon atoms are detected in the etching process, the etching process stops. A first interconnection layer 11a is formed in the first dielectric layer 11. The material of the first interconnection layer 11a is, for example, copper metal, and is formed by a physical vapor deposition process.
[0037] like Figure 2 and Figure 3 , an etching process is performed to form a first opening 13a and a second opening 13b in the second dielectric layer 13. In some embodiments, the first opening 13a is referred to as a groove, which is used to form a second interconnection layer in the second dielectric layer 13. The second opening 13b is referred to as a through hole, and a metal plug is formed in the through hole. The metal plug is used to connect the upper and lower interconnection layers, that is, to connect the first interconnection layer in the first dielectric layer 11 and the second interconnection layer in the second dielectric layer 13. A damaged layer 13c is formed in the first opening 13a and the second opening 13b. The depth of the second opening 13b is greater than the depth of the first opening 13a. The second opening 13b penetrates the second dielectric layer 13 and extends into the dielectric barrier layer 12, and a predetermined thickness d of the dielectric barrier layer 12 remains at the second opening 13b, as shown in FIG. Figure 3 After the etching process is performed, the remaining predetermined thickness d of the dielectric barrier layer 12 is 10 angstroms to 20 angstroms.
[0038] The etching process includes a first etching process and a second etching process.
[0039] like Figure 2As shown, the first etching process is used to etch the second dielectric layer 13, and a first opening 13a and a second opening 13b are formed in the second dielectric layer 13. The depth of the second opening 13b is greater than the depth of the first opening 13a. The first opening 13a is in the second dielectric layer 13, and the second opening 13b penetrates the second dielectric layer 13 to expose the surface of the dielectric barrier layer 12. The first etching process is dry etching. Specifically, the first etching process is an AIO (All-In-One) etching process. The AIO etching process integrates the three steps of through-hole etching, photoresist removal, and groove etching into one, and is completed in the same process. Compared with the process quality of the traditional through-hole first and then the groove, it also has great advantages in small plane control, photoresist selection ratio, through-hole edge roughness, etc. In the first etching process, when the sensor detects the presence of carbon ions and nitrogen ions, the etching stops, that is, the etching stops on the surface of the dielectric barrier layer.
[0040] like Figure 3 As shown, the second etching process is used to etch a portion of the thickness of the dielectric barrier layer 12, the second opening 13b extends into the dielectric barrier layer 12, and a portion of the thickness of the dielectric barrier layer 12 is retained at the second opening 13b. The second etching process is also a dry etching process. The first etching process and the second etching process are in the same etching chamber. The second etching process controls the etching thickness of the dielectric barrier layer 12 according to the etching time to retain the dielectric barrier layer 12 of a predetermined thickness d.
[0041] like Figure 4 As shown, an acid pickling process is performed to remove the damaged layer 13c in the first opening 13a and the second opening 13b and to remove the dielectric barrier layer 12 with a predetermined thickness d remaining at the second opening 13b, and the second opening 13b extends to the surface of the first dielectric layer 11 and exposes the first interconnect layer 11a in the first dielectric layer 11. The acid pickling process is an acid pickling process with a high etching selectivity ratio, specifically, the etching rate of the dielectric barrier layer 12 in the acid pickling process is greater than 20 times the etching rate of the second dielectric layer 12, that is, the ratio of the etching rate of the dielectric barrier layer 12 in the acid pickling process to the etching rate of the second dielectric layer 12 is greater than 20, or the etching selectivity ratio of the dielectric barrier layer 12 in the acid pickling process is greater than 20. In the pickling process with high etching selectivity, the pickling solution is, for example, phosphoric acid, which has a very low etching rate for ULK (Si-OC-chemical structure), but a high etching rate for Si-CN, and the etching rate can be adjusted by temperature. The specific temperature is adjusted by those skilled in the art according to time requirements, and this embodiment does not limit this. The process time of the pickling process is greater than 40 seconds.
[0042] The material of the second dielectric layer 13 is an ultra-low dielectric constant material, which has low mechanical strength and is porous and easy to absorb water. When the first opening 13a and the second opening 13b are formed in the second dielectric layer 13 by the AIO (All-In-One) etching process, the plasma containing F will damage the ultra-low dielectric constant material, thereby generating a damaged layer 13c on the surface of the first opening 13a and the second opening 13b. In this case, even if the EKC solution is used for wet cleaning before copper filling, the damaged layer 13c cannot be removed, resulting in poor TDDB (Time Dependent Dielectric Breakdown) of the interconnected metal layer. In this embodiment, the damaged layer 13c is removed by using an acidic solution before filling the first opening 13a and the second opening 13b with metal copper, thereby effectively improving the TDDB of the metal interconnection layer. In this embodiment, during the dielectric barrier etching (AIO SiCN etch) of the all-in-one etching process, a dielectric barrier film thickness of 10 to 20 Å is reserved, and finally the dielectric barrier is opened by pickling with a high etching selectivity ratio, and the cleaning time of the damaged layer 13c is greater than 40 seconds, while avoiding the uniformity variation of the pickling process or the problem of insufficient process window for large-size wafers, that is, avoiding the damage layer from being completely removed due to short-time pickling. In addition, since the dielectric barrier is opened by pickling, the oxidation and damage of the surface of the first interconnection layer 11a in the first dielectric layer caused by the etching process are also avoided.
[0043] like Figure 5As shown, after forming the second opening 13b penetrating the second dielectric layer 13 and the dielectric barrier layer 12, metal copper is filled in the first opening 13a and the second opening 13b to form a second interconnection layer 13d in the second dielectric layer in the first opening 13a, and a metal plug 13e connecting the upper and lower interconnection layers is formed in the second opening 13b. The second interconnection layer 13d and the metal plug 13e in the second dielectric layer can be formed by an electrochemical plating process or a physical vapor deposition process. Before forming the second interconnection layer 13d and the metal plug 13e in the second dielectric layer, a copper barrier layer and a copper seed layer are formed at the bottom and sidewalls of the first opening 13a and the second opening 13b. The copper barrier layer and the copper seed layer are formed by a chemical vapor deposition process, and the copper barrier layer includes a composite layer of a tantalum nitride layer and a tantalum layer. After forming metal copper in the first opening 13a and the second opening 13b, chemical mechanical polishing is performed on the metal copper filled in the first opening 13a and the second opening 13b to form a flat surface to form a second interconnection layer 13d and a metal plug 13e in the second dielectric layer. A dielectric barrier layer is formed on the surface of the second interconnection layer 13d and the metal plug 13e in the second dielectric layer, and the dielectric barrier layer is SiCN. The dielectric barrier layer is formed to prevent copper diffusion and to serve as an etching stop in the through-hole etching process of the upper layer.
[0044] like Figure 5 As shown, this embodiment also provides an interconnection structure, which is manufactured by any of the above-mentioned methods for manufacturing an interconnection structure, and includes a substrate 10, a first dielectric layer 11 and a second dielectric layer 13 formed from bottom to top on the substrate 10, and a dielectric barrier layer 12 located between the first dielectric layer 11 and the second dielectric layer 13. A first interconnection layer 11a is formed in the first dielectric layer 11, and a second interconnection layer 13d and a metal plug 13e are formed in the second dielectric layer. The metal plug 13e is used to connect the first interconnection layer 11a and the second interconnection layer 13d.
[0045] In summary, in an interconnect structure and a manufacturing method thereof provided by an embodiment of the present invention, an etching process is first performed to form a first opening and a second opening in the second dielectric layer, a damaged layer is formed in the first opening and the second opening, the depth of the second opening is greater than the depth of the first opening, the second opening penetrates the second dielectric layer and extends into the dielectric barrier layer, and a predetermined thickness of the dielectric barrier layer remains at the second opening; then an acid pickling process is performed to remove the damaged layer in the first opening and the second opening and the predetermined thickness of the dielectric barrier layer remaining at the second opening, the second opening extends to the surface of the first dielectric layer and exposes the first interconnect layer in the first dielectric layer. When etching the dielectric barrier layer, a predetermined thickness of the dielectric barrier layer is reserved, and finally the dielectric barrier layer is opened by a high etching selectivity acid pickling process, the time for cleaning the damaged layer can be greater than 40s, and the problem of variation in cleaning uniformity or insufficient process window for large-size wafers is avoided. And because the dielectric barrier layer is opened by the acid pickling process, oxidation and damage of the first interconnect layer in the first dielectric layer caused by the etching process is also avoided.
[0046] In addition, it should be recognized that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.
Claims
1. A method for manufacturing an interconnect structure, characterized in that: include: Providing a substrate, on which a first dielectric layer and a second dielectric layer and a dielectric barrier layer located between the first dielectric layer and the second dielectric layer are formed, and a first interconnection layer is formed in the first dielectric layer; Performing an etching process to form a first opening and a second opening in the second dielectric layer, wherein a damaged layer is formed in the first opening and the second opening, the depth of the second opening is greater than the depth of the first opening, the second opening penetrates the second dielectric layer and extends into the dielectric barrier layer, and a predetermined thickness of the dielectric barrier layer remains at the second opening; An acid pickling process is performed to remove the damaged layers in the first opening and the second opening and the dielectric barrier layer of a predetermined thickness remaining in the second opening, wherein the second opening extends to the surface of the first dielectric layer and exposes the first interconnection layer in the first dielectric layer.
2. The method for manufacturing an interconnection structure according to claim 1, characterized in that: After performing the etching process, the remaining predetermined thickness of the dielectric barrier layer is 10 angstroms to 20 angstroms.
3. The method for manufacturing an interconnection structure according to claim 1, characterized in that: The etching rate of the dielectric barrier layer in the pickling process is greater than 20 times the etching rate of the second dielectric layer.
4. The method for manufacturing an interconnection structure according to claim 1, characterized in that: The pickling process has a process time of more than 40 seconds.
5. The method for manufacturing an interconnect structure according to claim 1, characterized in that: The material of the first dielectric layer and the material of the second dielectric layer are both porous ultra-low dielectric constant materials.
6. The method for manufacturing an interconnect structure according to claim 1, characterized in that: The material of the dielectric barrier layer is carbon-doped silicon nitride.
7. The method for manufacturing an interconnect structure according to claim 1, characterized in that: The etching process includes a first etching process and a second etching process: Etching the second dielectric layer using the first etching process to form a first opening and a second opening in the second dielectric layer, wherein the depth of the second opening is greater than the depth of the first opening, and the second opening penetrates the second dielectric layer to expose the surface of the dielectric barrier layer; The second etching process is used to etch a portion of the thickness of the dielectric barrier layer, the second opening extends into the dielectric barrier layer, and a portion of the thickness of the dielectric barrier layer is retained at the second opening.
8. The method for manufacturing an interconnection structure according to claim 7, characterized in that: The first etching process is an AIO etching process.
9. The method for manufacturing an interconnection structure according to claim 7, characterized in that: The second etching process is a dry etching process.
10. An interconnect structure, characterized in that: The interconnect structure is manufactured by the manufacturing method of any one of claims 1 to 9.