Semiconductor device and manufacturing method

Abstract

The invention relates to a semiconductor device and a manufacturing method. Semiconductor devices and methods of manufacture are presented. In an embodiment, a method of manufacturing a semiconductor device includes forming a fin from a plurality of semiconductor materials; depositing a dummy gate over the fin; depositing a plurality of spacers adjacent to the dummy gate; removing the dummy gate to form an opening adjacent to the plurality of spacers; widening an opening adjacent to a top surface of the plurality of spacers; after widening, removing one of the plurality of semiconductor materials to form a nanowire; and depositing a gate electrode around the nanowire.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and manufacturing methods. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers of materials on a semiconductor substrate and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that should be addressed. Summary of the invention

[0004] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: forming fins from a plurality of semiconductor materials on a substrate; depositing a dummy gate on the fin; depositing a plurality of spacers adjacent to the dummy gate; removing the dummy gate to form an opening adjacent to the plurality of spacers; after removing the dummy gate, widening the opening adjacent to a top surface of the plurality of spacers, wherein widening the opening comprises: oxidizing a first portion of a side wall of the plurality of spacers; and removing the first portion; after the widening, removing one of the plurality of semiconductor materials to form a nanowire; and depositing a gate electrode around the nanowire.

[0005] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: removing a dummy gate electrode from between a first spacer and a second spacer above a semiconductor fin, the semiconductor fin comprising a first semiconductor material and a second semiconductor material different from the first semiconductor material; oxidizing a portion of a sidewall of the first spacer using a plasma precursor; removing the portion of the sidewall to form a first opening, the first opening having a first width adjacent to a top of the first spacer and a second width less than the first width; removing one of the first semiconductor material or the second semiconductor material to form a nanowire; and depositing a gate electrode within the first opening.

[0006] According to another embodiment of the present disclosure, a semiconductor device is provided, comprising: a plurality of nanowires; a gate stack overlying the plurality of nanowires; and a first spacer located on a sidewall of the gate stack, wherein the sidewall extends away from a top surface of the first spacer at a first angle between approximately 84° and approximately 88°, and wherein the first spacer has an oxygen concentration at a top of the first spacer that is higher than a bottom of the first spacer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for the sake of clarity of discussion, the size of various features may be arbitrarily increased or reduced.

[0008] Figure 1 An example of a nanostructured field effect transistor (nano-FET) according to some embodiments is shown in a three-dimensional view.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 11C , Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.13A , Fig. 13B , Fig. 13C , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig. 16C , Fig.16D , Fig.17A , Fig. 17B , Fig. 17C , Fig.17D , Fig.18A , Fig.18B , Fig.19A , Fig.19B , Fig.19C , Fig.19D , Fig.19E , Fig. 20A , Fig. 20B , Fig. 20C , Fig.21A , Fig. 21B , Fig. 21C , Fig.22A , Fig. 22B , Fig. 22C is a cross-sectional view of an intermediate stage in the fabrication of a nanostructure FET, according to some embodiments.

[0010] Fig.23A , Fig. 23B and Fig.23C is a cross-sectional view of a nanostructure FET according to some embodiments. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0012] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0013] Embodiments are described below in the specific context of dies including nanostructure FETs. However, various embodiments may be applied to dies including other types of transistors (eg, fin field effect transistors (FinFETs), planar transistors, etc.) instead of or in combination with nanostructure FETs.

[0014] Figure 1An example of a nanostructure FET (e.g., a nanowire FET, a nanosheet FET (Nano-SFET), etc.) according to some embodiments is shown in a three-dimensional view. The nanostructure FET includes a nanostructure 55 (e.g., a nanosheet, a nanowire, etc.) located on a fin 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 serves as a channel region of the nanostructure FET. The nanostructure 55 may include a p-type nanostructure, an n-type nanostructure, or a combination thereof. An isolation region 68 is disposed between adjacent fins 66, which may protrude above the isolation region 68 and protrude from between adjacent isolation regions 68. Although the isolation region 68 is described / illustrated as being separated from the substrate 50, as used herein, the term "substrate" may refer to a separate semiconductor substrate, or a combination of a semiconductor substrate and an isolation region. In addition, although the bottom portion of the fin 66 is shown as a single continuous material with the substrate 50, the bottom portion of the fin 66 and / or the substrate 50 may include a single material or multiple materials. In this context, the fin 66 refers to a portion extending between adjacent isolation regions 68.

[0015] The gate dielectric layer 100 is over the top surface of the fin 66 and along the top surface, sidewalls, and bottom surface of the nanostructure 55. The gate electrode 102 is over the gate dielectric layer 100. Epitaxial source / drain regions 92 are disposed on the fin 66 on opposite sides of the gate dielectric layer 100 and the gate electrode 102. The source / drain region(s) 92 may be referred to individually or collectively as a source or a drain, depending on the context.

[0016] Figure 1 Reference cross sections used in subsequent figures are further illustrated. Cross section AA' is along the longitudinal axis of the gate electrode 102 and in a direction perpendicular to the direction of current flow, for example, between the epitaxial source / drain regions 92 of the nanostructured FET. Cross section BB' is perpendicular to cross section AA' and parallel to the longitudinal axis of the fin 66 of the nanostructured FET and in the direction of current flow, for example, between the epitaxial source / drain regions 92 of the nanostructured FET. Cross section CC' is parallel to cross section AA' and extends through the epitaxial source / drain regions of the nanostructured FET. For clarity, subsequent figures refer to these reference cross sections.

[0017] Some embodiments discussed herein are discussed in the context of nanostructure FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. In addition, some embodiments contemplate aspects used in planar devices (e.g., planar FETs) or in fin field effect transistors (FinFETs).

[0018] Figures 2 to 22Cis a cross-sectional view of an intermediate stage in the fabrication of a nanostructure FET, according to some embodiments. Figures 2 to 6A , Fig.13A , Fig.14A , Fig.15A , Fig.18A , Fig.19A , Fig. 20A , Fig.21A , Fig. 21B , Fig.22A and Fig.23A Shows Figure 1 Reference section AA' is shown. Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 11C , Fig. 12B , Fig.12D , Fig. 13B , Fig. 14B , Fig. 15B , Fig.16A , Fig. 16B , Fig. 16C , Fig.16D , Fig.17A , Fig. 17B , Fig. 17C , Fig.17D , Fig.18B , Fig.19B , Fig.19C , Fig.19D , Fig.19E , Fig. 20B , Fig. 22B and Fig. 23B Shows Figure 1 Reference section BB' is shown. Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig. 12A , Fig. 12C , Fig. 13C , Fig. 20C , Fig. 21C , Fig. 22C and Fig.23C Shows Figure 1 Reference section CC' shown.

[0019] exist Figure 2In the embodiment of the present invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, for example, a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (for example, with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, for example, a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates may also be used, for example, a multilayer substrate or a gradient substrate. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0020] The substrate 50 has a region n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, for example, an NMOS transistor, such as an n-type nanostructure FET, and the p-type region 50P can be used to form a p-type device, for example, a PMOS transistor, such as a p-type nanostructure FET. The n-type region 50N can be physically separated from the p-type region 50P (as shown by the separator 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be set between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0021] Further in Figure 2 In the embodiment of the present invention, a multilayer stack 64 is formed on the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-C (collectively referred to as second semiconductor layers 53). For illustration purposes and as discussed in more detail below, the second semiconductor layer 53 will be removed and the first semiconductor layer 51 will be patterned to form a channel region of the nanostructure FET in the p-type region 50P. In addition, the first semiconductor layer 51 will be removed and the second semiconductor layer 53 will be patterned to form a channel region of the nanostructure FET in the n-type region 50N. However, in some embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of the nanostructure FET in the n-type region 50N, and the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of the nanostructure FET in the p-type region 50P.

[0022] In other embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of the nanostructure FET in both the n-type region 50N and the p-type region 50P. In other embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of the nanostructure FET in both the n-type region 50N and the p-type region 50P. In such embodiments, the channel regions in both the n-type region 50N and the p-type region 50P may have the same material composition (e.g., silicon, or another semiconductor material) and be formed simultaneously. Fig.23A , Fig. 23B and Fig.23C The structure resulting from such an embodiment is shown in which the channel regions in both the p-type region 50P and the n-type region 50N include, for example, silicon.

[0023] For illustrative purposes, the multilayer stack 64 is shown as including three layers of each of the first semiconductor layer 51 and the second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of the first semiconductor layer 51 and the second semiconductor layer 53. Each layer of the multilayer stack 64 may be grown epitaxially using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material suitable for a p-type nanostructure FET, such as silicon germanium, etc., and the second semiconductor layer 53 may be formed of a second semiconductor material suitable for an n-type nanostructure FET, such as silicon, silicon carbon, etc. For illustrative purposes, the multilayer stack 64 is shown as having a bottommost semiconductor layer suitable for a p-type nanostructure FET. In some embodiments, the multilayer stack 64 may be formed such that the bottommost layer is a semiconductor layer suitable for an n-type nanostructure FET.

[0024] The first semiconductor material and the second semiconductor material may be materials having high etching selectivity relative to each other. In this way, the first semiconductor layer 51 of the first semiconductor material may be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material in the n-type region 50N, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the n-type nanostructure FET. Similarly, the second semiconductor layer 53 of the second semiconductor material may be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material in the p-type region 50P, thereby allowing the first semiconductor layer 51 to be patterned to form the channel region of the p-type nanostructure FET.

[0025] Reference now Figure 3, according to some embodiments, fins 66 are formed in substrate 50, and nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 can be formed in multilayer stack 64 and substrate 50, respectively, by etching grooves in multilayer stack 64 and substrate 50. Etching can be any acceptable etching, for example, reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. Etching can be anisotropic. Forming nanostructure 55 by etching multilayer stack 64 can further define first nanostructures 52A-C (collectively referred to as first nanostructures 52) from first semiconductor layer 51, and define second nanostructures 54A-C (collectively referred to as second nanostructures 54) from second semiconductor layer 53. The first nanostructure 52 and the second nanostructure 54 can be further collectively referred to as nanostructure 55.

[0026] The fins 66 and nanostructures 55 may be patterned by any suitable method. For example, one or more photolithography processes may be used to pattern the fins 66 and nanostructures 55, including a double patterning process or a multi-patterning process. Typically, a double patterning or multi-patterning process combines a photolithography process and a self-alignment process, allowing the creation of patterns having, for example, a smaller pitch than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. A spacer is formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins 66.

[0027] For illustrative purposes, Figure 3 The fins 66 in the n-type region 50N and the p-type region 50P are shown as having substantially equal widths. In some embodiments, the width of the fins 66 in the n-type region 50N may be greater or thinner than the width of the fins 66 in the p-type region 50P. In addition, although each of the fins 66 and the nanostructures 55 are shown as having a consistent width throughout, in other embodiments, the fins 66 and / or the nanostructures 55 may have tapered sidewalls such that the width of each of the fins 66 and / or the nanostructures 55 increases continuously in a direction toward the substrate 50. In such an embodiment, each nanostructure 55 may have a different width and be trapezoidal.

[0028] exist Figure 4In the embodiment, a shallow trench isolation (STI) region 68 is formed adjacent to the fin 66. The STI region 68 can be formed by depositing an insulating material on the substrate 50, the fin 66 and the nanostructure 55 and between adjacent fins 66. The insulating material can be an oxide (e.g., silicon oxide), a nitride, etc., or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), etc., or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In an embodiment, the insulating material is formed so that an excess of insulating material covers the nanostructure 55. Although the insulating material is shown as a single layer, some embodiments may employ multiple layers. For example, in some embodiments, a liner (not shown separately) may first be formed along the surface of the substrate 50, the fin 66 and the nanostructure 55. Thereafter, a filling material such as described above may be formed over the liner.

[0029] A removal process is then applied to the insulating material to remove excess insulating material above the nanostructures 55. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. may be employed. The planarization process exposes the nanostructures 55 so that after the planarization process is completed, the top surfaces of the nanostructures 55 and the insulating material are flush.

[0030] The insulating material is then recessed to form STI regions 68. The insulating material is recessed so that the upper portions of the fins 66 in the n-type region 50N and the p-type region 50P protrude from between adjacent STI regions 68. In addition, the top surface of the STI region 68 can have a flat surface (as shown), a convex surface, a concave surface (e.g., a dished shape), or a combination thereof. The top surface of the STI region 68 can be formed to be flat, convex, and / or concave by appropriate etching. The STI region 68 can be recessed using an acceptable etching process, for example, an etching process that is selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the material of the fin 66 and the nanostructure 55). For example, oxide removal using an acid such as dilute hydrofluoric acid (dHF) can be used.

[0031] Above about Figures 2 to 4The described process is only one example of how the fin 66 and nanostructure 55 can be formed. In some embodiments, the fin 66 and / or nanostructure 55 can be formed using a mask and an epitaxial growth process. For example, a dielectric layer can be formed above the top surface of the substrate 50, and a groove can be etched through the dielectric layer to expose the substrate 50 below. The epitaxial structure can be epitaxially grown in the trench, and the dielectric layer can be recessed so that the epitaxial structure protrudes from the dielectric layer to form the fin 66 and / or nanostructure 55. The epitaxial structure may include alternating semiconductor materials described above, for example, a first semiconductor material and a second semiconductor material. In some embodiments in which the epitaxial structure is epitaxially grown, the epitaxially grown material can be doped in situ during growth, which can avoid previous and / or subsequent implantation, but in situ doping and implantation doping can be used together.

[0032] In addition, for illustrative purposes only, the first semiconductor layer 51 (and the resulting nanostructure 52) and the second semiconductor layer 53 (and the resulting nanostructure 54) are shown and discussed herein as including the same material in the p-type region 50P and the n-type region 50N. Thus, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be different materials in the p-type region 50P and the n-type region 50N, or may be formed in a different order.

[0033] Further in Figure 4 In the embodiment having different well types, a photoresist or other mask (not shown separately) may be used to implement different implantation steps for the n-type region 50N and the p-type region 50P. For example, a photoresist may be formed over the fins 66 and the STI region 68 in the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist may be formed using a spin coating technique and may be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implantation is performed in the p-type region 50P and the photoresist may be used as a mask to substantially prevent the n-type impurity from being implanted into the n-type region 50N. The n-type impurity may be phosphorus, arsenic, antimony, etc., implanted into the region at a concentration of about 10 13 Atom / cm 3 to about 10 14 Atom / cm 3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0034] After or before the implantation of the p-type region 50P, a photoresist or other mask (not shown separately) is formed over the fins 66, nanostructures 55, and STI regions 68 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using a spin coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent the p-type impurity from being implanted into the p-type region 50P. The p-type impurity can be boron, boron fluoride, indium, etc., which is implanted into the region at a concentration of about 10 13 Atom / cm 3 to about 10 14 Atom / cm 3 After implantation, the photoresist may be removed, for example, by an acceptable ashing process.

[0035] After implantation of n-type region 50N and p-type region 50P, annealing may be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fin may be in-situ doped during growth, which may avoid implantation, but in-situ doping and implantation doping may be used together.

[0036] exist Figure 5In the embodiment of the present invention, a dummy dielectric layer 70 is formed on the fin 66 and / or the nanostructure 55. The dummy dielectric layer 70 may be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and may be deposited or thermally grown according to an acceptable technique. A dummy gate layer 72 is formed on the dummy dielectric layer 70, and a mask layer 74 is formed on the dummy gate layer 72. The dummy gate layer 72 may be deposited on the dummy dielectric layer 70 and then planarized, for example, by CMP. The mask layer 74 may be deposited on the dummy gate layer 72. The dummy gate layer 72 may be a conductive material or a non-conductive material, and may be selected from the group consisting of amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 72 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials. The dummy gate layer 72 may be made of other materials with high etch selectivity relative to the etching of the isolation region. The mask layer 74 may include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the n-type region 50N and the p-type region 50P. Note that the dummy dielectric layer 70 is shown to cover only the fin 66 and the nanostructure 55 for illustration purposes only. In some embodiments, the dummy dielectric layer 70 may be deposited so that the dummy dielectric layer 70 covers the STI region 68, so that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI region 68.

[0037] FIG. 6A to FIG. 22C Various additional steps in fabricating an example device are shown. Fig. 6A and Figure 6B In the embodiment, the mask layer 74 may be patterned using acceptable photolithography and etching techniques (see Figure 5 ) to form a mask 78. The pattern of the mask 78 can then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form a dummy gate 76 and a dummy gate dielectric 71, respectively. The dummy gate 76 covers the corresponding channel region of the fin 66. The pattern of the mask 78 can be used to physically separate each dummy gate 76 from an adjacent dummy gate 76. The dummy gate 76 can also have a length direction that is substantially perpendicular to the length direction of the corresponding fin 66.

[0038] exist Fig. 7A and Figure 7B In Fig. 6A and Figure 6B A first spacer layer 80 and a second spacer layer 82 are formed over the structure shown. The first spacer layer 80 and the second spacer layer 82 will subsequently be patterned to act as spacers for forming self-aligned source / drain regions. Fig. 7A and Figure 7BIn the embodiment of the present invention, a first spacer layer 80 is formed on the top surface of the STI region 68; on the top surface and sidewalls of the fin 66, the nanostructure 55 and the mask 78; and on the sidewalls of the dummy gate 76 and the dummy gate dielectric 71. A second spacer layer 82 is deposited over the first spacer layer 80. The first spacer layer 80 may be formed of silicon oxycarbon nitride (SiO2) using a technique such as thermal oxidation. x N y C 1-x-y ), silicon oxide, silicon nitride, silicon oxynitride, etc., or deposited by CVD, ALD, etc. The second spacer layer 82 may be formed of a material having an etching rate different from that of the material of the first spacer layer 80, for example, silicon oxide, silicon nitride, silicon oxynitride, etc., and may be deposited by CVD, ALD, etc.

[0039] After forming the first spacer layer 80 and before forming the second spacer layer 82, an implant for lightly doped source / drain (LDD) regions (not shown separately) may be performed. In embodiments with different device types, similar to the above, Figure 4 As discussed in the implantation, a mask such as a photoresist may be formed over the n-type region 50N while exposing the p-type region 50P, and impurities of an appropriate type (e.g., p-type) may be implanted into the exposed fins 66 and nanostructures 55 in the p-type region 50P. The mask may then be removed. Subsequently, a mask such as a photoresist may be formed over the p-type region 50P while exposing the n-type region 50N, and impurities of an appropriate type (e.g., n-type) may be implanted into the exposed fins 66 and nanostructures 55 in the n-type region 50N. The mask may then be removed. The n-type impurity may be any of the previously discussed n-type impurities, and the p-type impurity may be any of the previously discussed p-type impurities. The lightly doped source / drain regions may have a density of approximately 1×10 15 Atom / cm 3 About 1×10 19 Atom / cm 3 Annealing can be used to repair implantation damage and activate the implanted impurities.

[0040] exist Fig. 8A and Figure 8B, the first spacer layer 80 and the second spacer layer 82 are etched to form the first spacer 81 and the second spacer 83. As will be discussed in more detail below, the first spacer 81 and the second spacer 83 are used to protect the sidewalls of the fin 66 and / or the nanostructure 55 during subsequent processing. The first spacer layer 80 and the second spacer layer 82 can be etched using a suitable etching process, for example, an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), etc. In some embodiments, the material of the second spacer layer 82 has a different etching rate than the material of the first spacer layer 80, so that the first spacer layer 80 can be used as an etch stop layer when patterning the second spacer layer 82, and so that the second spacer layer 82 can be used as a mask when patterning the first spacer layer 80. For example, the second spacer layer 82 can be etched using an anisotropic etching process, wherein the first spacer layer 80 is used as an etch stop layer, wherein the remaining portion of the second spacer layer 82 forms the second spacer 83, such as Fig. 8A Thereafter, the second spacer 83 is used as a mask when etching the exposed portion of the first spacer layer 80, thereby forming the first spacer 81, as shown in FIG. Fig. 8A shown.

[0041] like Fig. 8A As shown, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the fin 66 and / or the nanostructure 55. Figure 8B As shown, in some embodiments, the second spacer layer 82 can be removed from the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71, and the first spacer 81 is disposed on the sidewalls of the mask 78, the dummy gate 76, and the dummy dielectric layer 60. In other embodiments, a portion of the second spacer layer 82 can remain on the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71.

[0042] Figure 8A-B Also shown is a third spacer 85 formed adjacent to the first spacer 81 and the second spacer 83. In an embodiment, the third spacer 85 may include a similar material as the first spacer 81 and may be conformally deposited and patterned to cover the sidewalls of the first spacer 81 and the second spacer 83. However, any suitable materials and processes may be used.

[0043] Note that the above disclosure generally describes the process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, a different sequence of steps may be used (e.g., the first spacer 81 may be patterned before the second spacer layer 82 is deposited), additional spacers may be formed and removed, etc. In addition, different structures and steps may be used to form n-type devices and p-type devices.

[0044] exist Fig.9A and Fig. 9B In some embodiments, a first recess 86 is formed in the fin 66, the nanostructure 55, and the substrate 50. An epitaxial source / drain region will be subsequently formed in the first recess 86. The first recess 86 may extend through the first nanostructure 52 and the second nanostructure 54 and extend into the substrate 50. Fig.9A As shown, the top surface of the STI region 68 can be flush with the bottom surface of the first recess 86. In various embodiments, the fin 66 can be etched so that the bottom surface of the first recess 86 is disposed below the top surface of the STI region 68; etc. The first recess 86 can be formed by etching the fin 66, the nanostructure 55, and the substrate 50 using an anisotropic etching process such as RIE, NBE, etc. The first spacer 81, the second spacer 83, the third spacer 85, and the mask 78 mask some portions of the fin 66, the nanostructure 55, and the substrate 50 during the etching process for forming the first recess 86. Each layer in the nanostructure 55 and / or the fin 66 can be etched using a single etching process or multiple etching processes. A timed etching process can be used to stop etching the first recess 86 after the first recess 86 reaches a desired depth.

[0045] exist Fig. 10A and Fig. 10B In the embodiment, the portion of the sidewall of the layer (e.g., the first nanostructure 52) of the multilayer stack 64 formed of the first semiconductor material exposed by the first recess 86 is etched to form the sidewall recess 88 in the n-type region 50N, and the portion of the sidewall of the layer (e.g., the second nanostructure 54) of the multilayer stack 64 formed of the second semiconductor material exposed by the first recess 86 is etched to form the sidewall recess 88 in the p-type region 50P. Fig. 10BThe sidewalls of the first nanostructure 52 and the second nanostructure 54 in the sidewall recess 88 are shown as straight, but these sidewalls can be concave or convex. The sidewalls can be etched using an isotropic etching process, such as wet etching, etc. A mask (not shown) can be used to protect the p-type region 50P while etching the first nanostructure 52 using an etchant selective to the first semiconductor material, so that in the n-type region 50N, the second nanostructure 54 and the substrate 50 remain relatively unetched compared to the first nanostructure 52. Similarly, a mask (not shown) can be used to protect the n-type region 50N while etching the second nanostructure 54 using an etchant selective to the second semiconductor material, so that in the p-type region 50P, the first nanostructure 52 and the substrate 50 remain relatively unetched compared to the second nanostructure 54. In embodiments where the first nanostructure 52 includes, for example, SiGe and the second nanostructure 54 includes, for example, Si or SiC, the sidewalls of the first nanostructure 52 in the n-type region 50N may be etched using a dry etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like, and the sidewalls of the second nanostructure 54 in the p-type region 50P may be etched using a wet or dry etching process using hydrogen fluoride, another fluorine-based etchant, or the like.

[0046] exist Figures 11A-11C In the embodiment, a first internal spacer 90 is formed in the side wall recess 88. The first internal spacer 90 can be formed by Fig. 10A and Fig. 10B The structure shown is formed by depositing an internal spacer layer (not shown separately). The first internal spacer layer 90 serves as an isolation feature between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions will be formed in the first recess 86, and the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P will be replaced with the corresponding gate structure.

[0047] The inner spacer layer may be deposited by a conformal deposition process, such as CVD, ALD, etc. The inner spacer layer may include a material such as silicon nitride or silicon oxynitride, but any suitable material may be used, such as a low dielectric constant (low-k) material having a k value of less than about 3.5. The inner spacer layer may then be anisotropically etched to form the first inner spacer 90. Although the outer sidewalls of the first inner spacer 90 are shown flush with the sidewalls of the second nanostructure 54 in the n-type region 50N and flush with the sidewalls of the first nanostructure 52 in the p-type region 50P, the outer sidewalls of the first inner spacer 90 may extend beyond the sidewalls of the second nanostructure 54 and / or the first nanostructure 52, respectively, or be recessed from the second nanostructure 54 and / or the first nanostructure 52, respectively.

[0048] In addition, although the outer side wall of the first inner partition 90 is Fig. 11B Although shown as straight, the outer sidewall of the first inner spacer 90 may be concave or convex. For example, Fig. 11C An embodiment is shown in which the sidewalls of the first nanostructure 52 are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer 90 is recessed from the sidewalls of the second nanostructure 54 in the n-type region 50N. An embodiment is also shown in which the sidewalls of the second nanostructure 54 are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer 90 is recessed from the sidewalls of the first nanostructure 52 in the p-type region 50P. The inner spacer layer can be etched by an anisotropic etching process (e.g., RIE, NBE, etc.). The first inner spacer 90 can be used to prevent subsequent etching processes (e.g., etching processes used to form gate structures) from etched to subsequently formed source / drain regions (e.g., as described below with respect to Figure 12A-12C The epitaxial source / drain regions 92 discussed above may cause damage.

[0049] exist Figure 12A-12C In the embodiment, an epitaxial source / drain region 92 is formed in the first recess 86. In some embodiments, the source / drain region 92 can apply stress to the second nanostructure 54 in the n-type region 50N and the first nanostructure 52 in the p-type region 50P, thereby improving performance. Fig. 12B As shown, epitaxial source / drain regions 92 are formed in first recesses 86 so that each dummy gate 76 is disposed between a corresponding adjacent pair of epitaxial source / drain regions 92. In some embodiments, first spacers 81 are used to separate epitaxial source / drain regions 92 from dummy gates 76 by an appropriate lateral distance, and first internal spacers 90 are used to separate epitaxial source / drain regions 92 from nanostructures 55 by an appropriate lateral distance so that epitaxial source / drain regions 92 do not short circuit with a subsequently formed gate of the resulting nanostructure FET.

[0050] The epitaxial source / drain region 92 in the n-type region 50N (e.g., NMOS region) can be formed by masking the p-type region 50P (e.g., PMOS region). Then, the epitaxial source / drain region 92 is epitaxially grown in the first recess 86 of the n-type region 50N. The epitaxial source / drain region 92 may include any acceptable material suitable for an n-type nanostructure FET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 may include a material that applies tensile strain to the second nanostructure 54, such as silicon, silicon carbide, silicon carbide doped with phosphorus, silicon phosphide, etc. The epitaxial source / drain region 92 may have a surface that protrudes from the corresponding upper surface of the nanostructure 55 and may have a small facet.

[0051] The epitaxial source / drain region 92 in the p-type region 50P (e.g., a PMOS region) can be formed by masking the n-type region 50N (e.g., an NMOS region). The epitaxial source / drain region 92 is then epitaxially grown in the first recess 86 of the p-type region 50P. The epitaxial source / drain region 92 can include any acceptable material suitable for a p-type nanostructure FET. For example, if the first nanostructure 52 is silicon germanium, the epitaxial source / drain region 92 can include a material that applies compressive strain to the first nanostructure 52, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain region 92 can also have a surface that protrudes from a corresponding surface of the multilayer stack 64 and can have a small facet.

[0052] The epitaxial source / drain regions 92, the first nanostructures 52, the second nanostructures 54, and / or the substrate 50 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions, and then annealed. The impurity concentration of the source / drain regions may be about 1×10 19 Atom / cm 3 and about 1×10 21 Atom / cm 3 The n-type and / or p-type impurities used for the source / drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 may be doped in-situ during growth.

[0053] As a result of the epitaxial process used to form epitaxial source / drain regions 92 in n-type region 50N and p-type region 50P, the upper surfaces of epitaxial source / drain regions 92 have facets that extend laterally outward beyond the sidewalls of nanostructure 55. In some embodiments, these facets cause adjacent epitaxial source / drain regions 92 of the same nanostructure FET to merge, such as Fig. 12A In other embodiments, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is completed, such as Fig. 12C As shown. Fig. 12A and Fig. 12C In the illustrated embodiment, the first spacer 81 can be formed at the top surface of the STI region 68 to prevent epitaxial growth. In some other embodiments, the first spacer 81 can cover some portions of the sidewalls of the nanostructure 55 to further prevent epitaxial growth. In some other embodiments, the spacer etch used to form the first spacer 81 can be adjusted to remove the spacer material to allow the epitaxial growth area to extend to the surface of the STI region 68.

[0054] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used for the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of a different semiconductor material and may be doped to different dopant concentrations. In some embodiments, the dopant concentration of the first semiconductor material layer 92A may be less than the second semiconductor material layer 92B and greater than the third semiconductor material layer 92C. In embodiments where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited on the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited on the second semiconductor material layer 92B.

[0055] Fig.12D An embodiment is shown in which the sidewalls of the first nanostructure 52 in the n-type region 50N and the sidewalls of the second nanostructure 54 in the p-type region 50P are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer 90 is recessed from the sidewalls of the second nanostructure 54 and the first nanostructure 52, respectively. Fig.12D As shown, epitaxial source / drain regions 92 may be formed in contact with the first inner spacer 90 and may extend through sidewalls of the second nanostructures 54 in the n-type region 50N and sidewalls of the first nanostructures 52 in the p-type region 50P.

[0056] exist Figure 13A-13C In Fig. 6A , Fig. 12B and Fig. 12A A first interlayer dielectric (ILD) 96 is deposited over the structure shown. Figures 7A-12D The process will not change Fig. 6A). The first ILD 96 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain regions 92, the mask 78, and the first spacer 81. The CESL 94 may include a dielectric material having a different etch rate than the material of the overlying first ILD 96, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0057] exist Figure 14A-14B In the process, a planarization process such as CMP may be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76, and the portion of the first spacer 81 along the sidewall of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first ILD 96 are flush within process variations. Therefore, the top surface of the dummy gate layer 72 is exposed through the first ILD 96. In some embodiments, the mask 78 may remain, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 78 and the first spacer 81.

[0058] exist Fig.15A and Fig. 15B In the embodiment of the present invention, the dummy gate 76 and the mask 78 (if present) are removed in one or more etching steps to form a second recess 98. The portion of the dummy dielectric layer 60 in the second recess 98 is also removed. In some embodiments, the dummy gate 76 and the dummy dielectric layer 60 are removed by an anisotropic dry etching process. For example, the etching process may include a first etching process to remove a first portion of the dummy gate 76, and then a second etching process using a different etchant to provide better selectivity while still avoiding damage to the underlying STI region 68, so that the second etching process selectively etches the dummy gate 76 at a faster rate than the first ILD 96 or the first spacer 81. Each second recess 98 exposes and / or overlies a portion of the nanostructure 55 that is used as a channel region in a subsequently completed nanostructure FET. The portion of the nanostructure 55 that is used as a channel region is disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy dielectric layer 60 may serve as an etch stop layer when the dummy gate 76 is etched. The dummy dielectric layer 60 may then be removed after removing the dummy gate 76 .

[0059] exist Fig.16A and Fig. 16B In the embodiment, a reshaping process is performed after removing the dummy gate 76 to widen the second recess 98, wherein Fig. 16B Shows Fig.16A A close-up view of the dashed box marked 161 in FIG. In an embodiment, the reshaping process may include an oxidation step (in Fig.16A ) and the removal step ( Fig.16A Not shown, but discussed below Fig.17A ). However, any suitable number of steps may be used.

[0060] In an embodiment, the oxidation step 160 may begin by preparing a treatment precursor having an oxidation precursor and a reshaping precursor. In an embodiment, the oxidation precursor may be one or more precursors that react with the material of the first spacer 81 to form the first oxidized region 163, and may include oxygen, such as diatomic oxygen (O2), ozone, combinations thereof, etc. However, any suitable oxidation precursor may be used.

[0061] The reshaping precursor may be used as a diluent to help control the precise shape of the first oxidized region 163 by assisting in the ionization and dissociation of the oxidizing precursor (e.g., O2) (discussed further below). In an embodiment, the reshaping precursor may be an inert gas, such as helium, neon, argon, krypton, xenon, radon, combinations thereof, etc. However, any other suitable reshaping precursor may be used, including non-inert gas precursors.

[0062] In order to control the shape of the first oxidized region 163 that appears in the oxidation step 160, the amount of the oxidation precursor and the reshaping precursor is controlled to achieve the desired final widening of the first spacer 81. In an embodiment, the proportion of the oxidation precursor in the treatment precursor may be between about 20%-flow and about 60%-flow, for example, about 40%-flow. However, any suitable concentration may be used.

[0063] Once the process precursors are mixed, the process precursors may be ignited into a process plasma to generate individual atoms, ions, or radicals from the molecules within the process precursors. In an embodiment, the process precursors may be ignited into a plasma using, for example, a transformer coupled plasma generator, an inductively coupled plasma system, a remote plasma generator, etc., to prepare the process precursors for an oxidation process.

[0064] The processing plasma may be directed toward the first spacer 81 lining the second recess 98. When the processing plasma contacts the material of the first spacer 81, the oxygen atoms within the processing plasma will diffuse into and react with the material of the first spacer 81. As a result, the processing plasma will oxidize a portion of the material of the first spacer 81 and form a first oxidized region 163. In a specific embodiment, the first oxidized region 163 may be a SiO2-based material, although this may depend at least in part on the original material of the first spacer 81. x Materials such as , where x may be between about 1 and about 2. However, any suitable material may be used.

[0065] However, because the processing plasma does not extend equally throughout the second recess 98, and also because oxygen can diffuse into the first spacer 81 from multiple directions, the amount of oxygen diffused into the first spacer 81 is different at different depths of the second recess 98. Therefore, at a greater depth of the second recess 98, the amount of oxygen diffused into the material of the first spacer 81 will be less than at a shallower depth. Therefore, the first oxidized region 163 will have a smaller width at a greater depth, and have a maximum width along the top surface of the material of the first spacer 81. This results in a nearly triangular shape.

[0066] A closer look Fig. 16B , a close-up view of the dotted box 161 in FIG. 1 shows a specific embodiment in which the first oxidized region 163 is formed when the oxygen concentration of the processing plasma is about 20%. In this embodiment, the first oxidized region 163 is formed in a triangular shape so that the first oxidized region 163 has a first width W1 (along the top surface of the first spacer 81) between about 3.5 nm and about 4 nm, and has a first depth D1 between about 80 nm and about 100 nm. Therefore, the first oxidized region 163 can have a first angle θ1 between about 83° and about 85°, for example, about 84°. However, any suitable size can be used.

[0067] In addition, regarding the depth of the first oxidized region 163, the first depth D1 may be less than the overall height of the second recess 98. In some embodiments, for example, when the overall height of the second recess 98 is between about 30 nm and about 40 nm, the ratio of the first depth D1 to the overall height may be between about 0.25 and about 0.3. However, any suitable ratio may be used.

[0068] Fig. 16C Shown with Fig. 16BAnother embodiment similar to the embodiment shown, but in which the first oxidized region 163 is formed when the oxygen concentration of the processing plasma is about 40%. In this embodiment, the first oxidized region 163 is formed in a triangular shape, so that the first oxidized region 163 has a second width W2 (along the top surface of the first spacer 81) that is less than the first width W1, for example, a second width W2 between about 3nm and about 3.5nm, and can have a second depth D2 between about 80nm and about 100nm (for example, similar to the ratio of the overall height). Therefore, the first oxidized region 163 can have a second angle θ2 between about 85° and about 87°, for example, about 86°. However, any suitable size can be used.

[0069] Fig.16D Shown with Fig. 16B Another embodiment similar to the embodiment shown, but in which the first oxidized region 163 is formed when the oxygen concentration of the processing plasma is about 60%. In this embodiment, the first oxidized region 163 is formed in a triangular shape, so that the first oxidized region 163 has a third width W3 between about 2nm and about 3nm (along the top surface of the first spacer 81), and can have a third depth D3 between about 80nm and about 100nm (e.g., similar to the ratio of the overall height). Therefore, the first oxidized region 163 can have a third angle θ3 between about 87° and about 89°, for example, about 88°. However, any suitable size can be used.

[0070] It can be seen that by controlling the amount of oxygen in the processing precursor, the angle of the first oxidized region 163 can be further controlled between 84° and 88°. If the angle range is greater than 90°, the metal gate filling window will not be expanded. If the angle range is less than 84°, it will not be beneficial to the subsequent metal gate filling process.

[0071] Fig.17A A removal process for removing the first oxidized region 163 and widening the top of the second recess 98 is shown (in FIG. Fig.17A In an embodiment, the removal process 170 may be one or more wet etching processes that remove the oxidized material of the first oxidized region 163 without significantly removing the non-oxidized portion of the first spacer 81. However, any suitable removal process may be used.

[0072] In some embodiments, the removal process 170 may stop before removing all of the implanted oxygen. For example, although the removal process 170 may remove all of the first oxidized regions 163, after the removal process, a residual amount of oxygen may still remain in the first spacer 81. Therefore, the oxygen concentration adjacent to the top surface of the first spacer 81 may still be high, while the portion of the first spacer 81 adjacent to the deeper portion of the second recess 98 may have a lower oxygen concentration.

[0073] Fig. 17B The removal process 170 is shown Fig. 16B 10. In the embodiment of the present invention (e.g., a processing precursor having an oxygen percentage of 20%). Specifically, after the removal process 170, the second recess 98 has a first angle θ1 at a top surface adjacent to the second recess 98. In addition, the top of the second recess 98 may have a widened width, for example, a fourth width W4 between about 14.5 nm and about 15 nm. However, any suitable size may be used.

[0074] Fig. 17C The removal process 170 is shown. Fig. 16C 14. The embodiment of the present invention (e.g., a processing precursor having an oxygen percentage of 40%). Specifically, after the removal process 170, the second recess 98 has a second angle θ2 adjacent to the top surface of the second recess 98. In addition, the top of the second recess 98 may have a widened width, for example, a fifth width W5 between about 14 nm and about 14.5 nm. However, any suitable size may be used.

[0075] Fig.17D The removal process 170 is shown. Fig.16D 14. The embodiment of the present invention (e.g., a processing precursor having an oxygen percentage of 60%). Specifically, after the removal process 170, the second recess 98 has a third angle θ3 at a top surface adjacent to the second recess 98. In addition, the top of the second recess 98 may have a widened width, for example, a sixth width W6 between about 13 nm and about 14 nm. However, any suitable size may be used.

[0076] By controlling the oxidation amount of the first spacer 81 (or the first spacer 81 and the second spacer 83 or the third spacer 85), the shape and width of the second recess 98 can be well controlled to achieve a better filling process (described further below). With a better filling process, defects such as voids will be reduced, further improving device and yield performance.

[0077] Figure 18A-18BIt is shown that once the second recess 98 has been widened, the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P are removed, expanding the second recess 98. The first nanostructure 52 can be removed by forming a mask (not shown) over the p-type region 50P and performing an isotropic etching process such as a wet etch or the like using an etchant that is selective to the material of the first nanostructure 52, while the second nanostructure 54, the substrate 50, and the STI region 68 remain relatively unetched compared to the first nanostructure 52. In embodiments where the first nanostructure 52 includes, for example, SiGe and the second nanostructures 54A-54C include, for example, Si or SiC, the first nanostructure 52 in the n-type region 50N can be removed using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like.

[0078] The second nanostructure 54 in the p-type region 50P may be removed by forming a mask (not shown) over the n-type region 50N and performing an isotropic etching process such as a wet etch or the like using an etchant that is selective to the material of the second nanostructure 54, while the first nanostructure 52, the substrate 50, and the STI region 68 remain relatively unetched compared to the second nanostructure 54. In embodiments where the second nanostructure 54 includes, for example, SiGe and the first nanostructure 52 includes, for example, Si or SiC, the second nanostructure 54 in the p-type region 50P may be removed using hydrogen fluoride, another fluorine-based etchant, or the like.

[0079] In other embodiments, the channel regions in the n-type region 50N and the p-type region 50P can be formed simultaneously, for example, by removing the first nanostructure 52 in both the n-type region 50N and the p-type region 50P, or by removing the second nanostructure 54 in both the n-type region 50N and the p-type region 50P. In such embodiments, the channel regions of the n-type nanostructure FET and the p-type nanostructure FET can have the same material composition, for example, silicon, silicon germanium, etc. Fig.23A , Fig. 23B and Fig.23C The structure resulting from such an embodiment is shown in which the channel regions in both the p-type region 50P and the n-type region 50N are provided by the second nanostructure 54 and comprise silicon, for example.

[0080] exist Fig.19A and Fig.19B, a gate dielectric layer 100 and a gate electrode 102 are formed for replacing the gate. The gate dielectric layer 100 is conformally deposited in the second recess 98. In the n-type region 50N, the gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50, and the top surface, sidewalls, and bottom surface of the second nanostructure 54, and in the p-type region 50P, the gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50, and the top surface, sidewalls, and bottom surface of the first nanostructure 52. The gate dielectric layer 100 may also be deposited on the top surfaces of the first ILD 96, the CESL 94, the first spacer 81, and the STI region 68.

[0081] According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, etc., or a combination thereof. For example, in some embodiments, the gate dielectric may include a silicon oxide layer and a metal oxide layer located above the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 100 may have a k value greater than about 7.0 and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layer 100 may be the same or different in the n-type region 50N and the p-type region 50P. The formation method of the gate dielectric layer 100 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0082] The gate electrode 102 is deposited on the gate dielectric layer 100 and fills the rest of the second recess 98. The gate electrode 102 may include a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. Fig.19A and Fig.19B , a single-layer gate electrode 102 is shown, but the gate electrode 102 may include any number of liner layers, any number of work function adjustment layers, and filling materials. Any combination of layers constituting the gate electrode 102 may be deposited between adjacent second nanostructures 54 and between the second nanostructures 54A and the substrate 50 in the n-type region 50N, and may be deposited between adjacent first nanostructures 52 in the p-type region 50P.

[0083] The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P may occur simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material, and the formation of the gate electrode 102 may occur simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region may be formed by a different process, such that the gate dielectric layer 100 may be a different material and / or have a different number of layers, and / or the gate electrode 102 in each region may be formed by a different process, such that the gate electrode 102 may be a different material and / or have a different number of layers. When different processes are used, various masking steps may be used to mask and expose the appropriate regions.

[0084] After filling the second recess 98, a planarization process such as CMP may be performed to remove the material of the gate electrode 102 and the excess portions of the gate dielectric layer 100 that are above the top surface of the first ILD 96. The material of the gate electrode 102 and the remaining portions of the gate dielectric layer 100 thus form a replacement gate structure of the resulting nanostructure FET. The gate electrode 102 and the gate dielectric layer 100 may be collectively referred to as a "gate structure."

[0085] Figure 19C-19E Different embodiments are shown Fig.19B A close-up view of the frame 161 of FIG. First, observe Fig.19C , Fig.19C The gate electrode 102 is formed. Fig. 16B 98 ). Specifically, after forming the gate electrode 102, the top surface of the gate electrode 102 adjacent to the second recess 98 will have a first angle θ1. In addition, the gate electrode 102 may have a widened width, for example, a fourth width W4, and may have a seventh width W7 at the bottom of the gate electrode 102, such that the width ratio of the gate electrode 102 from the top to the bottom of the gate electrode 102 is between about 1 and about 1.5. If the width ratio is less than 1, the metal gate window will not be enlarged; and if the width ratio is greater than 1.5, the metal gate filling window will not benefit. However, any suitable size may be used.

[0086] Fig.19D The gate electrode 102 is formed. Fig. 16C 98. In particular, after forming the gate electrode 102, the gate electrode 102 has a second angle θ2 along the top surface of the second recess 98. In addition, the top of the gate electrode 102 may have a widened width, for example, a fifth width W5. However, any suitable size may be used.

[0087] Fig.19E The gate electrode 102 is formed. Fig.16D 98. In particular, after forming the gate electrode 102, the gate electrode 102 has a third angle θ3 at the top surface adjacent to the second recess 98. In addition, the top of the gate electrode 102 may have a widened width, for example, a sixth width W6. However, any suitable size may be used.

[0088] By utilizing the above process, the geometric limitations of metal gate gap filling can be improved as the size of integrated circuits decreases. Specifically, by increasing the funnel profile of the recess 98, voids and seams that are easily formed during the filling process of the recess 98 can be avoided. Therefore, electrical performance and yield can be improved by avoiding voids and seams.

[0089] exist Figure 20A-20C In the embodiment, the gate structure (including the gate dielectric layer 100 and the corresponding gate electrode 102 thereon) is recessed so that a recess is formed directly above the gate structure and between the opposing portions of the first spacer 81. A gate mask 104 including one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled in the recess, and then a planarization process is performed to remove excess portions of the dielectric material extending above the first ILD 96. A gate contact is subsequently formed through the gate mask 104 to contact the top surface of the recessed gate electrode 102.

[0090] like Figure 20A-20C As further shown, the second ILD 106 is deposited over the first ILD 96 and over the gate mask 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD, PECVD, etc.

[0091] exist Figure 21A-Figure 21C, the second ILD 106, the first ILD 96, the CESL 94, and the gate mask 104 are etched to form a third recess 108, which exposes the surface of the epitaxial source / drain region 92 and / or the gate structure. The third recess 108 can be formed by etching using an anisotropic etching process (e.g., RIE, NBE, etc.). In some embodiments, the third recess 108 can be etched through the second ILD 106 and the first ILD 96 using a first etching process; can be etched through the gate mask 104 using a second etching process; and can then be etched through the CESL 94 using a third etching process. A mask (e.g., a photoresist) can be formed over the second ILD 106 and patterned to mask portions of the second ILD 106 from the first etching process and the second etching process. In some embodiments, the etching process may over-etch so that the third recess 108 extends into the epitaxial source / drain region 92 and / or the gate structure, and the bottom of the third recess 108 may be flush with (e.g., at the same level, or having the same distance from the substrate) or lower than (e.g., closer to the substrate) the epitaxial source / drain region 92 and / or the gate structure. Figure 21B-Figure 21C The third recess 108 is shown as exposing the epitaxial source / drain region 92 and the gate structure in the same cross section, but in various embodiments, the epitaxial source / drain region 92 and the gate structure may be exposed in different cross sections, thereby reducing the risk of shorting subsequently formed contacts. After forming the third recess 108, a silicide region 110 is formed over the epitaxial source / drain region 92. In some embodiments, the silicide region 110 is formed as follows: a metal (not shown) capable of reacting with the semiconductor material (e.g., silicon, silicon germanium, germanium) of the underlying epitaxial source / drain region 92 to form a silicide region or a germanide region is first deposited over the exposed portion of the epitaxial source / drain region 92, for example, nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof, and then a thermal annealing process is performed to form the silicide region 110. The unreacted portion of the deposited metal is then removed, for example, by an etching process. Although the silicide region 110 is referred to as a silicide region, the silicide region 110 may also be a germanide region, or a silicon-germanide region (e.g., a region including silicide and germanide). In an embodiment, the silicide region 110 includes TiSi and has a thickness in a range between about 2 nm and about 10 nm.

[0092] Next, in Figure 22A-22CIn the embodiment of the present invention, contacts 112 and 114 (also referred to as contact plugs) are formed in the third recess 108. The contacts 112 and 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filling material. For example, in some embodiments, the contacts 112 and 114 each include a barrier layer and a conductive material 118, and are electrically coupled to the underlying conductive features (e.g., the gate electrode 102 and / or the silicide region 110 in the illustrated embodiment). The contact 114 is electrically coupled to the gate electrode 102 and may be referred to as a gate contact, and the contact 112 is electrically coupled to the silicide region 110 and may be referred to as a source / drain contact. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material 118 may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 106.

[0093] Figure 23A-23C Cross-sectional views of devices according to some alternative embodiments are shown. Fig.23A Shows Figure 1 Reference section AA' is shown. Fig. 23B Shows Figure 1 Reference section BB' is shown. Fig.23C Shows Figure 1 Reference section C-C' is shown. Figure 23A-23C In the Figure 22A-22C The same elements are formed by the same process. Figure 23A-23C In the embodiment, the channel regions in the n-type region 50N and the p-type region 50P include the same material. For example, the second nanostructure 54 (including silicon) provides a channel region for a p-type nanostructure FET in the p-type region 50P and for an n-type nanostructure FET in the n-type region 50N. Figure 23A-23C The structure of can be formed, for example, as follows: remove the first nanostructure 52 from both the p-type region 50P and the n-type region 50N at the same time; deposit the gate dielectric layer 100 and the gate electrode 102P (e.g., suitable for the gate electrode of the p-type nanostructure FET) around the second nanostructure 54 in the p-type region 50P; and deposit the gate dielectric layer 100 and the gate electrode 102N (e.g., suitable for the gate electrode of the n-type nanostructure FET) around the second nanostructure 54 in the n-type region 50N. In such an embodiment, the material of the epitaxial source / drain region 92 can be different from that of the p-type region 50P in the n-type region 50N, as described above.

[0094] Embodiments can achieve advantages. For example, by using oxidation and removal processes to widen the second recess 98, the shape and width of the second recess 98 can be well controlled to achieve a better filling process to form the gate electrode 102, so that the gate electrode 102 has fewer defects, such as gaps or seams. Therefore, defects are reduced, and overall device and yield performance can be improved.

[0095] In one embodiment, a method of manufacturing a semiconductor device includes: forming a fin from a plurality of semiconductor materials; depositing a dummy gate over the fin; depositing a plurality of spacers adjacent to the dummy gate; removing the dummy gate to form an opening adjacent to the plurality of spacers; widening the opening adjacent to the top surface of the plurality of spacers, wherein widening the opening includes: oxidizing a first portion of a sidewall of the plurality of spacers; and removing the first portion; after widening, removing one of the plurality of semiconductor materials to form a nanowire; and depositing a gate electrode around the nanowire. In one embodiment, after widening, one of the plurality of spacers has an oxygen concentration in the first portion greater than that in the second portion, the first portion being further away from the substrate than the second portion. In one embodiment, oxidizing the first portion is performed using a treatment precursor, the treatment precursor comprising: an oxidation precursor; and an inert gas precursor. In one embodiment, the method further includes igniting the treatment precursor into a plasma. In one embodiment, the oxygen percentage of the treatment precursor is about 20%. In one embodiment, the oxygen percentage of the treatment precursor is about 40%.

[0096] In one embodiment, a method of manufacturing a semiconductor device includes: removing a dummy gate electrode from between a first spacer and a second spacer above a semiconductor fin, the semiconductor fin including a first semiconductor material and a second semiconductor material different from the first semiconductor material; oxidizing a portion of a sidewall of the first spacer using a plasma precursor; removing the portion of the sidewall to form a first opening, the first opening having a first width adjacent to a top of the first spacer and a second width less than the first width; removing one of the first semiconductor material or the second semiconductor material to form a nanowire; and depositing a gate electrode within the first opening. In one embodiment, the method also includes generating a plasma precursor from a treatment precursor, wherein the treatment precursor includes an inert gas. In one embodiment, the treatment precursor includes an oxidizing gas. In one embodiment, the oxidizing gas is diatomic oxygen. In one embodiment, the oxygen percentage of the treatment precursor is about 60%. In one embodiment, the first angle of the sidewall of the gate electrode relative to the top surface of the first spacer is about 88°. In one embodiment, the oxygen percentage of the treatment precursor is about 40%. In one embodiment, the first angle of the sidewall of the gate electrode relative to the top surface of the first spacer is about 86°.

[0097] In one embodiment, a semiconductor device includes: a plurality of nanowires; a gate stack overlying the plurality of nanowires; and a first spacer on a sidewall of the gate stack, wherein the sidewall extends away from a top surface of the first spacer at a first angle between about 84° and about 88°, wherein the first spacer has a higher oxygen concentration at a top of the first spacer than at a bottom of the first spacer. In one embodiment, the first angle is about 84°. In one embodiment, the first angle is about 86°. In one embodiment, the first angle is about 88°. In one embodiment, the first spacer includes SiONC. In one embodiment, the gate stack has a funnel profile.

[0098] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0099] Example 1 is a method for manufacturing a semiconductor device, the method comprising: forming fins from multiple semiconductor materials over a substrate; depositing a dummy gate over the fin; depositing multiple spacers adjacent to the dummy gate; removing the dummy gate to form an opening adjacent to the multiple spacers; after removing the dummy gate, widening the opening adjacent to the top surface of the multiple spacers, wherein widening the opening comprises: oxidizing a first portion of the side walls of the multiple spacers; and removing the first portion; after the widening, removing one of the multiple semiconductor materials to form a nanowire; and depositing a gate electrode around the nanowire.

[0100] Example 2 is the method of Example 1, wherein, after the widening, one of the plurality of spacers has a greater oxygen concentration in a first portion than in a second portion, the first portion being further away from the substrate than the second portion.

[0101] Example 3 is the method of Example 1, wherein oxidizing the first portion is performed using a treatment precursor comprising: an oxidizing precursor; and an inert gas precursor.

[0102] Example 4 is the method of Example 3, further comprising: igniting the process precursor into a plasma.

[0103] Example 5 is the method of Example 4, wherein the oxygen percentage of the treated precursor is about 20%.

[0104] Example 6 is the method of Example 4, wherein the oxygen percentage of the treated precursor is about 40%.

[0105] Example 7 is a method for manufacturing a semiconductor device, the method comprising: removing a dummy gate electrode from between a first spacer and a second spacer above a semiconductor fin, the semiconductor fin comprising a first semiconductor material and a second semiconductor material different from the first semiconductor material; oxidizing a portion of a sidewall of the first spacer using a plasma precursor; removing the portion of the sidewall to form a first opening, the first opening having a first width adjacent to a top of the first spacer and a second width less than the first width; removing one of the first semiconductor material or the second semiconductor material to form a nanowire; and depositing a gate electrode within the first opening.

[0106] Example 8 is the method of Example 7, further comprising: generating the plasma precursor from a process precursor, wherein the process precursor includes an inert gas.

[0107] Example 9 is the method of Example 8, wherein the process precursor includes an oxidizing gas.

[0108] Example 10 is the method of Example 9, wherein the oxidizing gas is diatomic oxygen.

[0109] Example 11 is the method of Example 10, wherein the oxygen percentage of the treated precursor is about 60%.

[0110] Example 12 is the method of Example 11, wherein a first angle of a sidewall of the gate electrode relative to a top surface of the first spacer is approximately 88°.

[0111] Example 13 is the method of Example 10, wherein the oxygen percentage of the treated precursor is about 40%.

[0112] Example 14 is the method of Example 13, wherein a first angle of a sidewall of the gate electrode relative to a top surface of the first spacer is approximately 86°.

[0113] Example 15 is a semiconductor device comprising: a plurality of nanowires; a gate stack overlying the plurality of nanowires; and a first spacer located on a sidewall of the gate stack, wherein the sidewall extends away from a top surface of the first spacer at a first angle between approximately 84° and approximately 88°, wherein the first spacer has an oxygen concentration at a top of the first spacer that is higher than a bottom of the first spacer.

[0114] Example 16 is the semiconductor device of Example 15, wherein the first angle is approximately 84°.

[0115] Example 17 is the semiconductor device of Example 15, wherein the first angle is approximately 86°.

[0116] Example 18 is the semiconductor device of Example 15, wherein the first angle is approximately 88°.

[0117] Example 19 is the semiconductor device of Example 15, wherein the first spacer comprises SiONC.

[0118] Example 20 is the semiconductor device of Example 15, wherein the gate stack has a funnel profile.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming a fin from a plurality of semiconductor materials over a substrate; depositing a dummy gate on the fin; depositing a plurality of spacers adjacent to the dummy gate; removing the dummy gate to form an opening adjacent to the plurality of spacers; After removing the dummy gate, widening the opening adjacent to the top surface of the plurality of spacers, wherein widening the opening comprises: oxidizing first portions of sidewalls of the plurality of spacers; and removing the first portion; After the widening, removing one of the plurality of semiconductor materials to form a nanowire; and A gate electrode is deposited around the nanowires.

2. The method according to claim 1, wherein: After the widening, one of the plurality of spacers has a greater oxygen concentration in a first portion than in a second portion, the first portion being farther from the substrate than the second portion.

3. The method according to claim 1, wherein: Oxidizing the first portion is performed using a process precursor comprising: oxidative precursors; and Inert gas precursor.

4. The method according to claim 3, further comprising: The process precursor is ignited into a plasma.

5. The method according to claim 4, wherein: The oxygen percentage of the treated precursor was 20%.

6. The method according to claim 4, wherein: The oxygen percentage of the treated precursor was 40%.

7. A method for manufacturing a semiconductor device, the method comprising: removing a dummy gate electrode from between a first spacer and a second spacer over a semiconductor fin, the semiconductor fin comprising a first semiconductor material and a second semiconductor material different from the first semiconductor material; oxidizing a portion of a sidewall of the first spacer using a plasma precursor; removing the portion of the sidewall to form a first opening having a first width adjacent to a top of the first spacer and a second width less than the first width; removing one of the first semiconductor material or the second semiconductor material to form a nanowire; as well as A gate electrode is deposited in the first opening.

8. The method according to claim 7, further comprising: The plasma precursor is generated from a process precursor, wherein the process precursor comprises an inert gas.

9. The method according to claim 8, wherein: The process precursor includes an oxidizing gas.

10. A semiconductor device comprising: multiple nanowires; a gate stack overlying the plurality of nanowires; as well as A first spacer is located on a sidewall of the gate stack, wherein the sidewall extends away from a top surface of the first spacer at a first angle between 84° and 88°, wherein the first spacer has an oxygen concentration at a top of the first spacer that is higher than a bottom of the first spacer.

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