Method for improving reliability of middle-high voltage device

Abstract

The invention discloses a method for improving the reliability of a medium-high voltage device, which optimizes three photomask layouts of a Spacer1 process, an IOR process and an SAB process, can improve the performance of the device on the premise of not increasing the cost, and is characterized in that a first isolation photomask is utilized to protect a grid slot of a high-voltage region, and meanwhile, the width from a source drain to a channel in a medium-voltage region is defined, so that the reliability of the medium-high voltage device is improved. If the width from the source drain to the channel is greater than the width of the second isolation, executing isolation etching, and reserving the high-voltage region gate slot and the first isolation, close to the channel, of the source drain in the medium-voltage region; from subsequent execution to execution of an IOR process according to the prior art, covering a low-voltage region and a high-voltage region by using an IOR photomask, opening a medium-voltage region, etching an oxide layer of an active region of the medium-voltage region, and removing an oxide layer of a source-drain injection region by using first isolation of the medium-voltage region as a hard mask; and executing the follow-up process to the SAB process according to the prior art, and shielding the gate slot of the high-voltage region by using an SAB photomask.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a method for improving the reliability of medium-voltage devices and high-voltage devices on a 28nm process platform. Background Art

[0002] As mobile phone screens develop towards larger and foldable screens, the power consumption and display performance requirements for display driver chips have been raised to a new level. Due to the inherent advantages of AMOLED displays: thin panel thickness, high display color saturation, good power saving effect, low power consumption, and flexible display, AMOLED displays will become the first choice for mid-to-high-end smartphones in the future. The demand for AMOLED driver chip devices is divided into three categories: 1. Due to speed and power consumption requirements, core LV devices require low voltage and high speed requirements. 2. In order to drive TFT tubes, HV (20V-32V) high-voltage processes are required. 3. For current drive circuit design, 8V medium-voltage MV device requirements are required.

[0003] As device size continues to shrink, the thickness of traditional gate oxide SiON is reduced to below 2nm, and the gate leakage current increases. To solve this problem, the semiconductor industry uses high-K dielectric materials HfO2 and HfSiON to replace SiON as the gate oxide layer, and uses metal gates instead of polysilicon gates. This process is called HKMG process technology. Compared with the traditional SiON / Poly gate integration solution, the HKMG process can reduce the thickness of the transistor gate oxide layer and reduce power consumption by increasing transistor speed and reducing voltage. Developing HV (high voltage) and MV (medium voltage) device processes on the 28nm HKMG platform has become the mainstream solution for 28nm HV display drivers. The current 28nm HV platform is a Metal Gate structure, and there are two main challenges in the process: 1. The HV device is large in size, and additional slots (slots / gaps) will be added to prevent CMP-dishing of the Metal Gate. However, after the slots are introduced, subsequent processes are prone to cause HV-Gate oxide damage.

[0004] CMP-dishing is a phenomenon that occurs during the chemical mechanical planarization (CMP) process, which refers to the metal depression caused by the metal layer in low areas such as oxide cavities or grooves after CMP polishing. This may cause interconnect resistance, capacitance fluctuations, and even metal interconnect short circuits and open circuits, thereby affecting the chip yield.

[0005] 2. Due to the limitation of 28HK LV (low voltage) spacer (isolation) width, 8V MV medium voltage device GIDL (gate induced drain leakage) will occur. Summary of the invention

[0006] A series of simplified concepts are introduced in the Summary of the Invention, which are all simplifications of the prior art in the field, and will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention of the present invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0007] The technical problem to be solved by the present invention is to provide a method for improving the reliability of medium and high voltage devices by preventing HV-oxide damage caused by subsequent processes and improving GIDL without increasing process costs.

[0008] In order to solve the above technical problems, the method for improving the reliability of medium and high voltage devices provided by the present invention adopts the existing process to produce and deposit the first isolation (SP1), performs photolithography, uses the first isolation (SP1) mask to protect the gate slot of the high voltage area, and at the same time defines the width of the source and drain to the channel in the medium voltage area, the width of the source and drain to the channel is greater than the width of the second isolation (SP2), performs isolation etching, retains the gate slot of the high voltage area and the first isolation of the source and drain of the medium voltage area close to the channel, and performs subsequent processes according to the existing technology.

[0009] Preferably, the method for improving the reliability of medium and high voltage devices is further improved. When the IOR process is executed, photolithography is performed, and the low voltage area and the high voltage area are covered with the IOR mask, the medium voltage area is opened, and the oxide layer (AA-oxide) of the active area of ​​the medium voltage area is etched, and the first isolation (SP1) of the medium voltage area is used as a hard mask to remove the oxide layer of the source and drain injection area.

[0010] Preferably, the method for improving the reliability of medium and high voltage devices is further improved by depositing a SAB film when performing the IOR process, and using a SAB mask to shield the gate slot of the high voltage area when performing photolithography.

[0011] Preferably, the method for further improving the reliability of medium and high voltage devices is further improved, wherein the first isolation is doped silicon nitride (SICN) with a thickness ranging from 50 angstroms to 120 angstroms.

[0012] Preferably, the method for improving the reliability of medium and high voltage devices is further improved. When the SAB process is executed, when the high voltage area Si Recess process is performed, the recess depth of the high voltage area ranges from 300 angstroms to 500 angstroms, and the recess depth is finally level with the Si surface after the final HV-Gateoxide growth.

[0013] Preferably, the method for improving the reliability of medium and high voltage devices is further improved. When the SAB process is executed, when the Si Recess process in the medium voltage area is performed, the Recess depth range is 100 angstroms to 200 angstroms, and the final height is the same as the Si surface after the MV-Gate oxide grows.

[0014] Preferably, the method for improving the reliability of medium and high voltage devices is further improved, and when the SAB process is performed, the second isolation (SP2) is deposited using an oxide layer and a silicon nitride layer with the same process as that of the high voltage region.

[0015] On the basis of the existing technology, the present invention can achieve the following technical effects by modifying the three mask layouts of Spacer1, IOR and SAB without adding any additional process steps and without increasing the cost. Figure 1 As shown; 1. The HV slot is protected by the first isolation mask. During the Spacer1 etching process, the HV slot and the MV near the channel area are protected by the Spacer1 film, which reduces the damage caused by the process.

[0016] 2. Define the distance from MV source and drain to channel. This distance is greater than the width of spacer2. MV is close to the channel area and is blocked by MV-oxide. The source and drain area IMP injection is formed by self-alignment, which increases the distance from source and drain to channel and effectively reduces GIDL leakage.

[0017] 3. No additional film or thermal process is introduced, and there is no impact on LV devices.

[0018] 4. Spacer1, IOR and SAB are all existing masks, and there is no additional cost.

[0019] 5. The retained sp1 and SAB in the HV slot area form a protective layer to prevent HV-oxide damage caused by subsequent processes. For example, the impact of the surface oxide removal step in the salicide-dep process on the HV-Gate-oxide can be reduced.

[0020] The present invention can improve device performance without increasing costs by improving at least one mask layout of the Spacer1 process, the IOR process, and the SAB process. If the three mask layouts of the Spacer1 process, the IOR process, and the SAB process are all optimized and improved, the device performance can be significantly improved under the joint action of multiple aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings of the present invention are intended to illustrate the general characteristics of the methods, structures and / or materials used in specific exemplary embodiments of the present invention, and to supplement the description in the specification. However, the drawings of the present invention are schematic diagrams not drawn to scale, and thus may not accurately reflect the precise structure or performance characteristics of any given embodiment, and the drawings of the present invention should not be interpreted as limiting or restricting the range of values ​​or properties covered by the exemplary embodiments of the present invention. The present invention is further described in detail below in conjunction with the drawings and specific embodiments: Figure 1 It is a schematic diagram of the improved position of the device of the present invention.

[0022] Figure 2~Figure 26 It is a schematic diagram of the structure formed by each step of the embodiment of the present invention. DETAILED DESCRIPTION

[0023] The following is an explanation of the embodiments of the present invention by specific specific embodiments, and those skilled in the art can fully understand other advantages and technical effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and the details in this specification can also be applied based on different viewpoints, and various modifications or changes can be made without deviating from the general design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. The following exemplary embodiments of the present invention can be implemented in a variety of different forms and should not be interpreted as being limited to the specific embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary specific embodiments to those skilled in the art. It should be understood that when an element is referred to as "connected" or "coupled" to another element, the element can be directly connected or coupled to another element, or there can be an intermediate element. The difference is that when an element is referred to as "directly connected" or "directly coupled" to another element, there is no intermediate element. In all figures, the same reference numerals always represent the same element. As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items.

[0024] It should be noted that the preferred embodiment of the present invention provides an optimal solution that the applicant considers. For the sake of easy understanding of the brief description, the exemplary description of the embodiment of the present invention optimizes and modifies the three mask layouts of the Spacer1 process, the IOR process, and the SAB process. However, this should not be understood as a restriction that the above three mask layouts must be implemented at the same time. That is, any one of the three mask layouts can be improved, any two or three can be improved at the same time. Regardless of whether any one, any two or three are improved at the same time, the corresponding technical effect brought about by the improved mask layout still exists. The only difference is which solution is more effective.

[0025] The present invention provides a method for improving the reliability of medium and high voltage devices, which can be selectively applied to a 28nm process platform, comprising: 1) After zero mark, first perform HV-Well injection, such as Figure 2 As shown; Zero Mark is a structure used to mark the position during the preparation of semiconductor devices. It is usually used for lithography alignment and overlay marking of the crystal face and crystal back. When the device layer is formed on the back of the substrate, the zero mark can also be used as a grinding stop mark on the back of the substrate. HV-Well injection is a semiconductor manufacturing process used to form a high-voltage well in a semiconductor device. It is achieved by injecting impurities into the semiconductor material, which can change the electrical properties of the semiconductor to form a high-voltage well.

[0026] 2) AA-loop (including photolithography, etching, trench making and other processes, which can be completely based on existing technology and processes), after SiN-HM is removed, HV Drift injection is performed, such as Figure 3 , Figure 4 As shown; The AA-loop is used to form an active area, which refers to the area in a semiconductor device that can generate and control current.

[0027] HV Drift implantation is a semiconductor manufacturing process that is often used to form active areas in high-voltage semiconductor devices. In the semiconductor device manufacturing process, in order to meet the higher operating voltage requirements of high-voltage semiconductor devices, it is necessary to form a trench isolation structure in the semiconductor substrate and then perform N-type or P-type ion implantation.

[0028] 3) Then SiN-HM deposition is performed, and Si-Recess is formed in the HV region. After the depth of Recess is grown with the final HV-Gate oxide, the final height is level with the Si surface, such as Figure 5 , Figure 6 As shown; 4) Then carry out MV / LV well, HV drift, MV LDD injection process, such as Figure 7 shown.

[0029] 5) Then, the Si-Recess process is carried out in the MV region. The depth of the Recess of the 8V device is preferably 200 angstroms. After the MV-Gateoxide is grown, the final height of the Recess is flush with the Si surface, such as Figure 8~Figure 11 shown.

[0030] The Recess process is a process used to form a recessed or etched area during semiconductor manufacturing. It is commonly used to manufacture semiconductor devices such as transistors. By forming a specific recessed structure in the silicon material, the performance of the device can be controlled and optimized.

[0031] 6) Then DG-photo is performed to cover MV, remove oxide in LV area and oxide in HV area. Then LV-Gate-oxide and HK deposition are performed, followed by poly and HM dep, SiN and Oxide composite HM, such as Fig.12 shown.

[0032] DG-photo is a double-gate process mask. Double-gate semiconductor technology is a technology that uses two gates to control the flow of carriers in semiconductor device design. The double-gate process can improve the performance of the device. The double gate can be controlled by adjusting at least one of the following parameters, including: gate oxide thickness, gate material, gate length, gate width, gate dielectric material, gate polysilicon doping concentration, gate stack structure, source / drain alignment with the gate, and gate contact hole.

[0033] Preferably, the dual-gate process of the present invention refers to realizing two different gate oxide thicknesses in a set of processes, such as gate oxide 10 angstroms and 15 angstroms, so as to meet different device requirements.

[0034] 7) Form the patterns of LV, MV, HV and HV-slot Poly by dry etching, and then deposit spacer1 SiCN, such as Figure 13~Figure 15 shown.

[0035] 8) Spacer1-PH, protects HV slot, and defines the distance from MV source drain to channel. This distance is greater than the width of spacer2, increasing the distance from source drain to channel, effectively reducing GIDL leakage. At the same time, during the Spacer1 etching process, the HV slot and MV are protected by the Spacer1 film near the channel area, reducing the damage caused by the process, such as Figure 16~Figure 18 shown.

[0036] 10) LVLDD Photo, halo and LDD implantation and PR asher and strip processes. Since the HV-slot area and MV are close to the channel area and are protected by SP1, the oxide damage caused by asher and other processes can be reduced. Fig.19 shown.

[0037] 11) Spacer2 deposition, Spacer2-Dep uses oxide 20 angstroms + SiN 200 angstroms consistent with the 28HK platform, and Spacer2-Blanket etching forms a spacer2 structure. The HV slot area and MV are close to the channel area. Due to the protection of SP1 film, the introduction of spacer2 etch damage is reduced, which is beneficial to the reliability of HV and MV. Figure 20~Figure 21 Show.

[0038] IOR-Photo covers the LV and HV areas, opens the MV area, and etches the AA-oxide in the MV area. At this time, the SP1-SiN in the MV area is used as HM to block, and the oxide in the source and drain injection area is removed, increasing the distance from the source and drain to the channel. This reduces the damage caused by MV-oxide etching with the original IOR process advantage, and at the same time reduces the loss of MV Poly-oxide HM thickness, which increases the process window for subsequent MG-CMP dishes, such as Fig. 22 shown.

[0039] 12) MV is close to the channel area. Due to the MV-oxide shielding, the source and drain areas are formed by self-alignment. IMP injection increases the distance from the source and drain to the channel, effectively reducing the GIDL leakage, such as Fig.23 shown.

[0040] 13) SAB film deposition, followed by SAB-PH, shielding the HV slot area, e.g. Fig.24 , 25 shown.

[0041] 14) Due to the MV-oxide shielding, the MV AA area is self-aligned to form the salicide part of the source and drain area. Since the HV-slot area has been shielded, the impact of the surface oxide removal step of the salicide process on the HV-area damage before salicide-dep can be reduced, such as Fig.26 shown.

[0042] 15) Since the HV-slot area is already shielded, the impact of the salicide-dep process and the surface oxide removal step on the HV-Gate-oxide can be reduced.

[0043] 16) The subsequent process is consistent with the existing technology of 28HKMG process and will not be repeated here.

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. It will also be understood that, unless expressly defined herein, terms such as those defined in general dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not interpreted in an ideal or overly formal sense.

[0045] The present invention has been described in detail above through specific implementation modes and embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may also make many variations and improvements, which should also be regarded as the protection scope of the present invention.

Claims

1. A method for improving the reliability of medium and high voltage devices, using existing processes to deposit the first isolation, characterized in that: Perform photolithography, use the first isolation mask to protect the gate groove of the high-voltage area, and define the width of the source and drain to the channel in the medium-voltage area. The width of the source and drain to the channel is greater than the width of the second isolation. Perform isolation etching, retain the gate groove of the high-voltage area and the first isolation of the source and drain of the medium-voltage area close to the channel, and perform subsequent processes according to the existing technology.

2. The method for improving the reliability of medium and high voltage devices according to claim 1, when the IOR process is performed, is characterized in that: Perform photolithography, use IOR mask to cover the low voltage area and high voltage area, open the medium voltage area, etch the oxide layer of the active area of ​​the medium voltage area, use the first isolation of the medium voltage area as a hard mask, and remove the oxide layer of the source and drain injection area.

3. The method for improving the reliability of medium and high voltage devices according to claim 2, when the SAB process is performed, is characterized in that: Deposit the SAB film, and use the SAB mask to block the gate grooves in the high-voltage area during photolithography.

4. The method for improving the reliability of medium and high voltage devices according to claim 1, characterized in that: The first isolation is doped silicon nitride (SICN) with a thickness ranging from 50 angstroms to 120 angstroms.

5. The method for improving the reliability of medium and high voltage devices according to claim 1, when the SAB process is performed, is characterized in that: When performing the high-voltage Si Recess process, the depth of the high-voltage recess ranges from 300 angstroms to 500 angstroms. After the final HV-Gate oxide grows, the final height of the recess is flush with the Si surface.

6. The method for improving the reliability of medium and high voltage devices according to claim 1, when the SAB process is performed, is characterized in that: When performing the medium-voltage Si Recess process, the Recess depth ranges from 100 angstroms to 200 angstroms, and the final height is level with the Si surface after the MV-Gate oxide grows.

7. The method for improving the reliability of medium and high voltage devices according to claim 4, when the SAB process is performed, is characterized in that: The second isolation is deposited using the same process as the high voltage area, using an oxide layer and a silicon nitride layer.

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