High-density substrate stacked packaging structure and packaging method

Abstract

The present application provides a high-density substrate stacked packaging structure and a packaging method, which relate to the field of semiconductor packaging technology. The high-density substrate stacked packaging structure includes a first chip, a conductive wire arc, a first plastic package and a first dielectric layer. The first chip has a first solder pad. Both ends of the conductive wire arc are connected to the same first solder pad. The first plastic package covers the first chip; a first wiring layer electrically connected to the conductive wire arc is provided in the first dielectric layer. The first dielectric layer covers one side of the first plastic package close to the first solder pad. A first bump electrically connected to the first wiring layer is provided on the surface of the first dielectric layer. The shear force on the chip during the grinding process can be reduced to prevent the chip from being damaged or cracked.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging technology, and in particular to a high-density substrate stacking packaging structure and a packaging method. Background Art

[0002] The existing 2.5D packaging technology is to integrate and package multiple small chips together, and the electrical connection of the chip is formed by forming metal pillars on the surface of the chip pad. There are two main ways to form metal pillars. One is to electroplate metal pillars on the surface of the chip pad and then perform plastic sealing. The other is to first plastic seal the chip and then etch grooves on the plastic body and fill the grooves with metal materials to form metal pillars. Regardless of the method, the plastic body and metal pillars need to be ground after plastic sealing. In the grinding process, chemicals and grinding disc particles are used to make the metal pillars and the grinding disc rotate relative to each other to achieve flatness.

[0003] During the grinding process, the metal pillar is easily subjected to shear force, which causes cracks between the bottom of the metal pillar and the chip pad, leading to electrical failure and other problems. Summary of the invention

[0004] The object of the present invention is to provide a high-density substrate stacking packaging structure and a packaging method, which can effectively reduce the shear force on the chip during the grinding process and prevent the chip from being cracked or damaged.

[0005] In a first aspect, the present invention provides a high-density substrate stacked packaging structure, comprising:

[0006] A first chip, wherein the first chip has a first pad;

[0007] A conductive arc, two ends of which are connected to the same first pad;

[0008] a first plastic package, wherein the first plastic package covers the first chip;

[0009] A first dielectric layer, wherein a first wiring layer electrically connected to the conductive arc is provided in the first dielectric layer; the first dielectric layer covers a side of the first plastic package body close to the first pad;

[0010] A first bump electrically connected to the first wiring layer is provided on the surface of the first dielectric layer;

[0011] A second chip is electrically connected to the first bump.

[0012] In an optional embodiment, the conductive line arc has multiple crests and / or multiple troughs.

[0013] In an optional embodiment, a accommodating cavity is formed between the conductive wire arc and the first pad; the conductive wire arc is disconnected on a side away from the chip to form a first opening connected to the accommodating cavity; the conductive wire arc includes a first end and a second end forming the first opening; the first end and the second end are electrically connected to the first wiring layer, respectively.

[0014] In an optional implementation, the accommodating cavity is filled with a metal layer, or the accommodating cavity is filled with a first dielectric layer.

[0015] In an optional implementation, an annular blocking glue is provided on the chip, and the first pad and the conductive wire arc are located in the annular blocking glue.

[0016] In an optional embodiment, a removable filling glue is provided in the annular glue stopper.

[0017] In an optional embodiment, it also includes a second dielectric layer covering the side of the first plastic package away from the first pad; a second wiring layer is provided in the second dielectric layer, and a second bump electrically connected to the second wiring layer is provided on the surface of the second dielectric layer; the first wiring layer and the second wiring layer are electrically connected through a conductive column.

[0018] In an optional embodiment, a plurality of heat dissipation arcs are further included, a heat dissipation pad is provided on the first chip, one end of each heat dissipation arc is connected to the heat dissipation pad, and the other end is connected to the second dielectric layer; the plurality of heat dissipation arcs are arranged at the periphery of the first chip, and the middle of each heat dissipation arc is disconnected.

[0019] In an optional embodiment, the middle of the heat dissipation arc is disconnected to form a first arc and a second arc; one end of the first arc is connected to the heat dissipation pad, and the other end is connected to the first dielectric layer; one end of the second arc is connected to the first dielectric layer, and the other end is connected to the second dielectric layer;

[0020] A grounding point is provided in the second dielectric layer, and the second wire arc is electrically connected to the grounding point.

[0021] In a second aspect, the present invention provides a packaging method for preparing a high-density substrate stacked packaging structure as described in any one of the aforementioned embodiments.

[0022] In an optional embodiment, it includes:

[0023] Providing a carrier with a first chip mounted thereon;

[0024] forming a conductive arc on a first pad of the first chip;

[0025] forming a conductive column on the carrier;

[0026] Plastic-sealing the first chip to form a first plastic-sealed body;

[0027] Grinding the first plastic package body until the conductive arc is exposed;

[0028] A first dielectric layer having a first wiring layer is formed on one side of the first plastic package body close to the first pad; the first wiring layer is electrically connected to the conductive arc and the conductive column respectively.

[0029] In an optional implementation manner, after the step of forming a conductive arc on the first pad of the first chip, the method further includes:

[0030] An annular blocking glue is formed on the first chip; the first pad and the conductive wire arc are located in the annular blocking glue.

[0031] In an optional embodiment, after the step of forming a ring-shaped blocking glue on the first chip, the method further includes:

[0032] Forming a filling glue in the annular glue stopper;

[0033] After the step of grinding the first plastic package body until the conductive arc is exposed, the filling glue is removed.

[0034] In an optional embodiment, in the step of grinding the first plastic package body until the conductive arc is exposed:

[0035] The first plastic package body is ground until the conductive arc is broken, and a first opening is formed on a side of the conductive arc away from the first pad.

[0036] In an optional embodiment, the first chip is provided with a heat dissipation pad; before the step of plastic-sealing the first chip to form a first plastic-sealed body, the method further includes:

[0037] Bonding a wire between the carrier and the heat dissipation pad to form a heat dissipation wire arc;

[0038] In the step of grinding the first plastic package body until the conductive wire arc is broken: the heat dissipation wire arc is also broken at the same time.

[0039] The high-density substrate stacked packaging structure and packaging method provided by the embodiments of the present invention have the following beneficial effects:

[0040] The high-density substrate stacked packaging structure and packaging method provided by the embodiment of the present invention form a conductive arc on the first pad, thereby reducing the contact area between the conductive arc and the first pad during grinding, reducing the shear force on the first pad during grinding, and preventing the chip from having hidden cracks or cracks and electrical failure. At the same time, the bonding force between the plastic package and the chip can be improved, and the structure is more reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0042] Figure 1 A schematic diagram of a first structure of a high-density substrate stacked packaging structure provided by an embodiment of the present invention;

[0043] Figure 2 A schematic diagram of the structure of the conductive wire arc and the annular glue stopper before grinding of the high-density substrate stacked packaging structure provided by an embodiment of the present invention;

[0044] Figure 3 A schematic diagram of the structure of the conductive wire arc and the annular glue stopper after grinding of the high-density substrate stacked packaging structure provided by an embodiment of the present invention;

[0045] Figure 4 A schematic structural diagram of a first dielectric layer being filled in a receiving cavity of a high-density substrate stacked packaging structure provided by an embodiment of the present invention;

[0046] Figure 5 A schematic structural diagram of a metal layer filled in a receiving cavity of a high-density substrate stacked packaging structure provided by an embodiment of the present invention;

[0047] Figure 6 A second structural schematic diagram of a high-density substrate stacked packaging structure provided by an embodiment of the present invention;

[0048] Figure 7 A third structural schematic diagram of a high-density substrate stacked packaging structure provided by an embodiment of the present invention;

[0049] Figure 8 A fourth structural schematic diagram of a high-density substrate stacked package structure provided by an embodiment of the present invention;

[0050] Fig. 9 A schematic diagram of a local structure in which a heat dissipation arc is arranged on the first chip of the high-density substrate stacked package structure provided by an embodiment of the present invention;

[0051] Fig.10 A structural schematic diagram of another perspective of a first chip of a high-density substrate stacked package structure provided by an embodiment of the present invention having a heat dissipation arc arranged therein;

[0052] Fig.11 A fifth structural schematic diagram of a high-density substrate stacked packaging structure provided by an embodiment of the present invention;

[0053] Fig.12 and Fig.13 Schematic diagrams of structures with two different perspectives for adding an electrostatic ring to the first dielectric layer;

[0054] Figures 14 to 16 A schematic diagram of a manufacturing process of a high-density substrate stacked packaging structure provided by an embodiment of the present invention;

[0055] Fig.17 Another schematic diagram of a manufacturing process of a high-density substrate stacked package structure provided by an embodiment of the present invention;

[0056] Fig.18 A schematic diagram of the process of manufacturing a heat dissipation line arc of a high-density substrate stacked packaging structure provided by an embodiment of the present invention.

[0057] Icons: 100-high-density substrate stacked packaging structure; 110-first chip; 111-first pad; 112-conductive arc; 101-accommodating cavity; 113-first opening; 114-first end; 115-second end; 116-metal layer; 117-heat dissipation pad; 120-first plastic package; 130-first dielectric layer; 131-first graphic layer opening; 133-first wiring layer; 135-first bump; 140-ring-shaped glue stop; 141-filling Glue; 150-conductive column; 160-second chip; 161-second plastic package; 170-second dielectric layer; 171-second graphic layer opening; 173-second wiring layer; 175-grounding point; 177-second bump; 180-heat dissipation arc; 181-first arc; 182-second arc; 183-static ring; 190-solder ball; 200-carrier; 220-third dielectric layer; 221-first slot; 230-fourth dielectric layer; 231-second slot. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0059] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0060] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0061] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the product of the invention is usually placed when in use. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0062] In addition, the terms "horizontal", "vertical", "overhanging" and the like do not mean that the components are required to be absolutely horizontal or overhanging, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0063] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0064] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0065] Combination Figure 1A high-density substrate stacked package structure 100 provided in an embodiment of the present invention includes a first chip 110, a conductive arc 112, a first plastic package 120 and a first dielectric layer 130. The first chip 110 has a first pad 111. Both ends of the conductive arc 112 are connected to the same first pad 111. The first plastic package 120 covers the first chip 110. A first wiring layer 133 electrically connected to the conductive arc 112 is provided in the first dielectric layer 130. The first dielectric layer 130 covers one side of the first plastic package 120 close to the first pad 111. A first bump 135 electrically connected to the first wiring layer 133 is provided on the surface of the first dielectric layer 130. Since both ends of the conductive arc 112 are provided on the same first pad 111, the conductive arc 112 is arranged in an arch shape. A receiving cavity 101 can be formed between the first pad 111 and the conductive arc 112. In this way, it is helpful to reduce the contact area between the conductive arc 112 and the first pad 111, reduce the shear force on the first pad 111 during grinding, and prevent the chip from having hidden cracks or cracks and electrical failure. At the same time, the bonding force between the plastic package and the chip can be improved, and the structure is more reliable. In addition, the setting of the conductive arc 112 is also helpful to improve the conductivity of the first pad 111.

[0066] Combination Figure 2 and Figure 3 Optionally, since the middle part of the conductive wire arc 112 is suspended, a receiving cavity 101 is formed between the conductive wire arc 112 and the first pad 111. The side of the conductive wire arc 112 away from the first pad 111 is disconnected to form a first opening 113 connected to the receiving cavity 101. In this embodiment, the middle part of the conductive wire arc 112 is disconnected. The disconnected conductive wire arc 112 includes a first end 114 and a second end 115 forming the first opening 113; the first end 114 and the second end 115 are electrically connected to the first wiring layer 133, respectively. It can be understood that the disconnected conductive wire arc 112 is conducive to filling the dielectric layer or metal material into the receiving cavity 101, which is conducive to improving the bonding force.

[0067] It should be noted that, in this embodiment, the first end 114 and the second end 115 are simultaneously connected to the same first wiring layer 133. In some other embodiments, the first end 114 and the second end 115 can serve as two connection ends of the first pad 111, respectively connected to two different wiring structures, which can improve the wiring density and help increase the input and output ports of the first chip 110.

[0068] Optionally, the accommodating cavity 101 is filled with a metal layer 116 , or the accommodating cavity 101 is filled with a first dielectric layer 130 .

[0069] Combination Figure 4, the accommodating cavity 101 is filled with a first dielectric layer 130. The accommodating cavity 101 is kept in a hollow state during the plastic packaging. When the first plastic packaging body 120 is ground until the conductive arc 112 is ground, and the top of the conductive arc 112 is ground off, the accommodating cavity 101 is exposed. Then the first dielectric layer 130 is coated, and the first dielectric layer 130 can be filled into the accommodating cavity 101, thereby improving the filling property of the first dielectric layer 130 and thus improving the bonding force. Afterwards, an opening is formed on the first dielectric layer 130 to form a first wiring layer 133, and the first wiring layer 133 is electrically connected to the first pad 111 of the first chip 110 through the conductive arc 112.

[0070] Combination Figure 5 The accommodating cavity 101 is filled with a metal layer 116. After grinding the first plastic package 120 and breaking the conductive arc 112, a first dielectric layer 130 is coated, and a blocking measure is adopted to prevent the first dielectric layer 130 from filling the accommodating cavity 101. A first graphic layer opening 131 is formed on the first dielectric layer 130 (see Fig.15 ), and the first graphic layer opening 131 is connected to the accommodating cavity 101. When forming the first wiring layer 133, the metal material is filled into the first graphic layer opening 131 of the first dielectric layer 130 and the accommodating cavity 101. That is, the metal layer 116 in the accommodating cavity 101 and the first wiring layer 133 are made of the same material. The conductive arc 112 and the metal layer 116 in the accommodating cavity 101 are used together to electrically connect the first wiring layer 133 and the first pad 111 of the first chip 110. Of course, in some embodiments, the metal material in the accommodating cavity 101 may be different from the material of the first wiring layer 133, that is, by filling in stages, first filling the metal in the accommodating cavity 101 to act as a seed layer, and then forming the first wiring layer 133 to improve the bonding force. No specific limitation is made here.

[0071] Optionally, the filled metal layer 116 may be in a truncated cone or prism shape to improve the reliability of the electrical connection and the bonding strength, making the structure more reliable.

[0072] Combination Figure 6 Optionally, in some embodiments, the conductive arc 112 may not be worn off, and the first wiring layer 133 is connected to the top of the conductive arc 112, and the conductive arc 112 supports the bottom of the first wiring layer 133. The conductive arc 112 can also enhance the bonding force between the first pad 111 and the first wiring layer 133.

[0073] Combination Figure 7Optionally, the conductive arc 112 has multiple crests and / or multiple troughs. It can be understood that it can be one crest and two troughs, or two crests and one trough, or multiple crests and multiple troughs, which are not specifically limited here. In this way, it is beneficial to improve the bonding force between the conductive arc 112 and the first wiring layer 133 and improve the reliability of the electrical connection. In this embodiment, the conductive arc 112 adopts a structure of one trough and two crests, and the first wiring layer 133 is connected at the position of the trough, which is beneficial to improve the reliability of the connection. In addition, such a setting is also beneficial to improve the wiring accuracy when preparing the first wiring layer 133. Since it is necessary to expose and develop on the first dielectric layer 130 when preparing the first wiring layer 133. The conductive arc 112 is designed as a double-arched top or a multi-peak, multi-trough structure, which can play a shielding and protective role during the exposure and development process to prevent light from affecting the transistors on the surface of the first pad 111. Furthermore, the structure of multiple crests and multiple troughs is also beneficial to improving the bonding force, improving the structural strength of the bottom of the first wiring layer 133, and playing a supporting role.

[0074] Optionally, an annular blocking glue 140 is provided on the first chip 110, and the first pad 111 and the conductive wire arc 112 are located in the annular blocking glue 140. That is, the annular blocking glue 140 is provided on the periphery of the first pad 111, and the blocking glue can be cut on the periphery of the first pad 111 to form a blocking wall structure. In this way, the first plastic sealing body 120 can be prevented from entering the area surrounded by the annular blocking glue 140 during plastic sealing. Prevent the first plastic sealing body 120 from entering the accommodating cavity 101. When the first dielectric layer 130 is subsequently coated, the first dielectric layer 130 can be filled in the area within the annular blocking glue 140 and outside the accommodating cavity 101. Of course, the accommodating cavity 101 can be selectively filled with metal or the first dielectric layer 130, which is not specifically limited here.

[0075] It should be noted that, since the dielectric constant of the first dielectric layer 130 is smaller than the dielectric constant of the first plastic package 120, the first dielectric layer 130 is arranged close to the first pad 111 and the conductive arc 112, and the first plastic package 120 is arranged in the area outside the annular stopper 140, which is conducive to reducing transmission loss and improving transmission efficiency.

[0076] Optionally, a removable filling glue 141 is provided in the annular glue stopper 140 (see Fig.17 ). That is, after the annular stop glue 140 is formed, a filling glue 141 is formed in the area within the annular stop glue 140 to fill the area surrounded by the annular stop glue 140. Then, the first plastic sealing body 120 can only be formed in the area outside the annular stop glue 140. After the first plastic sealing body 120 is ground and the conductive wire arc 112 is ground off, the filling glue 141 is removed to form a cavity structure. Then, the first dielectric layer 130 is coated.

[0077] Optionally, a second chip 160 is mounted on the surface of the first dielectric layer 130. The second chip 160 is electrically connected to the first bump 135 on the surface of the first dielectric layer 130. The high-density substrate stacked package structure 100 also includes a second plastic package 161. The second plastic package 161 is used to cover the second chip 160 to protect the second chip 160. The second plastic package 161 is located on a side of the first dielectric layer 130 away from the first plastic package 120.

[0078] Optionally, the high-density substrate stacked package structure 100 further includes a second dielectric layer 170 covering the side of the first plastic package 120 away from the first pad 111. A second wiring layer 173 is provided in the second dielectric layer 170, and a second bump 177 electrically connected to the second wiring layer 173 is provided on the surface of the second dielectric layer 170; the first wiring layer 133 and the second wiring layer 173 are electrically connected through the conductive column 150. The preparation method of the second dielectric layer 170 and the second wiring layer 173 is similar to the preparation method of the first dielectric layer 130 and the first wiring layer 133. The double-sided wiring structure has a higher integration and a more compact structure, which is conducive to achieving high-density integration.

[0079] Combination Figures 8 to 10 Optionally, the high-density substrate stacked package structure 100 further includes a plurality of heat dissipation arcs 180. A heat dissipation pad 117 is provided on the first chip 110, one end of each heat dissipation arc 180 is connected to the heat dissipation pad 117, and the other end is connected to the second dielectric layer 170; a plurality of heat dissipation arcs 180 are arranged on the periphery of the first chip 110. The heat dissipation arc 180 is used to dissipate the heat around the first chip 110 to improve the heat dissipation performance. It should be noted that the heat dissipation pad 117 is not used for electrical connection, but is only used to improve the heat dissipation performance and facilitate the wire bonding operation of the heat dissipation arc 180.

[0080] Optionally, the middle of the heat dissipation arc 180 is disconnected. After disconnection, the heat dissipation arc 180 includes a first arc 181 and a second arc 182; one end of the first arc 181 is connected to the heat dissipation pad 117, and the other end is connected to the first dielectric layer 130; one end of the second arc 182 is connected to the first dielectric layer 130, and the other end is connected to the second dielectric layer 170.

[0081] It is understood that when the conductive arc 112 is ground, the heat dissipation arc 180 is also ground off, so that the heat dissipation arc 180 is divided into two sections, which is beneficial to improving the heat dissipation performance. In addition, the setting of the heat dissipation arc 180 is beneficial to improving the bonding force between the plastic package and the first chip 110.

[0082] Combination Fig.11Optionally, a grounding point 175 is provided in the second dielectric layer 170, and the second arc 182 is electrically connected to the grounding point 175. In this way, it is helpful to lead out and release the electrostatic ions gathered around the first chip 110 and the electrostatic ions gathered in the first dielectric layer 130, so as to avoid interference or damage to the first chip 110 and the first wiring layer 133 caused by static electricity.

[0083] Combination Fig.12 and Fig.13 Optionally, an electrostatic ring 183 may be provided in the first dielectric layer 130. The electrostatic ring 183 may be provided at the disconnection point of the heat dissipation arc 180 to electrically connect the first arc 181 and the second arc 182. In this way, it is also beneficial to lead out and release the static electricity on the first chip 110, the static electricity around the first chip 110, and the static electricity on the first dielectric layer 130, and the static electricity elimination effect is better and more thorough. It is also beneficial to improve the bonding force between the first chip 110 and the first plastic package 120, between the first chip 110 and the first dielectric layer 130, and improve the heat dissipation performance.

[0084] The second bumps 177 are used to form solder balls 190 for electrically connecting the high-density substrate stacked package structure 100 to a circuit board or other modules.

[0085] The high-density substrate stacked package structure 100 is similar to a structure in which the first chip 110 is embedded in the substrate, and the substrate is wired on both sides, one side is used to mount the second chip 160, and the other side is used to plant the ball. The integration of the high-density substrate stacked package structure 100 is greatly improved. When the first plastic package 120 is ground, the shear force on the first pad 111 of the first chip 110 can be reduced, which plays a good role in protecting the first chip 110, and the structure is more reliable, the bonding force is better, and the heat dissipation performance is better.

[0086] Combination Figures 14 to 16 The embodiment of the present invention provides a packaging method for preparing the above-mentioned high-density substrate stacked packaging structure 100. The packaging method is roughly as follows:

[0087] Step S10: Provide a carrier 200 with the first chip 110 mounted thereon. Optionally, the carrier 200 may be made of materials such as glass, silicon oxide or metal. A film layer (not shown) is coated on the carrier 200 for mounting the first chip 110. The film layer is made of thermoplastic material, including any one or more polymer composite materials such as epoxy resin, polyimide and benzocyclobutene. The film layer can play a separating role by irradiating ultraviolet light or heating. When mounting the first chip 110, the first pad 111 faces upward, that is, the side of the first chip 110 away from the first pad 111 is in contact with the film layer.

[0088] Step S20: forming a conductive arc 112 on the first pad 111 of the first chip 110. The conductive arc 112 is formed by wire bonding. The conductive arc 112 is arched.

[0089] Conductive pillars 150 are formed on the carrier 200. Metal wires roughly perpendicular to the carrier 200, namely the conductive pillars 150, are formed by wire bonding. Since the wire bonding operation needs to be performed on a metal surface. If the carrier 200 is made of metal material, the conductive pillars 150 can be formed by wire bonding directly on the carrier 200. If the carrier 200 is made of non-metallic material, it is necessary to first form a metal base layer on the carrier 200 and then perform wire bonding. The metal base layer can cover the entire carrier 200, or it can only cover the places where wire bonding is required to form the conductive pillars 150. It should be understood that the film layer should have avoidance holes in the places where the conductive pillars 150 need to be formed to expose the metal carrier 200 or the metal base layer on the carrier 200, so as to form the conductive pillars 150 by wire bonding.

[0090] Step S30: forming an annular blocking glue 140 on the first chip 110. The first pad 111 and the conductive arc 112 are located in the annular blocking glue 140. Optionally, a circle of glue is applied on the periphery of the first pad 111 of the first chip 110, and the fence structure is formed after being baked and cured.

[0091] Step S40: Plastic encapsulate the first chip 110 to form a first plastic encapsulation body 120. Optionally, the first plastic encapsulation body 120 is formed by injection molding or printing a liquid plastic encapsulation material and then baking it. The material of the first plastic encapsulation body 120 includes but is not limited to polymer composite materials such as epoxy resin and silicon dioxide. The annular retaining glue 140 is used to prevent the plastic encapsulation fluid from entering the first pad 111, that is, the first plastic encapsulation body 120 is located outside the space surrounded by the annular retaining glue 140, so that a cavity structure is formed in the annular retaining glue 140.

[0092] Step S50: Grind the first plastic package 120 until the conductive arc 112 is exposed. Optionally, a diamond needle is used to grind the surface of the first plastic package 120. The grinding mesh is 2000 to 4000 meshes and the grinding speed is 1000 r / m to 6000 r / m, so that the conductive arc 112 is exposed from the first plastic package 120. Optionally, the first plastic package 120 and the conductive arc 112 can be further ground until the conductive arc 112 is broken, and a first opening 113 is formed at the arched top of the conductive arc 112 away from the first pad 111.

[0093] During the grinding process, the conductive arc 112 is in the cavity structure, so the grinding efficiency is higher. The contact area between the first pad 111 and the conductive arc 112 is smaller, the shear force on the first pad 111 is smaller, and the damage to the first chip 110 is smaller, which is conducive to preventing cracks or hidden cracks in the first chip 110.

[0094] Step S60: A first dielectric layer 130 having a first wiring layer 133 is formed on one side of the first plastic package 120 close to the first pad 111. The first wiring layer 133 is electrically connected to the conductive arc 112 and the conductive column 150, respectively. Optionally, the first dielectric layer 130 may be formed by a spin coating process, and the material of the first dielectric layer 130 includes but is not limited to silicon nitride, silicon oxynitride, polyimide or benzocyclobutene. It is understood that, according to actual conditions, the first dielectric layer 130 may be filled in the accommodating cavity 101 formed by the conductive arc 112 and the first pad 111, or may not be filled in the accommodating cavity 101.

[0095] A photomask is used to cover the first dielectric layer 130, and an exposure and development process is used to form a first pattern layer opening 131 on the first dielectric layer 130. A first wiring layer 133 is formed by electroplating metal in the first pattern layer opening 131 using an electroplating process.

[0096] Optionally, a third dielectric layer 220 is spin-coated on the first dielectric layer 130, and the third dielectric layer 220 covers the first wiring layer 133. A first groove 221 exposing the first wiring layer 133 is formed on the third dielectric layer 220 by a dry etching process. A first bump 135 is formed by electroplating metal in the first groove 221 by an electroplating process. The material of the first bump 135 can be at least one of titanium TI, titanium tungsten TIWU and nickel NI. In this way, the weldability of the first bump 135 can be improved. The first bump 135 is used as a pad.

[0097] Step S70: Mount the second chip 160 on the third dielectric layer 220. The second chip 160 is a flip chip, and the second chip 160 and the first bump 135 are welded to achieve electrical connection. Optionally, when mounting the second chip 160, a TCB hot pressing process can be used to apply a certain pressure at a higher temperature (for example, about 200°C to about 300°C). Through the TCB hot pressing process, a filler is used to weld and fill between the bottom of the flip chip and the first bump 135, and the filler includes but is not limited to at least one of a non-conductive film (NCF) and a non-conductive paste (NCP). By using such a filler, the flow of solder between the flip chip and the pad can be reduced or minimized, thereby reducing or preventing defects such as short circuits, solder deformation, and non-wetting.

[0098] The second chip 160 is plastic-encapsulated, and a second plastic encapsulation body 161 is formed on the third dielectric layer 220. The material and the forming process of the second plastic encapsulation body 161 are similar to those of the first plastic encapsulation body 120, and are not described in detail here.

[0099] Step S80: UV light is irradiated on the side of the carrier 200 away from the first chip 110 to debond the film layer and the carrier 200 and remove the carrier 200. It can be understood that after removing the carrier 200, the conductive pillars 150 are exposed from the surface of the first plastic package 120.

[0100] Step S90: Spin-coat the second dielectric layer 170 on the side of the first plastic package 120 after the carrier 200 is removed. Use a photomask to cover the second dielectric layer 170, and use an exposure and development process to form a second graphic layer opening 171 on the second dielectric layer 170. Among them, the end of the conductive column 150 is exposed from the second graphic layer opening 171. Use an electroplating process to electroplate metal in the second graphic layer opening 171 to form a second wiring layer 173. In this way, the electrical connection between the first wiring layer 133 and the second wiring layer 173 is achieved through the conductive column 150.

[0101] The fourth dielectric layer 230 is spin-coated on the second dielectric layer 170, and the fourth dielectric layer 230 covers the second wiring layer 173. A mask is set above the fourth dielectric layer 230, and the fourth dielectric layer 230 is chemically changed by exposure and development technology, and the exposed area is removed by developer, thereby forming a second groove 231 exposing the second wiring layer 173. The metal material is electroplated in the second groove 231 again by electroplating to form a second bump 177. Formic acid is reflowed again to form a solder ball 190. The electroplated metal material includes first electroplating to form a copper column, and then electroplating at least one of titanium TI, titanium tungsten TIWU, nickel NI and tin silver SnAg on the surface of the copper column. Formic acid is used as a reducing agent to remove the oxide on the surface of the copper column by high temperature and chemical reaction, thereby promoting the bonding force between the copper column and the solder.

[0102] Step S100: finally cutting and separating to form single products.

[0103] Combination Fig.17 Optionally, after step S30, it also includes forming a filling glue 141 in the annular retaining glue 140. The filling glue 141 is used to fill the annular space surrounded by the annular retaining glue 140. This can further prevent subsequent plastic packaging materials from entering the annular space. After the step of grinding the first plastic packaging body 120 in step S50 until the conductive arc 112 is exposed, the filling glue 141 is removed. The cavity structure is regained. The cavity structure includes a accommodating cavity 101 on the inner side of the conductive arc 112 and a cavity structure between the outer side of the conductive arc 112 and the annular retaining glue 140. Among them, the cavity structure between the outer side of the conductive arc 112 and the annular retaining glue 140 is subsequently filled with the first dielectric layer 130. The accommodating cavity 101 on the inner side of the conductive arc 112 is filled with the first dielectric layer 130 or filled with metal according to actual needs. This arrangement can reduce transmission loss and improve transmission efficiency.

[0104] Optionally, the filling glue 141 is photoresist. The conductive arc 112 can be protected during the grinding process. After grinding, the first dielectric layer 130 is coated and can be removed during the exposure and development process to form a cavity structure. The process steps are simple and the process efficiency can be improved.

[0105] Combination Fig.18 Optionally, the first chip 110 is further provided with a heat dissipation pad 117. In this embodiment, the heat dissipation pad 117 serves to dissipate heat, does not serve as an electrical connection port, and has nothing to do with the functional electrical connection end of the first chip 110. Before step S40 of plastic-sealing the first chip 110 to form the first plastic package body 120, it also includes: bonding wires between the carrier 200 and the heat dissipation pad 117 to form a heat dissipation wire arc 180. The heat dissipation wire arc 180 can improve the heat dissipation performance of the first chip 110. The heat dissipation pad 117 serves as a wire bonding metal interface for the heat dissipation wire arc 180, which facilitates the wire bonding operation.

[0106] In the step of grinding the first plastic package 120 until the conductive arc 112 is broken, the heat dissipation arc 180 is simultaneously ground off. After the arched top of the heat dissipation arc 180 is ground off, the top of the heat dissipation arc and the top of the conductive arc 112 are located in the same plane. This arrangement is conducive to improving the heat dissipation performance, and enhancing the bonding force between the first plastic package 120 and the first dielectric layer 130, and also conducive to enhancing the bonding force between the first plastic package 120 and the first chip 110, and the structure is more reliable.

[0107] In this embodiment, the conductive pillar 150 is formed by making vertical lines on the carrier 200, so as to realize the electrical connection between the first wiring layer 133 and the second wiring layer 173. This method replaces the method of forming metal pillars by electroplating metal in the holes after laser opening or etching in the traditional packaging process, and solves the problem of voids in the metal pillar filling in the traditional process. Especially in the field of high-speed and high-frequency signals, the high-density substrate stacked packaging structure 100 provided by this embodiment has obvious advantages in signal transmission efficiency and effectively improves structural reliability.

[0108] The setting of the conductive arc 112 is conducive to improving the conductivity of the first pad 111, thereby increasing the signal transmission current and voltage and improving the signal transmission capacity. When performing the wiring process, it is conducive to improving the bonding force between the first wiring layer 133 and the first pad 111. Since the first opening 113 is formed at the arched top of the conductive arc 112 after grinding, the size of the first opening 113 is easy to control, thereby improving the wiring accuracy. In addition, the conductive arc 112 after grinding can prevent the surrounding first dielectric layer 130 from being affected by the diffraction or reflection of light, improve the accuracy of the first graphic layer opening 131 in the exposure and development process, prevent problems such as the opening being too large, and thus improve the wiring accuracy.

[0109] The design of the annular stop glue 140 structure can prevent the first plastic package 120 from entering the first pad 111. The first dielectric layer 130 is filled between the conductive arc 112 and the annular stop glue 140, and the conductive arc 112 is conducive to improving the bonding force between the first dielectric layer 130 and the first chip 110, and the structure is more reliable.

[0110] In summary, the high-density substrate stacked package structure 100 and the packaging method provided by the embodiment of the present invention have the following beneficial effects, including:

[0111] The high-density substrate stacked packaging structure 100 and packaging method provided by the embodiment of the present invention form a conductive arc 112 on the first pad 111, thereby reducing the contact area between the conductive arc 112 and the first pad 111 during grinding, reducing the shear force on the first pad 111 during grinding, and preventing the chip from having hidden cracks or cracks and electrical failure. At the same time, the bonding force between the plastic package and the chip can be improved, and the structure is more reliable.

[0112] Secondly, it is helpful to improve the bonding force between the dielectric layer and the metal layer 116, and it is helpful to improve the structural reliability and heat dissipation performance. The design of the first wiring layer 133 and the second wiring layer 173 is helpful to improve the integration. In addition, by setting the disconnected heat dissipation arc 180, the heat dissipation arc 180 is connected to the grounding point 175 of the second wiring layer 173, which can guide the discharge of static electricity and improve the heat dissipation performance and bonding force.

[0113] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some or all of the technical features therein. Any modifications, equivalent replacements, improvements, etc. made should be included in the protection scope of the present invention.

Claims

1. A high-density substrate stacked packaging structure, characterized in that: include: A first chip, wherein the first chip has a first pad; A conductive arc, two ends of which are connected to the same first pad; a first plastic package, wherein the first plastic package covers the first chip; a first dielectric layer, wherein a first wiring layer electrically connected to the conductive arc is provided in the first dielectric layer; The first dielectric layer covers a side of the first plastic package body close to the first pad; A first bump electrically connected to the first wiring layer is provided on the surface of the first dielectric layer; An accommodating cavity is formed between the conductive arc and the first pad; The conductive arc is disconnected at one side away from the chip to form a first opening connected to the accommodating cavity; the conductive arc includes a first end and a second end forming the first opening; the first end and the second end are electrically connected to the first wiring layer respectively.

2. The high-density substrate stacked package structure according to claim 1, characterized in that: The conductive line arc has a plurality of crests and / or a plurality of troughs.

3. The high-density substrate stacked packaging structure according to claim 1, characterized in that: The accommodating cavity is filled with a metal layer, or the accommodating cavity is filled with a first dielectric layer.

4. The high-density substrate stacked packaging structure according to claim 1, characterized in that: An annular blocking glue is arranged on the chip, and the first pad and the conductive wire arc are located in the annular blocking glue.

5. The high-density substrate stacked packaging structure according to claim 4, characterized in that: The annular rubber stopper is provided with removable filling rubber.

6. The high-density substrate stacked packaging structure according to any one of claims 1 to 5, characterized in that: It also includes a second dielectric layer covering the side of the first plastic package away from the first pad; a second wiring layer is arranged in the second dielectric layer, and a second bump electrically connected to the second wiring layer is arranged on the surface of the second dielectric layer; the first wiring layer and the second wiring layer are electrically connected through a conductive column.

7. The high-density substrate stacked package structure according to claim 6, characterized in that: It also includes multiple heat dissipation line arcs, a heat dissipation pad is provided on the first chip, one end of each heat dissipation line arc is connected to the heat dissipation pad, and the other end is connected to the second dielectric layer; multiple heat dissipation line arcs are arranged on the periphery of the first chip; and each heat dissipation line arc is disconnected in the middle.

8. The high-density substrate stacked package structure according to claim 7, characterized in that: The middle part of the heat dissipation arc is disconnected to form a first arc and a second arc; one end of the first arc is connected to the heat dissipation pad, and the other end is connected to the first dielectric layer; one end of the second arc is connected to the first dielectric layer, and the other end is connected to the second dielectric layer; A grounding point is provided in the second dielectric layer, and the second wire arc is electrically connected to the grounding point.

9. A packaging method, characterized in that: Used to prepare a high-density substrate stacked packaging structure as described in any one of claims 1-8.

10. The packaging method according to claim 9, characterized in that: include: Providing a carrier with a first chip mounted thereon; forming a conductive arc on a first pad of the first chip; forming a conductive column on the carrier; Plastic-sealing the first chip to form a first plastic-sealed body; Grinding the first plastic package body until the conductive arc is exposed; A first dielectric layer having a first wiring layer is formed on one side of the first plastic package body close to the first pad; the first wiring layer is electrically connected to the conductive arc and the conductive column respectively.

11. The packaging method according to claim 10, characterized in that: After the step of forming a conductive arc on the first pad of the first chip, the method further includes: An annular blocking glue is formed on the first chip; the first pad and the conductive wire arc are located in the annular blocking glue.

12. The packaging method according to claim 11, characterized in that: After the step of forming a ring-shaped blocking glue on the first chip, the method further includes: Forming a filling glue in the annular glue stopper; After the step of grinding the first plastic package body until the conductive arc is exposed, the filling glue is removed.

13. The packaging method according to claim 10, characterized in that: In the step of grinding the first plastic package body until the conductive arc is exposed: The first plastic package body is ground until the conductive arc is broken, and a first opening is formed on a side of the conductive arc away from the first pad.

14. The packaging method according to claim 13, characterized in that: The first chip is provided with a heat dissipation pad; before the step of plastic-sealing the first chip to form a first plastic-sealed body, the method further includes: Bonding a wire between the carrier and the heat dissipation pad to form a heat dissipation wire arc; In the step of grinding the first plastic package body until the conductive wire arc is broken: the heat dissipation wire arc is also broken by grinding at the same time.

Images