Surface mount technology package and surface mount technology substrate

Abstract

The present disclosure relates to a surface mount technology (SMT) package and an SMT substrate, the SMT package including: an SMT substrate including an interconnection layer, an insulating layer having an arrangement area for the interconnection layer, and a mask layer on an upper surface of the insulating layer; a member including an insulator and an external electrode having at least a portion on a surface of the insulator opposite to the SMT substrate; and solder electrically connecting the interconnect layer and the external electrode to each other. The mask layer has an opening, and the SMT substrate further includes an insulating support supporting the external electrode in the opening such that the external electrode is spaced apart from the interconnect layer and the insulating layer.

Description

Technical Field

[0001] The present disclosure relates to surface mount technology (SMT) packages and SMT substrates included therein. Background Art

[0002] Typically, components can be mounted on a printed circuit board according to SMT, and the printed circuit board can transmit inductance formed by the components or inductance-based phenomena (e.g., resonance, passive filtering, or antistatic) to a semiconductor chip or an electronic device printed circuit board (e.g., a motherboard and a mainboard).

[0003] Recently, the size of printed circuit boards and components has been reduced. Therefore, there is an increasing difficulty in ensuring the reliability of packages in which printed circuit boards and components are integrated according to SMT. Summary of the invention

[0004] The inventive concept provides a surface mount technology (SMT) package having improved reliability, and an SMT substrate included therein.

[0005] According to some aspects of the present inventive concept, there is provided an SMT package, comprising: an SMT substrate, the SMT substrate comprising an interconnection layer, an insulating layer having a layout area for the interconnection layer, and a mask layer on an upper surface of the insulating layer; a component comprising an insulator and an external electrode, the external electrode having at least a portion on a surface of the insulator opposite to the SMT substrate; and a solder electrically connecting the interconnection layer and the external electrode to each other. The mask layer may have an opening. The SMT substrate may further include an insulating support member that supports the external electrode in the opening so that the external electrode is spaced apart from the interconnection layer and the insulating layer.

[0006] According to some aspects of the present invention, there is provided an SMT substrate, comprising: an interconnection layer having first and second pad areas; an insulating layer having a layout area for the interconnection layer; a mask layer on an upper surface of the insulating layer and having an opening; a first insulating support member, in the opening so that a portion thereof overlaps with the first pad area; and a second insulating support member, in the opening so that a portion thereof overlaps with the second pad area.

[0007] According to some aspects of the present inventive concept, there is provided an SMT substrate, comprising: an insulating layer; an interconnection layer embedded in the insulating layer; a mask layer on the upper surface of the insulating layer and having an opening; and first, second, third and fourth insulating supports directly contacting the interconnection layer, respectively, the first, second, third and fourth insulating supports protruding from the mask layer toward the opening, respectively. The first, second, third and fourth insulating supports may be spaced apart from each other in the opening and may be arranged two-dimensionally. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features and advantages of the present invention will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0009] Figures 1A to 1F is a cross-sectional view showing an SMT package according to an example embodiment of the inventive concept and an SMT substrate included therein;

[0010] FIG. 2A to FIG. 2C is a plan view showing an arrangement of interconnection layers and insulating layers in an SMT package and an SMT substrate included therein according to an example embodiment of the inventive concept;

[0011] Figure 2D to Figure 2G is a plan view showing an arrangement of a mask layer and an insulating supporter in an SMT package and an SMT substrate included therein according to an example embodiment of the inventive concept;

[0012] FIG. 3A to FIG. 3E is a cross-sectional view illustrating a method of manufacturing an SMT package and an SMT substrate included therein according to an example embodiment of the inventive concept;

[0013] FIG. 4A to FIG. 4D is an enlarged cross-sectional view showing an SMT package according to an example embodiment of the inventive concept and an insulating support member of an SMT substrate included therein and surrounding structures thereof;

[0014] FIG. 5A to FIG. 5C is a cross-sectional view showing an SMT package according to an example embodiment of the inventive concept and an SMT substrate included therein; and

[0015] FIG. 6A to FIG. 6C is a perspective view illustrating components that may be included in an SMT package according to example embodiments of the inventive concepts. DETAILED DESCRIPTION

[0016] The detailed description of the inventive concept refers to the accompanying drawings, which illustrate by way of example specific embodiments in which the inventive concept can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the inventive concept. It should be understood that the various embodiments of the inventive concept may be different from each other, but are not necessarily mutually exclusive. For example, without departing from the spirit and scope of the inventive concept, various aspects of the example embodiments with specific shapes, structures and characteristics described herein may be implemented in another embodiment. In addition, it should be understood that the position or arrangement of each component within each disclosed embodiment may be changed without departing from the spirit and scope of the inventive concept. Therefore, the detailed description set forth below is not intended to be considered as having a limiting meaning, and the scope of the inventive concept is limited only by the appended claims and all equivalents claimed by those claims. The same reference numerals in the drawings indicate the same or similar functions in various examples of the embodiments.

[0017] Hereinafter, some examples of embodiments of the inventive concept will be described in detail with reference to the accompanying drawings so that those skilled in the art can practice the inventive concept.

[0018] Reference Figures 1A to 2G , SMT packages PKG1, PKG2, PKG3, PKG4, PKG5, PKG6, PKG7, and PKG8 according to some example embodiments of the inventive concepts may include SMT substrates 100a and 100b, components 200a and 200b, and solders 180a, 180b, 180c, and 180d.

[0019] The SMT substrates 100a and 100b may include an interconnection layer 120, an insulating layer 110, a mask layer 140, and insulating support members 145a, 145b, 145c, 145d, 145e, and / or 145f. The SMT substrate 100a may be an embedded trace substrate (ETS), and the SMT substrate 100b may be a protruding trace substrate (PTS), but the present disclosure is not limited thereto.

[0020] The interconnection layer 120 may include at least one of a plurality of interconnection layers 120a and 120b, and the plurality of interconnection layers 120a and 120b may be on the upper and lower portions of the insulating layer 110, respectively. The SMT substrate 100a may have a structure in which the interconnection layer 120a is embedded in the insulating layer 110, and the SMT substrate 100b may have a structure in which the interconnection layer 120a is on the upper surface of the insulating layer 110 and / or protrudes from the upper surface of the insulating layer 110. The insulating layer 110 may provide or have a layout area for the interconnection layer 120a. The interconnection layer 120 may include copper (Cu) or a copper alloy, but the present disclosure is not limited thereto. For example, the interconnection layer 120 may include aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof.

[0021] The insulating layer 110 may include a prepreg, but the present disclosure is not limited thereto. For example, the insulating layer 110 may include at least one of a photosensitive insulating material such as a photoimageable dielectric (PID) resin, a laminated film such as an Ajinomoto laminated film (ABF), a thermosetting resin such as an epoxy resin, or a thermoplastic resin such as a polyimide, a resin mixed with an inorganic filler, a flame retardant (FR-4), and bismaleimide triazine (BT).

[0022] For example, the interconnect layer 120 may have at least one of a pad region 120P and a ground region 120G. The pad region 120P may be connected to the interconnect of the interconnect layer 120, and the interconnect may extend in a horizontal direction (X direction and / or Y direction) and / or a vertical direction (Z direction). Therefore, the interconnect layer 120 may provide an electrical connection path for components 200a and 200b and solders 180a, 180b, 180c, and 180d electrically connected to the upper surface of the pad region 120P. The ground region 120G may surround the pad region 120P and may be spaced apart from the pad region 120P. The ground region 120G may shield external electromagnetic noise from the interconnect, serve as a heat dissipation path to the outside of the SMT substrates 100a and 100b, and improve the impedance stability of the interconnect.

[0023] The mask layer 140 may include at least one of a plurality of mask layers 140a and 140b, and the plurality of mask layers 140a and 140b may cover the upper surface and the lower surface of the insulating layer 110, respectively. The insulating material included in the mask layer 140 may be different from the insulating material included in the insulating layer 110. The mask layer 140 may include, but is not limited to, a material that may be included in a solder resist layer of a printed circuit board. For example, the mask layer 140 may include a material that may be included in a dry film resist, a photosensitive insulating material such as a PID resin, a laminated film such as ABF, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, a resin mixed with an inorganic filler, at least one of FR-4 and BT.

[0024] The mask layer 140 may include openings OP1, OP2, OP3, OP4, OP5, and OP6, and the size and shape of each of the openings OP1, OP2, OP3, OP4, OP5, and OP6 may be determined using surface mounting technology (SMT), but the present disclosure is not limited thereto. For example, the size and shape of each of the openings OP1, OP2, OP3, OP4, OP5, and OP6 may be determined based on the size and shape of each of the components 200a and 200b. Compared to a plurality of openings of a general ball grid array (BGA) substrate, the openings OP1, OP2, OP3, OP4, OP5, and OP6 may have a larger size and may have a shape closer to a polygonal shape (e.g., a rectangular shape).

[0025] The members 200 a and 200 b may overlap the openings OP1 , OP2 , OP3 , OP4 , OP5 , and OP6 in the Z direction, and may include an insulator 210 and an external electrode 230 .

[0026] The insulator 210 may form an impedance (e.g., capacitance, inductance, or resistance) or an impedance-based phenomenon (e.g., resonance, passive filtering, antistatic). For example, when the insulator 210 forms a capacitor, the insulator 210 may include a plurality of dielectric layers including a ferroelectric such as barium titanate (BaTiO3), and may include a plurality of internal electrodes between the plurality of dielectric layers. The plurality of internal electrodes may also be connected to the external electrode 230 to transmit the capacitance to the outside of the components 200a and 200b. For example, when the insulator 210 forms an inductance, the insulator 210 may include not only an insulating material but also magnetic powder particles (e.g., metal powder particles or ferrite powder particles) for increasing magnetic permeability, and may include a coil connected to the external electrode 230. For example, when the insulator 210 forms an impedance-based phenomenon, the insulator 210 may be a composite component having both a structure for forming capacitance and a structure for forming impedance.

[0027] At least a portion of the external electrode 230 may be on a surface (e.g., a lower surface) of the insulator 210 opposite to the SMT substrates 100a and 100b. The external electrode 230 may be on a surface of the insulator 210, and may transmit impedance or impedance-based phenomena formed by the insulator 210 to the SMT substrates 100a and 100b. To this end, the external electrode 230 may be electrically connected to the interconnection layer 120 via solders 180a, 180b, 180c, and 180d.

[0028] The external electrode 230 of the component 200a may include a first external electrode 231, a second external electrode 232, and a third external electrode 233 spaced apart from each other, and the external electrode 230 of the component 200b may include a first external electrode 231 and a second external electrode 232 spaced apart from each other. For example, the external electrode 230 may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof, and may include a resin containing a plurality of metal particles.

[0029] The solders 180a, 180b, 180c, and 180d may electrically connect the interconnection layer 120 and the external electrode 230 to each other. The first solder 181, the second solder 182, and the third solder 183 of the solders 180a, 180b, 180c, and 180d may be connected to the first external electrode 231, the second external electrode 232, and the third external electrode 233, respectively. For example, the solders 180a, 180b, 180c, and 180d may contain lead (Pb), tin (Sn), or an alloy (Sn-Ag-Cu) containing tin (Sn), and thus may have a melting point lower than that of the interconnection layer 120. At a temperature higher than the melting point, the solders 180a, 180b, 180c, and 180d may be flexibly connected between the upper surface of the interconnection layer 120a and the external electrode 230 by a reflow process or a thermocompression bonding (TCB) process in a flowable state. Thereafter, the temperature may be lowered, and the solders 180a, 180b, 180c, and 180d may adhere in a state of being connected to the upper surface of the interconnection layer 120a and the external electrode 230. Thus, the components 200a and 200b may be mounted on the SMT substrates 100a and 100b.

[0030] The sizes of the SMT substrates 100a and 100b and the components 200a and 200b can be gradually reduced. Therefore, the thickness of the external electrode 230 can be gradually reduced, and the upper surface of the interconnection layer 120a can be gradually moved downward. For example, when the interconnection layer 120a is embedded in the insulating layer 110, the upper surface of the interconnection layer 120a can be moved downward. The application frequency of this ETS structure can be gradually increased as the sizes of the SMT substrates 100a and 100b are reduced.

[0031] As the size of the SMT substrates 100a and 100b and / or the components 200a and 200b is reduced, the SMT substrates 100a and 100b and / or the components 200a and 200b may have improved performance relative to their size. However, the distance Z1 between the SMT substrates 100a and 100b and the insulator 210 of the components 200a and 200b may be reduced. As the distance Z1 is reduced, the difficulty level of ensuring the reliability between the SMT substrates 100a and 100b and the components 200a and 200b may increase. For example, as the distance Z1 is reduced, due to the cleaning after the reflow process, it may be difficult to ensure the reliability of removing foreign matter between the SMT substrates 100a and 100b and the components 200a and 200b. For example, as the distance Z1 is reduced, it may be difficult to ensure the reliability of filling a sealant such as epoxy molding compound (EMC) between the SMT substrates 100a and 100b and the components 200a and 200b (e.g., the performance of inhibiting the formation of gaps). For example, as the distance Z1 decreases, it may be difficult to ensure reliability in preventing an electrical short from occurring in the solders 180 a , 180 b , 180 c , and 180 d .

[0032] The insulating support members 145a, 145b, 145c, 145d, 145e, and 145f can support the external electrode 230 in the openings OP1, OP2, OP3, OP4, OP5, and OP6 so that the external electrode 230 is spaced apart from the interconnection layer 120 and the insulating layer 110. Therefore, even when the size of the SMT substrates 100a and 100b and / or the components 200a and 200b is reduced, the distance Z1 between the SMT substrates 100a and 100b and the insulator 210 of the components 200a and 200b can be effectively increased. In addition, the solders 180a, 180b, 180c, and 180d can be formed more stably.

[0033] The insulating supports 145a, 145b, 145c, 145d, 145e and 145f may include a first insulating support (e.g., the left side of 145a, 145b, 145c, 145d, 145e and 145f) and a second insulating support (e.g., the right side of 145a, 145b, 145c, 145d, 145e and 145f), and may be spaced apart from one opening OP1, OP2, OP3, OP4, OP5 or OP6 with the center portion of the opening OP1, OP2, OP3, OP4, OP5, OP6 inserted therebetween. A portion of the first insulating support member (e.g., the left side of 145a, 145b, 145c, 145d, 145e, and 145f) may overlap with the first pad area (e.g., the left side of 120P), and a portion of the second insulating support member (e.g., the right side of 145a, 145b, 145c, 145d, 145e, and 145f) may overlap with the second pad area (e.g., the right side of 120P).

[0034] Therefore, the insulating support members 145a, 145b, 145c, 145d, 145e, and 145f can more effectively support the external electrodes 230 of the components 200a and 200b with reduced sizes, and the distance between the SMT substrates 100a and 100b and the insulator 210 of the components 200a and 200b can be more effectively increased. In addition, even when the insulating support members 145a, 145b, 145c, 145d, 145e, and 145f have a relatively small size in the horizontal direction, a relatively large overlapping area in the Z direction between the insulating support members 145a, 145b, 145c, 145d, 145e, and 145f and the external electrodes 230 can be ensured, and the electrical connection path between the external electrodes 230 and the interconnection layer 120a can also be more stably ensured.

[0035] For example, the external electrode 230 may include a first external electrode 231 having at least a portion on a portion (e.g., a left region) of a surface (e.g., a lower surface) of the insulator 210 opposite to the SMT substrates 100a and 100b, and a second external electrode 232 having at least a portion on another region (e.g., a right region) of a surface (e.g., a lower surface) of the insulator 210 opposite to the SMT substrates 100a and 100b. The first insulating support (the left side of 145a, 145b, 145c, 145d, 145e, and 145f) may support the first external electrode 231 in the openings OP1, OP2, OP3, OP4, OP5, and OP6, and the second insulating support (the right side of 145a, 145b, 145c, 145d, 145e, and 145f) may support the second external electrode 232 in the openings OP1, OP2, OP3, OP4, OP5, and OP6.

[0036] For example, a portion of the insulating support members 145a, 145b, 145c, 145d, 145e, and 145f may be on the upper surface of the insulating layer 110, and another portion of the insulating support members 145a, 145b, 145c, 145d, 145e, and 145f may be on the upper surface of the interconnection layer 120a. Therefore, the insulating support members 145a, 145b, 145c, 145d, 145e, and 145f may support the external electrode 230 more stably.

[0037] Reference Figures 1A to 1D , the upper surface of the interconnection layer 120a may be in direct contact with the solder 180a, 180b, 180c, and 180d, and the interconnection layer 120a may be embedded in the insulating layer 110. Here, the average distance (Z2+Z3) between the lower surface of the external electrode 230 and the upper surface of the interconnection layer 120a may be greater than the average thickness (Z2) of the mask layer. This structure may also be a structure in which the insulating support members 145a, 145b, and 145c support the external electrode 230.

[0038] The insulating support members 145a, 145b, and 145c may include the same insulating material as the insulating material included in the mask layer 140. According to the description, the insulating support members 145a, 145b, and 145c may be considered to be included in the mask layer 140. For example, when the opening of the mask layer 140 is formed, the insulating support members 145a, 145b, and 145c may be formed together. When the insulating support members 145a, 145b, and 145c and the mask layer 140 are in direct contact with each other, the interface between the insulating support members 145a, 145b, and 145c and the mask layer 140 may not be observed.

[0039] The distance (Z2+Z3) between the lower surface of the external electrode 230 and the upper surface of the interconnection layer 120a may be greater than the thickness (Z2) of the mask layer, so that the upper surface of the interconnection layer 120a may be located at a level lower than the level of the upper surface of the insulating layer 110. The reference direction for measuring the height (level) may be the direction (Z direction) in which the SMT substrates 100a and 100b and the components 200a and 200b are relative to each other. When the insulating support members 145a, 145b, and 145c are in direct contact with the mask layer 140, a portion 146 of the insulating support members 145a, 145b, and 145c may be located at a level higher than the level of the upper surface of the insulating layer 110, and another portion 147 of the insulating support members 145a, 145b, and 145c may be located at a level lower than the level of the upper surface of the insulating layer 110. Therefore, the insulating support members 145a, 145b, and 145c may support the external electrode 230 more stably. For example, Z2 may be 10 μm or more and 30 μm or less, and Z3 may be greater than 0 μm and 5 μm or less, but the present disclosure is not limited thereto.

[0040] Reference Figure 1E and Figure 1F , the interconnection layer 120a may be on the upper surface of the insulating layer 110, and the insulating supports 145d and 145e may protrude upward toward the external electrode 230. A portion 146 of the insulating supports 145d and 145e may overlap the insulating layer 110 in the Z direction, another portion 147 of the insulating supports 145d and 145e may overlap the interconnection layer 120a in the Z direction, and an upper protrusion 148 of the insulating supports 145d and 145e may be located at a level higher than that of the upper surface of the mask layer 140. Therefore, the upper surface of the first insulating support (the left side of 145d and 145e) may be located at a level higher than that of the upper surface of the mask layer 140, and the upper surface of the second insulating support (the right side of 145d and 145e) may be located at a level higher than that of the upper surface of the mask layer 140.

[0041] According to the design, the insulating support members 145d and 145e may include an insulating material different from the insulating material included in the mask layer 140. For example, the insulating support members 145d and 145e may include an insulating material that may be included in the insulating layer 110, and may include an insulating material having a stiffness greater than that of the mask layer 140. The insulating materials having different stiffness (or Young's modulus) may be types of different insulating materials. For example, a portion 146 and another portion 147 of the insulating support members 145d and 145e may include the same insulating material as the insulating material included in the mask layer 140, and an upper protrusion 148 of the insulating support members 145d and 145e may include an insulating material different from the insulating material included in the mask layer 140.

[0042] Reference Figure 2B , Figure 2F and Figure 2G , the SMT packages PKG3 and PKG4 according to some example embodiments of the inventive concept may include first insulating supports (eg, Figure 2F and Figure 2G 146 in the upper left side), a second insulating support member (eg, Figure 2F and Figure 2G 146 in the upper right side), a third insulating support member (eg, Figure 2F and Figure 2G 146 in the lower left side) and the fourth insulating support member (eg, Figure 2F and Figure 2G The lower right side of 146 in FIG. 146) and the central parts of the openings OP5 and OP6 are interposed therebetween. Figure 1C and Figure 1D , the first insulating support member and the third insulating support member (e.g., the left side of 145b and 145c) can support the first external electrode 231, and the second insulating support member and the fourth insulating support member (e.g., the right side of 145b and 145c) can support the second external electrode 232.

[0043] A portion of the first insulating support member (eg, Figure 2F and Figure 2G The upper left side of 146 in FIG. 140A ) may overlap with the first pad region (eg, the left side of 120P), and another portion of the first insulating support member (eg, Figure 2F and Figure 2G The upper left side of 146 in the figure) may overlap with the insulating layer 110. A portion of the second insulating support member (eg, Figure 2F and Figure 2G The upper right side of 146 in the figure) may overlap with the second pad region (eg, the right side of 120P), and another portion of the second insulating support member (eg, Figure 2F and Figure 2G The portion of the third insulating support member (eg, the upper right side of 146 in FIG. 147 ) may overlap with the insulating layer 110. Figure 2F and Figure 2G The lower left side of 146 in the figure) may overlap with the first pad region (eg, the left side of 120P), and another portion of the third insulating support member (eg, Figure 2F and Figure 2G The lower left side of 146 in the figure) may overlap with the insulating layer 110. A portion of the fourth insulating support member (eg, Figure 2F and Figure 2G The lower right side of 146 in the figure) may overlap with the second pad region (eg, the right side of 120P), and another portion of the fourth insulating support member (eg, Figure 2F and Figure 2G The lower right side of 146 in the figure) may overlap with the insulating layer 110.

[0044] Therefore, the first, second, third and fourth insulating support members 145b and 145c can more effectively support the external electrodes 230 of the components 200a and 200b with reduced sizes, and the distance between the SMT substrates 100a and 100b and the insulator 210 of the components 200a and 200b can be more effectively increased. In addition, even when the insulating support members 145a, 145b, 145c, 145d, 145e and 145f have a relatively small size in the horizontal direction, a relatively large overlapping area in the Z direction between the first, second, third and fourth insulating support members 145b and 145c and the external electrodes 230 can be ensured, and an electrical connection path between the external electrodes 230 and the interconnection layer 120a can also be stably ensured.

[0045] For example, the first insulating support member (eg, Figure 2F and Figure 2G 146 in the upper left side), a second insulating support member (eg, Figure 2F and Figure 2G 146 in the upper right side), a third insulating support member (eg, Figure 2F and Figure 2G 146 in the lower left side) and the fourth insulating support member (eg, Figure 2F and Figure 2G The first, second, third, and fourth insulating support members 145b and 145c that protrude from the mask layer 140 toward the openings OP5 and OP6 may be implemented in the form of an irregular body on the boundary line of the openings OP5 and OP6, and may be different from a smooth shape such as a circle or a polygon.

[0046] Reference Figure 1D and Figure 2F, the external electrode 230 of the SMT package PKG4 according to some example embodiments of the present disclosure may further include a third external electrode 233, the third external electrode 233 having at least a portion on a surface (e.g., a lower surface) of the insulator 210 opposite to the SMT substrate 100a, and spaced apart from the first external electrode 231 and the second external electrode 232. The SMT package PKG4 may further include a fifth insulating support 149 supporting the third external electrode 233 in the opening OP5. The fifth insulating support 149 may be spaced apart from the first, second, third, and fourth insulating supports 146. Therefore, the SMT package PKG4 may more effectively support the component 200a, so that each of the first solder 181, the second solder 182, and the third solder 183 of the solder 180d may have a more stable size and / or shape, and the possibility of an electrical short circuit between the first solder 181, the second solder 182, and the third solder 183 may be further suppressed. That is, although the space between the SMT substrate 100a and the component 200a in the SMT package PKG4 is reduced due to the third external electrode 233, the reliability between the SMT substrate 100a and the component 200a in the SMT package PKG4 may be further improved.

[0047] For example, a portion of the fifth insulating support member 149 may be Figure 2A The fifth insulating support 149 may overlap the third pad region (e.g., the central portion of 120P) in FIG. 120P, and another portion of the fifth insulating support 149 may overlap the insulating layer 110. The fifth insulating support 149 may be spaced apart from the first, second, third, and fourth insulating support members 146, and may be surrounded by the first, second, third, and fourth insulating support members 146. Figure 2G , the fifth insulating support member can be omitted.

[0048] Reference Figure 2A , the number of the third pad region (eg, the central portion of 120P) of the interconnect layer may be multiple. Figure 2B , the third pad area of ​​the interconnect layer can be omitted. Figure 2C , a first pad region (eg, a left side of 120P) and a second pad region (eg, a right side of 120P) of the interconnect layer may be isolated from each other by the ground region 120G.

[0049] Reference Figure 1A and Figure 2D, the insulating support 145a may be in the form of a separator, dividing the opening into a plurality of openings OP1, OP2, and OP3. Therefore, each of the first solder 181, the second solder 182, and the third solder 183 of the solder 180a may have a more stable size and / or shape, and the possibility of an electrical short circuit between the first solder 181, the second solder 182, and the third solder 183 may be further suppressed. For example, the length (X2) of the insulating support 145a in the form of a separator in the X direction may be shorter than the length (Y2) of the insulating support 145a in the form of a separator in the Y direction, and may be shorter than Figure 2A The length (X1) of the pad region 120P in the X direction is shorter. For example, the length (Y2) of the insulating support member 145a in the form of a partition in the Y direction may be shorter than Figure 2A The length (Y1) of the pad region 120P in the Y direction is long. According to the design, the insulating supporter 145a may protrude from the mask layer 140 in the Y direction, but may have a relatively short protrusion so as not to be divided into a plurality of openings.

[0050] Reference Figure 2E , each of the first and second insulating supporters 145f may protrude from the mask layer 140 toward each other in the X direction. For example, the length (X3) of the protrusion of each of the first and second insulating supporters 145f in the X direction may be longer than the length (Y3) of the protrusion of each of the first and second insulating supporters 145f in the Y direction.

[0051] Reference Figure 2F , the shortest separation distance (Y5) between the first and second insulating supports (e.g., the upper side of 146) and the third and fourth insulating supports (e.g., the lower side of 146) can be greater than Figure 2A The longest separation distance (Y4) between the first and second insulating support members (upper side of 146) and the third and fourth insulating support members (lower side of 146) may be shorter than Figure 2A The length (Y1) of the pad area 120P in the Y direction is longer. The shortest separation distance (X5) between the first and third insulating supports (e.g., the left side of 146) and the second and fourth insulating supports (e.g., the right side of 146) can be longer than the shortest separation distance (Y5) between the first and second insulating supports (e.g., the upper side of 146) and the third and fourth insulating supports (e.g., the lower side of 146). The longest separation distance (X4) between the first and third insulating supports (e.g., the left side of 146) and the second and fourth insulating supports (e.g., the right side of 146) can be longer than the longest separation distance (Y4) between the first and second insulating supports (e.g., the upper side of 146) and the third and fourth insulating supports (e.g., the lower side of 146).

[0052] FIG. 3A to FIG. 3E Shows the manufacturing Figure 1A , Figure 2A and Figure 2D The SMT packaging method of PKG1 in Figure 3A , the first state PKG1-1 of the SMT package may have a structure in which the interconnection layer 120 is on the upper and lower portions of the insulating layer 110. For example, the horizontal shape of the interconnection layer 120 may be realized using photolithography.

[0053] Afterwards, in Figure 3B In the second state PKG1-2 of the SMT package, the mask layer 140L may have a structure in which the upper and lower surfaces of the insulating layer 110 are covered. Figure 3C In the third state PKG1 - 3 of the SMT package may have a structure in which the insulating supporter 145 a is formed together with the formation of the opening of the mask layer 140 .

[0054] Afterwards, in Figure 3D In the fourth state PKG1-4 of the SMT package, the component 200a may have a structure in which the component 200a is on the upper surface of the SMT substrate 100a. Figure 3E In the fifth state PKG1-5 of the SMT package, the solder 180a may connect the external electrode 230 of the component 200a and the interconnection layer 120a to each other. According to the design, the sealant 160 may be filled in the empty space on the upper side of the SMT substrate 100a. For example, the sealant 160 may be an epoxy molding compound (EMC).

[0055] Reference FIG. 4A to FIG. 4D , the insulating support members 145g, 145h, 145i, and 145j may be in direct contact with the external electrode 230. Figure 4D According to the design, the upper surface of the interconnection layer 120 and the upper surface of the insulating layer 110 may substantially form a plane.

[0056] Reference Figure 4A and Figure 4B , the roughness of the upper surfaces 146P and 146R of the insulating supports 145g and 145h may be greater than the roughness of the lower surfaces of the insulating supports 145g and 145h. For example, the upper surface 146P of the insulating support 145g may have a sawtooth shape, and the upper surface 146R of the insulating support 145h may have a concave shape. For example, the roughness of the upper surfaces 146P and 146R of the insulating supports 145g and 145h may be achieved using a plasma process or a fine particle collision process, but the present disclosure is not limited thereto.

[0057] Reference Figure 4CDue to the reaction of the insulating supporter 145i supporting the external electrode 230, a portion 146S of the insulating supporter 145i may be recessed by the external electrode 230. Therefore, the portion 146S of the insulating supporter 145i may be located at a level higher than that of the lower surface of the external electrode 230.

[0058] Reference Figure 5A The number of interconnection layers 120 (eg, three or more) of the SMT package PKG13 according to some example embodiments of the present disclosure may be greater than Figures 1A to 1F The number of interconnection layers 120 in the Z direction (one or two). Multiple interconnection layers 120a, 120b, and 120c may be stacked in the Z direction with a portion of the insulating layer 110 interposed therebetween, and may be electrically connected to each other in the Z direction through an interconnection path 125. For example, the interconnection path 125 may have a cylindrical shape, have an inclined side surface with a width decreasing upward, and may have a conformal path structure partially filled with a conductive material (e.g., copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof) or a filled path structure completely filled with a conductive material. At least a portion 120c of the multiple interconnection layers 120a, 120b, and 120c may be in the form of an interconnection extending in a horizontal direction according to patterning.

[0059] Reference Figure 5B , the SMT substrate 100b of the SMT package PKG14 according to some example embodiments of the present disclosure may include a core insulating layer 115. The core insulating layer 115 may include an insulating material that may be included in the insulating layer 110, and may have a stronger rigidity than that of the insulating material of the insulating layer 110. For example, the core insulating layer 115 may be formed based on a copper clad laminate (CCL), but the present disclosure is not limited thereto.

[0060] Reference Figure 5C , the SMT package PKG15 according to some example embodiments of the present disclosure may further include a semiconductor chip 250 mounted on the SMT substrate 100a. For example, the semiconductor chip 250 may include a chip pad 270 on the lower surface of the semiconductor chip 250, and may be electrically connected to the interconnection layer 120 via the chip pad 270 and the bump 280. The bump 280 may be in a plurality of through holes of the mask layer 140. The bump 280 may include a conductive material having a low melting point, such as a material that may be included in the solder 180a.

[0061] For example, semiconductor chip 250 may be a microprocessor such as a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an application processor (AP), a digital signal processor, a cryptographic processor, a controller, or an application specific integrated circuit (ASIC).

[0062] According to the design, the semiconductor chip 250 can be mounted on Figure 1E and Figure 1F Here, the semiconductor chip 250 may be a volatile memory such as a dynamic random access memory (DRAM) and a static random access memory (SRAM) or a nonvolatile memory such as a flash memory. Figure 1E and Figure 1F The SMT substrate 100b in the Figures 1A to 1D The SMT substrate 100a in the embodiment of the present invention can more effectively implement a high bandwidth memory (HBM).

[0063] The SMT substrate 100a may be mounted downward on an electronic device printed circuit board (PCB) 290. That is, the SMT substrate 100a and the SMT package PKG 15 may be within an electronic device. For example, the electronic device may include a smart phone, a personal digital assistant, a digital camera, a digital still camera, a network system, a computer, a monitor, a tablet computer, a laptop computer, a netbook, a television, a video game console, a smart watch, a car, etc. The electronic device printed circuit board 290 may be a motherboard or a mainboard.

[0064] Reference Figure 5C , Fig. 6A and Figure 6B , the components 200a and 200b may have a structure in which a plurality of first internal electrodes 221 and a plurality of second internal electrodes 222 are alternately positioned within the insulator 210. Fig. 6A , the first external electrode 231 of the component 200b may be connected to the plurality of first internal electrodes 221, and the second external electrode 232 of the component 200b may be connected to the plurality of second internal electrodes 222. Figure 6B , the first external electrode 231 and the second external electrode 232 of the component 200a may be connected to the plurality of first internal electrodes 221, and the third external electrode 233 of the component 200a may be connected to the plurality of second internal electrodes 222. Therefore, the components 200a and 200b may effectively form a capacitor.

[0065] According to the design, the component 200b may include a side edge portion 214 covering the plurality of first internal electrodes 221 and the plurality of second internal electrodes 222 in the Y direction and cover portions 212 and 213 covering the plurality of first internal electrodes 221 and the plurality of second internal electrodes 222 in the Z direction. Each of the plurality of dielectric layers of the insulator 210 may be between the plurality of first internal electrodes 221 and the plurality of second internal electrodes 222 and may include a dielectric such as barium titanate (BaTiO 3 ) ferroelectric material. The side edge portion 214 and the cover portions 212 and 213 may also include a ferroelectric material such as barium titanate (BaTiO3), but the present disclosure is not limited thereto. For example, the side edge portion 214 and the cover portions 212 and 213 may include an insulating material having a relatively low dielectric constant compared to the ferroelectric material and a higher performance for protecting the insulator 210.

[0066] Reference Figure 6C , the component 200c may include a coil 220 within an insulator 210. One end of the coil 220 may be connected to a first external electrode 231, and the other end of the coil 220 may be connected to a second external electrode 232. Therefore, the component 200c may effectively form an inductor.

[0067] For example, the coil 220 may be on the upper and lower surfaces of the insulating support layer 240 and may include a conductive material (e.g., copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof). The insulating support layer 240 may include an insulating material that may be included in the insulating layer of the SMT substrate. The insulator 210 may include not only an insulating material but also magnetic powder particles (e.g., metal powder particles and ferrite powder particles) for increasing magnetic permeability, and thus may have a higher magnetic permeability than the magnetic permeability of the insulating support layer 240. Figure 6C A film type inductor is shown, but the present disclosure is not limited thereto. For example, the component 200c may be implemented as a wound inductor or a stacked inductor, or as a bead or a common mode filter.

[0068] The SMT package according to some example embodiments of the inventive concepts and the SMT substrate included therein may more effectively ensure a distance between a component and the SMT substrate, thereby improving reliability between the component and the SMT substrate.

[0069] Although some examples of embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations are possible without departing from the scope of the inventive concept as defined by the appended claims.

[0070] This application claims the priority of Korean Patent Application No. 10-2023-0075290 filed in the Korean Intellectual Property Office on June 13, 2023, and Korean Patent Application No. 10-2023-0111672 filed in the Korean Intellectual Property Office on August 25, 2023, and the entire contents of the above applications are incorporated herein by reference.

Claims

1. A surface mount technology (SMT) package, include: A surface mount technology substrate comprising an interconnect layer, an insulating layer having a placement area for the interconnect layer, and a mask layer on an upper surface of the insulating layer; a component including an insulator and an external electrode having at least a portion on a surface of the insulator opposite to the surface mount technology substrate; as well as solder, electrically connecting the interconnect layer and the external electrode to each other, wherein the mask layer has an opening, and The surface mounting technology substrate further includes an insulating supporter, the insulating supporter supporting the external electrode in the opening so that the external electrode is spaced apart from the interconnection layer and the insulating layer.

2. The surface mount technology package according to claim 1, in: The first portion of the insulating support is on the upper surface of the insulating layer, and A second portion of the insulating support is on the upper surface of the interconnect layer. 3 . The surface mount technology package of claim 1 , wherein an upper surface of the interconnect layer is in direct contact with the solder and in direct contact with the insulating support. 4 . The surface mount technology package of claim 3 , wherein the upper surface of the interconnect layer is located at a level lower than that of the upper surface of the insulating layer.

5. The surface mount technology package according to claim 1, in: The upper surface of the interconnect layer is in direct contact with the solder, and The interconnect layer is embedded in the insulating layer. 6 . The surface mount technology package of claim 5 , wherein a distance between a lower surface of the external electrode and the upper surface of the interconnect layer is greater than a thickness of the mask layer. 7 . The surface mount technology package of claim 1 , wherein the insulating support comprises an insulating material which is the same material as the insulating material included in the mask layer.

8. The surface mount technology package of claim 1, wherein the insulating support is in direct contact with the mask layer.

9. The surface mount technology package of claim 1, wherein the insulating support protrudes toward the external electrode. 10 . The surface mount technology package of claim 9 , wherein the insulating support comprises an insulating material different from an insulating material included in the mask layer.

11. The surface mount technology package of claim 1, in: The external electrodes include a first external electrode and a second external electrode, the first external electrode having at least a portion on a portion of the surface of the insulator opposite to the surface mounting technology substrate, and the second external electrode having at least a portion on another portion of the surface of the insulator opposite to the surface mounting technology substrate, The insulating support member includes a first insulating support member supporting the first external electrode in the opening and a second insulating support member supporting the second external electrode in the opening, The first external electrode and the second external electrode are spaced apart from each other, and The first insulating supporter and the second insulating supporter are spaced apart from each other such that a portion of the opening is interposed therebetween.

12. The surface mount technology package of claim 1, further comprising: include: A semiconductor chip is mounted on the surface mounting technology substrate.

13. A surface mount technology (SMT) substrate, include: an interconnect layer having a first pad region and a second pad region; an insulating layer having a layout area for the interconnection layer; a mask layer on the upper surface of the insulating layer and having an opening; a first insulating support member, in the opening such that a portion of the first insulating support member overlaps the first pad region; as well as A second insulating supporter is provided in the opening such that a portion of the second insulating supporter overlaps with the second pad region.

14. The surface mounting technology substrate according to claim 13, further comprising: include: a third insulating support member, arranged in the opening so that a portion of the third insulating support member overlaps with the first pad region; as well as a fourth insulating support member, arranged in the opening so that a portion of the fourth insulating support member overlaps with the second pad region, The first insulating support, the second insulating support, the third insulating support and the fourth insulating support are spaced apart from each other such that a portion of the opening is interposed therebetween.

15. The surface mounting technology substrate according to claim 14, further comprising: include: a fifth insulating support member, arranged in the opening so that a portion of the fifth insulating support member overlaps with the third pad region of the interconnect layer, The fifth insulating support is spaced apart from the first insulating support, the second insulating support, the third insulating support and the fourth insulating support, and is surrounded by the first insulating support, the second insulating support, the third insulating support and the fourth insulating support. 16 . The surface mounting technology substrate of claim 14 , wherein each of the first insulating supporter, the second insulating supporter, the third insulating supporter, and the fourth insulating supporter protrudes from the mask layer toward the opening. 17 . The surface mount technology substrate of claim 13 , wherein each of the first insulating supporter and the second insulating supporter protrudes from the mask layer toward each other. 18 . The surface mount technology substrate of claim 13 , wherein each of the first insulating supporter and the second insulating supporter comprises a partition that partitions the opening.

19. A surface mount technology (SMT) substrate, include: Insulation layer; an interconnect layer embedded in the insulating layer; a mask layer on the upper surface of the insulating layer and having an opening; as well as a first insulating support, a second insulating support, a third insulating support and a fourth insulating support respectively in direct contact with the interconnect layer, the first insulating support, the second insulating support, the third insulating support and the fourth insulating support respectively protruding from the mask layer toward the opening, The first insulating support member, the second insulating support member, the third insulating support member and the fourth insulating support member are spaced apart from each other in the opening and are arranged two-dimensionally.

20. The surface mounting technology substrate according to claim 19, in: Each of the first insulating supporter, the second insulating supporter, the third insulating supporter, and the fourth insulating supporter includes an insulating material that is the same material as the insulating material included in the mask layer, and An upper surface of the interconnect layer is located at a level lower than that of the upper surface of the insulating layer.

Images