Three-dimensional interconnection transmission line and preparation method

Abstract

The invention discloses a three-dimensional interconnection transmission line and a preparation method, and belongs to the technical field of communication. The three-dimensional interconnection transmission line provided by the invention comprises a plurality of wafers which are sequentially stacked, and further comprises a coaxial TSV structure and a micro coaxial structure. Every two adjacent wafers are connected in a sealed mode, a cavity is formed between every two adjacent wafers, and at least one of the two adjacent wafers is provided with a through hole which penetrates through the wafer and is communicated with the cavity. The micro coaxial structure is arranged in the cavity, the coaxial TSV structure is arranged in the through hole and is in closed connection with the inner wall of the through hole, and a micro coaxial inner conductor of the micro coaxial structure is connected to a TSV inner conductor of the coaxial TSV structure. The coaxial TSV structure is located in the through hole and is in sealed connection with the inner wall of the through hole, the micro-coaxial structure is located in the cavity, only an external connection port, far away from one end of the micro-coaxial structure, of the coaxial TSV structure is exposed out of the wafer and is used for being electrically connected with other structures except the three-dimensional interconnection transmission line, and the air tightness of the three-dimensional interconnection transmission line is good.

Description

Technical Field

[0001] The present application belongs to the technical field of communications, and in particular, relates to a three-dimensional interconnection transmission line and a preparation method thereof. Background Art

[0002] With the rapid development of artificial intelligence, big data, data centers, etc., the amount of data processing has increased significantly, and data signals are also transmitted between inter-board devices at a higher rate. In order to realize real-time sharing and collaborative processing of data between inter-board devices, the inter-board interconnection transmission lines are required to have large bandwidth, low loss, and dispersion-free characteristics, and be compatible with high-speed backplane processes.

[0003] Existing transmission lines are easily affected by external interference, which is manifested in that the transmission lines are easily oxidized, easily damaged by external foreign objects, and easily short-circuited in a humid environment. Summary of the invention

[0004] The present application aims to at least to some extent solve the technical problem that the transmission line is easily disturbed by the outside world. To this end, the present application provides a three-dimensional interconnected transmission line and a preparation method thereof.

[0005] In a first aspect, an embodiment of the present application provides a three-dimensional interconnect transmission line, comprising:

[0006] A plurality of wafers stacked in sequence, two adjacent wafers being hermetically connected, and a closed chamber being formed between the two adjacent wafers, and at least one of the two adjacent wafers being provided with a through hole penetrating the wafer and communicating with the chamber;

[0007] A coaxial TSV structure and a micro-coaxial structure, wherein the micro-coaxial structure is arranged in the chamber, the coaxial TSV structure is arranged in the through hole and is tightly connected to the inner wall of the through hole, the micro-coaxial structure includes a micro-coaxial inner conductor, the coaxial TSV structure includes a TSV inner conductor, and the micro-coaxial inner conductor is connected to the TSV inner conductor.

[0008] In some embodiments, among the two adjacent wafers, a first groove is formed on one of the wafers, and a second groove is formed on the other wafer. The first groove and the second groove are arranged opposite to each other to enclose the chamber.

[0009] In some embodiments, the coaxial TSV structure further includes a TSV insulating layer and a TSV shielding layer, wherein the TSV insulating layer is sleeved outside the TSV inner conductor, and the TSV shielding layer is sleeved outside the TSV insulating layer and located between the inner wall of the through hole and the TSV insulating layer to achieve a sealed connection between the coaxial TSV structure and the inner wall of the through hole.

[0010] In some embodiments, part of the TSV insulating layer protrudes from the surface of the wafer and is located in the chamber (100a); the micro-coaxial inner conductor is located on the TSV insulating layer so that the micro-coaxial inner conductor is spaced apart from the wafer.

[0011] In some embodiments, in two adjacent wafers, the through holes are opened on both wafers, and at least some of the through holes on the two wafers are arranged opposite to each other, so that the TSV inner conductors located in the oppositely arranged through holes can be connected.

[0012] In some embodiments, in two adjacent wafers, the through holes are opened on both wafers, and at least part of the through holes on the two wafers are staggered.

[0013] In some embodiments, the micro-coaxial structure further includes an insulating support bridge, the insulating support bridge is suspended in the chamber, and at least a portion of the insulating support bridge is fixed between two adjacent wafers, and the micro-coaxial inner conductor is located on the insulating support bridge.

[0014] In a second aspect, an embodiment of the present application provides a method for preparing a three-dimensional interconnection transmission line, which is used to prepare the three-dimensional interconnection transmission line described in the first aspect, wherein the two adjacent wafers are an upper wafer and a lower wafer, respectively, and the preparation method comprises:

[0015] Fabricating a coaxial TSV structure on the bonding surface of the upper wafer and / or the lower wafer;

[0016] Processing grooves on the bonding surfaces of the upper wafer and the lower wafer;

[0017] Fabricating the micro-coaxial structure on the upper wafer and / or the lower wafer;

[0018] The bonding surface of the upper wafer is bonded to the bonding surface of the lower wafer.

[0019] In some embodiments, fabricating a coaxial TSV structure on the bonding surface of the upper wafer and / or the lower wafer includes:

[0020] Processing TSV holes on the bonding surface;

[0021] Fabricating a TSV shielding layer in the TSV hole;

[0022] Fabricating a TSV insulating layer hole inner section of a TSV insulating layer in the TSV shielding layer;

[0023] Fabricating a TSV inner conductor hole inner section of a TSV inner conductor in the TSV insulating layer;

[0024] The back side of the bonding surface is thinned until the coaxial TSV structure is exposed.

[0025] In some embodiments, fabricating the micro-coaxial structure on the upper wafer and / or the lower wafer includes:

[0026] Making an insulating support bridge and a TSV insulating layer extension section of the TSV insulating layer on the bonding surface where the coaxial TSV structure is located;

[0027] Manufacturing a TSV inner conductor extension section of the TSV inner conductor in the TSV insulation layer extension section;

[0028] The upper micro-coaxial inner conductor is manufactured on the insulating support bridge, the TSV insulating layer extension section and the TSV inner conductor extension section.

[0029] The present invention has at least the following beneficial effects:

[0030] The three-dimensional interconnection transmission line provided by the present invention includes a plurality of wafers stacked in sequence, and also includes a coaxial TSV structure and a micro-coaxial structure. Two adjacent wafers are hermetically connected, and a chamber is formed between the two adjacent wafers. Among the two adjacent wafers, at least one wafer is provided with a through hole that penetrates the wafer and is connected to the chamber. The micro-coaxial structure is arranged in the chamber, the coaxial TSV structure is arranged in the through hole, and is hermetically connected to the inner wall of the through hole, and the micro-coaxial inner conductor of the micro-coaxial structure is connected to the TSV inner conductor of the coaxial TSV structure.

[0031] After such a design, the coaxial TSV structure is located in the through hole and is tightly connected to the inner wall of the through hole, the micro-coaxial structure is located in the chamber, and only the external connection port of the coaxial TSV structure away from the micro-coaxial structure is exposed outside the wafer, which is used to electrically connect with other structures outside the three-dimensional interconnection transmission line. The three-dimensional interconnection transmission line has good airtightness, and external gases (such as oxygen), foreign matter (such as dust), water vapor, etc. will not enter the chamber. The coaxial TSV structure and micro-coaxial structure of the three-dimensional interconnection transmission line will not be oxidized, and will be protected from external foreign matter intrusion and damage, and will not short-circuit due to external water vapor, etc., thereby ensuring stable signal transmission and expanding the application scenarios of the three-dimensional interconnection transmission line.

[0032] The structural design of the coaxial TSV structure and the micro-coaxial structure also realizes the three-dimensional transmission of signals in the vertical and planar directions, enhances the compatibility with subsequent high-speed backplane processes, and enables the three-dimensional interconnection transmission line to have the characteristics of large bandwidth, low loss, and no dispersion. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following is a brief introduction to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 A schematic diagram of a three-dimensional interconnected transmission line in some embodiments of the present application is shown.

[0035] Figure 2 Shows Figure 1 A first perspective cross-sectional view of a three-dimensional interconnect transmission line is shown.

[0036] Figure 3 Shows Figure 1 A cross-sectional view from a second perspective of the three-dimensional interconnect transmission line shown.

[0037] Figure 4 Schematic diagrams of three-dimensional interconnected transmission lines in other embodiments of the present application are shown.

[0038] Figure 5 Shows Figure 4 An exploded schematic diagram of the first perspective of the three-dimensional interconnect transmission line shown.

[0039] Figure 6 Shows Figure 5 An exploded schematic diagram of a second perspective of a three-dimensional interconnect transmission line is shown.

[0040] Figure 7 A first-view schematic diagram of a three-dimensional interconnected transmission line in some other embodiments of the present application is shown.

[0041] Figure 8 A second viewing angle schematic diagram of a three-dimensional interconnected transmission line in some other embodiments of the present application is shown.

[0042] Fig. 9 Shows Figure 7 A cross-sectional view of a three-dimensional interconnect transmission line is shown.

[0043] Fig.10 A schematic diagram is shown after two TSV holes are etched on the bonding surface of the upper wafer.

[0044] Fig.11 Shows Fig.10 sectional view of .

[0045] Fig.12 A schematic diagram is shown after a TSV shielding layer is formed in a TSV hole.

[0046] Fig.13 Shows Fig.12 sectional view of .

[0047] Fig.14 A schematic diagram is shown after the TSV insulating layer hole inner section is manufactured in the TSV shielding layer.

[0048] Fig.15 Shows Fig.14 sectional view of .

[0049] Fig.16 The schematic diagram shows the process of manufacturing the inner segment of the TSV inner conductor hole in the inner segment of the TSV insulating layer hole.

[0050] Fig.17 Shows Fig.16 sectional view of .

[0051] Fig.18 A schematic diagram showing a process of opening a rectangular groove on the bonding surface of the upper wafer.

[0052] Fig.19 Shows Fig.18 sectional view of .

[0053] Fig. 20 The schematic diagram shows the process of manufacturing an insulating support bridge on the bonding surface of the upper wafer and manufacturing a TSV insulating layer extension section above the TSV insulating layer hole inner section.

[0054] Fig.21 Shows Fig. 20 sectional view of .

[0055] Fig. 22 A schematic diagram is shown after a TSV inner conductor extension section is fabricated within a TSV insulation layer extension section.

[0056] Fig.23 Shows Fig. 22 sectional view of .

[0057] Fig.24 A schematic diagram is shown after a micro-coaxial inner conductor is manufactured on a TSV inner conductor extension section, a TSV insulating layer extension section and an insulating support bridge.

[0058] Fig.25 A schematic diagram is shown after a groove for accommodating an insulating support bridge is opened on the bonding surface of the lower wafer.

[0059] Fig.26 A schematic diagram is shown after a groove for accommodating a micro-coaxial inner conductor is opened on the bonding surface of the lower wafer.

[0060] Fig. 27 Shows Fig.26 sectional view of .

[0061] Fig.28 A schematic diagram showing the bonding of the upper wafer and the lower wafer is shown.

[0062] Fig.29 A cross-sectional view is shown after the non-bonding surface of the upper wafer has been subjected to chemical mechanical polishing.

[0063] Fig.30 A flow chart of the preparation method in one or more embodiments of the present application is shown.

[0064] Figure numerals: 100 - three-dimensional interconnect transmission line, 100a - chamber, 110 - wafer, 110b - through hole, 120 - coaxial TSV structure, 121 - TSV inner conductor, 1211 - TSV inner conductor hole inner section, 1212 - TSV inner conductor extension section, 122 - TSV insulating layer, 1221 - TSV insulating layer hole inner section, 1222 - TSV insulating layer extension section, 123 - TSV shielding layer, 130 - micro-coaxial structure, 132 - insulating support bridge, 131 - micro-coaxial inner conductor. DETAILED DESCRIPTION

[0065] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0066] It should be noted that all directional indications in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between various components in a certain specific posture. If the specific posture changes, the directional indication will also change accordingly.

[0067] In the present invention, unless otherwise clearly specified and limited, the terms "connection", "fixation", etc. should be understood in a broad sense. For example, "fixation" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0068] In addition, in the present invention, descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0069] The air tightness of existing transmission lines is poor, and external gases, foreign objects and water vapor can easily enter the transmission lines, making the conductors and other components in the transmission lines susceptible to oxidation and damage by external foreign objects. The effect of water vapor can cause short circuits in the conductors.

[0070] In addition, existing transmission lines are unable to transmit signals in the vertical direction, and the process compatibility between the transmission lines and high-speed backplanes is poor.

[0071] In the related art, there is a technical problem that the transmission line is easily disturbed by the outside world. The embodiment of the present application provides a three-dimensional interconnected transmission line and a preparation method, which can at least solve the technical problem of the transmission line to a certain extent.

[0072] The present application is described below with reference to the accompanying drawings and specific embodiments:

[0073] like Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 As shown, the three-dimensional interconnect transmission line 100 includes a plurality of wafers 110 stacked in sequence, and also includes a coaxial TSV structure 120 and a micro coaxial structure 130 .

[0074] The number of wafers 110 is two or more, such as two, three, four, etc., which is not limited here. The plurality of wafers 110 are stacked in sequence from bottom to top.

[0075] The two adjacent wafers 110 are hermetically connected, and a closed chamber 100 a is formed between the two adjacent wafers 110 . Among the two adjacent wafers 110 , at least one wafer 110 is provided with a through hole 110 b penetrating the wafer 110 and communicating with the chamber 100 a .

[0076] The two adjacent wafers 110 are tightly connected so that the chamber 100a formed between the two adjacent wafers 110 is a closed chamber, and external water vapor, gas, foreign matter, etc. cannot enter the chamber 100a through the two wafers 110. The two adjacent wafers 110 can be tightly connected by bonding. Among the two adjacent wafers 110, at least one wafer 110 is provided with a through hole 110b that penetrates the wafer 110 and is connected to the chamber 100a. That is to say, among the two adjacent wafers 110, the through hole 110b can be provided on only one of the wafers 110, or the through holes 110b can be provided on both wafers 110.

[0077] The micro-coaxial structure 130 is disposed in the chamber 100a, the coaxial TSV structure 120 is disposed in the through hole 110b and is tightly connected to the inner wall of the through hole 110b, the micro-coaxial structure 130 includes a micro-coaxial inner conductor 131, the coaxial TSV structure 120 includes a TSV inner conductor 121, and the micro-coaxial inner conductor 131 is connected to the TSV inner conductor 121.

[0078] The coaxial TSV structure 120 is disposed in the through hole 110b, and the coaxial TSV structure 120 is tightly connected to the inner wall of the through hole 110b, so that external water vapor, impurities, etc. cannot enter the chamber 100a through the coaxial TSV structure 120 and the inner wall of the through hole 110b, that is, the coaxial TSV structure 120 blocks the through hole 110b. The micro-coaxial structure 130 has a micro-coaxial inner conductor 131, and the coaxial TSV structure 120 has a TSV inner conductor 121. The coaxial inner conductor and the TSV inner conductor 121 are electrically connected, so that the signal can be transmitted between the coaxial inner conductor and the TSV inner conductor 121. The outer layer of the coaxial TSV structure 120 (i.e., the TSV shielding layer 123 hereinafter) can be formed on the inner wall of the through hole 110b by electroplating, thereby realizing a tightly connected coaxial TSV structure 120 with the inner wall of the through hole 110b.

[0079] The number of through holes 110b is consistent with the number of coaxial TSV structures 120, and a coaxial TSV structure 120 is disposed in each through hole 110b. The micro-coaxial inner conductor 131 is used to connect multiple TSV inner conductors 121. The same micro-coaxial inner conductor 131 can be connected to two TSV inner conductors 121 at the same time, or more than two TSV inner conductors 121 at the same time. For example, three TSV inner conductors 121 can be connected at the same time, or five TSV inner conductors 121 can be connected at the same time. This is related to the application scenario of the three-dimensional interconnection transmission line 100, and the user can design it adaptively, which will not be elaborated here. The micro-coaxial inner conductor 131 has various shapes and sizes, such as Figure 2 and Figure 6As shown, one micro-coaxial inner conductor 131 is connected to two TSV inner conductors 121 at the same time. In these solutions, the micro-coaxial inner conductor 131 is in a long strip shape, and its two ends are respectively connected to the two TSV inner conductors 121. The end of the TSV inner conductor 121 exposed to the outside (that is, the end of the TSV inner conductor 121 away from the micro-coaxial inner conductor 131) is an external connection port for electrically connecting to other structures outside the three-dimensional interconnection transmission line 100.

[0080] After such design, the coaxial TSV structure 120 is located in the through hole 110b and is tightly connected to the inner wall of the through hole 110b, the micro-coaxial structure 130 is located in the chamber 100a, and only the external connection port of the coaxial TSV structure 120 away from the micro-coaxial structure 130 is exposed outside the wafer 110, and is used to electrically connect with other structures outside the three-dimensional interconnection transmission line 100. The three-dimensional interconnection transmission line 100 has good airtightness, and external gases (such as oxygen), foreign matter (such as dust), water vapor, etc. will not enter the chamber 100a. The coaxial TSV structure 120 and the micro-coaxial structure 130 of the three-dimensional interconnection transmission line 100 will not be oxidized, and will not be damaged by the invasion of external foreign matter, and will not be short-circuited due to external water vapor, etc., thereby ensuring stable transmission of signals and expanding the application scenarios of the three-dimensional interconnection transmission line.

[0081] The structural design of the coaxial TSV structure 120 and the micro-coaxial structure 130 also realizes three-dimensional transmission of signals in the vertical and planar directions, enhances compatibility with subsequent high-speed backplane processes, and enables the transmission line to have the characteristics of large bandwidth, low loss, and no dispersion.

[0082] In some embodiments, a shielding layer is provided on the inner wall of the chamber 100a, and the shielding layer can prevent electromagnetic waves outside the three-dimensional interconnection transmission line 100 from propagating into the chamber 100a, and can also prevent electromagnetic waves of the micro-coaxial inner conductor 131 from leaking outward, thereby facilitating the signal transmission performance of the coaxial TSV structure 120 and the micro-coaxial structure 130.

[0083] In some embodiments, in two adjacent wafers 110 , through holes 110 b are formed on both wafers 110 , and at least some of the through holes 110 b on the two wafers 110 are disposed opposite to each other, so that the TSV inner conductors 121 in the oppositely disposed through holes 110 b can be connected.

[0084] In these embodiments, through holes 110b are provided on both wafers 110, and some of the through holes 110b on the two wafers 110 are arranged relative to each other, so that the TSV inner conductors 121 on the two wafers 110 can be connected together to form a signal transmission path, so that the signal can be transmitted from one TSV inner conductor 121 to another TSV inner conductor 121, and the external connection port of the three-dimensional interconnection transmission line 100 can be located on the same surface of the same wafer 110, so as to facilitate the connection of the three-dimensional interconnection transmission line 100 with the outside world and reduce the connection difficulty, so that the three-dimensional interconnection transmission line 100 can be better compatible with the layout and wiring of the high-speed backplane and have better compatibility.

[0085] When the number of wafers 110 is set to three or more, the inner conductors of the TSV inner conductors 121 of the coaxial TSV structures 120 on two adjacent wafers 110 can be connected so that the signal can be transmitted. Figure 5 and Figure 6 As shown, in some embodiments, the three-dimensional interconnect transmission line 100 has three wafers 110. For ease of description, the definition Figure 5 The three wafers 110 from top to bottom are respectively a first wafer, a second wafer and a third wafer, and the corresponding Figure 6 From bottom to top, they are the first wafer, the second wafer, and the third wafer. Figure 5 The second wafer is provided with four through holes 110b, and each through hole 110b is provided with a coaxial TSV structure 120. Figure 6 , two micro-coaxial structures 130 are disposed on the second wafer, and the two ends of the micro-coaxial inner conductors 131 of the two micro-coaxial structures 130 are respectively connected to the TSV inner conductors 121 of the two coaxial TSV structures 120. Figure 5 , eight through holes 110b are opened on the first wafer, and a coaxial TSV structure 120 is disposed in each corresponding through hole 110b. Figure 6 Two micro-coaxial structures 130 are arranged on the first wafer, and the two ends of the micro-coaxial inner conductors 131 of the two micro-coaxial structures 130 are respectively connected to the TSV inner conductors 121 of the two coaxial TSV structures 120. The four through holes 110b of the second wafer are respectively arranged relative to the four through holes 110b on the first wafer, so that the TSV inner conductors 121 of the coaxial TSV structure 120 in the four through holes 110b of the second wafer can be connected to the TSV inner conductors 121 of the coaxial TSV structure 120 in the four through holes 110b on the first wafer (TSV inner conductors 121 not connected to the micro-coaxial structures 130 on the first wafer), so that the two micro-coaxial structures 130 on the second wafer can form a signal path with the outside world, and the eight external connection ports of the three-dimensional interconnection transmission line 100 are all located on the same surface of the first wafer (i.e. Figure 5On the upper end surface of the first wafer).

[0086] When there are two wafers 110 , at least some of the through holes 110 b on the two wafers 110 may be arranged opposite to each other so that the TSV inner conductors 121 on the two wafers 110 can be connected, so that signals can be transmitted or received through the two TSV inner conductors 121 at the same time.

[0087] In some embodiments, in two adjacent wafers 110 , through holes 110 b are formed on both wafers 110 , and at least some of the through holes 110 b on the two wafers 110 are staggered.

[0088] At least part of the through holes 110b are staggered, which means that the holes on the two wafers 110 can all be staggered, or part of them can be staggered, and part of them can be relatively arranged. In these embodiments, the coaxial TSV structure 120 is arranged on the two adjacent wafers 110, and at least part of the coaxial TSV structure 120 on the two wafers 110 is staggered. Such a design can make the external connection port of the three-dimensional interconnection transmission line 100 be located on different wafers 110, so as to facilitate the connection of the three-dimensional interconnection transmission line 100 with the outside world, reduce the connection difficulty, so that the three-dimensional interconnection transmission line 100 can be better compatible with the layout and wiring of the high-speed backplane, and have better compatibility.

[0089] In some embodiments, Figure 7 , Figure 8 and Fig. 9 As shown, in some embodiments, the three-dimensional interconnect transmission line 100 has two wafers 110. For ease of description, the definition Figure 7 The two wafers 110 from top to bottom are the fourth wafer and the fifth wafer, respectively. A through hole 110b is provided on the fourth wafer, and a coaxial TSV structure 120 is provided in the through hole 110b. A through hole 110b is provided on the fifth wafer, and a coaxial TSV structure 120 is provided in the through hole 110b. A micro-coaxial structure 130 is provided in the chamber 100a between the fourth wafer and the fifth wafer, and the two ends of the micro-coaxial inner conductor 131 of the micro-coaxial structure 130 are respectively connected to the TSV inner conductor 121 on the fourth wafer and the TSV inner conductor 121 on the fifth wafer. With this design, the two external connection ports of the three-dimensional interconnection transmission line 100 are respectively located on the upper end surface of the fourth wafer and the lower end surface of the fifth wafer.

[0090] The types of the coaxial TSV structure 120 are various, and may be BCB dielectric layer coaxial TSV, mixed dielectric layer coaxial TSV, quasi-coaxial TSV, mixed dielectric layer quasi-coaxial TSV, etc., which are not limited in the present application.

[0091] In some embodiments, the coaxial TSV structure 120 is a BCB dielectric layer coaxial TSV. In these embodiments, the coaxial TSV structure 120 further includes a TSV insulating layer 122 and a TSV shielding layer 123. The TSV insulating layer 122 is sleeved outside the TSV inner conductor 121, and the TSV shielding layer 123 is sleeved outside the TSV insulating layer 122 and is located between the inner wall of the through hole 110b and the TSV insulating layer 122. The TSV insulating layer 122 is tightly connected to the inner wall of the through hole 110b to achieve a tightly connected coaxial TSV structure 120 and the inner wall of the through hole 110b.

[0092] In some embodiments, a portion of the TSV insulating layer 122 protrudes from the surface of the wafer 110 and is partially located in the chamber 100 a ; the micro-coaxial inner conductor 131 is located on the TSV insulating layer 122 , so that the micro-coaxial inner conductor 131 is spaced apart from the wafer 110 .

[0093] In these embodiments, a portion of the TSV insulating layer 122 is located in the through hole 110b, and a portion protrudes from the surface of the wafer 110, is located outside the through hole 110b and is located in the chamber 100a. With this design, the TSV insulating layer 122 can not only insulate the TSV inner conductor 121 from the TSV shielding layer 123, but also support the micro-coaxial inner conductor 131, so that there is a gap between the micro-coaxial inner conductor 131 and the surface of the wafer 110, so that the micro-coaxial inner conductor 131 and the wafer 110 are insulated.

[0094] like Figure 2 As shown, the TSV insulating layer 122 may include a connected TSV insulating layer hole inner section 1221 and a TSV insulating layer protruding section 1222, wherein the TSV insulating layer hole inner section 1221 is located in the through hole 110b, and the TSV insulating layer protruding section 1222 is located outside the through hole 110b and protrudes from the surface of the wafer 110, and is used to support the micro-coaxial inner conductor 131. The TSV inner conductor 121 may include a connected TSV inner conductor hole inner section 1211 and a TSV inner conductor protruding section 1212, wherein the TSV inner conductor hole inner section 1211 is located in the TSV insulating layer hole inner section 1221, and the TSV inner conductor protruding section 1212 is located in the TSV insulating layer protruding section 1222. For ease of processing, the insulating layer hole inner section 1221 may be formed first, and then the TSV insulating layer protruding section 1222 may be formed. Similarly, the TSV inner conductor hole inner section 1211 may be formed first, and then the TSV inner conductor protruding section 1212 may be formed.

[0095] In some embodiments, among two adjacent wafers 110, a first groove is formed on one wafer 110, and a second groove is formed on the other wafer 110. The two grooves are arranged opposite to each other to form a chamber 100a; the micro-coaxial inner conductor 131 is suspended in the chamber 100a.

[0096] The opening of the first groove and the opening of the second groove are arranged opposite to each other, and the shapes of the grooves are not limited in this application. In some embodiments, the cross-sections of the first groove and the second groove are rectangular.

[0097] In some embodiments, the micro-coaxial structure 130 further includes an insulating support bridge 132 , which is suspended in the chamber 100 a and at least partially fixed between two adjacent wafers 110 . The micro-coaxial inner conductor 131 is located on the insulating support bridge 132 .

[0098] Part of the edge of the insulating support bridge 132 is fixed between two adjacent wafers 110, which is conducive to ensuring the connection effect between the insulating support bridge 132 and the wafer 110. The micro-coaxial inner conductor 131 is located on the insulating support bridge 132, and the insulating support bridge 132 is used to support the micro-coaxial inner conductor 131.

[0099] like Fig.30 As shown, based on the same inventive concept, the embodiment of the present application also provides a method for preparing a three-dimensional interconnection transmission line 100, which is used to prepare the above-mentioned three-dimensional interconnection transmission line 100. For the convenience of the following description, two adjacent wafers 110 are defined as an upper wafer and a lower wafer, respectively, and the preparation method includes steps S100, S200, S300 and S400.

[0100] S100 , manufacturing a coaxial TSV structure 120 on a bonding surface of an upper wafer and / or a lower wafer.

[0101] If the coaxial TSV structure 120 needs to be fabricated on both adjacent wafers 110, the coaxial TSV structure 120 is fabricated on both wafers 110. If the coaxial TSV structure 120 needs to be fabricated on only the upper wafer of the two adjacent wafers 110, the coaxial TSV structure 120 is fabricated on both the upper wafer. If the coaxial TSV structure 120 needs to be fabricated on only the lower wafer of the two adjacent wafers 110, the coaxial TSV structure 120 is fabricated on both the lower wafer.

[0102] Step S100 may include steps S110 , S120 , S130 , and S140 .

[0103] S110, such as Fig.10 and Fig.11 As shown, TSV holes are processed on the bonding surface.

[0104] The TSV hole in this step is a blind hole. Specifically, the TSV hole is etched on the bonding surface where the coaxial TSV structure 120 needs to be made. The TSV hole can be processed by dry etching, wet etching or laser drilling. In some schemes, deep reactive ion etching (DRIE) is used to etch the TSV hole. The deep reactive ion etching technology mainly includes the steps of applying photoresist, exposing, developing, etching, and removing photoresist. The process steps of etching TSV holes are known to those skilled in the art and will not be repeated here.

[0105] S120, such as Fig.12 and Fig.13 As shown, a TSV shielding layer 123 is formed in the TSV hole.

[0106] There are many methods for making the TSV shielding layer 123, which are not limited in the present application. In some embodiments, a seed layer is first deposited on the inner wall of the TSV hole to provide a conductive substrate for the subsequent electroplating process, ensuring that the electroplating layer can be evenly and densely deposited in the TSV through-hole 110b and on the surface of the wafer 110. Next, a photoresist is applied to the bonding surface and exposed and developed to ensure that the subsequent electroplating layer is only formed on the inner wall of the TSV hole. Next, electroplating is performed to form a TSV shielding layer 123 on the inner wall of the TSV hole. Finally, CMP (chemical mechanical polishing) is used to remove excess material on the wafer 110 (such as protrusions and photoresist residues that may be formed during the electroplating process) to achieve global flatness of the surface of the wafer 110.

[0107] S130, such as Fig.14 and Fig.15 As shown, a TSV insulating layer hole inner section 1221 of the TSV insulating layer 122 is fabricated in the TSV shielding layer 123 .

[0108] The TSV insulating layer hole inner segment 1221 may be deposited on the inner wall of the TSV shielding layer 123 by plasma enhanced chemical vapor deposition (PECVD), reduced pressure chemical vapor deposition (SACVD) or atomic layer deposition (ALD), which is not limited in the present application.

[0109] S140, such as Fig.16 and Fig.17 As shown, a TSV inner conductor hole inner section 1211 of the TSV inner conductor 121 is fabricated in the TSV insulating layer 122 .

[0110] The method for making the inner section 1211 of the TSV inner conductor hole is known to those skilled in the art. In some embodiments, first, a layer of photoresist is coated on the surface of the wafer 110 to define the area where the inner section 1211 of the TSV inner conductor hole needs to be made. Next, a barrier layer is deposited in the inner section 1221 of the TSV insulating layer hole to prevent metal atoms from diffusing into the silicon substrate during the subsequent electroplating process. Next, a seed layer is deposited to ensure that the electroplated layer can be uniformly and densely deposited on the surface of the wafer 110. Next, through exposure and development treatment, it is ensured that the subsequent electroplated layer is formed only in the inner section 1221 of the TSV insulating layer hole. Next, electroplating treatment is performed to form the TSV inner conductor 121 in the inner section 1221 of the TSV insulating layer hole. Next, the remaining photoresist on the surface of the wafer 110 is removed to expose the electroplated inner section 1211 of the TSV inner conductor hole. Finally, through CMP processing (chemical mechanical polishing), excess materials on the surface of the wafer 110 (such as protrusions and photoresist residues that may be formed during the electroplating process, etc.) are removed to achieve global flatness of the surface of the wafer 110.

[0111] S150 , thinning the back side of the bonding surface until the coaxial TSV structure 120 is exposed.

[0112] The back side of the bonding surface can be thinned by chemical mechanical polishing (CMP) or mechanical grinding, so that the end of the coaxial TSV structure 120 away from the bonding surface is exposed. It should be noted that after step S110, the TSV hole is a blind hole, and the function of S130 is to thin the bottom wall of the TSV hole so that the TSV hole becomes a through hole 110b, thereby exposing the end of the coaxial TSV structure 120 away from the bonding surface.

[0113] In some embodiments, Fig.29 As shown, after step S400 is completed, step S140 is performed, that is, after the bonding surface of the upper wafer and the bonding surface of the lower wafer are bonded, a thinning process is performed; such a design can reduce the probability of wafer 110 breaking to a certain extent and improve the qualified rate of the preparation of the three-dimensional interconnection transmission line 100.

[0114] S200, such as Fig.18 and Fig.26 As shown, grooves are processed on the bonding surfaces of the upper wafer and the lower wafer.

[0115] Grooves are processed on the bonding surfaces of the upper wafer and the lower wafer, so that after the upper wafer and the lower wafer are bonded, the two grooves surround and form a chamber 100a.

[0116] S300 , manufacturing a micro coaxial structure 130 on the upper wafer and / or the lower wafer.

[0117] If there is a need to manufacture micro-coaxial structures 130 on both adjacent wafers 110, the micro-coaxial structures 130 are manufactured on both wafers 110. If there is a need to manufacture micro-coaxial structures 130 on only the upper wafer of the two adjacent wafers 110, the micro-coaxial structures 130 are manufactured on the upper wafer. If there is a need to manufacture micro-coaxial structures 130 on only the lower wafer of the two adjacent wafers 110, the micro-coaxial structures 130 are manufactured on the lower wafer.

[0118] Step S300 may include steps S310 , S320 , and S330 .

[0119] S310, such as Fig. 20 and Fig.21 As shown, an insulating support bridge 132 and a TSV insulating layer extension section 1222 of the TSV insulating layer 122 are manufactured on the bonding surface where the coaxial TSV structure 120 is located.

[0120] There are various methods for making the insulating support bridge 132 and the TSV insulating layer extension 1222, and they are known to those skilled in the art. In some embodiments, photoresist is first applied to the wafer 110, followed by chemical mechanical polishing to expose the seed layer, and then negative photoresist is applied to define the pattern of the insulating support bridge 132 and the TSV insulating layer extension 1222; then exposure and development are performed to leave the insulating support bridge 132 and the TSV insulating layer extension 1222 formed by the negative photoresist.

[0121] S320, such as Fig. 22 and Fig.23 As shown, the TSV inner conductor extension section 1212 of the TSV inner conductor 121 is manufactured in the TSV insulation layer extension section 1222 .

[0122] The manufacturing methods of the TSV inner conductor extension section 1212 are also diverse and known to those skilled in the art. In some embodiments, first, a layer of photoresist is coated on the surface of the wafer 110 to define the area where the TSV inner conductor extension section 1212 needs to be made. Then, through exposure and development processing, it is ensured that the subsequent electroplating layer is formed only on the inner section 1211 of the TSV inner conductor hole. Then, electroplating treatment is performed to form the TSV inner conductor extension section 1212 on the inner section 1211 of the TSV inner conductor hole. Then, through CMP treatment (chemical mechanical polishing treatment), excess material on the surface of the wafer 110 (such as protrusions and photoresist residues that may be formed during the electroplating process) is removed to achieve global flattening of the surface of the wafer 110. Finally, all photoresists on the wafer 110 are removed.

[0123] S330, such as Fig.24As shown, the micro-coaxial inner conductor 131 is manufactured on the insulating support bridge 132 , the TSV insulating layer extending section 1222 and the TSV inner conductor extending section 1212 .

[0124] The manufacturing methods of the micro-coaxial inner conductor 131 are also diverse and known to those skilled in the art. In some embodiments, first, a layer of photoresist is coated on the surface of the wafer 110 to define the area where the micro-coaxial inner conductor 131 needs to be made. Then, through exposure and development processing, it is ensured that the subsequent electroplating layer is only formed on the insulating support bridge 132, the TSV insulating layer extension section 1222 and the TSV inner conductor extension section 1212. Then, electroplating treatment is performed to form the micro-coaxial inner conductor 131 on the insulating support bridge 132 and the TSV insulating layer extension section 1222. Then, through CMP treatment (chemical mechanical polishing treatment), excess materials on the surface of the wafer 110 (such as protrusions and photoresist residues that may be formed during the electroplating process) are removed to achieve global flatness of the surface of the wafer 110. Finally, all photoresists on the wafer 110 are removed.

[0125] S400, bonding the bonding surface of the upper wafer and the bonding surface of the lower wafer.

[0126] The bonding surface of the upper wafer is bonded to the bonding surface of the lower wafer so that the bonding surface of the upper wafer and the bonding surface of the lower wafer are tightly connected together, and external gas (such as oxygen), foreign matter (such as dust), water vapor, etc. will not enter the chamber 100a through the gap between the upper wafer and the lower wafer. In some schemes, the upper wafer and the lower wafer are bonded by Cu-Cu metal.

[0127] When the three-dimensional interconnect transmission line 100 includes three or more wafers 110 , the above steps S100 - S400 are repeated to form a multi-layer transmission structure.

[0128] The following introduction Figure 1 The method for preparing the three-dimensional interconnection transmission line 100 is shown as follows:

[0129] First, if Fig.10 and Fig.11 As shown, two TSV holes are etched on the bonding surface of the upper wafer;

[0130] Next, the TSV shielding layer 123 (such as Fig.12 and Fig.13 As shown), TSV insulation layer hole inner section 1221 (as shown Fig.14 and Fig.15 ) and the inner section 1211 of the TSV inner conductor hole (as shown Fig.16 and Fig.17 shown);

[0131] Then, if Fig.18 and Fig.19As shown, a rectangular groove is opened on the bonding surface of the upper wafer, and the rectangular groove is located between two TSV holes;

[0132] Then, if Fig. 20 and Fig.21 As shown, three insulating support bridges 132 are formed on the bonding surface of the upper wafer and are spaced apart along the length direction of the rectangular groove. The three support bridges span both sides of the rectangular groove, and a TSV insulating layer extension section 1222 is formed above the TSV insulating layer hole inner section 1221;

[0133] Then, if Fig. 22 and Fig.23 As shown, a TSV inner conductor extension section 1212 is made in a TSV insulating layer extension section 1222;

[0134] Then, if Fig.24 As shown, a micro-coaxial inner conductor 131 is manufactured on two TSV inner conductor extension sections 1212, two TSV insulating layer extension sections 1222 and three insulating support bridges 132. The middle of the micro-coaxial inner conductor 131 is supported by three insulating support bridges 132, and both ends are supported by two TSV bosses respectively, and both ends are also electrically connected to the two TSV inner conductor extension sections 1212 respectively.

[0135] Then, if Fig.25 As shown, three grooves are provided on the bonding surface of the lower wafer to avoid the insulating support bridge 132;

[0136] Then, if Fig.26 and Fig. 27 As shown, a groove for accommodating the micro-coaxial inner conductor 131 is provided on the bonding surface of the lower wafer;

[0137] Then, if Fig.28 As shown, the upper wafer and the lower wafer are Cu-Cu metal bonded;

[0138] Finally, if Fig.29 As shown, the non-bonding surface of the upper wafer is subjected to chemical mechanical polishing, so that one end of the coaxial TSV structure 120 away from the bonding surface is exposed as an external connection port to be connected to the outside world.

[0139] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0140] In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the fact that they can be implemented by ordinary technicians in this field. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0141] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A three-dimensional interconnect transmission line, It is characterized in that include: A plurality of wafers (110) are stacked in sequence, two adjacent wafers (110) are hermetically connected, and a closed chamber (100a) is formed between the two adjacent wafers (110); and at least one of the two adjacent wafers (110) is provided with a through hole (110b) that penetrates the wafer (110) and is connected to the chamber (100a); A coaxial TSV structure (120) and a micro-coaxial structure (130), wherein the micro-coaxial structure (130) is arranged in the chamber (100a), the coaxial TSV structure (120) is arranged in the through hole (110b) and is tightly connected to the inner wall of the through hole (110b), the micro-coaxial structure (130) includes a micro-coaxial inner conductor (131), the coaxial TSV structure (120) includes a TSV inner conductor (121), and the micro-coaxial inner conductor (131) is connected to the TSV inner conductor (121).

2. The three-dimensional interconnect transmission line according to claim 1, It is characterized in that Among the two adjacent wafers (110), one of the wafers (110) is provided with a first groove, and the other wafer (110) is provided with a second groove, and the first groove and the second groove are arranged opposite to each other to enclose the chamber (100a).

3. The three-dimensional interconnect transmission line according to claim 1, It is characterized in that The coaxial TSV structure (120) further comprises a TSV insulating layer (122) and a TSV shielding layer (123); the TSV insulating layer (122) is sleeved outside the TSV inner conductor (121); the TSV shielding layer (123) is sleeved outside the TSV insulating layer (122) and is located between the inner wall of the through hole (110b) and the TSV insulating layer (122).

4. The three-dimensional interconnect transmission line according to claim 3, It is characterized in that Part of the TSV insulating layer (122) protrudes from the surface of the wafer (110) and is located in the chamber (100a); the micro-coaxial inner conductor (131) is located on the TSV insulating layer (122), so that the micro-coaxial inner conductor (131) and the wafer (110) are spaced apart.

5. The three-dimensional interconnect transmission line according to any one of claims 1 to 4, It is characterized in that In two adjacent wafers (110), the through holes (110b) are provided on both wafers (110), and at least some of the through holes (110b) on the two wafers (110) are arranged opposite to each other, so that the TSV inner conductors (121) located in the oppositely arranged through holes (110b) can be connected.

6. The three-dimensional interconnect transmission line according to any one of claims 1 to 4, It is characterized in that In two adjacent wafers (110), the through holes (110b) are provided on both wafers (110), and at least some of the through holes (110b) on the two wafers (110) are staggered.

7. The three-dimensional interconnect transmission line according to any one of claims 1 to 4, It is characterized in that The micro-coaxial structure (130) further comprises an insulating support bridge (132), wherein the insulating support bridge (132) is suspended in the chamber (100a), and at least a portion of the insulating support bridge (132) is fixed between two adjacent wafers (110), and the micro-coaxial inner conductor (131) is located on the insulating support bridge (132).

8. A method for preparing a three-dimensional interconnect transmission line, It is characterized in that For preparing a three-dimensional interconnection transmission line according to any one of claims 1 to 7, the two adjacent wafers (110) are respectively an upper wafer (110) and a lower wafer (110), and the preparation method comprises: Fabricating a coaxial TSV structure (120) on the bonding surface of the upper wafer (110) and / or the lower wafer (110); Grooves are machined on the bonding surfaces of the upper wafer (110) and the lower wafer (110); Fabricating the micro-coaxial structure (130) on the upper wafer (110) and / or the lower wafer (110); The bonding surface of the upper wafer (110) and the bonding surface of the lower wafer (110) are bonded.

9. The method for preparing a three-dimensional interconnect transmission line according to claim 8, It is characterized in that The manufacturing of a coaxial TSV structure (120) on the bonding surface of the upper wafer (110) and / or the lower wafer (110) comprises: Processing TSV holes on the bonding surface; Making a TSV shielding layer (123) in the TSV hole; Manufacturing a TSV insulating layer hole inner section (1221) of the TSV insulating layer (122) in the TSV shielding layer (123); Manufacturing a TSV inner conductor hole inner section (1211) of a TSV inner conductor (121) in the TSV insulating layer (122); The back side of the bonding surface is thinned until the coaxial TSV structure (120) is exposed.

10. The method for preparing a three-dimensional interconnect transmission line according to claim 9, It is characterized in that The manufacturing of the micro-coaxial structure (130) on the upper wafer (110) and / or the lower wafer (110) comprises: Manufacturing an insulating support bridge (132) and a TSV insulating layer extension section (1222) of the TSV insulating layer (122) on the bonding surface where the coaxial TSV structure (120) is located; Manufacturing a TSV inner conductor extension section (1212) of the TSV inner conductor (121) in the TSV insulating layer extension section (1222); The upper micro-coaxial inner conductor (131) is manufactured on the insulating support bridge (132), the TSV insulating layer extension section (1222) and the TSV inner conductor extension section (1212).

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