Monolithic Integrated Diode Limiting Unit Based on Quasi-Vertical MPS and Preparation Method

Abstract

The present invention discloses a monolithic integrated diode limiting unit based on quasi-vertical MPS and a preparation method thereof. The limiting unit includes two silicon-based GaN quasi-vertical MPSs located on a silicon substrate, forming forward and reverse limiting diodes; a passivation layer covers the two MPSs and the silicon substrate; a thin-film protection resistor is located within the passivation layer; a first interconnecting metal connects the first end of the resistor to the cathode of the reverse limiting diode; a second interconnecting metal forms voltage input and output terminals, first and second reference voltage terminals, and also connects the cathode of the forward limiting diode to the first reference voltage terminal, connects the anode of the forward limiting diode, the cathode of the reverse limiting diode, and the first end of the thin-film protection resistor to the voltage output terminal, connects the anode of the reverse limiting diode to the second reference voltage terminal, and connects the second end of the resistor to the voltage input terminal 1. The diode limiting unit provided by the present invention has high voltage withstand performance and can be applied to high-power conditions.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuits, and particularly relates to a monolithic integrated diode limiting unit based on quasi-vertical MPS (Merged PIN Schottky) and a preparation method thereof. Background Art

[0002] Diode limiting units are commonly used in radio frequency systems and power electronic systems. Most power devices use high-power silicon single transistors in the form of discrete devices in diode limiting units. However, with the increasing requirements for the power handling capacity, miniaturization, and reliability of rectification systems, the existing board-level integrated diode limiting units will increasingly struggle to meet the needs of the times.

[0003] Existing diode limiting units mainly use Si-based devices, which have low device power density and are difficult to miniaturize under high-power conditions. With the increasing requirements for the efficiency, power density, and device volume of power handling equipment, Si-based devices are rapidly approaching the theoretical limits of their intrinsic material properties. In addition, the voltage application range of existing small-size diode limiting units is relatively narrow, and the breakdown voltage of the core device diode is relatively low.

[0004] Therefore, there is an urgent need for a diode limiting unit with high breakdown voltage performance that can be applied under high-power conditions. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a monolithic integrated diode limiting unit based on quasi-vertical MPS.

[0006] The technical problems to be solved by the present invention are realized through the following technical solutions:

[0007] A monolithic integrated diode limiting unit based on quasi-vertical MPS, comprising:

[0008] A silicon substrate;

[0009] Two silicon-based GaN quasi-vertical MPSs located on the silicon substrate; the two silicon-based GaN quasi-vertical MPSs respectively form a forward limiting diode and a reverse limiting diode;

[0010] A passivation layer; the passivation layer covers the two silicon-based GaN quasi-vertical MPSs and the silicon substrate;

[0011] A thin-film protection resistor; the thin-film protection resistor is located inside the passivation layer;

[0012] A first interconnect metal; the first interconnect metal is used to connect the first end of the thin-film protection resistor to the cathode of the reverse limiting diode;

[0013] The second interconnection metal; the second interconnection metal is used to form the voltage input terminal, voltage output terminal, first reference voltage terminal and second reference voltage terminal of the monolithic integrated diode limiting unit, and is also used to connect the cathode of the forward limiting diode to the first reference voltage terminal, connect the anode of the forward limiting diode, the cathode of the reverse limiting diode, and the first end of the thin film protection resistor to the voltage output terminal, connect the anode of the reverse limiting diode to the second reference voltage terminal, and connect the second end of the thin film protection resistor to the voltage input terminal.

[0014] Optionally, the silicon-based GaN quasi-vertical MPS includes: a silicon substrate, a GaN conduction layer, a GaN diffusion layer, one or more Mg-doped P-type BN field rings, a cathode ohmic metal, and an anode Schottky metal;

[0015] Wherein, the GaN conduction layer is stacked on the silicon substrate, and the GaN diffusion layer is stacked on the middle region of the upper surface of the GaN conduction layer; one or more annular grooves are provided on the top layer of the GaN diffusion layer; the plurality of annular grooves are concentrically arranged; the Mg-doped P-type BN material is deposited in the annular grooves to form the Mg-doped P-type BN field ring; the anode Schottky metal is located on the upper surface of the GaN diffusion layer and contacts the one or more Mg-doped P-type BN field rings; the cathode ohmic metal is located on the upper surface of the part of the GaN conduction layer not covered by the GaN diffusion layer and surrounds the GaN diffusion layer.

[0016] Optionally, the Mg doping concentration of the Mg-doped P-type BN field ring is 1.7×10 16 cm -3 ~3.0×10 17 cm -3 。

[0017] Optionally, the width of the Mg-doped P-type BN field ring is 2 μm to 4 μm, and the depth is 0.5 μm to 4 μm.

[0018] Optionally, when there are multiple annular grooves, the distance between adjacent annular grooves is 1 μm to 2.5 μm.

[0019] Optionally, the Si doping concentration of the GaN diffusion layer is 1.8×10 16 cm -3 ~5.0×10 17 cm -3 。

[0020] Optionally, the Si doping concentration of the GaN conduction layer is 1.0×10 18 cm -3 ~1.0×10 20 cm -3 。

[0021] The present invention also provides a preparation method of a monolithic integrated diode limiting unit based on quasi-vertical MPS, including:

[0022] Preparing two silicon-based GaN quasi-vertical structures on a silicon substrate; the two silicon-based GaN quasi-vertical structures are used to form two silicon-based GaN quasi-vertical MPSs subsequently;

[0023] Depositing a first passivation layer on the surface of the current device, and opening holes in the passivation layer to expose the anode region and the cathode region; the anode region corresponds to the anode of the silicon-based GaN quasi-vertical MPS; the cathode region corresponds to the cathode of the silicon-based GaN quasi-vertical MPS;

[0024] Depositing anode Schottky metal in the anode region and depositing cathode ohmic metal in the cathode region, so that the two silicon-based GaN quasi-vertical structures form two silicon-based GaN quasi-vertical MPSs, and depositing a thin-film protection resistor on the surface of the current passivation layer; wherein, the two silicon-based GaN quasi-vertical MPSs serve as a forward limiting diode and a reverse limiting diode respectively;

[0025] Depositing a second passivation layer on the surface of the current device, and opening holes in the passivation layer to expose the anode and cathode of the forward limiting diode, the anode and cathode of the reverse limiting diode, and the first end and the second end of the thin-film protection resistor;

[0026] Preparing a first interconnecting metal on the current device to connect the first end of the thin-film protection resistor to the cathode of the reverse limiting diode;

[0027] Depositing a third passivation layer on the surface of the current device, and opening holes in the passivation layer to expose the anode and cathode of the forward limiting diode, the anode and cathode of the reverse limiting diode, and the second end of the thin-film protection resistor;

[0028] Preparing a second interconnecting metal on the current device to form the voltage input terminal, the voltage output terminal, the first reference voltage terminal and the second reference voltage terminal of the monolithic integrated diode limiting unit, and connecting the cathode of the forward limiting diode to the first reference voltage terminal, connecting the anode of the forward limiting diode, the cathode of the reverse limiting diode, and the first end of the thin-film protection resistor to the voltage output terminal, connecting the anode of the reverse limiting diode to the second reference voltage terminal, and connecting the second end of the thin-film protection resistor to the voltage input terminal.

[0029] Optionally, preparing two silicon-based GaN quasi-vertical structures on a silicon substrate, including:

[0030] A GaN conduction layer and a GaN diffusion layer are sequentially epitaxially grown on a silicon substrate. The GaN diffusion layer is mesa-etched, and device isolation etching is performed on the etched GaN diffusion layer and the GaN conduction layer to form two silicon-based gallium nitride substrates; in the silicon-based gallium nitride substrates, the GaN diffusion layer is stacked on the middle region of the GaN conduction layer;

[0031] One or more annular grooves are etched on the top layer of the GaN diffusion layer of each of the two silicon-based gallium nitride substrates; wherein, a plurality of the annular grooves are concentrically arranged;

[0032] Mg-doped P-type BN material is deposited along the surface of the current GaN diffusion layer until the Mg-doped P-type BN material in each annular groove is higher than the upper edge of the annular groove, and thermal annealing is performed to activate the impurities;

[0033] The Mg-doped P-type BN material higher than the upper edge of the annular groove is removed, so that the remaining Mg-doped P-type BN material forms an Mg-doped P-type BN field limiting ring in the annular groove, and two silicon-based GaN quasi-vertical structures are obtained.

[0034] Compared with the prior art, the monolithic integrated diode limiting unit based on quasi-vertical MPS provided by the present invention has the following beneficial effects:

[0035] (1) In the prior art, most power devices still use high-power silicon single tubes in the form of discrete devices in the diode limiting unit. However, with the increasing requirements for the power handling capacity, equipment miniaturization, and equipment reliability of the rectification system, the existing board-level integrated diode limiting unit will increasingly struggle to meet the needs of the times. In the monolithic integrated diode limiting unit based on quasi-vertical MPS provided by the present invention, by integrating two silicon-based GaN quasi-vertical MPSs and thin-film protection resistors on a monolithic silicon substrate, and forming a monolithic integrated diode limiting unit based on GaN devices through interconnecting metals, the device integration degree is improved, the circuit volume is greatly reduced, it has smaller parasitic effects, higher power density, and can operate stably under more complex working conditions. Its excellent electrical performance and stability are suitable for applications in high-frequency, high-power, strong radiation and other occasions, as well as high-power power conversion systems with limited volume.

[0036] (2) Most of the diode limiting units in the prior art are made of Si-based materials. However, with the increasing requirements for the efficiency, power density, and device volume of power processing equipment, Si-based devices are rapidly approaching the theoretical limits of their intrinsic material properties. The monolithic integrated diode limiting unit provided by the present invention is a GaN device. Compared with Si-based materials, GaN has a larger bandgap width, a higher critical breakdown electric field, and a higher saturation velocity. Therefore, the monolithic integrated diode limiting unit provided by the present invention has better electrical characteristics, and its thermal conductivity, temperature stability, corrosion resistance, etc. are far superior to Si devices, and it can work stably under more complex working conditions.

[0037] (3) The voltage application range of the existing small-size diode limiting unit is relatively narrow, and the breakdown voltage of the core device diode is relatively low. The monolithic integrated diode limiting unit provided by the present invention uses silicon-based GaN material. While reducing the circuit cost, a quasi-vertical diode with an improved Mg-doped P-type BN MPS field limiting ring is used to replace the traditional Schottky diode. By utilizing the high breakdown field strength of the BN material and the electric field regulation ability of the MPS ring structure, the breakdown voltage level of the Schottky diode is greatly improved while ensuring the forward conduction ability of the diode as much as possible, broadening the power application window of the miniaturized integrated diode limiting unit, improving the breakdown voltage of the diode, and enhancing the power processing ability of the diode limiting unit.

[0038] The following will further elaborate on the present invention in conjunction with the accompanying drawings. Description of the Drawings

[0039] Figure 1 is a three-dimensional structural schematic diagram of a monolithic integrated diode limiting unit based on a quasi-vertical MPS provided by an embodiment of the present invention;

[0040] Figure 2 is Figure 1 a top view of the diode limiting unit shown;

[0041] Figure 3 is a structural schematic diagram of a silicon-based gallium nitride substrate exemplarily shown in an embodiment of the present invention;

[0042] Figure 4 is a three-dimensional structural schematic diagram of a silicon-based GaN quasi-vertical MPS exemplarily shown in an embodiment of the present invention;

[0043] Figure 5 is Figure 4 a cross-sectional view of the silicon-based GaN quasi-vertical MPS shown;

[0044] Figure 6 is a circuit schematic diagram of a monolithic integrated diode limiting unit based on a quasi-vertical MPS provided by an embodiment of the present invention;

[0045] Figure 7 is shown in Figure 6 the working principle of the circuit shown;

[0046] Figures 8 to 19 is a flowchart of a preparation method of a monolithic integrated diode limiting unit based on quasi-vertical MPS provided by an embodiment of the present invention. Detailed implementation manners

[0047] The present invention will be further described in detail below with reference to specific embodiments, but the implementation manners of the present invention are not limited thereto.

[0048] In order to enable the diode limiting unit to have high breakdown voltage performance and be applicable to high-power conditions, an embodiment of the present invention provides a monolithic integrated diode limiting unit based on quasi-vertical MPS. Refer to Figure 1 and Figure 2 shown, the device includes: a silicon substrate (Si-substrate) 10, two silicon-based GaN quasi-vertical MPSs located on the silicon substrate 10, a passivation layer 20, a thin-film protection resistor R, a first interconnect metal, and a second interconnect metal.

[0049] Among them, the two silicon-based GaN quasi-vertical MPSs respectively form a forward limiting diode D1 and a reverse limiting diode D2. Here, both limiting units adopt a quasi-vertical diode structure, which is convenient for using on-chip wiring to connect their circuits, thereby realizing the circuit construction of the entire monolithic integrated diode limiting unit.

[0050] Optionally, in one implementation manner, the silicon-based GaN quasi-vertical MPS may include: a silicon substrate 10, a GaN conduction layer, a GaN diffusion layer, a cathode ohmic metal, and an anode Schottky metal.

[0051] Among them, the GaN conduction layer (N+GaN) is stacked on the silicon substrate, and the GaN diffusion layer (N GaN) is stacked on the middle region of the upper surface of the GaN conduction layer to form a silicon-based gallium nitride sink, as Figure 3 ; the anode Schottky metal (Anode) is located on the upper surface of the GaN diffusion layer; the cathode ohmic metal (Cathode) is located on the upper surface of the part of the GaN conduction layer not covered by the GaN diffusion layer and surrounds the GaN diffusion layer, as Figure 4 .

[0052] In another implementation manner, refer to Figure 4 and Figure 5 , the silicon-based GaN quasi-vertical MPS may include: a silicon substrate 10, a GaN conduction layer, a GaN diffusion layer, one or more Mg-doped P-type BN field rings, a cathode ohmic metal, and an anode Schottky metal.

[0053] Among them, the GaN conduction layer is stacked on the silicon substrate 10, and the GaN diffusion layer is stacked on the middle region of the upper surface of the GaN conduction layer; one or more annular grooves are provided on the top layer of the GaN diffusion layer; the multiple annular grooves are concentrically arranged; Mg-doped P-type BN material is deposited in the annular grooves to form an Mg-doped P-type BN field limiting ring; the anode Schottky metal (Anode) is located on the upper surface of the GaN diffusion layer and contacts one or more Mg-doped P-type BN field limiting rings; the cathode ohmic metal (Cathode) is located on the upper surface of the part of the GaN conduction layer not covered by the GaN diffusion layer and surrounds the GaN diffusion layer.

[0054] Preferably, the Si doping concentration of the GaN conduction layer is 1.0×10 18 cm -3 ~1.0×10 20 cm -3 。

[0055] Preferably, the Si doping concentration of the GaN diffusion layer is 1.8×10 16 cm -3 ~5.0×10 17 cm -3 。

[0056] Preferably, the Mg doping concentration of the Mg-doped P-type BN field limiting ring is 1.7×10 16 cm -3 ~3.0×10 17 cm -3 。

[0057] Preferably, the width of the Mg-doped P-type BN field limiting ring is 2 μm to 4 μm, and the depth is 0.5 μm to 4 μm. In practice, the specific width and depth of the Mg-doped P-type BN field limiting ring can be determined according to the breakdown voltage and forward conduction ability, and the number of rings can be determined according to the current-carrying requirement, and can be one or more. Among them, when there are multiple annular grooves, the distance between adjacent annular grooves is preferably 1 μm to 2.5 μm.

[0058] Continue to refer to Figure 1 and Figure 2 , the passivation layer 20 covers the two silicon-based GaN quasi-vertical MPSs and the silicon substrate 10; specifically, the passivation layer 20 is formed by multiple growths, which covers the silicon-based GaN quasi-vertical MPS as a whole. On the one hand, it realizes the protection and electrical isolation of the device, and on the other hand, it makes the upper surface of the overall structure of the diode limiting unit form a relatively flat plane, so as to perform metal interconnection between internal devices on this plane, which will be described in detail later.

[0059] Preferably, the material of the passivation layer 20 can be SiN, but it is not limited thereto.

[0060] Refer toFigure 1 and Figure 2 , the thin film protection resistor is located inside the passivation layer; the material forming the thin film protection resistor can be TaN, NiCr, etc. In practice, according to the required resistance value, different resistance values can be achieved by setting different aspect ratios, so as to obtain the corresponding current-carrying capacity.

[0061] The first interconnect metal is used to connect the first end of the thin film protection resistor R to the cathode of the reverse limiting diode D2. The embodiment of the present invention does not limit the material of the first interconnect metal. In practice, the first interconnect metal is located inside the passivation layer.

[0062] The second interconnect metal is used to form the voltage input terminal 1, voltage output terminal 2, first reference voltage terminal 3, and second reference voltage terminal 4 of the monolithic integrated diode limiting unit, see Figure 1 and Figure 2 ; the second interconnect metal is also used to connect the cathode of the forward limiting diode D1 to the first reference voltage terminal 3, connect the anode of the forward limiting diode D1, the cathode of the reverse limiting diode D2, and the first end of the thin film protection resistor R to the voltage output terminal 2, connect the anode of the reverse limiting diode D2 to the second reference voltage terminal 4, and connect the second end of the thin film protection resistor R to the voltage input terminal 1.

[0063] In practice, the second interconnect metal includes two parts. One part is located on the top of the passivation layer, including the metal forming the voltage input terminal 1, voltage output terminal 2, first reference voltage terminal 3, and second reference voltage terminal 4, and also including the metal connecting the anode of the forward limiting diode D1 to the voltage output terminal 2; the other part of the second interconnect metal is located inside the passivation layer and is used to connect the part of the second interconnect metal located on the top of the passivation layer to the underlying first interconnect metal, including: the metal connecting the cathode of the forward limiting diode D1 to the first reference voltage terminal 3, the metal connecting the first interconnect metal to the anode of the forward limiting diode D1 and the voltage output terminal 2, and the metal connecting the second end of the thin film protection resistor R to the voltage input terminal 1.

[0064] Thus, through the first interconnect metal and the second interconnect metal, the thin film protection resistor and the two limiting diodes are connected together to form a circuit as shown in Figure 6 shown. Based on the circuit shown in Figure 6 shown, the working principle of the monolithic integrated diode limiting unit provided by the embodiment of the present invention will be described below.

[0065] See Figure 7, assume that the turn-on voltages of the forward clamping diode D1 and the reverse clamping diode D2 are both Vth. The second reference voltage terminal 4 is connected to the forward clamping reference voltage Uf, the first reference voltage terminal 3 is connected to the reverse clamping reference voltage Ur, the input voltage of the voltage input terminal 1 is Uin, which is a sinusoidal AC signal with an amplitude of U0.

[0066] When the input voltage Uin of the voltage input terminal 1 is in the positive polarity cycle, the reverse clamping diode D2 must be reverse cut-off. When Uin is less than the sum of Uf and Vth, at this time the forward clamping diode D1 remains cut-off, and the voltage of the voltage output port 2 is the same as the voltage of the voltage input port 1. When the value of Uin is greater than the sum of Uf and Vth, at this time the forward clamping diode D1 conducts. Due to the clamping characteristic of the diode, the voltage of the anode of D1 is limited to Vth + Uf, that is, the output voltage remains unchanged, triggering clamping. As the input voltage value gradually drops below the sum of Uf and Vth, the forward clamping diode D1 is cut off again, and the voltage of the voltage output terminal 2 is synchronized with the voltage of the voltage input terminal 1 again, completing the forward clamping process.

[0067] When the input voltage Uin of the voltage input terminal 1 is in the negative polarity cycle, the forward clamping diode D1 is reverse cut-off. When Uin is greater than the sum of Ur and Vth, at this time the reverse clamping diode D2 remains cut-off, and the voltage of the voltage output port 2 is the same as the voltage of the voltage input port 1. When the value of Uin is less than the sum of Ur and Vth, at this time the reverse clamping diode D2 conducts. Due to the clamping characteristic of the diode, the voltage of the cathode of D2 is limited to Vth + Ur, that is, the output voltage remains unchanged, triggering clamping. As Uin gradually rises below the sum of Ur and Vth, the reverse clamping diode D2 is cut off again, and the voltage of the voltage output terminal 2 is synchronized with the voltage of the voltage input terminal 1 again, completing the reverse clamping process.

[0068] In the monolithic integrated diode clamping unit based on quasi-vertical MPS provided by the embodiment of the present invention, by integrating two silicon-based GaN quasi-vertical MPSs and thin-film protection resistors on a monolithic silicon substrate, and forming a monolithic integrated diode clamping unit based on GaN devices through interconnecting metals, the device integration degree is improved, the circuit volume is greatly reduced, it has smaller parasitic effects and higher power density, and can work stably under more complex working conditions. Its excellent electrical performance and stability can be suitable for applications in high-frequency, high-power, strong radiation and other occasions as well as high-power power conversion systems with limited volume.

[0069] The monolithic integrated diode limiting unit provided by the embodiment of the present invention is a GaN device. Compared with Si-based materials, GaN has a larger bandgap width, a higher critical breakdown electric field, and a higher saturation velocity. Therefore, the monolithic integrated diode limiting unit provided by the present invention has better electrical characteristics, and its thermal conductivity, temperature stability, corrosion resistance, etc. are far superior to Si devices, and it can work stably under more complex working conditions.

[0070] The monolithic integrated diode limiting unit provided by the embodiment of the present invention uses a silicon-based GaN material. While reducing the circuit cost, a quasi-vertical diode with an improved Mg-doped P-type BN MPS field limiting ring is used to replace the traditional Schottky diode. By utilizing the high breakdown field strength of the BN material and the electric field regulation ability of the MPS ring structure, the breakdown voltage level of the Schottky diode is greatly improved while ensuring the forward conduction ability of the diode as much as possible, broadening the power application window of the miniaturized integrated diode limiting unit, improving the breakdown voltage of the diode, and enhancing the power handling ability of the diode limiting unit.

[0071] Based on the same inventive concept, the embodiment of the present invention also provides a preparation method of a monolithic integrated diode limiting unit based on a quasi-vertical MPS, including the following steps:

[0072] Step 1: Prepare two silicon-based GaN quasi-vertical structures on a silicon substrate 10; these two silicon-based GaN quasi-vertical structures are used to form two silicon-based GaN quasi-vertical MPSs subsequently.

[0073] Specifically, preparing two silicon-based GaN quasi-vertical structures on a silicon substrate 10 includes:

[0074] (1) Epitaxially grow a GaN conduction layer and a GaN diffusion layer on the silicon substrate 10 in sequence, perform mesa etching on the GaN diffusion layer, as shown in Figure 8 subfigure (a); then perform device isolation etching on the etched GaN diffusion layer and GaN conduction layer, as shown in Figure 8 subfigure (b), thereby forming two silicon-based gallium nitride substrates; in this silicon-based gallium nitride substrate, the GaN diffusion layer is stacked in the middle region of the GaN conduction layer.

[0075] (2) Etch one or more annular grooves on the top layer of the GaN diffusion layer of each of the two silicon-based gallium nitride substrates, as shown in Figure 9 subfigure (c); among them, multiple annular grooves are concentrically arranged, see Figure 5 ;

[0076] (3) Deposit Mg-doped P-type BN material along the current GaN diffusion layer surface until the Mg-doped P-type BN material in each annular groove is higher than the upper edge of the annular groove, and perform thermal annealing to activate impurities, as shown in Figure 9 subfigure (d).

[0077] (4) Remove the Mg-doped P-type BN material that is higher than the upper edge of the annular groove, so that the remaining Mg-doped P-type BN material forms a Mg-doped P-type BN field limiting ring in the annular groove, obtaining two silicon-based GaN quasi-vertical structures, as shown in Figure 10 subfigure (e) in

[0078] Step 2: Deposit the first passivation layer 20 on the surface of the current device, as shown in Figure 10 subfigure (f) in ; Open holes in this passivation layer to expose the anode region and the cathode region, as shown in Figure 11 subfigure (g) in ; The anode region corresponds to the anode of the silicon-based GaN quasi-vertical MPS; the cathode region corresponds to the cathode of the silicon-based GaN quasi-vertical MPS.

[0079] Among them, the anode region is located on the upper surface of the GaN diffusion layer and includes the regions where each Mg-doped P-type BN field limiting ring is located; the cathode region is located on the upper surface of the part of the GaN conducting layer that is not covered by the GaN diffusion layer and surrounds the GaN diffusion layer.

[0080] Step 3: Deposit anode Schottky metal in the anode region and cathode ohmic metal in the cathode region, so that the two silicon-based GaN quasi-vertical structures form two silicon-based GaN quasi-vertical MPSs, and deposit a thin film protection resistor on the surface of the current passivation layer.

[0081] Specifically, first deposit Schottky metal in the anode region. This anode Schottky metal is located on the upper surface of the GaN diffusion layer and contacts each Mg-doped P-type BN field limiting ring, as shown in Figure 11 subfigure (h) in ; Exemplarily, the anode Schottky metal is, for example, a Ni / Au laminated structure, but is not limited thereto.

[0082] Then, deposit cathode ohmic metal in the cathode region. This cathode ohmic metal is located on the upper surface of the part of the GaN conducting layer that is not covered by the GaN diffusion layer and surrounds the GaN diffusion layer, as shown in Figure 12 subfigure (i) in ; Exemplarily, this cathode ohmic metal is, for example, a Ti / Al / Ni / Au laminated structure, and is also not limited thereto.

[0083] Thus, the two silicon-based GaN quasi-vertical structures form two silicon-based GaN quasi-vertical MPSs, and these two silicon-based GaN quasi-vertical MPSs serve as the forward limiting diode D1 and the reverse limiting diode D2 respectively.

[0084] Then, deposit a thin film protection resistor R beside the two silicon-based GaN quasi-vertical MPSs, as shown in Figure 13 .

[0085] Step 4: Deposit the second passivation layer 20 on the surface of the current device, as shown in Figure 14; Open holes in the passivation layer to expose the anode and cathode of the forward clamping diode D1, the anode and cathode of the reverse clamping diode D2, and the first end and second end of the thin-film protection resistor R, as shown in Figure 15 .

[0086] Step Five: Prepare the first interconnecting metal on the current device to connect the first end of the thin-film protection resistor to the cathode of the reverse clamping diode D2, as shown in Figure 16 .

[0087] Figure 16 In [reference], the first interconnecting metal is obtained through the first-layer metal interconnection.

[0088] It should be noted that Figure 16 and subsequent Figures 17 to 19 The metal interconnection lines shown are only for indicating the preparation timing and approximate location of the interconnecting metal, and do not represent the actual metal interconnection relationship. The actual metal interconnection relationship is subject to what is shown in Figure 6 , Figure 1 , Figure 2 .

[0089] Step Six: Deposit the third passivation layer 20 on the surface of the current device, as shown in Figure 17 ; Open holes in the passivation layer to expose the anode and cathode of the forward clamping diode D1, the anode and cathode of the reverse clamping diode D2, and the second end of the thin-film protection resistor, as shown in Figure 18 .

[0090] Step Seven: Prepare the second interconnecting metal on the current device to form the voltage input terminal 1, voltage output terminal 2, first reference voltage terminal 3, and second reference voltage terminal 4 of the monolithic integrated diode clamping unit, and connect the cathode of the forward clamping diode D1 to the first reference voltage terminal 3, connect the anode of the forward clamping diode D1, the cathode of the reverse clamping diode D2, and the first end of the thin-film protection resistor to the voltage output terminal 2, connect the anode of the reverse clamping diode D2 to the second reference voltage terminal 4, and connect the second end of the thin-film protection resistor to the voltage input terminal 1, as shown in Figure 19 .

[0091] Figure 19 In [reference], the second interconnecting metal is obtained through the second-layer metal interconnection.

[0092] It should be noted that for the preparation method embodiments, since the structures prepared are basically similar to those of the device embodiments, the description is relatively simple. For related parts, please refer to the partial description of the device embodiments.

[0093] It should be noted that the terms "first", "second", etc. are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present disclosure.

[0094] In the description of this specification, the description referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0095] Although the present application has been described in connection with various embodiments herein, however, in the process of implementing the claimed present application, those skilled in the art can understand and achieve other variations of the disclosed embodiments by viewing the accompanying drawings and the disclosure. In the description of the present invention, the term "including" does not exclude other components or steps, the term "a" or "one" does not exclude a plurality of cases, and the meaning of "a plurality" is two or more, unless otherwise specifically defined. In addition, certain measures are described in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0096] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by terms such as "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

[0097] In the present invention, unless otherwise clearly specified or limited, the terms "mounted", "connected", "coupled", "fixed", etc. shall be construed in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral one; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0098] In the present invention, unless otherwise clearly specified or limited, the first feature being "above" or "below" the second feature may include the direct contact between the first and second features, or may include the situation where the first and second features are not in direct contact but in contact through additional features therebetween. Moreover, the first feature being "above", "over" and "on top of" the second feature includes that the first feature is directly above and obliquely above the second feature, or merely means that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "beneath" and "underneath" the second feature includes that the first feature is directly below and obliquely below the second feature, or merely means that the horizontal height of the first feature is lower than that of the second feature.

[0099] The above content is a further detailed description of the present invention in combination with specific preferred embodiments. It cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A monolithic integrated diode limiter unit based on quasi-vertical MPS, characterized in that Comprising: A silicon substrate; Two silicon-based GaN quasi-vertical MPSs located on the silicon substrate; The two silicon-based GaN quasi-vertical MPSs respectively form a forward limiting diode and a reverse limiting diode; A passivation layer; the passivation layer covers the two silicon-based GaN quasi-vertical MPSs and the silicon substrate; A thin-film protection resistor; the thin-film protection resistor is located inside the passivation layer; A first interconnecting metal; the first interconnecting metal is used to connect the first end of the thin-film protection resistor to the cathode of the reverse limiting diode; A second interconnecting metal; the second interconnecting metal is used to form the voltage input terminal, voltage output terminal, first reference voltage terminal, and second reference voltage terminal of the monolithic integrated diode limiting unit, and is also used to connect the cathode of the forward limiting diode to the first reference voltage terminal, connect the anode of the forward limiting diode, the cathode of the reverse limiting diode, and the first end of the thin-film protection resistor to the voltage output terminal, connect the anode of the reverse limiting diode to the second reference voltage terminal, and connect the second end of the thin-film protection resistor to the voltage input terminal; The silicon-based GaN quasi-vertical MPS comprises: a silicon substrate, a GaN conducting layer, a GaN diffusion layer, one or more Mg-doped P-type BN field limiting rings, a cathode ohmic metal, and an anode Schottky metal; Wherein, the GaN conducting layer is stacked on the silicon substrate, and the GaN diffusion layer is stacked on the middle region of the upper surface of the GaN conducting layer; one or more annular grooves are provided on the top layer of the GaN diffusion layer; the plurality of annular grooves are concentrically arranged; Mg-doped P-type BN material is deposited in the annular grooves to form the Mg-doped P-type BN field limiting rings; the anode Schottky metal is located on the upper surface of the GaN diffusion layer and contacts the one or more Mg-doped P-type BN field limiting rings; the cathode ohmic metal is located on the upper surface of the part of the GaN conducting layer not covered by the GaN diffusion layer and surrounds the GaN diffusion layer.

2. The monolithic integrated diode limiting unit based on quasi-vertical MPS according to claim 1, wherein The Mg doping concentration of the Mg-doped P-type BN field limiting ring is 1.7×10 16 cm -3 ~3.0×10 17 cm -3 .

3. The monolithic integrated diode limiting unit based on quasi-vertical MPS according to claim 1, wherein The width of the Mg-doped P-type BN field limiting ring is 2 μm to 4 μm, and the depth is 0.5 μm to 4 μm.

4. The monolithic integrated diode limiting unit based on quasi-vertical MPS according to claim 1, characterized in that When there are multiple annular grooves, the spacing between adjacent annular grooves is 1 μm to 2.5 μm.

5. The monolithic integrated diode limiting unit based on quasi-vertical MPS according to claim 1, characterized in that, The Si doping concentration of the GaN diffusion layer is 1.8×10 16 cm -3 ~5.0×10 17 cm -3 .

6. The monolithic integrated diode limiting unit based on quasi-vertical MPS according to claim 1, wherein The Si doping concentration of the GaN conduction layer is 1.0×10 18 cm -3 ~1.0×10 20 cm -3 .

7. A preparation method of a monolithic integrated diode limiting unit based on quasi-vertical MPS, characterized in that, Comprising: Fabricating two silicon-based GaN quasi-vertical structures on a silicon substrate; The two silicon-based GaN quasi-vertical structures are used to subsequently form two silicon-based GaN quasi-vertical MPSs; Depositing a first passivation layer on the surface of the current device, and opening holes in the first passivation layer to expose the anode region and the cathode region; The anode region corresponds to the anode of the silicon-based GaN quasi-vertical MPS; the cathode region corresponds to the cathode of the silicon-based GaN quasi-vertical MPS; Depositing an anode Schottky metal in the anode region and depositing a cathode ohmic metal in the cathode region, so that the two silicon-based GaN quasi-vertical structures form two silicon-based GaN quasi-vertical MPSs, and depositing a thin-film protection resistor on the surface of the current first passivation layer; wherein, the two silicon-based GaN quasi-vertical MPSs respectively serve as a forward limiting diode and a reverse limiting diode; Deposit a second passivation layer on the current device surface, and open holes in the second passivation layer to expose the anode and cathode of the forward limiting diode, the anode and cathode of the reverse limiting diode, and the first end and the second end of the thin-film protection resistor; Fabricate a first interconnect metal on the current device to connect the first end of the thin-film protection resistor to the cathode of the reverse limiting diode; Deposit a third passivation layer on the current device surface, and open holes in the third passivation layer to expose the anode and cathode of the forward limiting diode, the anode and cathode of the reverse limiting diode, and the second end of the thin-film protection resistor; Fabricate a second interconnect metal on the current device to form the voltage input terminal, the voltage output terminal, the first reference voltage terminal and the second reference voltage terminal of the monolithic integrated diode limiting unit, connect the cathode of the forward limiting diode to the first reference voltage terminal, connect the anode of the forward limiting diode, the cathode of the reverse limiting diode and the first end of the thin-film protection resistor to the voltage output terminal, connect the anode of the reverse limiting diode to the second reference voltage terminal, and connect the second end of the thin-film protection resistor to the voltage input terminal; Fabricate two silicon-based GaN quasi-vertical structures on a silicon substrate, including: Epitaxially grow a GaN conduction layer and a GaN diffusion layer on the silicon substrate in sequence, perform mesa etching on the GaN diffusion layer, and perform device isolation etching on the etched GaN diffusion layer and the GaN conduction layer to form two silicon-based gallium nitride substrates; in the silicon-based gallium nitride substrate, the GaN diffusion layer is stacked on the middle region of the GaN conduction layer; Etch one or more annular grooves on the top layer of the GaN diffusion layer of each of the two silicon-based gallium nitride substrates; wherein, a plurality of the annular grooves are concentrically arranged; Deposit Mg-doped P-type BN material along the surface of the current GaN diffusion layer until the Mg-doped P-type BN material in each annular groove protrudes above the upper edge of the annular groove, and perform thermal annealing to activate impurities; Remove the Mg-doped P-type BN material protruding above the upper edge of the annular groove, so that the remaining Mg-doped P-type BN material forms an Mg-doped P-type BN field limiting ring in the annular groove, and two silicon-based GaN quasi-vertical structures are obtained.

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