Semiconductor device and preparation method thereof

Abstract

The invention discloses a semiconductor device and a preparation method thereof, and is applied to the technical field of semiconductor devices. The functional layer is located on the surface of one side of the substrate; at least one main transistor and at least one auxiliary transistor are formed on the functional layer; the source end of the main transistor is connected with the drain end of the auxiliary transistor; the source end of the auxiliary transistor is grounded, and the gate end of the auxiliary transistor is vacant or grounded; the gate width of the auxiliary transistor is larger than that of the main transistor. An additional auxiliary transistor is cascaded to a main transistor to form a cascode structure, so that the adjustment of an impedance point is realized. The auxiliary transistor is connected in series to realize voltage reduction, so that the power matching difficulty of the device is reduced, and the main transistor is easy to match. Meanwhile, the auxiliary transistor connected in series with the source electrode of the main transistor is in a normally-open state, so that the power amplifier efficiency and gain of the main transistor are not influenced, and the performance of the device is ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a semiconductor device and a method for preparing the semiconductor device. Background Art

[0002] Semiconductor power devices or chips are the foundation of contemporary wireless communications, the Internet of Everything, and the smart world. As a type of semiconductor power device, GaN HEMT (High electron mobility transistor) devices are often used in the design of high-frequency, high-power, and high-efficiency RF (Radio Frequency Signal) devices due to their very high electron mobility and excellent high-frequency characteristics. They are widely used in communications, radar, satellite communications, wireless television and other fields.

[0003] GaN HEMT takes into account the high power density, high efficiency and high frequency characteristics of GaN devices. However, it also has natural disadvantages in GaN low-power, high-efficiency PA (power amplifier) ​​applications. The reason is that the impedance of low-power devices is very large and is often located in the high reflection area of ​​the Smith chart. The impedance is extremely sensitive, which makes the input and output matching network design of the power amplifier extremely difficult and there is a problem of difficulty in matching design.

[0004] Therefore, how to provide a technical solution that can ensure the high frequency and high efficiency characteristics of the device while keeping the device impedance point away from the high reflection area of ​​the Smith chart is an urgent problem to be solved by those skilled in the art. Summary of the invention

[0005] An object of the present invention is to provide a semiconductor device which can keep the impedance point of the device away from the high reflection area of ​​the Smith chart while ensuring the high frequency and high efficiency characteristics of the device; another object of the present invention is to provide a method for preparing a semiconductor device which can keep the impedance point of the device away from the high reflection area of ​​the Smith chart while ensuring the high frequency and high efficiency characteristics of the device.

[0006] In order to solve the above technical problems, the present invention provides a semiconductor device, comprising:

[0007] substrate;

[0008] A functional layer is located on the surface of one side of the substrate; the functional layer is formed with at least one main transistor and at least one auxiliary transistor; the source end of the main transistor is connected to the drain end of the auxiliary transistor; the source end of the auxiliary transistor is grounded, and the gate end of the auxiliary transistor is vacant or grounded;

[0009] The gate width of the auxiliary transistor is greater than the gate width of the main transistor.

[0010] Optionally, a ratio of the gate width of the main transistor to the gate width of the auxiliary transistor ranges from 1:1.1 to 1:1.2.

[0011] Optionally, the functional layer includes an epitaxial layer located on a surface of one side of the substrate, and the epitaxial layer forms a two-dimensional electron gas in an active region;

[0012] The active region includes a first active region located in the main transistor and a second active region located in the auxiliary transistor, and the length of the second active region along the extension direction of the gate electrode is greater than the length of the first active region along the extension direction of the gate electrode. Optionally, the active region is an axisymmetric shape, the first active region is a rectangle, the second active region is a rectangle, the long side of the first active region is parallel to the long side of the second active region, and the gate electrode is arranged along the wide side direction of the first active region and the wide side direction of the second active region.

[0013] Optionally, a first air bridge is provided on the side of the epitaxial layer facing away from the substrate, and the first air bridge is in contact with the source electrode of the main transistor and the drain electrode of the auxiliary transistor, and the first air bridge is isolated from the drain electrode of the main transistor, the gate electrode of the main transistor, the source electrode of the auxiliary transistor, and the gate electrode of the auxiliary transistor.

[0014] Optionally, a common electrode is provided at the junction of the first active area and the second active area, and the portion of the common electrode located in the first active area serves as the source electrode of the main transistor, and the portion of the common electrode located in the second active area serves as the drain electrode of the auxiliary transistor.

[0015] Optionally, a first drain contact electrode is provided on one side of the first active region, and a first gate contact electrode is provided on the other side; the first drain contact electrode is in contact with the drain electrode of the main transistor, and the first gate contact electrode is in contact with the gate electrode of the main transistor.

[0016] Optionally, a second source contact electrode is provided on one side of the second active region, and a second gate contact electrode is provided on the other side; the second source contact electrode is in contact with the source electrode of the auxiliary transistor, and the second gate contact electrode is in contact with the gate electrode of the auxiliary transistor.

[0017] Optionally, a ground layer is provided on the side of the substrate facing away from the functional layer, a first back hole extending to the second source contact electrode is provided in a region of the side of the substrate facing away from the functional layer corresponding to the second source contact electrode, and the second source contact electrode is electrically connected to the ground layer through the first back hole;

[0018] And / or, a second back hole extending to the second gate contact electrode is provided in a region of the substrate opposite to the functional layer and corresponding to the second gate contact electrode, and the second gate contact electrode is electrically connected to the ground layer through the second back hole.

[0019] Optionally, a second drain contact electrode is provided on one side of the second active region, and a second gate contact electrode is provided on the other side; the second drain contact electrode is in contact with the drain electrode of the auxiliary transistor, and the second gate contact electrode is in contact with the gate electrode of the auxiliary transistor.

[0020] Optionally, a second air bridge is provided on a side of the first active region facing away from the substrate, the second air bridge is in contact with the source electrode of the main transistor, and the second air bridge is isolated from the drain electrode of the main transistor and the gate electrode of the main transistor;

[0021] The second air bridge is connected to the second drain contact electrode via a connecting line;

[0022] And / or, a third air bridge is provided on the side of the second active region facing away from the substrate, the third air bridge is in contact with the source electrode of the auxiliary transistor, and the third air bridge is isolated from the drain electrode of the auxiliary transistor and the gate electrode of the auxiliary transistor.

[0023] Optionally, a ground layer is provided on the side of the substrate facing away from the functional layer, and a third back hole extending to the second source electrode is provided in the area corresponding to the source electrode of the auxiliary transistor on the side of the substrate facing away from the functional layer, and the source electrode of the auxiliary transistor is interconnected with the ground layer through the third back hole.

[0024] Optionally, the second gate electrode and the second source electrode are connected to each other.

[0025] This embodiment also provides a method for preparing a semiconductor device, comprising:

[0026] obtaining a substrate;

[0027] A functional layer is arranged on the surface of one side of the substrate to make the semiconductor device; the functional layer is formed with at least one main transistor and at least one auxiliary transistor; the source end of the main transistor is connected to the drain end of the auxiliary transistor; the source end of the auxiliary transistor is grounded, and the gate end of the auxiliary transistor is vacant or grounded; the gate width of the auxiliary transistor is greater than the gate width of the main transistor.

[0028] Optionally, providing a functional layer on the surface of one side of the substrate includes:

[0029] Disposing an epitaxial layer on one side surface of the substrate;

[0030] An active region is provided based on the epitaxial layer; the epitaxial layer forms a two-dimensional electron gas in the active region; the active region includes a first active region located in the main transistor and a second active region located in the auxiliary transistor, and a length of the second active region along a gate electrode extension direction is greater than a length of the first active region along a gate electrode extension direction;

[0031] The main transistor is manufactured based on the first active region, and the auxiliary transistor is manufactured based on the second active region.

[0032] A semiconductor device provided by the present invention comprises: a substrate; a functional layer located on a surface of one side of the substrate; the functional layer is formed with at least one main transistor and at least one auxiliary transistor; the source end of the main transistor is connected to the drain end of the auxiliary transistor; the source end of the auxiliary transistor is grounded, and the gate end of the auxiliary transistor is vacant or grounded; the gate width of the auxiliary transistor is greater than the gate width of the main transistor.

[0033] The impedance point can be adjusted by cascading additional auxiliary transistors to the main transistor to form a cascode structure. By connecting the auxiliary transistors in series, the voltage can be reduced, thereby reducing the difficulty of power matching of the device, making the impedance of the main transistor close to 50 ohms, which is easy to match. At the same time, since the auxiliary transistor connected in series with the source of the main transistor is in a normally open state, it will not affect the efficiency and gain of the main transistor power amplifier, thus ensuring the performance of the device.

[0034] The present application also provides a method for preparing a semiconductor device, which also has the above-mentioned beneficial effects and will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0036] FIG1 is a circuit diagram of a semiconductor device provided by an embodiment of the present invention;

[0037] FIG2 is a process flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0038] FIG3 is a schematic diagram of a partial structure of a semiconductor device provided by an embodiment of the present invention;

[0039] Figures 4 to 7 A partial process flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0040] Figure 8A schematic structural diagram of a first specific semiconductor device provided by an embodiment of the present invention;

[0041] Fig. 9 A schematic structural diagram of a second specific semiconductor device provided by an embodiment of the present invention;

[0042] Fig.10 A schematic structural diagram of a third specific semiconductor device provided by an embodiment of the present invention;

[0043] Fig.11 A schematic structural diagram of a fourth specific semiconductor device provided by an embodiment of the present invention.

[0044] In the figure: 1. main transistor, 11. source electrode, 12. drain electrode, 121. first drain contact electrode, 13. gate electrode, 131. first gate contact electrode, 2. auxiliary transistor, 211. second source contact electrode, 221. second drain contact electrode, 231. second gate contact electrode, 3. epitaxial layer, 31. first active area, 32. second active area, 41. first air bridge, 42. second air bridge, 43. third air bridge, 51. first back hole, 52. second back hole, 53. third back hole. DETAILED DESCRIPTION

[0045] The core of the present invention is to provide a semiconductor device. In the prior art, GaN HEMT has the characteristics of low-power, high-efficiency PA, but the impedance of the low-power device is very large, often located in the high-reflection area of ​​the Smith chart, and the impedance is extremely sensitive, which makes the input and output matching network design of the power amplifier extremely difficult, and there is a problem of difficulty in matching design.

[0046] The semiconductor device provided by the present invention includes: a substrate; a functional layer located on the surface of one side of the substrate; the functional layer is formed with at least one main transistor and at least one auxiliary transistor; the source end of the main transistor is connected to the drain end of the auxiliary transistor; the source end of the auxiliary transistor is grounded, and the gate end of the auxiliary transistor is vacant or grounded; the gate width of the auxiliary transistor is greater than the gate width of the main transistor.

[0047] The impedance point can be adjusted by cascading additional auxiliary transistors to the main transistor to form a cascode structure. By connecting the auxiliary transistors in series, the voltage can be reduced, thereby reducing the difficulty of power matching of the device, making the impedance of the main transistor close to 50 ohms, which is easy to match. At the same time, since the auxiliary transistor connected in series with the source of the main transistor is in a normally open state, it will not affect the efficiency and gain of the main transistor power amplifier, thus ensuring the performance of the device.

[0048] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0049] Embodiment 1

[0050] Please refer to FIG. 1 , which is a circuit diagram of a semiconductor device provided by an embodiment of the present invention.

[0051] Referring to Figure 1, in this embodiment, the semiconductor device includes: a substrate; a functional layer located on a surface of one side of the substrate; the functional layer is formed with at least one main transistor 1 and at least one auxiliary transistor 2; the gate terminal of the main transistor 1 is usually a control terminal, the drain terminal of the main transistor 1 is usually an output terminal, and the source terminal of the main transistor 1 is connected to the drain terminal of the auxiliary transistor 2; the source terminal of the auxiliary transistor 2 is grounded, and the gate terminal of the auxiliary transistor 2 is vacant or grounded; the gate width of the auxiliary transistor 2 is greater than the gate width of the main transistor 1.

[0052] The above-mentioned substrate is the base of the entire semiconductor device, and the subsequent structures in the semiconductor device need to be set based on the substrate. The substrate mainly plays the role of supporting and dissipating heat in the semiconductor chip. The material of the substrate can be SiC (silicon carbide), Si (silicon), sapphire, etc. The specific material and specific size of the substrate can be set according to actual conditions, and no specific limitation is made here.

[0053] The above-mentioned functional layer is usually arranged on one side surface of the substrate, and the functional layer is formed with at least one main transistor 1 and at least one auxiliary transistor 2, that is, the main transistor 1 and the auxiliary transistor 2 are usually integrated on the same substrate and formed based on the same functional layer. The specific structure of the functional layer will be described in detail in the subsequent content, and will not be repeated here.

[0054] The main transistor 1 is the main working transistor, so the gate terminal of the main transistor 1 is specifically the control terminal of the entire semiconductor device, and the drain terminal of the main transistor 1 is usually the output terminal of the semiconductor device. The source terminal of the main transistor 1 needs to be connected to the drain terminal of the auxiliary transistor 2, so as to form a cascode structure, that is, a common source and common gate structure, and the impedance point is adjusted by the auxiliary transistor 2. As for the auxiliary transistor 2, its drain terminal needs to be connected to the source terminal of the main transistor 1, and the source terminal of the auxiliary transistor 2 needs to be grounded, and the gate terminal of the auxiliary transistor 2 needs to be vacant or grounded, so that the auxiliary transistor 2 is a normally-on device, that is, the auxiliary transistor 2 is in a normally-on state, so as to avoid the auxiliary transistor 2 from affecting the efficiency and generation of the power amplifier PA.

[0055] In this embodiment, the gate width of the auxiliary transistor 2 needs to be greater than the gate width of the main transistor 1, so that the saturation current of the auxiliary transistor 2 is greater than the saturation current of the main transistor 1, ensuring that the setting of the auxiliary transistor 2 will not affect the power and efficiency of the main transistor 1. Specifically, in this embodiment, the ratio of the gate width of the main transistor 1 to the gate width of the auxiliary transistor 2 can be specifically in the range of 1:1 to 1:2, and can be specifically in the range of 1:1.05 to 1:1.5. Preferably, in this embodiment, the ratio of the gate width of the main transistor 1 to the gate width of the auxiliary transistor 2 is generally in the range of 1:1.1 to 1:1.2. For example, the ratio of the gate width of the main transistor 1 to the gate width of the auxiliary transistor 2 can be specifically 1:1.1, 1:1.11, 1:1.12, 1:1.1, 1:1.15, 1:1.18, 1:1.2, etc., to avoid the influence of the auxiliary transistor 2 on the main transistor 1. Of course, the specific ratio of the gate width of the main transistor 1 to the gate width of the auxiliary transistor 2 needs to be set according to the actual position of the impedance point, and the impedance point can be adjusted by adjusting the ratio of the gate widths of the two.

[0056] A semiconductor device provided in this embodiment realizes the adjustment of impedance point by forming a cascode structure by cascading an additional auxiliary transistor 2 to the main transistor 1. By connecting the auxiliary transistor 2 in series, the voltage is reduced, thereby reducing the difficulty of power matching of the device, making the impedance of the main transistor 1 close to 50 ohms, which is easy to match. At the same time, since the auxiliary transistor 2 connected in series with the source of the main transistor 1 is in a normally open state, it will not affect the efficiency and gain of the power amplifier of the main transistor 1, thereby ensuring the performance of the device.

[0057] The specific structure of a semiconductor device provided by the present invention will be described in detail in the following embodiments of the invention.

[0058] Embodiment 2

[0059] Please refer to FIG. 2 , which is a process flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention.

[0060] Referring to FIG. 2 , in an embodiment of the present invention, a method for preparing a semiconductor device includes:

[0061] S101: Obtain a substrate.

[0062] S102: a functional layer is provided on one surface of the substrate to produce a semiconductor device.

[0063] In the embodiment of the present invention, the functional layer is formed with at least one main transistor 1 and at least one auxiliary transistor 2; the source terminal of the main transistor 1 is connected to the drain terminal of the auxiliary transistor 2; the source terminal of the auxiliary transistor 2 is grounded, and the gate terminal of the auxiliary transistor 2 is vacant or grounded; the gate width of the auxiliary transistor 2 is greater than the gate width of the main transistor 1. The specific structure of the functional layer can refer to the above embodiment, and will not be repeated here.

[0064] The present embodiment provides a method for preparing a semiconductor device, which realizes the adjustment of the impedance point by cascading an additional auxiliary transistor 2 to the main transistor 1 to form a cascode structure. By connecting the auxiliary transistor 2 in series, the voltage is reduced, thereby reducing the difficulty of power matching of the device, making the impedance of the main transistor 1 close to 50 ohms, which is easy to match. At the same time, since the auxiliary transistor 2 connected in series with the source of the main transistor 1 is in a normally open state, it will not affect the efficiency and gain of the power amplifier of the main transistor 1, thereby ensuring the performance of the device.

[0065] Embodiment 3

[0066] Please refer to FIG. 3 , which is a schematic diagram of a partial structure of a semiconductor device provided by an embodiment of the present invention.

[0067] Different from the above-mentioned invention embodiment, the present invention embodiment further defines the specific structure of the functional layer on the basis of the above-mentioned invention embodiment. The rest of the contents have been described in detail in the above-mentioned invention embodiment and will not be repeated here.

[0068] Referring to Figure 3, in this embodiment, the functional layer includes an epitaxial layer 3 located on the surface of one side of the substrate, and the epitaxial layer 3 forms a two-dimensional electron gas in the active area; the active area includes a first active area 31 located in the main transistor 1 and a second active area 32 located in the auxiliary transistor 2, and the length of the second active area 32 along the extension direction of the gate electrode 13 is greater than the length of the first active area 31 along the extension direction of the gate electrode 13.

[0069] The epitaxial layer 3 is arranged on the surface of one side of the substrate, and the epitaxial layer 3 forms a two-dimensional electron gas (2DEG) in the active area, so that a channel of a semiconductor device can be formed based on the two-dimensional electron gas. In this embodiment, the epitaxial layer 3 generally includes a channel layer, an insertion layer, a barrier layer and a cap layer grown sequentially on the surface of the substrate, and the epitaxial layer 3 is generally arranged on the surface of the buffer layer, and there is generally a nucleation layer between the buffer layer and the substrate. Due to the spontaneous polarization of the barrier layer and the channel layer, the above-mentioned two-dimensional electron gas is formed on the upper surface of the channel layer and the insertion layer as the channel of the semiconductor device. The specific structure of the epitaxial layer 3 can be referred to the prior art, and will not be repeated here.

[0070] In this embodiment, the above-mentioned active area is divided into two parts, namely, a first active area 31 and a second active area 32, wherein the first active area 31 is located in the area where the main transistor 1 is located, and it will specifically work as the active area of ​​the main transistor 1. The second active area 32 is located in the area where the auxiliary transistor 2 is located, and it will specifically work as the active area of ​​the auxiliary transistor 2. In order to achieve that the gate width of the auxiliary transistor 2 is greater than the gate width of the main transistor 1, in this embodiment, the length of the second active area 32 along the extension direction of the gate electrode 13 can be set to be greater than the length of the first active area 31 along the extension direction of the gate electrode 13. Since the gates in the semiconductor device are arranged to straddle the active area along the preset direction of the active area, by setting the length of the second active area 32 along the extension direction of the gate electrode 13 to be greater than the length of the first active area 31 along the extension direction of the gate electrode 13, the gate width in the auxiliary transistor 2 can be increased, so that the gate width of the auxiliary transistor 2 is greater than the gate width of the main transistor 1.

[0071] Specifically, in the present embodiment, the first active region 31 may be rectangular, and the second active region 32 may also be rectangular. In this case, the long side of the first active region 31 is parallel to the long side of the second active region 32, and the gate electrode 13 is arranged along the width direction of the first active region 31 and the width direction of the second active region 32 as shown in the figure. In the present embodiment, the active region may be generally rectangular extending left and right, and the rectangle with a slightly narrower width in the left half of the active region serves as the first active region 31, and the rectangle with a slightly wider width in the right half serves as the second active region 32. In the present embodiment, the first active region 31 and the second active region 32 may have a colinear axis, and in this case, the long side of the upper side of the second active region 32 will protrude from the long side of the upper side of the first active region 31, and the long side of the lower side of the second active region 32 will also protrude from the long side of the lower side of the first active region 31. In this embodiment, the long side of the upper side of the second active area 32 may also be flush with the long side of the upper side of the first active area 31, in which case the long side of the lower side of the second active area 32 will protrude from the long side of the lower side of the first active area 31; or the long side of the lower side of the second active area 32 may be flush with the long side of the lower side of the first active area 31, in which case the long side of the upper side of the second active area 32 will protrude from the long side of the upper side of the first active area 31. Of course, in this embodiment, the first active area 31 and the second active area 32 may also be two separate active areas, and their specific structures may be set according to actual conditions, and are not specifically limited here.

[0072] In this embodiment, the source electrode 11 of the main transistor 1, the drain electrode 12 of the main transistor 1 and the gate electrode 13 of the main transistor 1 are arranged in the first active area 31 along the long side direction of the first active area 31, and the source electrode 11 of the auxiliary transistor 2, the drain electrode 12 of the auxiliary transistor 2 and the gate electrode 13 of the auxiliary transistor 2 are arranged in the second active area 32 along the long side direction of the second active area 32; the source electrode 11 of the main transistor 1 and the drain electrode 12 of the main transistor 1 are arranged alternately, and the gate electrode 13 of the main transistor 1 is located between the adjacent source electrode 11 of the main transistor 1 and the drain electrode 12 of the main transistor 1; the source electrode 11 of the auxiliary transistor 2 and the drain electrode 12 of the auxiliary transistor 2 are arranged alternately, and the gate electrode 13 of the auxiliary transistor 2 is located between the adjacent source electrode 11 of the auxiliary transistor 2 and the drain electrode 12 of the auxiliary transistor 2.

[0073] In this embodiment, the main transistor 1 has a source electrode 11 of the main transistor 1, a drain electrode 12 of the main transistor 1 and a gate electrode 13 of the main transistor 1, and the auxiliary transistor 2 has a source electrode 11 of the auxiliary transistor 2, a drain electrode 12 of the auxiliary transistor 2 and a gate electrode 13 of the auxiliary transistor 2. The source electrode 11 of the main transistor 1, the drain electrode 12 of the main transistor 1 and the gate electrode 13 of the main transistor 1 are all located in the first active area 31, the source electrode 11 of the main transistor 1 and the drain electrode 12 of the main transistor 1 are arranged alternately, and the gate electrode 13 of the main transistor 1 is located between the adjacent source electrode 11 of the main transistor 1 and the drain electrode 12 of the main transistor 1. Usually, the gate electrode 13 of the main transistor 1 is close to the first source and far away from the first drain to prevent breakdown between the first gate and the first drain.

[0074] Correspondingly, in this embodiment, the source electrode 11 of the auxiliary transistor 2, the drain electrode 12 of the auxiliary transistor 2 and the gate electrode 13 of the auxiliary transistor 2 are all located in the second active area 32, the source electrode 11 of the auxiliary transistor 2 and the drain electrode 12 of the auxiliary transistor 2 are arranged alternately, and the gate electrode 13 of the auxiliary transistor 2 is located between the adjacent source electrode 11 of the auxiliary transistor 2 and the drain electrode 12 of the auxiliary transistor 2. Usually, the gate electrode 13 of the auxiliary transistor 2 is close to the second source and away from the second drain to prevent breakdown between the second gate and the second drain. The specific connection method between the main transistor 1 and the auxiliary transistor 2 will be described in detail in the following invention embodiments, and will not be repeated here.

[0075] Embodiment 4

[0076] Please refer to Figures 4 to 7 , Figures 4 to 7 A partial process flow chart of a method for preparing a semiconductor device provided in an embodiment of the present invention.

[0077] See also Figure 4 In an embodiment of the present invention, a method for preparing a semiconductor device includes:

[0078] S201: Obtain a substrate.

[0079] S202: an epitaxial layer is provided on a surface of one side of the substrate.

[0080] Corresponding to the above-mentioned embodiment three, in this step, it is first necessary to set an epitaxial layer 3 on the surface of one side of the substrate. The structure of the epitaxial layer 3 can be: GaN / AlGaN, GaN / AlN / AlGaN, GaN / AlN / AlGaN / GaN, etc. The specific content can refer to the existing technology and will not be repeated here.

[0081] See also Figure 5After this step, before setting the active area, the surface of the epitaxial layer 3 can be processed to facilitate the formation of ohmic contact with some electrodes. In this embodiment, the epitaxial layer 3 can be processed first by Si ion implantation, so that the epitaxial layer 3 can be easily connected to the metal material in the Si ion implantation area. In this embodiment, a Si ion implantation protective layer, such as a SiN layer, can be grown on the surface of the epitaxial layer 3 first; then Si ions are implanted into the positions corresponding to the source electrode 11 of the main transistor 1, the drain electrode 12 of the main transistor 1, the source electrode 11 of the auxiliary transistor 2, and the drain electrode 12 of the auxiliary transistor 2 in the epitaxial layer 3 to realize the source electrode and drain electrode of the main transistor 1, and the source electrode and drain electrode of the auxiliary transistor 2 need to be in ohmic contact with the epitaxial layer 3. After that, the Si ion implantation protective layer can be removed by, for example, LPCVD (Low Pressure Chemical Vapor Deposition), and finally a passivation layer is grown on the substrate surface again, and the passivation layer can be a SiN layer.

[0082] S203: Setting an active region based on the epitaxial layer.

[0083] See also Figure 6 In this embodiment, the epitaxial layer 3 forms a two-dimensional electron gas in the active area; the active area includes a first active area 31 located in the main transistor 1 and a second active area 32 located in the auxiliary transistor 2, and the length of the second active area 32 along the extension direction of the gate electrode 13 is greater than the length of the first active area 31 along the extension direction of the gate electrode 13.

[0084] In this step, an isolation protection layer corresponding to the active area morphology can be first formed on the surface of the epitaxial layer 3, and then N ions or Ar are specifically implanted into the passive area in the epitaxial layer 3 to destroy the two-dimensional electron gas below the passive area to form an insulating area. The two-dimensional electron gas below the area that is pre-isolated and protected and not implanted with ions in this step is retained, thereby forming the active area of ​​this embodiment. The width of the second active area 32 on the right side of the active area can be slightly larger than the width of the first active area 31 on the left side, in order to ensure that the saturation current of the auxiliary transistor 2 formed on the right side is slightly larger than the main transistor 1 formed on the left side.

[0085] S204: manufacturing a main transistor based on the first active region, and manufacturing an auxiliary transistor based on the second active region.

[0086] See also Figure 7In this step, the passivation layer can be etched first to expose the Si ion implantation area, and then the conductive material is prepared in the Si ion implantation area by evaporation or other processes and then annealed, so that the epitaxial layer 3 of the conductive material and the semiconductor material undergoes an alloy reaction in the Si ion implantation area to form an ohmic contact. The conductive material is usually an ohmic contact metal to form the source electrode 11 of the main transistor 1, the drain electrode 12 of the main transistor 1, the source electrode 11 of the auxiliary transistor 2, and the drain electrode 12 of the auxiliary transistor 2. The conductive material can be a composite material such as Ti / Al / Ni / Au, Ti / Al / Ti, or Ti / Pt / Au / Ti, which is not specifically limited here.

[0087] Afterwards, in this step, another passivation layer may be re-deposited on the surface of the above-mentioned structure by a process such as PECVD (Plasma Enhance Chemical Vapour Deposition), and the passivation layer may be a SiN layer.

[0088] Referring to Figure 3, thereafter, in this step, the position of the gate electrode 13 of the main transistor 1 and the gate electrode 13 of the auxiliary transistor 2 on the surface of the epitaxial layer 3 can be etched to expose the area on the surface of the epitaxial layer 3 corresponding to the above-mentioned gate electrode, and a gate metal is set in this area by deposition and other processes. The gate metal can be NiAu, NiPbAu, etc. The gate metal needs to form a Schottky contact with the epitaxial layer 3 to form the gate electrode 13 of the main transistor 1 and the gate electrode 13 of the auxiliary transistor 2, thereby completing the preparation of the partial structure of the main transistor 1 and the auxiliary transistor 2.

[0089] Afterwards, another passivation layer may be re-deposited on the surface of the structure where the gate electrode 13 of the main transistor 1 and the gate electrode 13 of the auxiliary transistor 2 are prepared, and the passivation layer may be a SiN layer; and then the passivation layer may be etched to prepare the source field plate corresponding to the passivation layer, the first drain contact electrode 121, the first gate contact electrode 131, the second source contact electrode 211, the second gate contact electrode 231, and the connection structure between the source end of the main transistor 1 and the drain end of the auxiliary transistor 2, until the preparation of the main transistor 1 and the auxiliary transistor 2 is completed. The specific content will be described in detail in the following invention embodiments, and will not be repeated here.

[0090] The method for manufacturing a semiconductor device provided in this embodiment can integrate the main transistor 1 and the auxiliary transistor 2 in the same substrate, thereby realizing the miniaturization of the semiconductor device.

[0091] The specific contents of the semiconductor device manufacturing method provided by the present invention will be described in detail in the following invention embodiments.

[0092] Embodiment 5

[0093] Please refer to Figures 8 to 10 , Figure 8 A schematic structural diagram of a first specific semiconductor device provided by an embodiment of the present invention; Fig. 9 A schematic structural diagram of a second specific semiconductor device provided by an embodiment of the present invention; Fig.10 A schematic structural diagram of a third specific semiconductor device provided by an embodiment of the present invention.

[0094] Different from the above-mentioned invention embodiment, the present invention embodiment further defines the specific structures of the main transistor 1 and the auxiliary transistor 2 on the basis of the above-mentioned invention embodiment. The rest of the contents have been described in detail in the above-mentioned invention embodiment and will not be repeated here.

[0095] See also Figure 8 In this embodiment, a first air bridge 41 is provided on the side of the epitaxial layer 3 facing away from the substrate, and the first air bridge 41 is in contact with the source electrode 11 of the main transistor 1 and the drain electrode 12 of the auxiliary transistor 2. The first air bridge 41 is isolated from the drain electrode 12 of the main transistor 1, the gate electrode 13 of the main transistor 1, the source electrode 11 of the auxiliary transistor 2, and the gate electrode 13 of the auxiliary transistor 2.

[0096] In this embodiment, the source end of the main transistor 1 and the drain end of the auxiliary transistor 2 are connected by the first air bridge 41. The first air bridge 41 is specifically set above the active area and each electrode, and the first air bridge 41 is in contact with the source electrode 11 of each main transistor 1 and the drain electrode 12 of each auxiliary transistor 2, and is isolated from other electrodes, including the drain electrode 12 of the main transistor 1, the gate electrode 13 of the main transistor 1, the source electrode 11 of the auxiliary transistor 2, and the gate electrode 13 of the auxiliary transistor 2, so that the first air bridge 41 can only conduct the source electrode 11 of the main transistor 1 and the drain electrode 12 of the auxiliary transistor 2, so that the source end of the main transistor 1 and the drain end of the auxiliary transistor 2 are connected. The specific material of the air bridge can be set according to the actual situation, as long as it is a conductive material.

[0097] Correspondingly, in this embodiment, a common electrode is arranged at the junction of the first active area 31 and the second active area 32 , and the portion of the common electrode located in the first active area 31 serves as the source electrode 11 of the main transistor 1 , and the portion of the common electrode located in the second active area 32 serves as the drain electrode 12 of the auxiliary transistor 2 .

[0098] In this embodiment, an electrode can be further provided at the junction of the first active area 31 and the second active area 32. The electrode is a common electrode, that is, the common electrode is partially located in the first active area 31 and partially located in the second active area 32. The portion located in the first active area 31 will serve as the source of the main transistor 1, that is, as the source electrode 11 of the main transistor 1; and the portion located in the second active area 32 will serve as the drain of the auxiliary transistor 2, that is, as the drain electrode 12 of the auxiliary transistor 2. At this time, the common electrode is equivalent to a structure in which the source electrode 11 of the main transistor 1 and the drain electrode 12 of the auxiliary transistor 2 are interconnected. Obviously, when the above-mentioned first air bridge 41 is provided, the air bridge needs to be in contact with the common electrode.

[0099] In this embodiment, a first drain contact electrode 121 is provided on one side of the first active region 31 , and a first gate contact electrode 131 is provided on the other side; the first drain contact electrode 121 is in contact with the drain electrode 12 of the main transistor 1 , and the first gate contact electrode 131 is in contact with the gate electrode 13 of the main transistor 1 .

[0100] Since the source electrodes 11 of the main transistors 1 mentioned above are interconnected through the first air bridge 41, only the first drain contact electrode 121 and the first gate contact electrode 131 need to be provided here accordingly. Usually, the first drain contact electrode 121 and the first gate contact electrode 131 are located on both sides of the first active area 31, and the first drain contact electrode 121 is in contact with the drain electrode 12 of each main transistor 1, serving as a connection point for the drain end of the main transistor 1 to the outside; and the first gate contact electrode 131 is in contact with the gate electrode 13 of each main transistor 1, serving as a connection point for the gate end of the main transistor 1 to the outside.

[0101] Correspondingly, in the present embodiment, a second source contact electrode 211 is provided on one side of the second active region 32, and a second gate contact electrode 231 is provided on the other side; the second source contact electrode 211 is in contact with the source electrode 11 of the auxiliary transistor 2, and the second gate contact electrode 231 is in contact with the gate electrode 13 of the auxiliary transistor 2.

[0102] Since the drain electrodes 12 of the auxiliary transistors 2 of the above-mentioned auxiliary transistors 2 are interconnected through the first air bridge 41, only the second source contact electrode 211 and the second gate contact electrode 231 need to be set here accordingly. Usually, the second source contact electrode 211 and the second gate contact electrode 231 are located on both sides of the second active area 32, and the second source contact electrode 211 is in contact with the source electrodes 11 of each auxiliary transistor 2, serving as a connection point for the source end of the auxiliary transistor 2 to the outside; and the second gate contact electrode 231 will be in contact with the gate electrode 13 of each auxiliary transistor 2, serving as a connection point for the gate end of the auxiliary transistor 2 to the outside.

[0103] In this embodiment, the source terminal of the auxiliary transistor 2 needs to be grounded. Therefore, in this embodiment, two specific structures for grounding the source terminal of the auxiliary transistor 2 are specifically provided.

[0104] See also Figure 8 First, in this structure, no other grounding structure is provided, but the second source contact electrode 211 is grounded through a conductive wire such as a gold wire during device packaging, and the ground layer connected to the second source contact electrode 211 can be the ground layer of the packaging structure. If the gate terminal of the auxiliary transistor 2 is not grounded but left vacant in this structure, there is no need to provide a ground layer in the semiconductor device, and after the functional layer is prepared, only the back side of the substrate needs to be thinned.

[0105] See also Fig. 9 , the second type, in this structure, a ground layer is provided on the side of the substrate facing away from the functional layer, and a first back hole 51 extending to the second source contact electrode 211 is provided in the area corresponding to the second source contact electrode 211 on the side of the substrate facing away from the functional layer, and the second source contact electrode 211 is electrically connected to the ground layer through the first back hole 51. That is, in this structure, a ground layer is provided on the back side of the substrate, and the first back hole 51 extends from the ground layer to the second source contact electrode 211, so that the second source contact electrode 211 can be electrically connected to the ground layer through the first back hole 51, thereby realizing the grounding of the source terminal of the auxiliary transistor 2.

[0106] As for the gate terminal of the auxiliary transistor 2, it can be grounded or not set up or left vacant. When the gate terminal of the auxiliary transistor 2 needs to be grounded, the second gate contact electrode 231 can be connected to the ground layer, including the ground layer of the packaging structure, through a conductive wire such as a gold wire. Fig.10 , a second back hole 52 extending to the second gate contact electrode 231 may also be provided in the area corresponding to the second gate contact electrode 231 on the side of the substrate facing away from the functional layer, and the second gate contact electrode 231 is electrically connected to the ground layer through the second back hole 52. The second back hole 52 extends from the ground layer on the back side of the substrate to the second gate contact electrode 231, so that the second gate contact electrode 231 can be electrically connected to the ground layer through the second back hole 52, thereby realizing the grounding of the gate terminal of the auxiliary transistor 2.

[0107] Regarding the preparation of the semiconductor device in this embodiment, it can be after the preparation method disclosed in Example 4, specifically when preparing the source field plate, the passivation layer is etched corresponding to the source field plate, the first drain contact electrode 121, the first gate contact electrode 131, the first source contact electrode and the second gate contact electrode 231, and then the conductive material is evaporated at the corresponding position and thickened to form the source field plate, the first drain contact electrode 121, the first gate contact electrode 131, the first source contact electrode and the second gate contact electrode 231.

[0108] Afterwards, another passivation layer can be re-deposited on the surface of the structure where each contact electrode is prepared. The passivation layer can be a SiN layer. Then, the passivation layer is specifically etched to correspond to the source electrode 11 of the main transistor 1, the drain electrode 12 of the auxiliary transistor 2, the first drain contact electrode 121, the first gate contact electrode 131, the first source contact electrode and the second gate contact electrode 231. The conductive material is evaporated and thickened at the exposed position. Here, a first air bridge 41 connecting the source electrode 11 of the main transistor 1 and the drain electrode 12 of the auxiliary transistor 2 needs to be formed, and the conductive material at the above contact electrode position is further thickened to ensure that the contact electrode is easy to lead out. Finally, a passivation layer such as SiN or PI (polyimide) glue is prepared on the surface of the structure where the first air bridge 41 is prepared to complete the preparation of the front structure of the semiconductor device.

[0109] When it is necessary to set the above-mentioned first back hole 51 and / or second back hole 52, it is usually after the front structure of the semiconductor device is set, and a hole is first opened from the corresponding position on the back side of the substrate, and the above-mentioned first back hole 51 and second back hole 52 are formed by etching and other processes. Finally, the back side of the substrate includes conductive materials such as NiAu metal set in each back hole to form a ground layer on the back side of the semiconductor device, and the corresponding source terminal and / or gate terminal of the auxiliary transistor 2 are grounded.

[0110] A semiconductor device provided in this embodiment connects the source terminal of the main transistor 1 with the drain terminal of the auxiliary transistor 2 by providing a first air bridge 41 , and its structure is relatively simple, which facilitates the preparation of the device.

[0111] Embodiment 6

[0112] Please refer to Fig.11 , Fig.11 A schematic structural diagram of a fourth specific semiconductor device provided by an embodiment of the present invention.

[0113] Different from the above-mentioned invention embodiment, the present invention embodiment further defines the specific structures of the main transistor 1 and the auxiliary transistor 2 on the basis of the above-mentioned invention embodiment. The rest of the contents have been described in detail in the above-mentioned invention embodiment and will not be repeated here.

[0114] See also Fig.11 In this embodiment, the structure of the main transistor 1 is similar to that of the main transistor 1 in the fifth embodiment, and a first drain contact electrode 121 is disposed on one side of the first active region 31, and a first gate contact electrode 131 is disposed on the other side; the first drain contact electrode 121 is in contact with the drain electrode 12 of the main transistor 1, and the first gate contact electrode 131 is in contact with the gate electrode 13 of the main transistor 1. Correspondingly, in this embodiment, a second drain contact electrode 221 is disposed on one side of the second active region 32, and a second gate contact electrode 231 is disposed on the other side; the second drain contact electrode 221 is in contact with the drain electrode 12 of the auxiliary transistor 2, and the second gate contact electrode 231 is in contact with the gate electrode 13 of the auxiliary transistor 2.

[0115] That is, in the present embodiment, a second drain contact electrode 221 in contact with the drain electrode 12 of each auxiliary transistor 2 is arranged on one side of the second active area 32 instead of a second source contact electrode 211, and a second gate contact electrode 231 in contact with the gate electrode 13 of each auxiliary transistor 2 is also arranged on the other side.

[0116] In the present embodiment, the source electrodes 11 of the main transistor 1 can be interconnected through a second air bridge 42, that is, in the present embodiment, a second air bridge 42 is provided on the side of the first active area 31 facing away from the substrate, the second air bridge 42 is in contact with the source electrode 11 of the main transistor 1, and the second air bridge 42 is isolated from the drain electrode 12 of the main transistor 1 and the gate electrode 13 of the main transistor 1; the second air bridge 42 is interconnected with the second drain contact electrode 221 through a connecting line.

[0117] The second air bridge 42 is only set above the first active area 31. The second air bridge 42 is only in contact with the source electrode 11 of each main transistor 1 and is isolated from the gate electrode 13 and the drain electrode 12 of the main transistor 1. The source electrodes 11 of each main transistor 1 are interconnected through the second air bridge 42. In this embodiment, the second air bridge 42 and the second drain contact electrode 221 can be connected to each other through a connecting wire made of a conductive material, so that the source end of the main transistor 1 is connected to the drain end of the auxiliary transistor 2. In order to reduce the length of the connecting wire to reduce its resistance, in this embodiment, the connecting wire can pass through the boundary between the first active area 31 and the second active area 32 to connect the second air bridge 42 and the second drain contact electrode 221.

[0118] As for the source electrode 11 of the auxiliary transistor 2, in this embodiment, a third air bridge 43 may be provided on the side of the second active region 32 facing away from the substrate, and the third air bridge 43 is in contact with the source electrode 11 of the auxiliary transistor 2, and the third air bridge 43 is isolated from the drain electrode 12 of the auxiliary transistor 2 and the gate electrode 13 of the auxiliary transistor 2. The third air bridge 43 is only provided above the second active region 32, and the third air bridge 43 is only in contact with the source electrode 11 of each auxiliary transistor 2 and is isolated from the gate electrode 13 of the auxiliary transistor 2 and the drain electrode 12 of the auxiliary transistor 2, and the source electrodes 11 of each auxiliary transistor 2 are interconnected through the third air bridge 43.

[0119] As for the structure of grounding the source end of the auxiliary transistor 2, in this embodiment, a ground layer can be specifically provided on the side of the substrate facing away from the functional layer, and a third back hole 53 extending to the source electrode 11 of the auxiliary transistor 2 is provided in the area corresponding to the source electrode 11 of the auxiliary transistor 2 on the side of the substrate facing away from the functional layer, and the source electrode 11 of the auxiliary transistor 2 is interconnected with the ground layer through the third back hole 53, so as to realize the grounding of the source end of the auxiliary transistor 2. It should be noted that since the third air bridge 43 has interconnected the source electrodes 11 of each auxiliary transistor 2, the third back hole 53 only needs to be provided at the position corresponding to the source electrode 11 of some auxiliary transistors 2 on the back of the substrate, and can even be provided at the position corresponding to the source electrode 11 of one auxiliary transistor 2, and does not need to be provided at the position corresponding to the source electrodes 11 of all auxiliary transistors 2 on the back of the substrate.

[0120] In this embodiment, when the gate terminal of the auxiliary transistor 2 needs to be grounded, the gate electrode 13 of the auxiliary transistor 2 and the source electrode 11 of the auxiliary transistor 2 can be directly connected to each other, that is, the gate terminal of the auxiliary transistor 2 can be grounded by interconnecting with the source terminal of the auxiliary transistor 2. In the present invention, the gate terminal of the auxiliary transistor 2 can be connected to an additional series resistor at the ground terminal to ensure the stability of the gate terminal of the auxiliary transistor 2.

[0121] A semiconductor device provided in this embodiment can connect the source end of the main transistor 1 with the drain end of the auxiliary transistor 2 by setting a second air bridge 42 and a connecting wire structure, wherein the length of the air bridge to be prepared is shorter and the yield rate is higher.

[0122] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0123] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0124] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0125] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0126] The semiconductor device and its preparation method provided by the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principle and implementation method of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of ​​the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A semiconductor device, It is characterized in that include: substrate; A functional layer located on a surface of one side of the substrate; The functional layer is formed with at least one main transistor (1) and at least one auxiliary transistor (2); the source terminal of the main transistor (1) is connected to the drain terminal of the auxiliary transistor (2); the source terminal of the auxiliary transistor (2) is grounded, and the gate terminal of the auxiliary transistor (2) is vacant or grounded; The gate width of the auxiliary transistor (2) is greater than the gate width of the main transistor (1).

2. The semiconductor device according to claim 1, It is characterized in that The ratio of the gate width of the main transistor (1) to the gate width of the auxiliary transistor (2) ranges from 1:1.1 to 1:1.

2.

3. The semiconductor device according to claim 1, It is characterized in that The functional layer comprises an epitaxial layer (3) located on a surface of one side of the substrate, wherein the epitaxial layer (3) forms a two-dimensional electron gas in an active region; The active region comprises a first active region (31) located in the main transistor (1) and a second active region (32) located in the auxiliary transistor (2), wherein the length of the second active region (32) along the extension direction of the gate electrode is greater than the length of the first active region (31) along the extension direction of the gate electrode.

4. The semiconductor device according to claim 3, It is characterized in that The first active region (31) is rectangular, the second active region (32) is rectangular, the long side of the first active region is parallel to the long side of the second active region, and the gate electrode is arranged along the width direction of the first active region and the width direction of the second active region.

5. The semiconductor device according to claim 3, It is characterized in that A first air bridge (41) is provided on the side of the epitaxial layer (3) facing away from the substrate, the first air bridge (41) being in contact with the source electrode (11) of the main transistor (1) and the drain electrode (22) of the auxiliary transistor (2), and the first air bridge (41) being isolated from the drain electrode (12) of the main transistor (1), the gate electrode (13) of the main transistor (1), the source electrode (21) of the auxiliary transistor (2), and the gate electrode (23) of the auxiliary transistor (2).

6. The semiconductor device according to claim 5, It is characterized in that A common electrode is provided at the junction of the first active area (31) and the second active area (32); the portion of the common electrode located in the first active area (31) serves as a source electrode (11) of the main transistor (1), and the portion of the common electrode located in the second active area (32) serves as a drain electrode (22) of the auxiliary transistor (2).

7. The semiconductor device according to claim 1, It is characterized in that A first drain contact electrode (121) is provided on one side of the first active region (31), and a first gate contact electrode (131) is provided on the other side; the first drain contact electrode (121) is in contact with the drain electrode (12) of the main transistor (1), and the first gate contact electrode (131) is in contact with the gate electrode (13) of the main transistor (1); A second source contact electrode (211) is provided on one side of the second active region (32), and a second gate contact electrode (231) is provided on the other side; the second source contact electrode (211) is in contact with the source electrode (21) of the auxiliary transistor (2), and the second gate contact electrode (231) is in contact with the gate electrode (23) of the auxiliary transistor (2).

8. The semiconductor device according to claim 7, It is characterized in that A ground layer is provided on the side of the substrate facing away from the functional layer, a first back hole (51) extending to the second source contact electrode (211) is provided in a region of the side of the substrate facing away from the functional layer corresponding to the second source contact electrode (211), and the second source contact electrode (211) is electrically connected to the ground layer through the first back hole (51); And / or, a second back hole (52) extending to the second gate contact electrode (231) is provided in a region of the substrate on a side facing away from the functional layer and corresponding to the second gate contact electrode (231), and the second gate contact electrode (231) is electrically connected to the ground layer through the second back hole (52).

9. The semiconductor device according to claim 3, It is characterized in that A second drain contact electrode (221) is provided on one side of the second active region (32), and a second gate contact electrode (231) is provided on the other side; the second drain contact electrode (221) is in contact with the drain electrode (22) of the auxiliary transistor (2), and the second gate contact electrode (231) is in contact with the gate electrode (23) of the auxiliary transistor (2).

10. The semiconductor device according to claim 9, It is characterized in that A second air bridge (42) is provided on the side of the first active region (31) facing away from the substrate, the second air bridge (42) is in contact with the source electrode (11) of the main transistor (1), and the second air bridge (42) is isolated from the drain electrode (12) of the main transistor (1) and the gate electrode (13) of the main transistor (1); The second air bridge (42) is connected to the second drain contact electrode (221) via a connecting wire; And / or, a third air bridge (43) is provided on the side of the second active region (32) facing away from the substrate, the third air bridge (43) is in contact with the source electrode (21) of the auxiliary transistor (2), and the third air bridge (43) is isolated from the drain electrode (22) of the auxiliary transistor (2) and the gate electrode (23) of the auxiliary transistor (2).

11. The semiconductor device according to claim 10, It is characterized in that A ground layer is provided on the side of the substrate facing away from the functional layer, and a third back hole (53) extending to the source electrode (21) is provided in a region of the side of the substrate facing away from the functional layer corresponding to the source electrode (21) of the auxiliary transistor (2), and the source electrode (21) of the auxiliary transistor (2) is connected to the ground layer via the third back hole (53).

12. A method for preparing a semiconductor device, It is characterized in that include: obtaining a substrate; Arranging a functional layer on the surface of one side of the substrate to manufacture the semiconductor device; The functional layer is formed with at least one main transistor (1) and at least one auxiliary transistor (2); the source terminal of the main transistor (1) is connected to the drain terminal of the auxiliary transistor (2); the source terminal of the auxiliary transistor (2) is grounded, and the gate terminal of the auxiliary transistor (2) is vacant or grounded; the gate width of the auxiliary transistor (2) is greater than the gate width of the main transistor (1).

Images