Display panel, preparation method thereof and display device

Abstract

The invention provides a display panel and a preparation method thereof and a display device.The display panel comprises a substrate, an active layer, a first insulating layer and a first metal layer, the first insulating layer comprises a first insulating branch and a second insulating branch, the first metal layer comprises a first electrode, a first grid electrode and a second electrode, and the display panel comprises a transistor. The transistor comprises an active layer, a first electrode, a first grid electrode and a second electrode; the first electrode and the second electrode are electrically connected with the active layer; in the first direction, the first grid electrode and the active layer are at least partially overlapped, the first grid electrode and the first insulating part are at least partially overlapped, and the first electrode and the second insulating part are at least partially overlapped; the first gate includes a first side, and a cut-off position of the first gate on the first side is the same as a cut-off position of the first insulating portion. The first electrode, the first grid electrode and the second electrode are arranged on the same layer, so that the thin design of the display panel is facilitated, the morphology of the first grid electrode and the first insulating branch part is adjusted, and the regularity of the whole structure is ensured.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0002] With the continuous development of display technology, display panels have been widely used in people's production and life. In order to better meet people's needs, the display panel can be adjusted, such as adjusting the film layer in the display panel, so as to improve the overall effect of the display panel. Summary of the invention

[0003] The embodiments of the present invention provide a display panel and a method for preparing the same, and a display device. By adjusting the setting positions of a first electrode, a first gate, and a second electrode, and adjusting the morphology of a first insulating portion in combination with the first gate, the overall thinness of the display panel is ensured, while the overall regularity of the display panel is ensured, thereby ensuring the overall display effect of the display panel.

[0004] In a first aspect, an embodiment of the present invention provides a display panel, including:

[0005] substrate;

[0006] An active layer, located on one side of the substrate;

[0007] A first insulating layer, located on a side of the active layer away from the substrate, comprising a first insulating sub-part and a second insulating sub-part;

[0008] a first metal layer, located on a side of the first insulating layer away from the substrate, comprising a first electrode, a first gate and a second electrode; the display panel comprises a transistor, the transistor comprises the active layer, the first electrode, the first gate and the second electrode, the first electrode and the second electrode are both electrically connected to the active layer; along a first direction, the first gate at least partially overlaps with the active layer, the first gate at least partially overlaps with the first insulating sub-portion, and the first electrode at least partially overlaps with the second insulating sub-portion;

[0009] The first gate comprises a first side, and on the first side, a cut-off position of the first gate is the same as a cut-off position of the first insulating sub-portion;

[0010] The first direction is a direction perpendicular to the plane where the substrate is located.

[0011] In a second aspect, an embodiment of the present invention provides a method for manufacturing a display panel, the method comprising:

[0012] providing a substrate;

[0013] preparing an active layer, wherein the active layer is located on one side of the substrate;

[0014] preparing a first insulating film layer, wherein the first insulating film layer is located on a side of the active layer away from the substrate;

[0015] A first metal layer is prepared, wherein the first metal layer is located on a side of the first insulating film layer away from the substrate, and comprises a first electrode, a first gate electrode, and a second electrode; the display panel comprises a transistor, and the transistor comprises the active layer, the first electrode, the first gate electrode, and the second electrode, and the first electrode and the second electrode are both electrically connected to the active layer;

[0016] Using the first metal layer as a mask, the first insulating film layer is etched to form a first insulating layer, wherein the first insulating layer includes a first insulating portion and a second insulating portion, and along a first direction, the first gate at least partially overlaps with the active layer, the first gate at least partially overlaps with the first insulating portion, and the first electrode at least partially overlaps with the second insulating portion; wherein the first direction is a direction perpendicular to the plane where the substrate is located.

[0017] In a third aspect, an embodiment of the present invention provides a display device, comprising the display panel described in the first aspect.

[0018] An embodiment of the present invention provides a display panel, in which a transistor includes an active layer, a first electrode, a first gate electrode, and a second electrode, and the first electrode and the second electrode overlap at least partially with the active layer; wherein, in the display panel, a first insulating layer and a first metal layer, the first insulating layer is located on a side of the active layer away from the substrate, and the first metal layer is located on a side of the first insulating layer away from the substrate. The first metal layer includes a first electrode, a first gate electrode, and a second electrode, that is, the first electrode, the first gate electrode, and the second electrode are prepared in the same layer, so that the process preparation cost of the display panel can be reduced, and further, it is also beneficial to realize the thin design of the display panel. Furthermore, the first insulating layer includes a first insulating subsection and a second insulating subsection, and along a direction perpendicular to the plane where the substrate is located, the first gate electrode overlaps at least partially with the active layer, the first gate electrode also overlaps at least partially with the first insulating subsection, and the first electrode overlaps at least partially with the second insulating subsection. At the same time, the cutoff position of the first gate on the first side is the same as the cutoff position of the first insulating section, and the morphology of the first insulating section is similar to that of the first gate, which is beneficial to ensuring the regularity of the overall structure of the display panel, and the cutoff position of the first insulating section is the same as the first side, which is convenient for the implementation of complete conductorization of the active layer and improves the contact resistance problem of the transistor, thereby ensuring the overall display effect of the display panel.

[0019] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the following briefly introduces the drawings required to describe the embodiments. Obviously, the drawings introduced are only drawings of a part of the embodiments to be described in the present invention, rather than all the drawings. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 is a schematic structural diagram of a first display panel provided by an embodiment of the present invention;

[0022] Figure 2 is a schematic top view of a first transistor provided by an embodiment of the present invention;

[0023] Figure 3 yes Figure 2 A schematic diagram of a first cross section along the section line A-A';

[0024] Figure 4 yes Figure 2 A second cross-sectional schematic diagram along the section line A-A';

[0025] Figure 5 yes Figure 2 A schematic diagram of a preparation process along the section line A-A';

[0026] Figure 6 yes Figure 2 A schematic diagram of a first cross section along the section line BB';

[0027] Figure 7 is a schematic structural diagram of a second display panel provided by an embodiment of the present invention;

[0028] Figure 8 is a schematic structural diagram of a third display panel provided by an embodiment of the present invention;

[0029] Fig. 9 yes Figure 8 A schematic diagram of the first cross section along the section line C-C';

[0030] Fig.10 is a schematic structural diagram of a fourth display panel provided by an embodiment of the present invention;

[0031] Fig.11 yes Fig.10 A schematic diagram of a first cross section along the section line D-D';

[0032] Fig.12 is a schematic structural diagram of a fifth display panel provided by an embodiment of the present invention;

[0033] Fig.13 yes Fig.12 A schematic diagram of a first cross section along the section line E-E';

[0034] Fig.14 yes Fig.12 A schematic diagram of a first cross section along the section line F-F';

[0035] Fig.15 is a schematic structural diagram of a sixth display panel provided by an embodiment of the present invention;

[0036] Fig.16 is a schematic structural diagram of a seventh display panel provided by an embodiment of the present invention;

[0037] Fig.17 yes Fig.16 A schematic diagram of the first structure of the scanning signal line;

[0038] Fig.18 is a schematic structural diagram of an eighth display panel provided by an embodiment of the present invention;

[0039] Fig.19 yes Fig.18 A schematic diagram of the first structure of the scanning signal line;

[0040] Fig. 20 yes Fig.18 A second structural diagram of the middle scanning signal line;

[0041] Fig.21 is a schematic structural diagram of a ninth display panel provided by an embodiment of the present invention;

[0042] Fig. 22 yes Fig.21 A schematic diagram of a first cross section along the section line G-G';

[0043] Fig.23 yes Fig.21 A second cross-sectional schematic diagram along the section line G-G';

[0044] Fig.24 yes Fig.21 A third cross-sectional diagram along the section line G-G';

[0045] Fig.25 is a schematic structural diagram of a tenth display panel provided by an embodiment of the present invention;

[0046] Fig.26 is a schematic structural diagram of an eleventh display panel provided by an embodiment of the present invention;

[0047] Fig. 27 yes Figure 8 A schematic diagram of a structure of the middle H region;

[0048] Fig.28 is a schematic structural diagram of a twelfth display panel provided by an embodiment of the present invention;

[0049] Fig.29 is a schematic structural diagram of a thirteenth display panel provided by an embodiment of the present invention;

[0050] Fig.30 is a schematic structural diagram of a fourteenth display panel provided by an embodiment of the present invention;

[0051] Fig.31 is a schematic structural diagram of a fifteenth display panel provided by an embodiment of the present invention;

[0052] Fig.32 yes Figure 2 A third cross-sectional diagram along the section line A-A';

[0053] Fig.33 is a top view schematic diagram of the first active layer;

[0054] Fig.34 is a schematic top view of a second transistor provided by an embodiment of the present invention;

[0055] Fig.35 is a top view schematic diagram of the first active layer;

[0056] Fig.36 is a schematic structural diagram of a sixteenth display panel provided by an embodiment of the present invention;

[0057] Fig.37 yes Fig.36 A schematic diagram of a first cross section along the section line H-H';

[0058] Fig.38 yes Fig.36 A second cross-sectional schematic diagram along the section line H-H';

[0059] Fig.39 is a schematic cross-sectional view of a transistor provided by an embodiment of the present invention;

[0060] Fig.40 yes Figure 8 The first enlarged schematic diagram of the middle area H;

[0061] Fig.41 yes Fig.40 A first cross-sectional schematic diagram along section line II';

[0062] Fig.42 yes Figure 8 A second enlarged schematic diagram of the middle region H;

[0063] Fig.43 yes Fig.42 A schematic diagram of the first cross section along the section line J-J';

[0064] Fig.44 yes Figure 8 A third enlarged schematic diagram of the middle area H;

[0065] Fig.45 yes Fig.44 A schematic diagram of a first cross section along the section line K-K';

[0066] Fig.46 yes Fig.40 A second cross-sectional schematic diagram along section line II';

[0067] Fig.47 is a schematic diagram of a preparation process of a first display panel provided by an embodiment of the present invention;

[0068] Fig.48 is a cross-sectional schematic diagram of a manufacturing process of a display panel provided by an embodiment of the present invention;

[0069] Fig.49 is a schematic top view of a manufacturing process of a display panel provided by an embodiment of the present invention;

[0070] Fig.50 is a schematic diagram of a preparation process of a second display panel provided by an embodiment of the present invention;

[0071] Fig.51 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0072] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0073] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a system, product or device comprising a series of units is not necessarily limited to those steps or units clearly listed, but may include other units that are not clearly listed or inherent to these products or devices.

[0074] Figure 1 is a schematic structural diagram of a first display panel provided by an embodiment of the present invention, Figure 2 is a schematic top view of a first transistor provided by an embodiment of the present invention, Figure 3 yes Figure 2 The first cross-sectional diagram along the section line A-A' is shown in FIG. Figure 4 yes Figure 2 The second cross-sectional diagram along the section line A-A', refer to Figures 1 to 4 As shown, an embodiment of the present invention provides a display panel 10, which includes: a substrate 100; an active layer 200, which is located on one side of the substrate 100; a first insulating layer 300, which is located on a side of the active layer 200 away from the substrate 100, and includes a first insulating portion 310 and a second insulating portion 320; a first metal layer 400, which is located on a side of the first insulating layer 300 away from the substrate, and includes a first electrode 411, a first gate 412 and a second electrode 413; the display panel 10 includes a transistor 410, and the transistor 410 includes the active layer 200, the first electrode 411, the first gate 412 and the second electrode 413. The gate 412 and the second electrode 413, the first electrode 411 and the second electrode 413 are all electrically connected to the active layer 200; along the first direction X1, the first gate 412 at least partially overlaps with the active layer 200, the first gate 412 at least partially overlaps with the first insulating section 310, and the first electrode 411 at least partially overlaps with the second insulating section 320; the first gate 412 includes a first side 4121, and on the first side 4121, the cutoff position of the first gate 412 is the same as the cutoff position of the first insulating section 310; wherein the first direction X1 is a direction perpendicular to the plane where the substrate 100 is located.

[0075] Among them, reference Figure 3As shown, the display panel 10 includes a substrate 100 and a film structure such as a metal layer and an insulating layer on one side of the substrate 100. Specifically, the display panel includes an active layer 200, a first insulating layer 300 and a first metal layer 400. The active layer 200 is located on one side of the substrate 100, and the first metal layer 300 is located on a side of the active layer 200 away from the substrate 100. The material of the active layer 200 may include silicon or metal oxide, such as indium gallium zinc oxide.

[0076] For further information, please refer to Figures 1 to 3 As shown, the display panel 10 includes a transistor 410, and the transistor 410 includes an active layer 200, a first electrode 411, a first gate electrode 412, and a second electrode 413, wherein the first electrode 411 and the second electrode 413 are both electrically connected to the active layer 200, and the first gate electrode 412 at least partially overlaps with the active layer 200 along the first direction X1. It should be noted that Figure 2 and Figure 3 Only one relative position relationship between the first electrode 411, the first gate 412, and the second electrode 413 is shown. For different transistors 410, the relative positions of the first electrode 411, the first gate 412, and the second electrode 413 are diverse, and the embodiments of the present invention will not be illustrated one by one here. The control signal received by the first gate 412 of the transistor 410 is used to control the conduction and cutoff of the transistor 410. The first electrode 411 of the transistor 410 is one of the source or the drain, and the second electrode 413 of the transistor 410 is the other of the source or the drain. Figure 1 As shown, the display panel 10 includes a plurality of pixels 20 arranged in an array. The pixel 20 may include a transistor 410 . The display function of the display panel 10 is realized by controlling the on and off state of the transistor 410 .

[0077] Further, the display panel 10 includes a driving circuit (not specifically shown in the figure), and the driving circuit includes the above-mentioned transistor 410. The driving circuit can be a pixel circuit or a peripheral driving circuit, wherein the peripheral driving circuit can include a shift register circuit, an electrostatic protection circuit, a visual test circuit, and the like. Taking the pixel circuit as an example, the pixel circuit includes at least one transistor 410. If the display panel is a liquid crystal display panel, the transistor 410 included in the pixel circuit can be connected between the data signal line and the pixel electrode, and the gate of the transistor 410 is connected to the gate signal line. Under the control of the signal provided by the gate signal line, the data signal provided by the data signal line is transmitted to the pixel electrode, and the pixel electrode and the common electrode generate an electric field for controlling the rotation of the liquid crystal molecules. If the display panel is an organic light-emitting display panel (OLED) or an inorganic light-emitting diode display panel (LED), the pixel circuit can be a circuit such as a 7T1C circuit, which drives the light-emitting element to emit light by providing a driving current to the light-emitting element.

[0078] Specifically, refer to Figure 2 and Figure 3 As shown, the first metal layer 400 includes a first electrode 411, a first gate electrode 412, and a second electrode 413, that is, the first electrode 411, the first gate electrode 412, and the second electrode 413 in the transistor 410 are all prepared simultaneously by using the same process when preparing the first metal layer 400. Compared with the process in which the preparation of the gate electrode is performed separately from the preparation of the source / drain electrode, the process preparation cost of the display panel 10 can be reduced. Further, the first insulating layer 300 includes a first insulating sub-portion 310 and a second insulating sub-portion 320. Along the first direction X1, the first gate electrode 412 at least partially overlaps with the first insulating sub-portion 310, the first electrode 411 at least partially overlaps with the second insulating sub-portion 320, and the second electrode 413 can overlap with another second insulating sub-portion 320. Furthermore, the first electrode 411 , the first gate electrode 412 and the second electrode 413 are all located on the side of the first insulating layer 300 away from the substrate 100 , that is, the first gate electrode 412 , the first electrode 411 and the second electrode 413 are arranged in the same layer, which is beneficial to realize the thin design of the display panel 10 .

[0079] For further reference, Figure 2 and Figure 3 As shown, the first gate 412 includes a first side 4121, and the first side 4121 can be understood as a side edge of the first gate 412. Figure 3 As shown, on the first side 4121, the cut-off position of the first gate 412 is the same as the cut-off position of the first insulating sub-portion 310, that is, the morphology of the first gate 412 and the first insulating sub-portion 310 is consistent. The cut-off position of the first gate 412 can be understood as the edge of the pattern of the first gate 412; the cut-off position of the first insulating sub-portion 310 can be understood as the edge of the pattern of the first insulating sub-portion 310, that is, the morphology of the edge of the first gate 412 and the first insulating sub-portion 310 is consistent, which reflects the regularity of the overall structure of the display panel 10.

[0080] Furthermore, the morphology of the first insulating portion 310 is similar to that of the first gate 412, which can be achieved through a self-alignment process. Figure 4 As shown, Figure 4The display panel 10 is shown after the first electrode 411, the first gate electrode 412 and the second electrode 413 are prepared and before the insulating layer is etched again; further, the first metal layer 400 can be used as a mask to etch the first insulating layer 300, that is, the first insulating layer 300 that is not covered by the metal patterns of the first metal layer 400 and exposed to the outside is etched, so as to adjust the morphology of the first insulating sub-portion 310, that is, perform a self-alignment process to ensure that the edge morphology of the first gate electrode 412 and the first insulating sub-portion 310 is consistent. Specifically, compared Figure 3 and Figure 4 As shown, the cut-off position of the first insulating sub-portion 310 is made the same as the cut-off position of the first gate 412 through the self-alignment process, thereby ensuring the regularity of the overall structure of the display panel 10. Optionally, when the self-alignment process is adopted and the first gate 412 is used as a standard, there may be a process error when etching the first insulating sub-portion 310, so when the distance between the cut-off position of the first gate 412 and the cut-off position of the first insulating sub-portion 310 is less than or equal to 0.5 microns, it can be understood that the cut-off position of the first insulating sub-portion 310 is the same as the cut-off position of the first gate 412.

[0081] Specifically, refer to Figure 2 and Figure 3 As shown, the first electrode 411, the first gate electrode 412 and the second electrode 413 are arranged in the same layer, and are all located on the side of the first insulating layer 300 away from the substrate 100, which can reduce the number of film layers of the display panel 10 as a whole, and thus reduce the overall film thickness of the display panel 10; at the same time, the first electrode 411, the first gate electrode 412 and the second electrode 413 are prepared simultaneously using the same process, which can reduce the process preparation cost of the display panel 10.

[0082] For example, the adjustment of the shape of the first insulating portion 310 may be formed by etching the first insulating layer 300 twice. Figure 4 As shown, after the first insulating layer 300 is etched for the first time, an opening is formed in the first insulating layer 300, as shown in FIG. Figure 4 As shown in the middle area m1, after the first insulating layer 300 forms an opening and before the first metal layer is prepared, the active layer 200 is firstly conductive (such as ion doping). Specifically, the area of ​​the active layer 200 exposed by the opening of the first insulating layer 300 is conductive to form a source region and a drain region, so that the source region and the drain region of the active layer can form good electrical contacts with the source and the drain formed subsequently, respectively. After the active layer 200 is firstly conductive, the first electrode 411, the first gate 412 and the second electrode 413 in the transistor 410 are prepared, as shown in FIG. Figure 4However, after the first etching, the cut-off position of the first insulating sub-portion 310 is different from the cut-off position of the first gate 412. In the direction parallel to the plane where the substrate 100 is located, the size of the first insulating sub-portion 310 is larger than the size of the first gate 412. For the portion of the active layer 200 that is covered by the first insulating sub-portion 310 and does not overlap with the first gate 412 (such as Figure 4 As shown in the portion covered by the middle region m3, the formed transistor will have a contact resistance problem. Since this portion of the active layer 200 is covered by the first insulating portion 310, it is not conductive and cannot play the role of a conductor in the source region or the drain region. Since this portion of the active layer 200 does not overlap with the first gate 412, it cannot play the role of a channel region. This portion is located between the source region and the channel region and between the drain region and the channel region, causing the transistor to have a contact resistance problem and thus cannot be turned on normally. The first insulating layer 300 is etched a second time through a self-alignment process to expose this portion of the active layer 200, which is conducive to improving the conductive properties of this portion of the active layer 200 by conducting it again. After the improvement, this portion of the active layer is as shown in FIG. Figure 3 As shown in the middle region m2, it is conductive.

[0083] Figure 5 for Figure 3 For comparison, see Figure 5 As shown, before preparing the first metal layer 400, the first insulating layer 300 is etched to form a first insulating portion 310 with the same size as the first gate to be formed. Figure 5 As shown in the middle region m4, the size of the first gate is the same as the pattern cut-off position of the first insulating section 310. When forming the first gate, the first gate is likely to cover the side wall of the first insulating section. On the one hand, the first gate cannot form a planar structure, which affects the function of the gate. On the other hand, the part of the first gate extending to the side wall of the first insulating section may contact the active layer, causing the transistor to fail. Therefore, the display panel 10 provided by the embodiment of the present invention and the process adjustment process of the first insulating layer 300 can improve the contact resistance problem of the transistor on the one hand, and can ensure the formation of a planar gate on the other hand, thereby reducing the occurrence of transistor failure.

[0084] Figure 6 yes Figure 2 The first cross-sectional diagram along the section line B-B', refer to Figure 2 and Figure 6 As shown, the first electrode 411 includes a second side 4111 , and on the second side 4111 , the cut-off position of the first electrode 411 is the same as the cut-off position of the second insulating sub-portion 320 .

[0085] For further reference, Figure 2 and Figure 6As shown, the first electrode 411 includes a second side 4111, and the second side 4111 can be understood as a side of the first electrode 411. For example, from a top view, the shape of the first electrode 411 can be rectangular, circular or semi-circular ("U" shape), etc. The embodiment of the present invention does not specifically limit the shape of the first electrode 411. According to different types of display panels 10 or different types of transistors 410, the shape of the first electrode 411 can be adaptively adjusted. Furthermore, the side of the first electrode 411 can be any side of the two opposite sides along its width direction. For example, refer to Figure 6 As shown, the side of the first electrode 411 can be understood as: when the first electrode 411 is a strip electrode, the side of both sides along the width direction. Figure 6 As shown, on the second side 4111, the cut-off position of the first electrode 411 is the same as the cut-off position of the second insulating sub-portion 320, that is, the morphology of the first electrode 411 and the second insulating sub-portion 320 is consistent. The cut-off position of the first electrode 411 can be understood as the edge of the pattern of the first electrode 411; the cut-off position of the second insulating sub-portion 320 can be understood as the edge of the pattern of the second insulating sub-portion 320, that is, the edge morphology of the first electrode 411 and the second insulating sub-portion 320 is consistent, which reflects the regularity of the overall structure of the display panel 10.

[0086] Furthermore, the first insulating sub-section 310 and the second insulating sub-section 320 are made of the same material, and the first electrode 411 and the first gate 412 are made of the same material. The first insulating sub-section 310 is etched twice through the first gate 412 using a self-alignment process, so that the cut-off position of the first gate 412 is the same as the cut-off position of the first insulating sub-section 310; at the same time, the second insulating sub-section 320 is etched twice through the first electrode 411 using a self-alignment process, so that the cut-off position of the first electrode 411 is the same as the cut-off position of the second insulating sub-section 320.

[0087] Similarly, at least one side of the second electrode 413 , the cut-off position of the second electrode 413 is the same as the cut-off position of another second insulating portion.

[0088] Continue to refer Figure 3 As shown, in the first cross section, the cross section of the first gate 412 intersects with the cross section of the first insulating portion 310 at the first edge 311, and the first edge 311 is a line segment; wherein the first cross section is a plane determined by the second direction X2 and the first direction X1, and the second direction X2 intersects with the first side 4121 and is parallel to the plane where the substrate 100 is located.

[0089] Specifically, the first cross section is determined by the second direction X2 and the first direction X1, and the second direction X2 intersects the first side 4121 and is parallel to the plane where the substrate 100 is located, then the first cross section can be understood as Figure 3 The cross-sectional directions of the cross-sectional views shown in . Figure 3 As shown, in this cross-sectional view, the cross-section of the first gate 412 and the first insulating sub-portion 310 intersects at the first side 311 (refer to Figure 3 ). The first side 311 is a line segment, which can be understood as that the first gate 412 and the first insulating sub-part 310 are both formed by stacking film layers with flat surfaces, and do not include the portion of the first gate 412 covering the side wall of the film layer of the first insulating sub-part 310, so that the first gate 412 can be prevented from contacting the active layer 200, thereby ensuring the stability of the signal transmission of the transistor 410, thereby ensuring the display effect of the display panel 10.

[0090] Furthermore, the cut-off position of the first gate 412 is the same as the cut-off position of the first insulating sub-portion 310, which is achieved through a secondary process, that is, the preparation process is Figure 4 to Figure 3 As shown. That is, the first insulating division 310 is etched twice. The first etching is: etching the insulating film layer to form the first insulating division 310 and the second insulating division 320; the second etching is: adjusting the cutoff position of the first insulating division 310 to the cutoff position of the first gate 412 through a self-alignment process. If the self-alignment process is not adopted, and the cutoff position of the first insulating division 310 is directly adjusted to the cutoff position of the first gate 412, the first gate 412 will cover the side wall portion of the first insulating division 310 due to the deviation in preparing the film layer, that is, the first edge 311 is a broken line rather than a line segment, so that the first gate 412 will be in contact with the active layer 200, affecting the working performance of the transistor 410. Specifically, refer to Figure 5 As shown, if the size of the first insulating sub-portion 310 is directly set to be the same as the size of the first gate 412 to be formed through the first etching process, when the first gate 412 is prepared, it is considered that during the film deposition process, at least part of the first gate 412 will overlap the side wall of the first insulating sub-portion 310, that is, Figure 5 Thus, the first gate 412 and the cross section of the first insulating portion 310 intersect at the second side 311a (refer to Figure 5). Wherein, the second side 311a is a broken line rather than a line segment, which can be understood as the first gate 412 covering the surface of the first insulating sub-section 310, which includes the surface of the first insulating sub-section 310 away from the substrate 100 and the side of the first insulating sub-section 310, so that the first gate 412 may be in contact with the active layer 200, so that the stability of the signal transmission of the transistor 410 cannot be guaranteed, thereby affecting the signal transmission effect in the display panel 10. Therefore, in order to ensure the working stability of the transistor 410, the first insulating layer 300 should be etched twice (including the second self-alignment process), which can effectively improve the contact resistance problem of the transistor 410, thereby ensuring the overall signal transmission effect of the display panel 10.

[0091] Continue to refer Figure 2 and Figure 3 As shown, the active layer 200 includes a channel region 210 and a doped region 220. In a plane parallel to the plane where the substrate 100 is located, along a third direction X3, the doped region 220 is connected to the first gate 412 at the first side 4121 of the first gate 412, wherein the third direction X3 is parallel to the plane where the substrate 100 is located and intersects with the first side 4121.

[0092] Specifically, the active layer 200 includes a channel region 210 and a doped region 220. Figure 2 and Figure 3 As shown, the channel region 210 can be understood as the first gate 411 in the corresponding area of ​​the active layer 200 along the first direction X1, and the control signal received by the first gate 411 can control the channel region 210 to be turned on or off; the doping region 220 can be understood as the active layer 200 After ion doping, the doping region 220 has conductivity and can input or output related signals (such as data signals).

[0093] For further reference, Figure 2 and Figure 3 As shown, along the third direction X3, the doped region 220 is connected to the first gate 412 at the first side 4121 of the first gate 412, that is, the area outside the channel region 210 of the active layer 200 is the doped region 220. It should be noted that in Figure 3 In the figure, the second direction X2 and the third direction X3 refer to the same direction. Although both the second direction X2 and the third direction X3 are parallel to the plane where the substrate 100 is located, the second direction X2 refers to the direction of the cross section to be obtained, and the third direction X3 is the direction from the doping region 220 to the channel region 210. The two directions have different meanings, but they are in the same direction. Figure 3 and Figure 4As shown, the cut-off position of the first gate 412 is the same as the cut-off position of the first insulating sub-portion 310. Through the self-alignment process, the occupied area of ​​the first insulating sub-portion 310 at the active layer 200 is reduced, and the reduced first insulating sub-portion 310 is ion-doped again in the corresponding area of ​​the active layer 200, thereby ensuring that the area of ​​the doped region 220 in the active layer 200 is large. The display panel 10 provided by the embodiment of the present invention can improve the conductivity of the transistor 410 by increasing the area of ​​the doped region 220 in the active layer 200, ensure the reliability of the signal transmission of the display panel 10, and thus ensure the display effect of the display panel 10.

[0094] Continue to refer Figure 2 and Figure 3 As shown, the doping region 220 includes a first doping section 221 and a second doping section 222; the first doping section 221 is located on a side of the second doping section 222 away from the channel region 210, along the first direction X1, the first doping section 221 at least partially overlaps with the first electrode 411, and the second doping section 222 is located between the first doping section 221 and the channel region 210; the ion doping concentration of the second doping section 222 is equal to the ion doping concentration of the first doping section 221.

[0095] Specifically, refer to Figure 2 and Figure 3 As shown, the doping region 220 includes a first doping section 221 and a second doping section 222, wherein the first doping section 221 is located on a side of the second doping section 222 away from the channel region 210, and the first doping section 221 at least partially overlaps with the first electrode 411 along the first direction X1, that is, the first doping section 221 can be understood as: before preparing the first electrode 411, the region in the active layer 200 that is transformed from a semiconductor to a conductor, and the first electrode 411 realizes electrical connection between the first electrode 411 and the active layer 200 by contacting the first doping section 221.

[0096] Furthermore, the second doping sub-portion 222 is located between the first doping sub-portion 221 and the channel region 210. Figure 3 and Figure 4 As shown, the second doping sub-section 222 can be understood as follows: after the first insulating sub-section 310 is subjected to the self-alignment process, the active layer 200 includes a partial region where the first insulating sub-section 310 is removed by the self-alignment process, and the region is then transformed from a semiconductor to a conductor by ion doping. Therefore, the doping region 220 of the active layer 200 includes the first doping sub-section 221 and the second doping sub-section 222, and the conductivity of the active layer 200 is ensured by the first doping sub-section 221 and the second doping sub-section 222, thereby ensuring the working stability of the transistor 410.

[0097] Furthermore, the ion doping concentration of the first doping section 221 is adjusted to be the same or similar to the ion doping concentration of the second ion doping section 222, so as to ensure that the overall conductive effect of the active layer 200 is balanced, thereby further reflecting the working stability of the transistor 410, ensuring the signal transmission effect of the display panel 10, and improving the display effect of the display panel 10.

[0098] Figure 7 is a schematic structural diagram of a second display panel provided by an embodiment of the present invention, Figure 8 is a schematic diagram of the structure of a third display panel provided by an embodiment of the present invention, referring to Figure 3 , Figure 7 and Figure 8 As shown, the display panel 10 also includes a plurality of data signal lines 510 and a plurality of scanning signal lines 520; the plurality of data signal lines 510 are arranged along a fourth direction X4 and extend along a fifth direction X5; the plurality of scanning signal lines 520 are arranged along a fifth direction X5 and extend along the fourth direction X4; wherein the fourth direction X4 and the fifth direction X5 intersect, and the fourth direction X4 and the fifth direction X5 are parallel to the plane where the substrate 100 is located; the data signal line 510 is electrically connected to the first electrode 411, and the scanning signal line 520 is electrically connected to the first gate 412; the data signal line 510 or the scanning signal line 411 is located in the first metal layer 400.

[0099] Specifically, the display panel 10 includes a plurality of data signal lines 510 and scan signal lines 520. The scan signal lines 520 are electrically connected to the first gate electrode 412. The control signal in the scan signal lines 520 is transmitted to the first gate electrode 412, thereby adjusting the transistor 410 to be turned on or off. The data signal lines 510 are electrically connected to the first electrode 411. The data signal in the data signal lines 510 is transmitted to the transistor 410 through the first electrode 411.

[0100] Specifically, refer to Figure 7 As shown, Figure 7 The partial structural diagram of the display panel 10 is used to reflect the relative position relationship between the plurality of data signal lines 510, the plurality of scanning signal lines 520 and the plurality of transistors 410. Figure 7 As shown, a plurality of data signal lines 510 are arranged along the fourth direction X4 and extend along the fifth direction X5; a plurality of scan signal lines 520 are arranged along the fifth direction X5 and extend along the fourth direction X4, that is, the extension direction of the data signal lines 510 intersects with the extension direction of the scan signal lines 520; wherein the fourth direction X4 can be understood as Figure 7 In the middle direction, the fifth direction X5 can be understood as Figure 7It should be noted that the first direction X1, the second direction X2, the third direction X3, the fourth direction X4 and the fifth direction X5 mentioned in the whole text are all directions indicated in the corresponding embodiments and the corresponding drawings, and there may be situations where the directions are the same, for example Figure 3 In the figure, the second direction X2 and the third direction X3 are in the same direction.

[0101] Specifically, the first metal layer 400 includes a first electrode 411 and a first gate 412. Figure 3 As shown, the first metal layer 400 is located on the side of the first insulating layer 300 away from the substrate 100. One of the data signal line 510 electrically connected to the first electrode 411 or the scanning signal line 520 electrically connected to the first gate 412 can also be arranged on the first metal layer 400, so as to reduce the number of film layers occupied by the wiring in the display panel 10, thereby being beneficial to realizing the thin design of the display panel 10. For example, refer to Figure 8 As shown, the data signal line 510 is arranged in the first metal layer 400, that is, the data signal line 510 is arranged in the same layer as the first electrode 411. On the one hand, the reliability of the electric signal transmission is ensured, and on the other hand, the number of film layers in the display panel 10 can be reduced, which is conducive to the thin design of the display panel 10. At the same time, it can also reflect the simplification of the preparation process of the display surface 10 and save costs. Optionally, the scanning signal line 5200 can also be arranged in the first metal layer 400, that is, the scanning signal line 520 is arranged in the same layer as the first gate 412.

[0102] Furthermore, the signals transmitted in the scan signal line 520 and the data signal line 510 are different, so the two cannot be short-circuited. At the same time, the extension direction of the scan signal line 520 and the data signal line 510 is different, so along the thickness direction of the display panel 10, that is, along the first direction X1, there will be an overlapping area between the data signal line 510 and the scan signal line 520. In order to avoid the short circuit between the scan signal line 520 and the data signal line 510, the scan signal line 520 and the data signal line 510 are arranged in different layers to ensure the stable transmission of the signal and the stable operation of the transistor 410.

[0103] Fig. 9 yes Figure 8 The first cross-sectional diagram along the section line C-C' is shown in FIG. Fig.10 is a schematic structural diagram of a fourth display panel provided by an embodiment of the present invention, Fig.11 yes Fig.10 The first cross-sectional diagram along the section line D-D' is shown in FIG. Fig.12 is a schematic structural diagram of a fifth display panel provided by an embodiment of the present invention, Fig.13 yes Fig.12 The first cross-sectional diagram along the section line E-E' is shown in FIG. Fig.14 yes Fig.12 The first cross-sectional diagram along the section line F-F' is shown in FIG. Fig.15 is a schematic structural diagram of a sixth display panel provided by an embodiment of the present invention, Fig.16 is a schematic diagram of the structure of a seventh display panel provided by an embodiment of the present invention, referring to Figures 8 to 16 As shown, the data signal line 510 is located in the first metal layer 400 .

[0104] Specifically, refer to Figure 8 , Fig.10 , Fig.12 , Fig.15 and Fig.16 As shown, the data signal line 510 and the first electrode 411 in the display panel 10 are both located in the first metal layer 400. Fig. 9 , Fig.11 and Fig.14 As shown, the data signal line 510 and the first electrode 411 are located in the same film layer. While ensuring the stability of the electrical connection between the data signal line 510 and the first electrode 411, the number of film layers of the display panel 10 as a whole can be reduced, and the manufacturing cost of the display panel 10 can be reduced while achieving a thin design.

[0105] Furthermore, when the data signal line 510 is located in the first metal layer 400, in order to ensure that the signals in the data signal line 510 and the scan signal line 520 are stably transmitted, the scan signal line 520 is arranged in various ways. Figure 8 , Fig.10 , Fig.12 , Fig.15 and Fig.16 shown.

[0106] The specific setting method for the scanning signal line is as follows:

[0107] Continue to refer Figure 8 and Fig. 9 As shown, the display panel 10 further includes a second metal layer 600 . The second metal layer 600 is located on a side of the first metal layer 400 away from the substrate 100 . The scan signal line 520 is located on the second metal layer 600 .

[0108] Specifically, refer to Figure 8 and Fig. 9 As shown, the display panel 10 further includes a second metal layer 600, and the second metal layer 600 is located on a side of the first metal layer 400 away from the substrate 100. Fig. 9 As shown, Fig. 9Only a partial area of ​​the scanning signal line 520 is shown, and not all scanning signal lines 520 are shown. Along the first direction X1, the second metal layer 600 is located on the side of the first interlayer insulating layer 610 away from the first metal layer 400. The setting of the first interlayer insulating layer 610 ensures stable transmission of signals between the first metal film layer 400 and the second metal film layer 600. Optionally, the material of the first metal layer 400 and the second metal layer 600 can be Ti / Al / Ti metal stack or Mo / Al / Mo metal stack, etc., so that the resistance of the first metal layer 400 and the second metal layer 600 can be small, and the transmission effect of the electrical signal can be ensured.

[0109] For further reference, Figure 8 and Fig. 9 As shown, the scanning signal line 520 can be arranged at the film layer where the second metal layer 600 is located. The scanning signal line 520 located in the second metal layer 600 is electrically connected to the first gate 412 through a via hole to ensure the transmission of the control signal, thereby ensuring the regulation of the working state of the transistor 410.

[0110] Continue to refer Fig.10 and Fig.11 As shown, the display panel 10 further includes a third metal layer 700 , which is located on a side of the first metal layer 400 close to the substrate 100 ; the scan signal line 520 is located on the third metal layer 700 .

[0111] Specifically, refer to Fig.10 and Fig.11 As shown, the display panel 10 further includes a third metal layer 700, and the third metal layer 600 is located on a side of the first metal layer 400 close to the substrate 100. Fig.11 As shown, Fig.11 Only a part of the scanning signal line 520 is shown, and not all scanning signal lines 520 are shown. Optionally, the material of the first metal layer 400 can be Ti / Al / Ti metal stack or Mo / Al / Mo metal stack, and the material of the third metal layer 700 can be Mo, etc., so that the resistance of the first metal layer 400 and the third metal layer 700 can be small, and the transmission effect of the electrical signal can be ensured.

[0112] For further reference, Fig.10 and Fig.11 As shown, the scanning signal line 520 can be arranged at the film layer where the third metal layer 700 is located. The first gate 412 is electrically connected to the scanning signal line 520 through a via hole, that is, the scanning signal line 520 located in the third metal layer 700 is transmitted to the first gate 412 located in the first metal layer 400 through the via hole, thereby ensuring the transmission of the control signal, thereby ensuring the regulation of the working state of the transistor 410.

[0113] For further information, please refer to Figure 12 to Figure 14 As shown, the display panel 10 further includes a light shielding structure 710 , which includes a first light shielding pattern 711 . Along the first direction X1 , the first light shielding pattern 711 at least partially overlaps with the active layer 200 . The light shielding structure 710 is located in the third metal layer 700 .

[0114] The display panel 10 further includes a light shielding structure 710, which has the effect of blocking light transmission. Further, the light shielding structure 710 is located in the third metal layer 700, that is, the light shielding structure 710 is located on the side of the first metal layer 400 close to the substrate 100. The light shielding layer 710 also includes a first light shielding pattern 711, Figure 12 to Figure 14 As shown, along the first direction X1, the first shading pattern 711 at least partially overlaps with the active layer 200, that is, the first shading pattern 711 can block part of the light transmitted to the active layer 200, thereby avoiding the threshold drift of the transistor 410. Specifically, if the active layer 200 of the transistor 410 is exposed to light, which will affect its working stability, for example, when the transistor 410 is an oxide transistor (IndiumGalliumZincOxide, IGZO), its active layer 200 is more easily affected by light, so the first shading pattern 711 can play a role in shading light, avoiding the threshold drift of the transistor 410, ensuring the working stability of the transistor 410, and if the transistor 410 is a transistor in the pixel circuit, it can also ensure the overall display effect of the display panel 10.

[0115] For further reference, Fig.13 As shown, the first light shielding pattern 711 is located in the third metal layer, referring to Fig.14 As shown, the scanning signal line 520 and the first shading pattern 711 are both located in the third metal layer 700 , which can reduce the number of film layers of the display panel 10 , is beneficial to realize the thin design of the display panel 10 , and can also reduce the process preparation cost of the display panel 10 .

[0116] Continue to refer Fig.15 As shown, the light shielding structure 710 further includes a first light shielding extension pattern 712 , and the first light shielding extension pattern 712 connects the first light shielding pattern 711 and the scan signal line 520 .

[0117] Specifically, refer to Fig.15 As shown, the light shielding structure 710 further includes a first light shielding extension pattern 712. Since the light shielding structure 710 is located in the third metal layer 700, the corresponding first light shielding extension pattern 712 and the first light shielding pattern 711 are also located in the third metal layer 700. At the same time, the scanning signal line 520 electrically connected to the first gate 412 is also located in the third metal layer 700.

[0118] For further information, please refer to Fig.15 As shown, the first light shielding pattern 711 is electrically connected to the scanning signal line 520 through the first light shielding extension pattern 712, and the first light shielding pattern 711 and the first light shielding extension pattern 712 also correspond to the control signal in the transmission scanning signal line 520. In the first direction X1, the first light shielding pattern 711 at least partially overlaps with the active layer 200 (the relative position of the first light shielding pattern 711 and the active layer 200 along the first direction X1 can be referred to Fig.13 ), and the first light shielding pattern 711 is electrically connected to the scanning signal line 520 through the first light shielding extension pattern 712, so that the first light shielding pattern 711 is equivalent to the bottom gate of the transistor 410, and can also control the conduction and shutdown of the transistor 410. That is, in the transistor 410, the first gate 412 can be considered as its top gate, and the first light shielding pattern 711 can be considered as its bottom gate, then the transistor 410 is a top-bottom dual-gate transistor, thereby improving the working stability and reliability of the transistor 410, and ensuring the reliability of signal transmission in the display panel 10.

[0119] Fig.17 yes Fig.16 The first structural diagram of the scanning signal line, continue to refer to Fig.16 and Fig.17 As shown, the scanning signal line 520 includes a plurality of first divisions 521 and a plurality of second divisions 522; the first divisions 521 and the second divisions 522 are arranged in sequence along the fourth direction X4, and two adjacent first divisions 521 are electrically connected via the second divisions 522; along the fifth direction X5, the width of the first division 521 is greater than the width of the second division 522; along the first direction X1, the first division 521 at least partially overlaps with the active layer 200, and the second division 522 does not overlap with the active layer 200; the first division 521 is multiplexed as the first shading pattern 711.

[0120] Specifically, refer to Fig.16 As shown, the scan signal line 520 extending along the fourth direction X4 includes a first subsection 521 and a second subsection 522, and the first subsection 521 and the second subsection 522 are sequentially arranged along the fourth direction X4. It can be understood that along the fourth direction X4, two adjacent first subsections 521 are electrically connected through the second subsection 522, and two adjacent second subsections 522 are electrically connected through the first subsection 521. The control signal transmitted by the scan signal line 520 is transmitted sequentially through the first subsection 521, the second subsection 522, and the first subsection 521.

[0121] Further, in Fig.16 In the example, the first direction X1 can be understood as being perpendicular to Fig.16The direction of the plane shown, or the direction perpendicular to the plane determined by the fourth direction X4 and the fifth direction X5. Specifically, along the first direction X1, the first subdivision 521 overlaps with the active layer 200 at least partially, that is, the first subdivision 521 is located on the side of the active layer 200 close to the substrate 100, and the control signal is transmitted in the first subdivision 521, then the first subdivision 521 can be understood as the bottom gate of the corresponding transistor 410. The second subdivision 522 does not overlap with the active layer 200 along the first direction X1, which is equivalent to a connection structure, and the first subdivisions 521 arranged in sequence along the fourth direction X4 are electrically connected, that is, it is ensured that the first subdivisions 521 can all obtain relevant control signals. Further, the first gate 412 is electrically connected to the scan signal line 520, and the first gate 412 can be connected to the corresponding first subdivision 521 through a via hole, so that the transistor 410 is a top-bottom dual-gate transistor, ensuring the working accuracy and stability of the transistor 410. The scanning signal line 520 includes a plurality of first subdivisions 521 and a plurality of second subdivisions 522, and both the first subdivisions 521 and the second subdivisions 522 are located in the third metal layer 700. It can be understood that the scanning signal line 520 for providing a control signal is set at the third metal layer 700, and in the extension path of the scanning signal line 520, a part of the area overlaps with the active layer 200 in the first direction X1. While realizing the control of the transistor 410, the corresponding bottom gate structure (i.e., the first subdivision 521) is also added to improve the control effect of the transistor 410 and ensure the working stability of the transistor 410.

[0122] For further reference, Fig.17 As shown, along the fifth direction X5, the width of the first division 521 is greater than the width of the second division 522, wherein the first division 521 can serve as the bottom gate of the transistor 410, and the second division 522 has a portion overlapping with the data signal line 510. By reducing the width of the second division 522, the parasitic capacitance between the scanning signal line 520 and the data signal line 510 can be reduced.

[0123] Furthermore, along the first direction X1, the first division 521 in the scanning signal line 520 at least partially overlaps with the active layer 200, and the first division 521 can be reused as the first shading pattern 711. This can also reduce the number of film layers set in the display panel 10, which is beneficial to realizing the thin design of the display panel 10, and at the same time can also reduce the process preparation cost of the display panel 10.

[0124] Fig.18 is a schematic structural diagram of an eighth display panel provided by an embodiment of the present invention, Fig.19 yes Fig.18 The first structural diagram of the scanning signal line, Fig. 20 yes Fig.18 The second structural diagram of the scanning signal line, refer to Figures 18 to 20 As shown, the scan signal line 520 is provided with a plurality of hollow units 5211 , and the first light shielding pattern 711 is located in the hollow units 5211 .

[0125] For further reference, Fig.18 As shown, the line width of the scanning signal line 520 can be increased to reduce the resistance of the scanning signal line 520, thereby ensuring the effect of signal transmission on the scanning signal line 520.

[0126] Specifically, refer to Figures 18 to 20 As shown, by increasing the line width of the scan signal line 520, the resistance on the scan signal line 520 can be reduced, thereby ensuring the reliability and stability of signal transmission in the scan signal line 520. Furthermore, the scan signal line 520 with increased line width can at least partially overlap with the transistor 410 along the first direction X1.

[0127] For further reference, Fig.18 and Fig.19 As shown, the scanning signal line 520 can be arranged in the same layer as the shading structure 710 to reduce the overall film thickness of the display panel 10. The scanning signal line 520 also includes a plurality of hollow units 5211, and the scanning signal line 520 with a larger width can at least partially overlap with the active layer 200. At the same time, along the first direction X1, the first shading pattern 711 also at least partially overlaps with the active layer 200; therefore, the first shading pattern 711 can be arranged at the hollow unit 5211, so that while ensuring that the scanning signal line 520 has a wider line width, the first shading pattern 711 and the scanning signal line 520 can also be arranged in the same layer to reduce the overall film thickness of the display panel 10. For example, refer to Fig.19 As shown, only part of the scanning signal line 520 is shown in the figure, and two hollow units 5211 are used as an example for explanation. The two hollow units 5211 shown are respectively provided with a first light shielding pattern 711a and a first light shielding pattern 711b, wherein the first light shielding pattern 711a and the first light shielding pattern 711b correspond to the active layer 200 of different transistors 410 respectively.

[0128] Optional, reference Fig.18 and Fig. 20As shown, the scanning signal line 520 can be arranged in the same layer as the shading structure 710 to reduce the overall film thickness of the display panel 10. The scanning signal line 520 with a larger width can at least partially overlap with the active layer 200. At the same time, along the first direction X1, the first shading pattern 711 also at least partially overlaps with the active layer 200. The scanning signal line 520 as a metal wiring can also block the transmitted light, so part of the scanning signal line 520 corresponding to the active layer 200 can be reused as the first shading pattern 711, which can also reduce the process preparation process of the display panel 10 and reduce the overall film thickness of the display panel 10. For example, refer to Fig. 20 As shown in the figure, only part of the scanning signal line 520 is shown, and two first light shielding patterns 711 are used as an example for explanation. The first light shielding pattern 711a and the first light shielding pattern 711b shown correspond to the active layer 200 of different transistors 410, respectively. Fig. 20 The first light shielding pattern 711 a and the second light shielding pattern 711 b are part of the structure of the scanning signal line 520 .

[0129] Fig.21 is a schematic structural diagram of a ninth display panel provided by an embodiment of the present invention, Fig. 22 yes Fig.21 The first cross-sectional diagram along the section line G-G' is shown in FIG. Fig.23 yes Fig.21 The second cross-sectional diagram along the section line G-G', Fig.24 yes Fig.21 The third cross-sectional diagram along the section line G-G', see Figure 21 to Figure 24 As shown, the first metal layer 400 further includes a plurality of metal blocks 420 . Along the fourth direction X4 , the metal blocks 420 are located between two adjacent data signal lines 510 , and along the first direction X1 , the metal blocks 420 overlap with the scan signal lines 520 .

[0130] Specifically, refer to Fig.21 and Fig. 22 As shown, the first metal layer 400 further includes a plurality of metal blocks 420. Along the fourth direction X4, the metal blocks 420 are located between two adjacent data signal lines 510. Fig.21 Only the approximate location of the metal block 420 is shown, and the specific size and shape of the metal block 420 are not specifically limited. Further, the metal block 420 can play a positioning effect during the preparation process of the display panel 10 or be used to improve the structural stability of the display panel 10. For example, refer to Fig. 22As shown, the display panel 10 is taken as an example of a liquid crystal display panel, and the display panel 10 further includes a planarization layer 620, a second interlayer insulating layer 630, a liquid crystal layer 640 and a color filter substrate 650; wherein the color filter substrate 650 further includes a black matrix 651, a color resist 652 and a support unit 653, and along the first direction X1, the metal block 420 and the support unit 653 at least partially overlap, that is, the metal block 420 can be used as a position mark to facilitate the preparation of the support unit 653. Further, the metal block 420 can also be used as a structure arranged opposite to the support unit 653 on the color filter substrate 650, that is, as a pad against the support unit 653, so as to ensure the overall structural stability of the display panel 10.

[0131] For further reference, Figure 21 to Figure 24 As shown, along the first direction X1, the metal block 420 overlaps with the scan signal line 520, for details, refer to Fig.24 As shown, if the metal block 420 is electrically connected to the scanning signal line 520 through a via, the metal block 420 is equivalent to being electrically connected in parallel with the scanning signal line 520, thereby reducing the resistance of the scanning signal line 520, thereby ensuring the reliability and stability of the signal transmission on the scanning signal line 520, thereby ensuring the working stability and reliability of the transistor 410.

[0132] Fig.25 is a schematic structural diagram of a tenth display panel provided by an embodiment of the present invention, Fig.26 is a schematic diagram of the structure of an eleventh display panel provided in an embodiment of the present invention, referring to Fig.25 and Fig.26 As shown, the display panel 10 further includes a plurality of scan connection lines 530 , and the scan connection lines 530 are electrically connected to the scan signal lines 520 ; the scan connection lines 530 are located in the first metal layer 400 and extend along a fifth direction X5 .

[0133] Specifically, refer to Fig.25 As shown, the display panel 10 further includes a plurality of scan connection lines 530, the scan connection lines 530 and the data signal lines 510 are both located in the first metal layer 400, and the scan connection lines 530 and the data signal lines 510 are both extended along the fifth direction X5, and the plurality of scan connection lines 530 are arranged along the fourth direction X4. Fig.25 As shown, the scanning connection line 530 and the scanning signal line 520 extend in different directions and are located in different film layers. Fig. 22 The middle area Z) realizes the electrical connection between the scan connection line 530 and the scan signal line 520.

[0134] For further reference, Fig.26 As shown, Fig.26 It can be understood as Fig.25Schematic diagram of the routing direction of the data signal line 510, the scan connection line 530 and the scan signal line 520. Fig.26 As shown, the data signal line 510 is electrically connected to the data driving circuit 120, and the data driving circuit 120 provides a data signal to the data signal line 510, and the data signal line 510 then transmits the data signal to the transistor 410. The scan connection line 530 is electrically connected to the scan driving circuit 110, and the scan driving circuit 110 provides a control signal to the scan connection line 530, and the scan connection line 530 then transmits the control signal to the transistor 410 through the scan signal line 520. The scan connection line 530 and the data signal line 510 are both located in the first metal layer 400, and the scan connection line 530 and the data signal line 510 both extend along the fifth direction X5; the scan signal line 520 is located in the third metal layer 700, and the scan signal line 520 extends along the fourth direction X4. A scan connection line 530 is electrically connected to a scan signal line 520 through a via, so that the input end of the scan signal can be transferred to the lower frame of the display panel 10, that is, Fig.26 The setting position of the scanning driving circuit 110 is shown in FIG.

[0135] When the data signal line 510 and the scan signal line 520 are located in different layers, the scan signal line 520 can also realize signal transmission through the additional scan connection line 530. In this way, the scan drive circuit 110 can be set at the upper frame or the lower frame of the display panel 10 to reduce the size of the left and right frames. The scan drive circuit 110 can use an integrated circuit (IC) to reflect the flexibility of the wiring setting in the display panel 10. In addition, the scan connection line 530 is set in the same layer as the data signal line 510, which does not increase the film thickness of the display panel 10, which is beneficial to realize the thin design of the display panel 10.

[0136] Fig. 27 yes Figure 8 A structural diagram of the middle H area, continue to refer to Figure 8 and Fig. 27 As shown, the scan signal line 520 includes a third section 523 and a fourth section 524 ; along the first direction X1 , the third section 523 at least partially overlaps with the data signal line 510 , and the fourth section 524 does not overlap with the data signal line 510 ; the line width of the third section 523 is less than or equal to the line width of the fourth section 524 .

[0137] Specifically, refer to Figure 8As shown, the scanning signal line 520 extends along the fourth direction X4, and the data signal line 510 extends along the fifth direction X5. Then, along the first direction X1, part of the scanning signal line 520 and the data signal line 510 will overlap. In order to avoid a large parasitic capacitance between the scanning signal line 520 and the data signal line 510, the line width of the scanning signal line 520 is adjusted to ensure that the signals transmitted in the scanning signal line 520 and the signals transmitted in the data signal line 510 are stable.

[0138] Specific, combined Fig. 27 As shown, the scan signal line 520 includes a third section 523 and a fourth section 524, wherein the third section 523 can be understood as a partial area where the scan signal line 520 overlaps with the data signal line 510 along the first direction X1, and the fourth section 524 can be understood as a partial area where the scan signal line 520 does not overlap with the data signal line 510 along the first direction X1. Further, the scan signal line 520 is prone to generate parasitic capacitance with the data signal line 510 in the third section 523, so the line width of the third section 523 is reduced and adjusted to reduce the routing area where the parasitic capacitance is generated. Specifically, refer to Fig. 27 As shown, the line width of the third section 523 is L1, the line width of the fourth section 524 is L2, and L1 is adjusted to be smaller than L2. In general, by reducing the line width of the third section 523 to avoid generating a large parasitic capacitance, while ensuring the line width of the fourth section 524, the overall resistance of the scanning signal line 520 can be prevented from being too large, thereby ensuring the stability and reliability of signal transmission in the scanning signal line 520 and the data signal line 510.

[0139] Fig.28 is a schematic diagram of the structure of a twelfth display panel provided by an embodiment of the present invention, and further reference is made to Figure 8 and Fig.28 As shown, the data signal line 510 includes a fifth section 511 and a sixth section 512 ; along the first direction X1 , the fifth section 511 at least partially overlaps with the active layer 200 , and the sixth section 512 does not overlap with the active layer 200 ; the fifth section 511 is reused as the first electrode 411 .

[0140] For further reference, Figure 8 and Fig.28As shown, the data signal line 510 includes a fifth subsection 511 and a sixth subsection 512, wherein along the first direction X1, the fifth subsection 511 at least partially overlaps with the active layer 200, and the data signal line 510 and the first electrode 411 are both located in the first metal layer 400, then the fifth subsection 511 can be reused as the first electrode 411, that is, it can be understood that when the data signal line 510 is in the first metal layer 400, the first electrode 411 is a part of the data signal line 510. At the same time, the sixth subsection 512 can be understood as the main part extending along the fifth direction X5. Further, Figure 8 The fifth subsection 511 and the sixth subsection 512 may be two parts of the data signal line 510. Fig.28 The sixth subdivision 512 may include the fifth subdivision 511 , and the specific arrangement of the fifth subdivision 511 and the sixth subdivision 512 is flexible.

[0141] Optionally, the above embodiment takes the data signal line located in the first metal layer as an example to further describe the various ways of setting the scan signal line. Furthermore, the scan signal line can also be set in the first metal layer, and the setting position of the data signal line is also diverse.

[0142] Fig.29 is a schematic structural diagram of a thirteenth display panel provided by an embodiment of the present invention, Fig.30 is a schematic structural diagram of a fourteenth display panel provided by an embodiment of the present invention, Fig.31 is a schematic diagram of the structure of a fifteenth display panel provided by an embodiment of the present invention, referring to Figure 29 to Figure 31 shown.

[0143] Specifically, refer to Figure 29 to Figure 31 As shown, the scanning signal line 520 and the first gate electrode 412 in the display panel 10 are both located in the first metal layer 400. While ensuring the stability of the electrical connection between the scanning signal line 520 and the first gate electrode 412, the number of film layers of the display panel 10 as a whole can be reduced, and while achieving a thin design, the process manufacturing cost of the display panel 10 can also be reduced.

[0144] Furthermore, when the scan signal line 520 is located in the first metal layer 400, in order to ensure that the signals in the data signal line 510 and the scan signal line 520 are stably transmitted, the data signal line 510 can be arranged in various ways. Figure 29 to Figure 31 shown.

[0145] The specific settings for the data signal line are as follows:

[0146] Specifically, refer to Fig.29As shown, the display panel 10 further includes a second metal layer 600, and the second metal layer 600 is located on a side of the first metal layer 400 away from the substrate 100. The data signal line 510 can be arranged at the film layer where the second metal layer 600 is located. The data signal line 510 located in the second metal layer 600 is electrically connected to the first electrode 411 through a via hole to ensure the transmission of the control signal, thereby ensuring the regulation of the working state of the transistor 410.

[0147] Specifically, refer to Fig.30 As shown, the display panel 10 further includes a third metal layer 700, and the third metal layer 600 is located on a side of the first metal layer 400 close to the substrate 100. Fig.30 As shown, the data signal line 510 can be arranged at the film layer where the third metal layer 700 is located. The first electrode 411 is electrically connected to the data signal line 510 through a via hole, that is, the data signal line 510 located in the third metal layer 700 is transmitted to the first electrode 411 located in the first metal layer 400 through the via hole, thereby ensuring the transmission of the control signal, thereby ensuring the regulation of the working state of the transistor 410.

[0148] For further reference, Fig.31 As shown, the display panel 10 further includes a light shielding structure 710, which has the effect of blocking light transmission. Further, the light shielding structure 710 is located in the third metal layer 700, that is, the light shielding structure 710 is located on the side of the first metal layer 400 close to the substrate 100. The light shielding layer 710 further includes a first light shielding pattern 711, Fig.31 As shown, along the first direction X1 , the first light shielding pattern 711 at least partially overlaps with the active layer 200 , that is, the first light shielding pattern 711 can block part of the light transmitted to the active layer 200 , thereby preventing the transistor 410 from threshold drift.

[0149] For further reference, Fig.31 As shown, the first light shielding pattern 711 is located in the third metal layer, and the data signal line 510 and the first light shielding pattern 711 are both located in the third metal layer 700, so that the number of film layers of the display panel 10 can be reduced, which is beneficial to the thin design of the display panel 10, and can also reduce the process preparation cost of the display panel 10. That is, when the scanning signal line 520 is located in the first metal layer 400, the setting position and method of the data signal line 510 are similar to the setting position and method of the scanning signal line 520 when the data signal line 510 is located in the first metal layer 400.

[0150] Fig.32 yes Figure 2 The third cross-sectional diagram along the section line A-A' is shown in the figure. Fig.33 Schematic diagram of the top view of the first active layer. Fig.34is a schematic top view of a second transistor provided by an embodiment of the present invention, Fig.35 is a top view of the first active layer, see Figure 1 , Figure 2 , Figure 32 to Figure 35 As shown, the doping region 220 includes a first electrode doping region 220a and a second electrode doping region 220b. Along the first direction X1, the first electrode doping region 220a at least partially overlaps with the first electrode 411, and the second electrode doping region 220b at least partially overlaps with the second electrode 413; the first electrode doping region 220a and the second electrode doping region 220b are located on both sides of the channel region 210.

[0151] Specifically, the transistor 410 includes a first electrode 411 and a second electrode 413, and the first electrode 411 and the second electrode 413 are both electrically connected to the active layer 200. Fig.32 and Fig.33 As shown, the doping region 220 includes a first doping region 220a and a second doping region 220b, the first electrode 411 is electrically connected to the active layer 200 through the first doping region 220a, and the second electrode 413 is electrically connected to the active layer 200 through the second doping region 220b. It should be noted that Fig.32 and Figure 2 In order to make the marking of the doping region 220 clearer, the first doping region 220a and the second doping region 220b are referred to as Fig.32 shown.

[0152] Further, the first doping region 220a and the second doping region 220b are flexible in their locations relative to the communication region 210, which can be understood as the flexibility in the locations between the first electrode 411, the second electrode 413 and the first gate 412. Fig.32 and Fig.33 As shown, the first electrode doping region 220a and the second electrode doping region 220b are located at opposite sides of the channel region 210. Fig.34 and Fig.35 As shown, the first electrode doping region 220a and the second electrode doping region 220b are located on two adjacent sides of the channel region 210. Fig.34 and Fig.35 As shown, the first gate 412 in the transistor 410 includes a first gate sub-portion 412a and a second gate sub-portion 412b, the first electrode doping region 220a is located on one side of the first gate sub-portion 412a, and the second electrode doping region 220b is located on one side of the second gate sub-portion 412b, wherein the transistor 410 can be understood as a dual-gate electrode. Further, Fig.34 The transistor 410 shown is the transistor 410 in the liquid crystal display panel 10 , and the second electrode 413 is electrically connected to the pixel electrode 810 .

[0153] In general, the first gate 412, the first electrode 411 and the second electrode 413 have different setting positions based on different types of transistors 410, so the setting positions of the channel region 210, the first electrode doping region 220a and the second electrode doping region 220b in the active layer 200 are also flexible. Figure 32 to Figure 35 Only the locations of the channel region 210 , the first electrode doping region 220 a and the second electrode doping region 220 b in a portion of the active layer 200 are shown, and the embodiments of the present invention do not show all the embodiments one by one.

[0154] Fig.36 is a schematic structural diagram of a sixteenth display panel provided by an embodiment of the present invention, Fig.37 yes Fig.36 The first cross-sectional diagram along the section line H-H' is shown in the figure below. Fig.36 and Fig.37 As shown, the display panel 10 includes a display area AA and a non-display area NA, and the non-display area NA is located on at least one side of the display area AA; the display panel 10 also includes a plurality of signal lines 900 located in the non-display area NA; the signal line 900 includes a first signal routing line 910 and a second signal routing line 920; the plurality of first signal routing lines 910 are arranged along a fourth direction X4 and extend along a fifth direction X5; the plurality of second signal routing lines 920 are arranged along a fifth direction X5 and extend along the fourth direction X4; wherein the fourth direction X4 and the fifth direction X5 intersect, and the fourth direction X3 and the fifth direction X5 are parallel to the plane where the substrate 100 is located; the first signal routing line 910 or the second signal routing line 920 is located in the first metal layer 400.

[0155] Specifically, refer to Fig.37 As shown, the display panel 10 includes a display area AA and a non-display area NA, and the display area AA is used to realize the display function of the display panel 10. The non-display area NA includes a display controller connected to the data signal line 510, such as a driver chip (not specifically shown in the figure), and the display controller provides a data signal to the data signal line 510, thereby driving the display panel 10 to realize the display function. The non-display area NA surrounds at least part of the display area AA, and the embodiment of the present invention does not make specific limitations based on the specific positions of the display area AA and the non-display area NA.

[0156] For further reference, Fig.36 As shown, the display panel 10 includes a plurality of signal lines 900 in the non-display area NA, the signal lines 900 include a first signal line 910 and a second signal line 920, the first signal line 910 and the second signal line 920 extend in different directions, and the first signal line 910 can be understood as Fig.36 The second signal line 920 extends along the column direction, that is, the fifth direction X5. Fig.36 The middle part extends along the row direction, that is, the fourth direction X4.

[0157] Specifically, the extension direction of the first signal line 910 intersects with the extension direction of the second signal line 920. To avoid short circuit between the first signal line 910 and the second signal line 920 at non-via locations, the first signal line 910 and the second signal line 920 are disposed in different layers.

[0158] Specifically, the display panel 10 includes a first metal layer 400, and the first metal layer 400 is located on a side of the first insulating layer 300 away from the substrate 100. In order to reduce the number of film layers in the display panel 10, Fig.37 As shown, one of the first signal line 910 or the second signal line 920 can also be set in the first metal layer 400, so as to reduce the number of film layers occupied by the wiring in the display panel 10, which is beneficial to realize the thin design of the display panel 10.

[0159] Exemplary, reference Fig.37 As shown, the first signal line 910 and the second signal line 920 are arranged in different layers, the first signal line 910 can be electrically connected to the second signal line 920 through a via, and the signal transmitted in the first signal line 910 is transmitted to the transistor 410c of the driving circuit 1000 located in the non-display area NA through the second signal line 920. Fig.37 The second signal line 920 is disposed in the first metal layer 400 as an example for illustration, and the arrangement of the first signal line 910 and the second signal line 920 is flexible.

[0160] Fig.38 yes Fig.36 The second cross-sectional diagram along the section line H-H' is shown in the figure below. Figure 36 to Figure 38 As shown, the display panel 10 further includes a fourth metal layer 611 , which is located on a side of the first metal layer 400 away from the substrate 100 ; the first signal trace 910 is located on the first metal layer 400 ; and the second signal trace 920 is located on the fourth metal layer 611 .

[0161] Specifically, refer to Fig.38 As shown, the display panel 10 further includes a fourth metal layer 611, which is located on a side of the first metal layer 400 away from the substrate 100. Fig. 9 As shown, the film layer setting of the fourth metal layer 611 can be at the same position as the film layer setting position of the second metal layer 600 .

[0162] For further reference, Fig.38As shown, when the first signal wiring 910 is located in the first metal layer 400, the second signal wiring 920 can be set in the fourth metal layer 611. Furthermore, the second signal wiring 920 can also be set in the first metal layer 400, and the first metal wiring 910 can be set in the fifth metal layer 611. The arrangement of the first signal wiring 910 and the second signal wiring 920 can be adaptively adjusted according to different display panels 10.

[0163] Continue to refer Fig.36 and Fig.37 As shown, the display panel 10 further includes a fifth metal layer 720 , which is located on a side of the first metal layer 400 close to the substrate 100 ; the first signal trace 910 is located on the first metal layer 400 ; and the second signal trace 920 is located on the fifth metal layer 720 .

[0164] Specifically, refer to Fig.37 As shown, the display panel 10 further includes a fifth metal layer 720, which is located on a side of the first metal layer 400 close to the substrate 100. Fig.13 As shown, the film layer setting of the fifth metal layer 720 can be the same as the film layer setting position of the third metal layer 700.

[0165] For further reference, Fig.37 As shown, when the first signal wiring 910 is located in the first metal layer 400, the second signal wiring 920 can be set in the fifth metal layer 720. Furthermore, the first signal wiring 910 can also be set in the fifth metal layer 720, and the second metal wiring 920 can be set in the first metal layer 400. The arrangement of the first signal wiring 910 and the second signal wiring 920 can be adaptively adjusted according to different display panels 10.

[0166] Continue to refer Fig.36 As shown, the display panel 10 also includes a driving circuit 1000 located in the non-display area NA; the first signal line 910 includes at least one of a common signal line, a high-level signal line, a low-level signal line, a clock signal line, a reset signal line, a start signal line and a ground line; the second signal line 920 includes a connecting line, and the driving circuit 1000 is electrically connected to the first signal line 910 via the connecting line.

[0167] The driving circuit 1000 may be a scan driving circuit, including a plurality of shift registers arranged in cascade, the shift registers being connected to the scan signal line 520 and being used to provide a scan signal to the scan signal line 520. The scan driving circuit receives a signal provided by the first signal line 910 to form a scan signal step by step.

[0168] Fig.39is a cross-sectional schematic diagram of a transistor provided by an embodiment of the present invention, with reference to Figure 2 and Fig.39 As shown, the transistor 410 includes a first transistor 410a and / or a second transistor 410b; the active layer 200a of the first transistor 410a includes a silicon semiconductor portion, and the active layer 200 of the second transistor 410b includes an oxide semiconductor portion.

[0169] Specifically, the transistor 410 may include a first transistor 410a, the active layer 200a of the first transistor 410a includes a silicon semiconductor portion, and the first transistor may be understood as a low temperature polysilicon transistor (LTPS), which has the advantages of high switching speed, high carrier mobility, and low power. The transistor 410 may also include a second transistor 410b, the active layer 200b of the second transistor 410b includes an oxide semiconductor portion, and the second type of transistor may be understood as an oxide transistor (Indium Gallium Zinc Oxide, IGZO), which has the advantages of low leakage current.

[0170] For further reference, Fig.39 As shown, the display panel 10 may include a first transistor 410a and a second transistor 410b at the same time, and in the first transistor 410a, the first electrode 411a, the first gate 412a and the second electrode 413a are arranged in the same layer, and in the second transistor 410b, the first electrode 411b, the first gate 412b and the second electrode 413b are arranged in the same layer. When the display panel 10 includes the first transistor 41a and the second transistor 410b, it can have the advantages of high switching speed, high carrier mobility, low power and low leakage current.

[0171] For further reference, Figure 2 As shown, the display panel 10 may include only one type of transistor 410. Figure 2 When the active layer 200 is a silicon semiconductor portion, the display panel 10 includes a first transistor 410a; Figure 2 When the active layer 200 is an oxide semiconductor portion, the display panel 10 includes a second transistor 410 b .

[0172] Fig.40 yes Figure 8 The first enlarged schematic diagram of the middle area H, Fig.41 yes Fig.40 The first cross-sectional diagram along the section line I-I' is shown in the figure. Fig.42 yes Figure 8 The second enlarged schematic diagram of the middle area H, Fig.43 yes Fig.42The first cross-sectional diagram along the section line J-J' is shown in the figure. Fig.44 yes Figure 8 The third enlarged schematic diagram of the middle area H, Fig.45 yes Fig.44 The first cross-sectional diagram along the section line K-K' is shown in the figure below. Figure 8 , Figures 40 to 45 As shown, the display panel 10 also includes an insulating layer 1100 and an electrode layer 800; the insulating layer 1100 includes a planarization layer 620 and a passivation layer 1110, the planarization layer 620 is located on the side of the first metal layer 400 away from the substrate 100, and the electrode layer 800 is located on the side of the planarization layer 620 away from the substrate 100; the electrode layer 800 includes a pixel electrode 810 and a common electrode 820, the pixel electrode 810 is electrically connected to the second electrode 820, the passivation layer 1110 includes a first passivation layer 1111 and a second passivation layer 1112, the first passivation layer 1111 is located on a layer of the planarization layer 620 close to the first metal layer 400, and the second passivation layer 1112 is located between the pixel electrode 810 and the common electrode 820.

[0173] Specifically, the display panel 10 includes an insulating layer 1100, referring to Figures 40 to 45 As shown, the planarization layer 620 in the insulating layer 1100 is located on the side of the first passivation layer 1111 away from the substrate 100, and the planarization layer 620 can ensure the flatness of the entire film layer of the display panel 10. Further, the display panel also includes an electrode layer 800, which is located on the side of the planarization layer 620 away from the substrate 100.

[0174] Specifically, refer to Figures 40 to 45 As shown, the electrode layer 800 includes a pixel electrode 810 and a common electrode 820, and the pixel electrode 810 is electrically connected to the second electrode 413 of the transistor 410. The pixel electrode 810 and the common electrode 820 are insulated from each other. Further, in different display panels 10, the relative arrangement positions of the pixel electrode 810 and the common electrode 820 are diverse. For example, refer to Fig.40 and Fig.41 As shown, the film layer where the pixel electrode 810 is located is located on the side of the film layer where the common electrode 820 is located away from the substrate 100, and along the first direction X1, the second passivation layer 1112 is located between the pixel electrode 810 and the common electrode 820 to prevent the pixel electrode 810 and the common electrode 820 from shorting. Fig.42 and Fig.43 As shown, the film layer where the pixel electrode 810 is located is located on the side of the film layer where the common electrode 820 is located close to the substrate 100, and along the first direction X1, the second passivation layer 1112 is located between the pixel electrode 810 and the common electrode 820 to prevent the pixel electrode 810 and the common electrode 820 from shorting. Fig.44 and Fig.45 As shown, the film layer where the pixel electrode 810 is located is arranged in the same layer as the film layer where the common electrode 820 is located, and the second passivation layer 1112 is located between the pixel electrode 810 and the common electrode 820 along the direction of the plane where the substrate 100 is located, so as to avoid short circuit between the pixel electrode 810 and the common electrode 820. It should be noted that Fig.43 The pixel electrode 810 and the common electrode 820 are arranged in different layers. Fig.44 The pixel electrode 810 and the common electrode 820 are arranged in the same layer. Fig.44 As shown, when the pixel electrode 810 and the common electrode 820 are arranged in the same layer, both the pixel electrode 810 and the common electrode 820 are in a comb shape, and the comb teeth are opposite and cross-arranged to form a horizontal electric field.

[0175] Furthermore, if the display panel 10 is a liquid crystal display panel, it also includes a liquid crystal layer (not specifically shown in the figure), and the liquid crystal layer includes a plurality of liquid crystal molecules, and the liquid crystal molecules are used to deflect under the action of the voltage signal in the pixel electrode 810 and the voltage signal in the common electrode 820, and transmit the light provided by the backlight module (not shown in the figure), thereby realizing the display effect of the liquid crystal display panel. Further, the liquid crystal display panel provided by the embodiment of the present invention can be a twisted nematic liquid crystal display panel, in which case the pixel electrode 810 and the common electrode 820 can be arranged on two sides of the liquid crystal layer that are relatively arranged, and the liquid crystal molecules are used to deflect vertically under the action of the voltage signal in the pixel electrode 810 and the voltage signal in the common electrode 820. Alternatively, the liquid crystal display panel provided by the embodiment of the present invention can also be a planar control mode display panel, in which case the pixel electrode 810 and the common electrode 820 can be arranged on the same side of the liquid crystal layer, and the liquid crystal molecules are used to deflect in plane under the action of the voltage signal in the pixel electrode 810 and the voltage signal in the common electrode 820. Furthermore, the planar control mode display panel may include a Fringe Field Switching (FFS) display panel or an In-Plane Switching (IPS) display panel. The embodiment of the present invention does not limit the specific type of the liquid crystal display panel. The subsequent embodiments are described by taking the liquid crystal display panel as a planar control mode display panel. Furthermore, for different display panels 10, the number and type of the insulating layer 1100 can be adaptively adjusted, and the embodiments of the present invention will not be described in detail one by one.

[0176] Fig.46 yes Fig.40 The second cross-sectional diagram along the section line I-I', see Fig.46As shown, the display panel 10 includes a liquid crystal display panel; the liquid crystal display panel also includes a liquid crystal layer 640 and an opposing substrate 660, the liquid crystal layer 640 is located on the side of the first metal layer 400 away from the substrate 100, and the opposing substrate 660 is located on the side of the liquid crystal layer 640 away from the substrate 100.

[0177] Specifically, the display panel 10 may be a liquid crystal display panel, such as Fig.46 As shown, the liquid crystal display panel further includes a liquid crystal layer 640. The liquid crystal layer 640 is located on a side of the first metal layer 400 away from the substrate. Fig.46 In the figure, the common electrode 820 and the pixel electrode 810 are both located on the side of the liquid crystal layer 640 close to the substrate 100. The common electrode 820 and the pixel electrode 810 can also be located on both sides of the liquid crystal layer 640, respectively, and the embodiment of the present invention does not specifically limit this. Further, the liquid crystal display panel also includes an opposing substrate 660, and the opposing substrate 660 is located on a layer of the liquid crystal layer 660 away from the substrate 100. Optionally, the opposing substrate 660 can also include a color filter substrate, a polarizer, an insulating layer, an alignment layer, etc., and the embodiment of the present invention does not specifically limit the specific film layer included in the opposing substrate 660.

[0178] Optionally, the display panel 10 may also be an organic light-emitting display panel (Organic Light-Emitting Diode, OLED) and an inorganic light-emitting diode display panel (Light-Emitting Diode, LED), that is, the types of the display panel 10 are diverse.

[0179] Based on the same inventive concept, an embodiment of the present invention further provides a method for preparing a display panel. Fig.47 is a schematic diagram of a preparation process of a first display panel provided by an embodiment of the present invention, Fig.48 is a cross-sectional schematic diagram of a manufacturing process of a display panel provided by an embodiment of the present invention, Fig.49 is a schematic top view of a manufacturing process of a display panel provided by an embodiment of the present invention, with reference to Figure 47 to Figure 49 As shown, the preparation method comprises:

[0180] S110 , providing a substrate 100 .

[0181] Specifically, refer to Fig.48 Step a and Fig.49 As shown in step a.

[0182] Exemplarily, the provided substrate may be a rigid substrate, such as glass, or a flexible substrate, and the embodiment of the present invention does not limit the type of substrate. Further, a film layer of a metal layer and an insulating layer is subsequently prepared on one side of the substrate.

[0183] S120 , preparing an active layer 200 .

[0184] Specifically, refer to Fig.48 Step b and Fig.49 As shown in step b.

[0185] The active layer 200 is located on one side of the substrate 100. Specifically, the display panel includes a transistor, the active layer is a film layer structure in the transistor, and the active layer in the transistor is electrically connected to a first electrode and a second electrode in the transistor.

[0186] S130 , preparing a first insulating film layer 300 .

[0187] Specifically, refer to Fig.48 Step c and Fig.49 As shown in step c.

[0188] The first insulating film layer 300 is located at a layer of the active layer 200 away from the substrate 100 , that is, the first insulating film layer covers the active layer.

[0189] Optional, reference Fig.48 Step d and Fig.49 As shown in step d, the first insulating film layer is initially etched to form an opening on the first insulating film layer, wherein the opening y / y1 exposes at least a portion of the active layer, and the active layer 200 can be first conductively connected through the opening y / y1, i.e., first ion doping is performed so that the active layer includes a source region and a drain region respectively contacting the subsequently formed source and drain.

[0190] S140, preparing a first metal layer 400 / 410 / 411 / 412 / 413.

[0191] Specifically, refer to Fig.48 Steps e and f, refer to Fig.49 As shown in steps e and f.

[0192] The first metal film layer 400 is prepared on a layer of the first insulating film layer away from the substrate, and the first metal film layer is patterned and etched to form a first electrode 411 , a first gate 412 and a second electrode 413 .

[0193] Specifically, the display panel includes a transistor, and the transistor includes an active layer, a first electrode, a first gate electrode, and a second electrode, wherein the first electrode and the second electrode are both electrically connected to the active layer, and the first gate electrode at least partially overlaps with the active layer along the thickness direction of the substrate. It should be noted that for different transistors, the relative positions of the first electrode, the first gate electrode, and the second electrode are diverse, and the embodiments of the present invention are not illustrated one by one here. The control signal received by the first gate electrode of the transistor is used to control the conduction and cutoff of the transistor, the first electrode of the transistor is one of the source electrode or the drain electrode, and the second electrode of the transistor is the other of the source electrode or the drain electrode.

[0194] The position of the pattern of the first gate electrode can avoid the opening of the insulating film layer to ensure the flatness of the first gate electrode pattern and avoid the first gate electrode extending to the side wall position of the opening of the insulating film layer.

[0195] Specifically, the first metal layer includes a first electrode, a first gate electrode, and a second electrode, that is, the first electrode, the first gate electrode, and the second electrode in the transistor are all prepared simultaneously using the same process when preparing the first metal layer, which can reduce the process preparation cost of the display panel compared to the process of preparing the gate electrode and the source / drain electrode separately. Furthermore, the first electrode, the first gate electrode, and the third electrode are all located on the side of the first insulating film layer away from the substrate, that is, the first gate electrode, the first electrode, and the second electrode are arranged in the same layer, which is beneficial to realize the thin design of the display panel.

[0196] S150 , using the first metal layer as a mask, etching the first insulating film layer to form a first insulating layer 300 .

[0197] Specifically, refer to Fig.48 Step g and Fig.49 As shown in step g.

[0198] Specifically, the first metal layer is used as a mask to etch the first insulating film layer, the first insulating film layer covering the first metal layer is retained, and the first insulating film layer not covered by the first metal layer is etched. The etched first insulating film layer 300 includes a first insulating sub-portion 310 and a second insulating sub-portion 320, along the thickness direction of the substrate, the first gate 412 at least partially overlaps with the first insulating sub-portion 310, and the first electrode 411 at least partially overlaps with the second insulating sub-portion 320.

[0199] Furthermore, the first metal layer is used as a mask for etching, and the morphology of the first insulating section will be similar to that of the first gate. That is, the cutoff position of the first gate is the same as the cutoff position of the first insulating section, that is, the morphology of the first gate and the first insulating section is consistent. Among them, the cutoff position of the first gate can be understood as the edge of the first gate pattern; the cutoff position of the first insulating section can be understood as the edge of the first insulating section pattern, that is, the morphology of the edge of the first gate and the first insulating section is consistent, thus reflecting the regularity of the overall structure of the display panel.

[0200] Furthermore, the morphology of the first insulating section is similar to that of the first gate, which can be understood as being achieved by a self-alignment process of the first gate. Specifically, the first metal layer can be used as a mask to etch the first insulating film layer, that is, the first insulating layer that is not covered by the metal patterns of the first metal layer and exposed to the outside is etched, so as to adjust the morphology of the first insulating section, that is, perform a self-alignment process to ensure that the edge morphology of the first gate and the first insulating section is consistent. Optionally, when the self-alignment process is used and the first gate is used as a standard to etch the first insulating section, there may be process errors, so when the distance between the cut-off position of the first gate and the cut-off position of the first insulating section is less than or equal to 0.5 microns, it can be understood that the cut-off position of the first insulating section is the same as the cut-off position of the first gate.

[0201] Specifically, the first electrode, the first gate electrode and the second electrode are arranged in the same layer, and are all located on the side of the first insulating layer away from the substrate. This can reduce the number of film layers of the display panel as a whole, and thus reduce the overall film thickness of the display panel. At the same time, the first electrode, the first gate electrode and the second electrode are prepared simultaneously using the same process, which can reduce the process preparation cost of the display panel.

[0202] Further, on the first side, the cut-off position of the first gate is the same as the cut-off position of the first insulating sub-section, that is, the edge of the first gate pattern has the same morphology as the edge of the first insulating sub-section pattern, or it can be understood that the first gate and the first insulating sub-section have the same or similar shapes. Specifically, the morphology of the first insulating sub-section can be adjusted according to the morphology of the first gate, so that the occupied area of ​​the first insulating sub-section at the active layer can be reduced, that is, the exposed area of ​​the active layer is increased, and the exposed area can be again conductively set, that is, the area of ​​the active layer that can be conductively increased, thereby improving the overall conductive properties and ensuring the working effect of the transistor in the display panel.

[0203] Exemplarily, the adjustment of the shape of the first insulating portion 310 can be formed by etching the first insulating layer 300 twice. After the first insulating layer 300 is etched for the first time, the first insulating layer 300 will form an opening y. After the opening y is formed in the first insulating layer 300 and before the first metal layer 400 is prepared, the active layer 200 is first conductive (such as ion doping). Specifically, the area of ​​the active layer 200 exposed by the opening y of the first insulating layer 300 is conductive to form a source region and a drain region, so that the source region and the drain region of the active layer can form good electrical contacts with the source and the drain formed subsequently. After the active layer 200 is first conductive, the first electrode 411, the first gate 412 and the second electrode 413 in the transistor 410 are prepared. However, after the first etching, the cut-off position of the first insulating sub-portion 310 is different from the cut-off position of the first gate 412. In the direction parallel to the plane where the substrate 100 is located, the size of the first insulating sub-portion 310 is larger than the size of the first gate 412. For the portion of the active layer 200 covered by the first insulating sub-portion 310 and not overlapping with the first gate 412, the formed transistor will have a contact resistance problem. Since the portion of the active layer 200 is covered by the first insulating sub-portion 310, it is not conductive and cannot play the role of a conductor in the source region or the drain region. Since the portion of the active layer 200 does not overlap with the first gate 412, it cannot play the role of a channel region. The portion is located between the source region and the channel region and between the drain region and the channel region, so that the transistor has a contact resistance problem, and thus there is a situation where it cannot be turned on normally. The first insulating layer 300 is etched for the second time by a self-alignment process, so that the portion of the active layer 200 can be exposed, which is conducive to improving the conductive properties of the portion of the active layer 200 by conducting it again.

[0204] If the first insulating layer 300 is etched to a size of the first insulating sub-section 310 that is the same as the size of the first gate to be formed before the first metal layer 400 is prepared, the first gate is likely to cover the side wall of the first insulating sub-section when the first gate is formed. On the one hand, the first gate cannot form a planar structure, which affects the function of the gate. On the other hand, the portion of the first gate extending to the side wall of the first insulating sub-section may contact the active layer, causing the transistor to fail. Therefore, the display panel 10 provided by the embodiment of the present invention and the process adjustment process of the first insulating layer 300 can improve the contact resistance problem of the transistor on the one hand, and can ensure the formation of a planar gate on the other hand, thereby reducing the occurrence of transistor failure.

[0205] Fig.50 is a schematic diagram of the preparation process of the second display panel provided by an embodiment of the present invention, with reference to Fig.50 As shown, the preparation method also includes:

[0206] S210 , providing a substrate 100 .

[0207] For further reference, Fig.49 As shown in step a, a light shielding structure 710 can also be prepared on the substrate 100. The light shielding structure 710 has the effect of blocking light transmission. Further, the light shielding structure 710 is located in the third metal layer 700, that is, the light shielding structure 710 is located on the side of the first metal layer 400 close to the substrate 100.

[0208] S220 , preparing an active layer 200 .

[0209] S230 , preparing a first insulating film layer 300 .

[0210] S240, conducting the active layer for the first time.

[0211] Specifically, refer to Fig.48 Steps d and Fig.49 As shown in step d, the first insulating film layer prepared on the side of the active layer away from the substrate includes an opening, such as Fig.48 As shown in the area marked in step d in , or refer to Fig.49 The area y1 and area y2 marked in step d are formed by etching the first insulating film layer for the first time after the first insulating film layer is prepared to form a corresponding opening. To ensure the electrical connection between the first electrode prepared subsequently and the active layer. Further, through the opening ( Fig.49 The active layer is first conductively doped (ion doped) in the region y1 marked in step d, referring to Fig.49 The area indicated by 201 in step d. Fig.49 The region y2 in step d can be used to electrically connect the first gate electrode to be prepared later to the light shielding structure, so that the prepared transistor can be a top-bottom dual-gate transistor, which provides the working stability of the transistor. Optionally, if the light shielding structure 710 is not prepared on the third metal layer 700 when preparing the transistor, it is not necessary to prepare the light shielding structure 710 on the third metal layer 700. Fig.49 An opening is designed at area y2 in step d.

[0212] S250 , using the first metal layer as a mask, etching the first insulating film layer to form a first insulating layer.

[0213] S260, performing a second conductorization on the exposed active layer.

[0214] Specifically, refer to Fig.48 Steps g and Fig.49As shown in step g, after forming the first insulation, that is, forming the first insulation sub-section and the second insulation sub-section by using the first metal layer as a mask, the active layer is subjected to a second conductorization (or understood as a second ion doping of the active layer region). Specifically, refer to Fig.48 Step f and step g and Fig.49 In step f and step g, after the first metal film layer is etched twice using the first metal layer as a mask, the size and morphology of the first insulating portion formed are similar to those of the first gate, which is equivalent to reducing the space occupied by the first insulating film layer on the active layer, and further conducting the additional space in the active layer for the second time, referring to Fig.49 The area indicated by 202 in step g can ensure that the overall conductive performance of the active layer is better, thereby improving the reliability of the electrical signal transmitted in the active layer, and further improving the contact resistance problem of the transistor, thereby ensuring the overall signal transmission effect of the display panel.

[0215] Based on the same inventive concept, an embodiment of the present invention further provides a display device, Fig.51 is a schematic diagram of the structure of a display device provided by an embodiment of the present invention, such as Fig.51 As shown, the display device 1 includes the display panel 10 described in any of the above embodiments. Therefore, the display device 1 provided in the embodiment of the present invention has the corresponding beneficial effects in the above embodiments, which will not be repeated here. Exemplarily, the display device 1 can be an electronic device such as a mobile phone, a computer, a display, a tablet, a smart wearable device (for example, a smart watch), and a vehicle-mounted display device, which is not limited in the embodiment of the present invention.

[0216] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: include: substrate; An active layer, located on one side of the substrate; A first insulating layer, located on a side of the active layer away from the substrate, comprising a first insulating sub-part and a second insulating sub-part; a first metal layer, located on a side of the first insulating layer away from the substrate, comprising a first electrode, a first gate electrode, and a second electrode; the display panel comprises a transistor, the transistor comprises the active layer, the first electrode, the first gate electrode, and the second electrode, and the first electrode and the second electrode are both electrically connected to the active layer; Along a first direction, the first gate at least partially overlaps with the active layer, the first gate at least partially overlaps with the first insulating sub-portion, and the first electrode at least partially overlaps with the second insulating sub-portion; The first gate comprises a first side, and on the first side, a cut-off position of the first gate is the same as a cut-off position of the first insulating sub-portion; The first direction is a direction perpendicular to the plane where the substrate is located.

2. The display panel according to claim 1, characterized in that: The first electrode comprises a second side, on which a cut-off position of the first electrode is the same as a cut-off position of the second insulating subsection.

3. The display panel according to claim 1, characterized in that: In a first cross section, a cross section of the first gate and a cross section of the first insulating portion intersect at a first side, and the first side is a line segment; The first cross section is a plane determined by a second direction and the first direction, and the second direction intersects the first side and is parallel to the plane where the substrate is located.

4. The display panel according to claim 1, characterized in that: The active layer includes a channel region and a doped region, and in a plane parallel to the plane where the substrate is located, along a third direction, the doped region is connected to the first gate at a first side of the first gate, wherein the third direction is parallel to the plane where the substrate is located and intersects with the first side.

5. The display panel according to claim 4, characterized in that: The doping region includes a first doping subsection and a second doping subsection; The first doping sub-portion is located at a side of the second doping sub-portion away from the channel region, along the first direction, the first doping sub-portion at least partially overlaps with the first electrode, and the second doping sub-portion is located between the first doping sub-portion and the channel region; The ion doping concentration of the second doping section is equal to the ion doping concentration of the first doping section.

6. The display panel according to claim 1, characterized in that: The display panel further includes a plurality of data signal lines and a plurality of scan signal lines; A plurality of the data signal lines are arranged along a fourth direction and extend along a fifth direction; a plurality of the scan signal lines are arranged along the fifth direction and extend along the fourth direction; wherein the fourth direction and the fifth direction intersect, and the fourth direction and the fifth direction are parallel to the plane where the substrate is located; The data signal line is electrically connected to the first electrode, and the scanning signal line is electrically connected to the first gate; the data signal line or the scanning signal line is located in the first metal layer.

7. The display panel according to claim 6, characterized in that: The data signal line is located in the first metal layer.

8. The display panel according to claim 7, characterized in that: The display panel further includes a second metal layer, wherein the second metal layer is located on a side of the first metal layer away from the substrate; The scanning signal line is located in the second metal layer.

9. The display panel according to claim 7, characterized in that: The display panel further includes a third metal layer, and the third metal layer is located on a side of the first metal layer close to the substrate; The scan signal line is located in the third metal layer.

10. The display panel according to claim 9, characterized in that: The display panel further includes a light shielding structure, the light shielding structure includes a first light shielding pattern, and along the first direction, the first light shielding pattern at least partially overlaps with the active layer; The light shielding structure is located in the third metal layer.

11. The display panel according to claim 10, characterized in that: The light shielding structure further includes a first light shielding extension pattern, and the first light shielding extension pattern connects the first light shielding pattern and the scanning signal line.

12. The display panel according to claim 10, characterized in that: The scanning signal line comprises a plurality of first sub-sections and a plurality of second sub-sections; the first sub-sections and the second sub-sections are arranged in sequence along the fourth direction, and two adjacent first sub-sections are electrically connected via the second sub-sections; Along the fifth direction, the width of the first section is greater than the width of the second section; Along the first direction, the first sub-portion at least partially overlaps with the active layer, and the second sub-portion does not overlap with the active layer; The first division is multiplexed into the first light shielding pattern.

13. The display panel according to claim 10, characterized in that: The scan signal line is provided with a plurality of hollow units, and the first light shielding pattern is located in the hollow units.

14. The display panel according to claim 10, characterized in that: The first metal layer further includes a plurality of metal blocks. Along the fourth direction, the metal blocks are located between two adjacent data signal lines, and along the first direction, the metal blocks overlap with the scan signal lines.

15. The display panel according to claim 9, characterized in that: The display panel further comprises a plurality of scan connection lines, wherein the scan connection lines are electrically connected to the scan signal lines; The scan connection line is located in the first metal layer and extends along the fifth direction.

16. The display panel according to claim 6, characterized in that: The scanning signal line includes a third subsection and a fourth subsection; In the first direction, the third sub-portion at least partially overlaps with the data signal line, and the fourth sub-portion does not overlap with the data signal line; The line width of the third section is smaller than or equal to the line width of the fourth section.

17. The display panel according to claim 6, characterized in that: The data signal line includes a fifth subsection and a sixth subsection; Along the first direction, the fifth sub-portion at least partially overlaps with the active layer, and the sixth sub-portion does not overlap with the active layer; The fifth subsection is multiplexed as the first electrode.

18. The display panel according to claim 4, characterized in that: The doping region includes a first electrode doping region and a second electrode doping region, along the first direction, the first electrode doping region at least partially overlaps with the first electrode, and the second electrode doping region at least partially overlaps with the second electrode; The first electrode doping region and the second electrode doping region are located at two sides of the channel region.

19. The display panel according to claim 1, characterized in that: The display panel comprises a display area and a non-display area, wherein the non-display area is located at least on one side of the display area; the display panel further comprises a plurality of signal lines located in the non-display area; the signal lines comprise a first signal line and a second signal line; A plurality of the first signal lines are arranged along a fourth direction and extend along a fifth direction; a plurality of the second signal lines are arranged along the fifth direction and extend along the fourth direction; wherein the fourth direction and the fifth direction intersect, and the fourth direction and the fifth direction are parallel to the plane where the substrate is located; The first signal routing line or the second signal routing line is located in the first metal layer.

20. The display panel according to claim 19, characterized in that: The display panel further comprises a fourth metal layer, wherein the fourth metal layer is located on a side of the first metal layer away from the substrate; The first signal trace is located at the first metal layer; The second signal trace is located in the fourth metal layer.

21. The display panel according to claim 19, characterized in that: The display panel further includes a fifth metal layer, and the fifth metal layer is located on a side of the first metal layer close to the substrate; The first signal trace is located at the first metal layer; The second signal trace is located in the fifth metal layer.

22. The display panel according to claim 19, characterized in that: The display panel further comprises a driving circuit located in the non-display area; The first signal line includes at least one of a common signal line, a high level signal line, a low level signal line, a clock signal line, a reset signal line, a start signal line and a ground line; The second signal wiring includes a connecting wiring, and the driving circuit is electrically connected to the first signal wiring through the connecting wiring.

23. The display panel according to claim 1, characterized in that: The transistor includes a first transistor and / or a second transistor; The active layer of the first transistor includes a silicon semiconductor portion, and the active layer of the second transistor includes an oxide semiconductor portion.

24. The display panel according to claim 1, characterized in that: The display panel also includes an insulating layer and an electrode layer; The insulating layer comprises a planarization layer and a passivation layer, the planarization layer is located on a side of the first metal layer away from the substrate, and the electrode layer is located on a side of the planarization layer away from the substrate; The electrode layer includes a pixel electrode and a common electrode, the pixel electrode is electrically connected to the second electrode, the passivation layer includes a first passivation layer and a second passivation layer, the first passivation layer is located in a layer of the planarization layer close to the first metal layer, and the second passivation layer is located between the pixel electrode and the common electrode.

25. The display panel according to claim 1, characterized in that: The display panel comprises a liquid crystal display panel; The liquid crystal display panel further includes a liquid crystal layer and an opposing substrate. The liquid crystal layer is located on a side of the first metal layer away from the substrate, and the opposing substrate is located on a side of the liquid crystal layer away from the substrate.

26. A method for preparing a display panel, characterized in that: The preparation method comprises: providing a substrate; preparing an active layer, wherein the active layer is located on one side of the substrate; preparing a first insulating film layer, wherein the first insulating film layer is located on a side of the active layer away from the substrate; Prepare a first metal layer, the first metal layer is located on a side of the first insulating film layer away from the substrate, and includes a first electrode, a first gate electrode, and a second electrode; the display panel includes a transistor, the transistor includes the active layer, the first electrode, the first gate electrode, and the second electrode, and the first electrode and the second electrode are both electrically connected to the active layer; Using the first metal layer as a mask, the first insulating film layer is etched to form a first insulating layer, wherein the first insulating layer includes a first insulating portion and a second insulating portion, and along a first direction, the first gate at least partially overlaps with the active layer, the first gate at least partially overlaps with the first insulating portion, and the first electrode at least partially overlaps with the second insulating portion; wherein the first direction is a direction perpendicular to the plane where the substrate is located.

27. The preparation method according to claim 26, characterized in that: Preparing the first metal layer includes: The first insulating film layer has an opening, and the opening exposes at least a portion of the active layer. Before preparing the first metal layer, the active layer is firstly conductively processed; After forming the first insulating layer, the exposed active layer is subjected to a second conductorization.

28. A display device, characterized in that: A display panel comprising any one of claims 1-25.

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