Silicon-on-insulator (SOI)-based photo-generated current resistant transistor structure and preparation method thereof

Abstract

The invention discloses an SOI-based photo-generated current resistant transistor structure and a preparation method thereof, and belongs to the field of semiconductor device preparation and radiation hardening. The top layer silicon, the buried oxide layer and the supporting layer jointly form an SOI substrate material; the source-drain region and the channel region are located in the top layer silicon, and the doping types of the source-drain region and the channel region are the same; the gate dielectric layer is located above the exterior of the top layer silicon; and the grid electrode is positioned above the insulating dielectric layer. According to the invention, the source, the drain and the channel are realized by adopting the same doping type, so that the formation of a PN junction is avoided, the generation of radiation induced current is greatly reduced, and the current amplification effect of a parasitic PNP structure is also immunized; by adopting the PN-junction-free structure, the process steps are remarkably reduced, the process complexity is reduced, for example, lightly doped source and drain process modules and other process modules can be cancelled, and the process manufacturing cost is reduced.

Description

Technical Field

[0001] This invention relates to the fields of semiconductor device fabrication and radiation hardening technology, and in particular to an SOI-based anti-photocurrent transistor structure and its fabrication method. Background Technology

[0002] With the continuous development of aerospace and nuclear fields, the requirements for the radiation resistance of devices are constantly increasing, and new requirements are being placed on indicators such as dose rate resistance. Although device structure, materials, and other aspects are constantly evolving, and the design schemes for radiation-resistant devices are becoming more and more numerous, they still cannot fully meet the requirements of radiation environments, such as high instantaneous dose rate environments.

[0003] Currently, radiation-hardened device structures are mainly based on enhancement-mode transistor structures on bulk silicon or SOI substrates. Through structural design and process hardening, single-particle and total dose effects can be suppressed to a certain extent. However, these transistors are based on PN junction structures, which make it difficult to completely suppress photocurrent. Furthermore, special designs are required for the fabrication process and device structure, resulting in complex processes and high costs. Summary of the Invention

[0004] The purpose of this invention is to provide an SOI-based anti-photocurrent transistor structure and its fabrication method to solve the problems in the background art.

[0005] To address the aforementioned technical problems, this invention provides a SOI-based photocurrent-resistant transistor structure, comprising: a top silicon layer, a buried oxide layer, a support layer, a source / drain and channel region, an insulating dielectric layer, and a gate; wherein,

[0006] The top silicon layer, buried oxide layer, and support layer together constitute the SOI substrate material;

[0007] The source, drain, and channel regions are located in the top silicon layer, and the source, drain, and channel have the same doping type.

[0008] The gate dielectric layer is located above the outer surface of the top silicon layer; the gate electrode is located above the insulating dielectric layer.

[0009] In one embodiment, the thickness of the top silicon layer is 1 to 500 nanometers, and the thickness of the buried oxide layer is 5 to 10,000 nanometers.

[0010] In one embodiment, the source / drain and channel regions are formed by ion implantation or diffusion of the same type of impurity ions, with the doping type being P-type or N-type, and the doping element being phosphorus, boron, indium, or arsenic or other group III-V elements, with a doping concentration of 0-1E20 / cm³. -3 .

[0011] In one embodiment, the insulating dielectric layer is SiO2, oxynitride, TiO2, HfO2, Si3N4, ZrO2, Ta2O5, barium strontium titanate (BST), lead zirconate titanate piezoelectric ceramic (PZT), or Al2O3, with a thickness of 0.1–20 nanometers.

[0012] In one embodiment, the gate is made of polysilicon, tantalum, tungsten, tantalum nitride, or titanium nitride, and has a thickness of 2 to 5000 nanometers.

[0013] This invention also provides a method for fabricating a photocurrent-resistant transistor structure based on SOI, comprising the following steps:

[0014] An SOI substrate is provided, which includes a top silicon layer, a buried oxide layer, and a support layer;

[0015] Source, drain, and channel regions are formed in the top silicon layer through ion implantation or diffusion;

[0016] An insulating dielectric layer is formed on the outer surface of the top silicon layer by deposition or oxidation; gate material is deposited on the insulating dielectric layer and anisotropic etching is performed to form the gate.

[0017] The present invention provides a SOI-based anti-photocurrent transistor structure and its fabrication method, which have the following beneficial effects:

[0018] (1) By using the same doping type to realize the source, drain and channel, the formation of PN junction is avoided, the generation of radiation-induced current is greatly reduced, and the current amplification effect of parasitic PNP structure is also immune.

[0019] (2) By adopting a PN junction-free structure, the number of process steps and process complexity can be significantly reduced. For example, lightly doped source and drain process modules can be eliminated, thereby reducing the manufacturing cost.

[0020] (3) The structure is suitable for single-gate, surrounding-gate and other devices, and has a certain range of applications. Attached Figure Description

[0021] Figure 1 This invention provides an SOI-based anti-photocurrent transistor structure.

[0022] Figure 2 This is a schematic diagram of the SOI substrate structure;

[0023] Figure 3 This is a schematic diagram after the source, drain, and channel regions have been prepared. Detailed Implementation

[0024] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the SOI-based photocurrent-resistant transistor structure and its fabrication method proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0025] This invention provides a SOI-based transistor structure resistant to photocurrent generation, the structure of which is as follows: Figure 1 As shown, it includes a top silicon layer 1, a buried oxide layer 2, a support layer 3, a source / drain and channel region 4, an insulating dielectric layer 5, and a gate 6; wherein, the top silicon layer 1, the buried oxide layer 2, and the support layer 3 together constitute the SOI substrate material; the source / drain and channel region 4 is located in the top silicon layer 1, and the source / drain and channel doping types are the same; the gate dielectric layer 5 is located above and outside the top silicon layer 1; the gate 6 is located above the insulating dielectric layer 5.

[0026] The thickness of the top silicon layer 1 is 1 to 500 nanometers, and the thickness of the buried oxide layer 2 is 5 to 10,000 nanometers. The source / drain and channel regions 4 are formed by ion implantation or diffusion of the same type of impurity ions, with p-type or n-type doping and doping elements such as phosphorus, boron, indium, or arsenic (Group III-V elements) at a doping concentration of 0-1E20 / cm³. -3 The insulating dielectric layer 5 is made of SiO2, oxynitrides, TiO2, HfO2, Si3N4, ZrO2, Ta2O5, barium strontium titanate (BST), lead zirconate titanate piezoelectric ceramic (PZT), or Al2O3, with a thickness of 0.1–20 nm. The gate 6 is made of polycrystalline silicon, tantalum, tungsten, tantalum nitride, or titanium nitride, with a thickness of 2–5000 nm.

[0027] The SOI-based photocurrent-resistant transistor structure of this invention is fabricated by the following method:

[0028] like Figure 2 As shown, an SOI substrate is provided, which includes a top silicon layer 1, a buried oxide layer 2, and a support layer 3;

[0029] like Figure 3 As shown, source / drain and channel regions 4 are formed in the top silicon layer 1 by ion implantation or diffusion;

[0030] like Figure 1 As shown, an insulating dielectric layer 5 is formed on the outer surface of the top silicon layer 1 by deposition or oxidation; a gate material is deposited on the insulating dielectric layer 5 and anisotropic etching is performed to form a gate 6.

[0031] This invention avoids the formation of PN junctions by using the same doping type to realize the source, drain, and channel, significantly reducing the generation of radiation-induced current and eliminating the current amplification effect of parasitic PNP structures. By adopting a PN junction-free structure, it significantly reduces process steps and process complexity, such as eliminating lightly doped source and drain process modules, thus reducing manufacturing costs. This structure is suitable for single-gate and gate-all-around devices and has a certain range of applications.

[0032] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. An SOI-based anti-photogalvanic current transistor structure, characterized by, Comprise: Top layer silicon (1), buried oxygen layer (2), support layer (3), source and drain and channel region (4), insulating dielectric layer (5), gate (6); wherein, The top layer silicon (1), buried oxygen layer (2), support layer (3) together constitute SOI substrate material; The source and drain and channel region (4) is located in the top layer silicon (1), and the source and drain and channel doping type is same; The gate dielectric layer (5) is located above the top layer silicon (1) outside; The gate (6) is located above the insulating dielectric layer (5).

2. The SOI-based anti-photo-generated-current transistor structure of claim 1, wherein, The thickness of the top layer silicon (1) is 1 to 500 nanometers, and the thickness of the buried oxygen layer (2) is 5 to 10000 nanometers.

3. The SOI-based anti-photo-generated-current transistor structure of claim 1, wherein, The source-drain and channel region (4) is formed by ion implantation or diffusion of the same type of impurity ions, the doping type is P type or N type, the doping element is phosphorus, boron, indium or arsenic or other group III-V elements, and the doping concentration is 0-1E20 / cm -3 .

4. The SOI-based anti-photo-generated-current transistor structure of claim 1, wherein the buried oxide layer is formed of silicon dioxide. The insulating dielectric layer (5) is SiO2, nitride oxide, TiO2, HfO2, Si3N4, ZrO2, Ta2O5, barium strontium titanate BST, lead zirconate titanate piezoelectric ceramic PZT or Al2O3, and the thickness is 0.1-20 nanometers.

5. The SOI-based anti-photo-generated-current transistor structure of claim 1, wherein, The gate (6) is polysilicon, tantalum, tungsten, tantalum nitride or titanium nitride, and the thickness is 2-5000 nanometers.

6. A method of manufacturing a SOI-based anti-photocurrent transistor structure according to any one of claims 1 to 5, characterized in that, Comprise the following steps: Providing SOI substrate, SOI substrate comprises top layer silicon, buried oxygen layer and support layer; Forming source and drain and channel region by ion implantation or diffusion in top layer silicon; Forming insulating dielectric layer on the external surface of top layer silicon by deposition or oxidation; Depositing gate material on the insulating dielectric layer, and carrying out anisotropic etching to form gate.

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