Semiconductor power device, preparation method, power module, conversion circuit and vehicle

Abstract

The invention discloses a semiconductor power device, a preparation method, a power module, a conversion circuit and a vehicle. The semiconductor power device comprises a substrate; the semiconductor epitaxial layer is positioned on one side of the substrate; the semiconductor epitaxial layer comprises a drift region, a body region and a contact region which are sequentially far away from the substrate; a gate trench and a gate structure, wherein the gate trench is located on the surface of one side, away from the substrate, of the semiconductor; the gate structure is located in the gate trench; the super junction structure is located in the drift region and located on the side, close to the substrate, of the gate structure; wherein the super junction structure comprises a first conductive type super junction and second conductive type super junctions which are positioned on two opposite sides of the first conductive type super junction in a direction parallel to the substrate; the conduction type of the second conduction type super junction is opposite to that of the drift region, and the second conduction type super junction covers a corner between the bottom surface and the side wall of the gate structure. According to the technical scheme provided by the invention, the breakdown problem of the gate insulating layer is improved, and the on-resistance of the device is reduced.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor technology, and in particular, to a semiconductor power device, a preparation method, a power module, a conversion circuit and a vehicle. Background Art

[0002] As a representative of the third generation of semiconductor materials, silicon carbide (SiC) has excellent physical and electrical properties. Compared with silicon materials, SiC materials have a larger bandgap, high breakdown electric field, high thermal conductivity, high electron saturation rate, and strong radiation resistance. Therefore, semiconductor power devices made of SiC materials can not only operate stably at higher temperatures, but are also suitable for high voltage and high frequency scenarios.

[0003] Currently, trench SiC power devices made of SiC materials have the advantages of high current density and small cell size. However, in trench SiC power devices, the high electric field at the bottom and corner of the gate trench will increase the electric field on the gate insulating layer, making the gate insulating layer easy to be broken down. Figure 1 It is a structural schematic diagram of a semiconductor power device provided in the related art. Figure 2 yes Figure 1 The schematic diagram of the structure shown in the figure forms an electric field shielding structure during the preparation process, refer to Figure 1 and Figure 2 In the related art, after forming an epitaxial layer 2 on a substrate 1, a source trench 5 with a relatively deep depth is formed on opposite sides of a gate trench 4 by etching, and then ions of the opposite conductivity type to the epitaxial layer 2 are injected into the bottom and sidewalls of the source trench 5, thereby forming an electric field shielding structure 3 with a depth greater than the gate trench depth on both sides of the gate trench 4; if the substrate 1 is a heavily doped N-type substrate, the epitaxial layer 2 is an N-type epitaxial layer, and the electric field shielding structure 3 is a P-type heavily doped region formed in the N-type epitaxial layer; the P+ and N+ shown in the accompanying drawings indicate that the ion doping concentration in the region is high, and the P- and N- indicate that the ion doping concentration in the region is low. Due to the high ion implantation concentration, the P-type heavily doped region is easy to form a wider depletion layer with the N-type epitaxial layer, reducing the current conduction path, thereby increasing the on-resistance of the semiconductor power device. Therefore, how to improve the problem of gate insulation layer breakdown in semiconductor power devices while reducing the on-resistance of the device is a technical problem that needs to be solved urgently by people in this field. Summary of the invention

[0004] Embodiments of the present invention provide a semiconductor power device, a preparation method, a power module, a conversion circuit and a vehicle, so as to improve the problem of gate insulation layer breakdown in the semiconductor power device and reduce the on-resistance.

[0005] According to one aspect of the present invention, there is provided a semiconductor power device, comprising:

[0006] substrate;

[0007] A semiconductor epitaxial layer is located on one side of the substrate; the semiconductor epitaxial layer comprises a drift region, a body region and a contact region which are sequentially away from the substrate;

[0008] A gate trench and a gate structure, wherein the gate trench is located on a surface of the semiconductor epitaxial layer away from the substrate; and the gate structure is located in the gate trench;

[0009] A super junction structure is located in the drift region and on the side of the gate structure close to the substrate; wherein the super junction structure includes a first conductivity type super junction and a second conductivity type super junction located on opposite sides of the first conductivity type super junction in a direction parallel to the substrate; the second conductivity type super junction is opposite to the conductivity type of the drift region, and the second conductivity type super junction covers the corner between the surface and the side wall of the gate structure close to the substrate.

[0010] Optionally, the contact region includes a first conductive type contact region and a second conductive type contact region; the second conductive type contact region is located at opposite sides of the gate trench; the first conductive type contact region is located between the gate trench and the second conductive type contact region, and is located on a side of the body region away from the substrate;

[0011] Wherein, the distance from the second conductive type contact area to the substrate is greater than the distance from the gate trench to the substrate.

[0012] Optionally, the gate trench includes at least two sub-trench, the at least two sub-trench are arranged in sequence in the direction from the semiconductor epitaxial layer to the substrate, and the width of the sub-trench close to the substrate in two adjacent sub-trench is smaller than the width of the sub-trench far from the substrate; the two adjacent sub-trench are connected to each other;

[0013] The first conductive type super junction is provided at least at the bottom of the sub-trench closest to the substrate, and the second conductive type super junction extends along the sidewall of the sub-trench closest to the substrate at least to the step surface between two adjacent sub-trenches closest to the substrate.

[0014] Optionally, the gate trench includes two sub-trench, namely a first-level sub-trench and a second-level sub-trench located at the bottom of the first-level sub-trench;

[0015] The first conductive type super junction is located at the bottom of the second-level sub-trench; the second conductive type super junction is located at two opposite sides of the first conductive type super junction and extends toward the first-level sub-trench along the sidewall of the second-level sub-trench.

[0016] Optionally, the second conductive type contact region is located at a side of the body region away from the substrate; a thickness of the second conductive type contact region is less than a total thickness of the first conductive type contact region and the body region;

[0017] Alternatively, the second conductive type contact region is located on a side of the first conductive type contact region away from the gate trench and on a side of the body region away from the gate trench; a thickness of the second conductive type contact region is greater than or equal to a total thickness of the first conductive type contact region and the body region.

[0018] Optionally, the semiconductor epitaxial layer further includes a current diffusion layer;

[0019] In the case where the second conductive type contact region is located on a side of the body region away from the substrate and the thickness of the second conductive type contact region is less than the total thickness of the first conductive type contact region and the body region, the current diffusion layer is located between the body region and the drift region;

[0020] When the second conductive type contact region is located on the first conductive type contact region and a side of the body region away from the gate trench, and the thickness of the second conductive type contact region is greater than or equal to the total thickness of the first conductive type contact region and the body region, the current diffusion layer is located between the body region and the drift region, and between the second conductive type contact region and the drift region.

[0021] According to another aspect of the present invention, a method for preparing a semiconductor power device is provided, which is used to prepare the semiconductor power device according to any embodiment of the present invention; comprising:

[0022] providing a substrate;

[0023] A semiconductor epitaxial layer is formed on one side of a substrate; the semiconductor epitaxial layer comprises a drift region, a body region and a contact region which are sequentially away from the substrate, and a super junction structure located in the drift region; wherein the super junction structure comprises a first conductive type super junction and a second conductive type super junction located on opposite sides of the first conductive type super junction in a direction parallel to the substrate, and the second conductive type super junction is opposite to the conductive type of the drift region;

[0024] forming a gate trench on a surface of the semiconductor epitaxial layer away from the substrate;

[0025] A gate structure is formed in the gate trench; the super junction structure is located on a side of the gate structure close to the substrate; and the second conductive type super junction covers a corner between a surface and a sidewall of the gate structure close to the substrate.

[0026] Optionally, forming a semiconductor epitaxial layer on one side of the substrate includes:

[0027] forming a first semiconductor epitaxial sublayer of a first conductivity type on one side of the substrate, and performing ion implantation in the first semiconductor epitaxial sublayer to form the super junction structure;

[0028] forming a second semiconductor epitaxial sublayer of the first conductivity type on a side of the first semiconductor epitaxial sublayer away from the substrate, and performing ion implantation in the second semiconductor epitaxial sublayer to form a body region and a first conductivity type contact region;

[0029] Ion implantation is performed again at both ends of the first conductive type contact area to form a second conductive type contact area; wherein the contact area includes a first conductive type contact area and a second conductive type contact area; and the distance from the bottom surface of the second conductive type contact area to the substrate is greater than the distance from the bottom surface of the gate trench to the substrate.

[0030] Optionally, before performing ion implantation in the second semiconductor epitaxial sublayer to form the body region and the first conductive type contact region, the method further includes:

[0031] A current diffusion layer is formed between the body region and the drift region.

[0032] Optionally, the gate trench includes a first-level sub-trench and a second-level sub-trench located at the bottom of the first-level sub-trench;

[0033] Forming a gate trench on a surface of the semiconductor epitaxial layer away from the substrate comprises:

[0034] From the surface of the semiconductor epitaxial layer away from the substrate, sequentially etching the contact region, the body region, the drift region to the top of the super junction structure to form a first-level sub-trench;

[0035] A first conductive type super junction at a portion of the thickness of the bottom of the first-level sub-trench is etched to form a second-level sub-trench; the width of the second-level sub-trench is smaller than the width of the first-level sub-trench.

[0036] Optionally, a gate structure is formed in the gate trench, comprising:

[0037] forming a gate insulating layer on the sidewalls and bottom of the gate trench;

[0038] A polysilicon gate is formed in a cavity surrounded by the gate insulating layer; wherein the gate structure includes the gate insulating layer and the polysilicon gate.

[0039] According to another aspect of the present invention, a power module is provided, comprising a substrate and at least one semiconductor power device according to any one of the embodiments of the present invention, wherein the substrate is used for carrying the semiconductor power device.

[0040] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0041] The power conversion circuit includes a circuit board and at least one semiconductor power device as described in any embodiment of the present invention, and the semiconductor power device is electrically connected to the circuit board.

[0042] According to another aspect of the present invention, a vehicle is provided, comprising a load and a power conversion circuit as described in any embodiment of the present invention, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0043] The technical solution provided by the embodiment of the present invention covers the corner between the bottom surface and the side wall of the gate structure by the second conductive type super junction, which plays a role in shielding the electric field at the bottom of the gate structure, thereby improving the reliability of the device; by arranging the first conductive type super junction between the second conductive type super junction, the conductive channel can be increased, thereby reducing the on-resistance of the device. Instead of arranging source trenches on opposite sides of the gate trench to form a deeper electric field shielding structure in the related art, the problem of increased on-resistance of the device due to the formation of a wider depletion layer between the electric field shielding structure and the semiconductor epitaxial layer can be avoided.

[0044] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 It is a structural schematic diagram of a semiconductor power device provided in the related art;

[0047] Figure 2 yes Figure 1 A schematic diagram of the structure of the structure shown in the preparation process to form an electric field shielding structure;

[0048] Figure 3 is a schematic structural diagram of a semiconductor power device provided by an embodiment of the present invention;

[0049] Figure 4 is a schematic structural diagram of another semiconductor power device provided by an embodiment of the present invention;

[0050] Figure 5 is a schematic structural diagram of another semiconductor power device provided by an embodiment of the present invention;

[0051] Figure 6 is a schematic structural diagram of another semiconductor power device provided by an embodiment of the present invention;

[0052] Figure 7 is a flow chart of a method for preparing a semiconductor power device provided by an embodiment of the present invention;

[0053] Figure 8-Figure 9 It is a structural schematic diagram corresponding to step S1210 in a method for preparing a semiconductor power device provided in an embodiment of the present invention;

[0054] Figure 10-11 It is a structural schematic diagram corresponding to step S1220 in a method for preparing a semiconductor power device provided in an embodiment of the present invention;

[0055] Fig.12 is another structural schematic diagram corresponding to step S1220 in a method for preparing a semiconductor power device provided in an embodiment of the present invention;

[0056] Fig.13 It is a structural schematic diagram corresponding to step S1230 in a method for preparing a semiconductor power device provided in an embodiment of the present invention;

[0057] Fig.14 It is a structural schematic diagram corresponding to step S1310 in a method for preparing a semiconductor power device provided in an embodiment of the present invention;

[0058] Fig.15 It is a structural schematic diagram corresponding to step S1320 in a method for preparing a semiconductor power device provided in an embodiment of the present invention;

[0059] Fig.16 It is a structural schematic diagram corresponding to step S1420 in a method for preparing a semiconductor power device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0060] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0061] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0062] An embodiment of the present invention provides a semiconductor power device. Figure 3 is a schematic diagram of the structure of a semiconductor power device provided by an embodiment of the present invention, with reference to Figure 3 , semiconductor power devices include:

[0063] Substrate 10;

[0064] The semiconductor epitaxial layer 20 is located on one side of the substrate 10; the semiconductor epitaxial layer 20 includes a drift region 21, a body region 22 and a contact region which are sequentially away from the substrate 10;

[0065] A gate trench and a gate structure 30, wherein the gate trench is located on a surface of the semiconductor away from the substrate 10; and the gate structure 30 is located in the gate trench;

[0066] The super junction structure 40 is located in the drift region 21 and on the side of the gate structure 30 close to the substrate 10; wherein the super junction structure 40 includes a first conductivity type super junction 41 and a second conductivity type super junction 42 located on opposite sides of the first conductivity type super junction 41 in a direction parallel to the substrate 10; the second conductivity type super junction 42 is opposite to the conductivity type of the drift region 21, and the second conductivity type super junction 42 covers the corner between the surface and the side wall of the gate structure 30 close to the substrate 10.

[0067] Specifically, the material of the substrate 10 may be the same as or different from the material of the semiconductor epitaxial layer 20. In an embodiment of the present invention, the material of the substrate 10 is the same as the material of the semiconductor epitaxial layer 20, and both may be SiC. That is, the semiconductor power device in the embodiment of the present invention may be a trench SiC power device. SiC has excellent physical and electrical properties. Compared with silicon materials, SiC materials have a large bandgap, and have the advantages of high breakdown electric field, high thermal conductivity, high electron saturation rate, and strong radiation resistance. Therefore, semiconductor devices made of SiC materials can not only operate stably at higher temperatures, but are also suitable for high voltage and high frequency scenarios.

[0068] The surface of the semiconductor epitaxial layer 20 away from the substrate 10 includes at least one gate trench. The gate trench can be formed by sequentially etching the contact region, the body region 22 and the drift region 21 of a partial thickness from the surface of the semiconductor epitaxial layer 20 away from the substrate 10. The gate structure 30 is disposed in the gate trench, and the gate structure 30 includes a polysilicon gate 31 and a gate insulating layer 32 located between the polysilicon gate 31 and the gate trench. The material of the gate insulating layer 32 may include at least one of aluminum oxide and silicon oxide.

[0069] The semiconductor epitaxial layer 20 also includes a super junction structure 40, which is located in the drift region 21 at the bottom of the gate structure 30. The super junction structure 40 includes a first conductivity type super junction 41 and a second conductivity type super junction 42 located on opposite sides of the first conductivity type super junction 41. The first conductivity type super junction 41 has the same conductivity type as the drift region 21, and the first conductivity type super junction 41 can cover the bottom surface of the gate structure 30. The second conductivity type super junction 42 has an opposite conductivity type to the drift region 21, and the second conductivity type super junction 42 covers the corner between the bottom surface and the side wall of the gate structure 30. The second conductivity type super junction 42 is arranged at the corner between the bottom surface and the side wall of the gate structure 30, which can play a role in shielding the electric field at the bottom of the gate structure 30, preventing the gate insulation layer 32 at the corner of the gate trench from being broken down, thereby improving the reliability of the device; the first conductivity type super junction 41 is arranged between the second conductivity type super junction 41, which can increase a conductive channel at the bottom of the gate structure 30, thereby reducing the on-resistance of the device.

[0070] The semiconductor power device provided by the embodiment of the present invention has a super junction structure 40 arranged at the bottom of the gate structure 30, and the super junction structure 40 includes a first conductive type super junction 41 and a second conductive type super junction 42 located on opposite sides of the first conductive type super junction 41; the first conductive type super junction 41 has the same conductive type as the drift region 21, and the second conductive type super junction 42 has the opposite conductive type as the drift region 21. The second conductive type super junction 42 covers the corner between the bottom surface and the sidewall of the gate structure 30, which can play a role in shielding the electric field at the bottom of the gate structure 30, thereby improving the reliability of the device; by arranging the first conductive type super junction 41 between the second conductive type super junctions, the conductive channel can be increased, thereby reducing the on-resistance of the device. Instead of arranging source trenches on opposite sides of the gate trench in the related art to form a deep electric field shielding structure, the problem of increasing the on-resistance of the device due to the formation of a wider depletion layer between the electric field shielding structure and the semiconductor epitaxial layer 20 (drift region 21) can be avoided.

[0071] The above is the core inventive concept of the present invention. The semiconductor power device is described in detail below with reference to the accompanying drawings.

[0072] Optionally, the conductivity type of the drift region 21 is the same as the first conductivity type super junction 41, that is, the first conductivity type; the conductivity type of the body region 22 is the same as the second conductivity type super junction 42, that is, the second conductivity type. If the first conductivity type is N-type, the second conductivity type is P-type; if the first conductivity type is P-type, the second conductivity type is N-type.

[0073] Among them, the N-type doping ions can be P (phosphorus) or N (nitrogen) ions, and the P-type doping ions can be Al (aluminum) ions or B (boron) ions. The doping concentration of ions in the drift region 21 is less than the doping concentration of ions in the first conductive type super junction 41; the doping concentration of ions in the body region 22 is less than the doping concentration of ions in the second conductive type super junction 42.

[0074] Based on the above embodiments, Figure 3 Optionally, the contact region includes a first conductive type contact region 23 and a second conductive type contact region 24; the second conductive type contact region 24 is located on opposite sides of the gate trench; the first conductive type contact region 23 is located between the gate trench and the second conductive type contact region 24, and is located on the side of the body region 22 away from the substrate 10.

[0075] The first conductive type contact region 23 and the second conductive type contact region 24 are both heavily doped regions. The ion doping concentration in the first conductive type contact region 23 is greater than the ion doping concentration in the first conductive type super junction 41, and the ion doping concentration in the second conductive type contact region 24 is greater than the ion doping concentration in the second conductive type super junction 42.

[0076] In the embodiment of the present invention, the distance from the bottom surface of the second conductive type contact region 24 to the substrate 10 is greater than the distance from the bottom surface of the gate structure 30 to the substrate 10. Compared with the method in the related art in which the distance from the bottom surface of the electric field shielding structure (second conductive type heavily doped region) to the substrate 10 is less than the distance from the bottom surface of the gate trench to the substrate 10, the technical solution provided by the embodiment of the present invention can make the second conductive type heavily doped regions (second conductive type contact regions 24) on both sides of the gate trench injected shallowly, and cannot form a wider depletion layer with the first conductive type drift region 21. Therefore, the semiconductor device provided by the embodiment of the present invention has a large on-state current and a small on-resistance.

[0077] On the basis of the above embodiments, optionally, the gate trench includes at least two sub-trench, the at least two sub-trench are arranged in sequence in the direction from the semiconductor epitaxial layer 20 to the substrate 10, and the width of the sub-trench close to the substrate 10 of the two adjacent sub-trench is smaller than the width of the sub-trench far from the substrate 10, that is, the width gradually decreases; the two adjacent sub-trench are connected to each other; wherein, at least the bottom of the sub-trench closest to the substrate 10 is provided with a first conductivity type super junction 41, and the second conductivity type super junction 42 extends along the sidewall of the sub-trench closest to the substrate 10 at least to the step surface between the two adjacent sub-trench closest to the substrate 10. The gate structure 30 is a step structure including at least two steps.

[0078] Figure 3 In the figure, the gate trench includes two sub-trench, namely a first-level sub-trench and a second-level sub-trench located at the bottom of the first-level sub-trench; the first conductive type super junction 41 is located at the bottom of the second-level sub-trench; the second conductive type super junction 42 is located on the opposite sides of the first conductive type super junction 41, and extends toward the first-level sub-trench along the sidewall of the second-level sub-trench.

[0079] Based on the above embodiments, please continue to refer to Figure 3 Optionally, the second conductive type contact region 24 is located on the side of the body region 22 away from the substrate 10; the thickness of the second conductive type contact region 24 is less than the total thickness of the first conductive type contact region 23 and the body region 22. The depth of the second conductive type heavily doped region implanted on both sides of the gate trench can be reduced, and the second conductive type heavily doped region is separated from the drift region 21 by the lightly doped body region 22, so the on-state current of the semiconductor device provided by the embodiment of the present invention can be further increased, and the on-resistance can be reduced.

[0080] Based on the above embodiments, Figure 4 is a schematic diagram of the structure of another semiconductor power device provided by an embodiment of the present invention, referring to Figure 4In another embodiment of the present invention, the second conductive type contact region 24 is located on a side of the first conductive type contact region 23 away from the gate trench and on a side of the body region 22 away from the gate trench; the thickness of the second conductive type contact region 24 may be greater than or equal to the total thickness of the first conductive type contact region 23 and the body region 22. The thickness of the second conductive type contact region 24 may be determined according to specific circumstances. It should be noted that in order to ensure that the device has a smaller on-resistance, the distance from the second conductive type contact region 24 to the substrate 10 is greater than the distance from the gate structure 30 to the substrate 10.

[0081] Based on the above embodiments, Figure 5 is a schematic diagram of the structure of another semiconductor power device provided by an embodiment of the present invention, Figure 6 is a schematic diagram of the structure of another semiconductor power device provided by an embodiment of the present invention, referring to Figure 5 and Figure 6 Optionally, the semiconductor epitaxial layer 20 also includes a current diffusion layer 25 .

[0082] The current diffusion layer 25 may be formed by implanting doping ions of the first conductivity type, and the ion doping concentration in the current diffusion layer 25 is greater than the ion doping concentration in the drift region 21 .

[0083] refer to Figure 5 , when the second conductive type contact region 24 is located at a side of the body region 22 away from the substrate 10 and the thickness of the second conductive type contact region 24 is less than the total thickness of the first conductive type contact region 23 and the body region 22 , the current diffusion layer 25 is located between the body region 22 and the drift region 21 ;

[0084] refer to Figure 6 When the second conductive type contact region 24 is located on the side of the first conductive type contact region 23 and the body region 22 away from the gate trench, and the thickness of the second conductive type contact region 24 is greater than or equal to the total thickness of the first conductive type contact region 23 and the body region 22, the current diffusion layer 25 is located between the body region 22 and the drift region 21, and between the second conductive type contact region 24 and the drift region 21.

[0085] The technical solution provided by the embodiment of the present invention can further reduce the on-resistance of the device by adding a current diffusion layer 25 of the first conductivity type with a higher concentration.

[0086] Based on the above embodiments, Figure 3 to Figure 6 , optionally, the semiconductor power device further comprises:

[0087] A first electrode 50 is located on a side of the substrate 10 away from the semiconductor epitaxial layer 20;

[0088] The second electrode 60 is located on a surface of the semiconductor epitaxial layer 20 away from the substrate 10 , and is in contact with the first conductive type contact region 23 and the second conductive type contact region 24 .

[0089] The materials of the first electrode 50 and the second electrode 60 may both include metal materials. The first electrode 50 may be a drain electrode D, and the second electrode 60 may be a source electrode S; or the first electrode 50 may be a source electrode S, and the second electrode 60 may be a drain electrode D. In the embodiment of the present invention, the first electrode 50 is a drain electrode D, and the second electrode 60 is a source electrode S, which are used for conducting the device.

[0090] Furthermore, an interlayer insulating layer ILD is formed on the upper surface of the gate structure 30 ; the second electrode 60 is located on the side of the interlayer insulating layer ILD away from the gate structure 30 and on the contact area surface not covered by the interlayer insulating layer ILD. The interlayer insulating layer ILD is used to isolate the second electrode 60 from the gate structure 30 .

[0091] Furthermore, the semiconductor power device further includes a passivation layer 70 and a protection layer 80 located on the second electrode 60. The material of the passivation layer 70 may include silicon nitride (SiN), and the material of the protection layer 80 may include polyimide.

[0092] An embodiment of the present invention further provides a method for preparing a semiconductor power device, which is used to prepare the semiconductor power device described in any embodiment of the present invention. Figure 7 is a flow chart of a method for preparing a semiconductor power device provided by an embodiment of the present invention, with reference to Figure 7 , the preparation method of the semiconductor power device comprises:

[0093] S110 , providing a substrate.

[0094] S120. Forming a semiconductor epitaxial layer on one side of the substrate; the semiconductor epitaxial layer includes a drift region, a body region and a contact region which are sequentially away from the substrate, and a super junction structure located in the drift region; wherein the super junction structure includes a first conductive type super junction and a second conductive type super junction located on opposite sides of the first conductive type super junction in a direction parallel to the substrate, and the second conductive type super junction is opposite to the conductive type of the drift region.

[0095] Specifically, the material of the substrate 10 may be the same as or different from the material of the semiconductor epitaxial layer 20. In the embodiment of the present invention, the material of the substrate 10 is the same as the material of the semiconductor epitaxial layer 20, and both may be SiC. A drift region 21, a body region 22, and a contact region that are sequentially away from the substrate 10, and a super junction structure 40 located in the drift region 21 may be formed in the semiconductor epitaxial layer 20 by multiple ion implantations.

[0096] The conductivity type of the drift region 21 is the same as the first conductivity type super junction 41, which is the first conductivity type; the conductivity type of the body region 22 is the same as the second conductivity type super junction 42, which is the second conductivity type. If the first conductivity type is N-type, the second conductivity type is P-type; if the first conductivity type is P-type, the second conductivity type is N-type. Among them, the N-type doping ions can be P (phosphorus) or N (nitrogen) ions, and the P-type doping ions can be Al (aluminum) ions or B (boron) ions. The doping concentration of ions in the drift region 21 is less than the doping concentration of ions in the first conductivity type super junction 41; the doping concentration of ions in the body region 22 is less than the doping concentration of ions in the second conductivity type super junction 42.

[0097] The contact region includes a first conductive type contact region 23 and a second conductive type contact region 24; the second conductive type contact region 24 is formed on opposite sides of the gate trench; the first conductive type contact region 23 is formed between the gate trench and the second conductive type contact region 24. The first conductive type contact region 23 and the second conductive type contact region 24 are both heavily doped regions. The ion doping concentration in the first conductive type contact region 23 is greater than the ion doping concentration in the first conductive type super junction 41, and the ion doping concentration in the second conductive type contact region 24 is greater than the ion doping concentration in the second conductive type super junction 42.

[0098] S130, forming a gate trench on a surface of the semiconductor epitaxial layer away from the substrate.

[0099] Specifically, at least one gate trench is formed on the surface of the semiconductor epitaxial layer 20 away from the substrate 10. The gate trench can be formed by etching the contact region, the body region 22 and the drift region 21 of a partial thickness from the surface of the semiconductor epitaxial layer 20 away from the substrate 10 in sequence by photolithography.

[0100] S140, forming a gate structure in the gate trench; wherein the super junction structure is located on a side of the gate structure close to the substrate, and the second conductive type super junction covers a corner between a surface of the gate structure close to the substrate and a sidewall.

[0101] The method for preparing a semiconductor power device provided in an embodiment of the present invention forms a super junction structure 40 at the bottom of the gate structure 30, and covers the corner between the bottom surface and the side wall of the gate structure 30 with a second conductive type super junction 42, which can shield the electric field at the bottom of the gate structure 30, thereby improving the reliability of the device; by forming a first conductive type super junction 41 between the second conductive type super, a conductive channel can be increased, thereby reducing the on-resistance of the device.

[0102] Based on the above embodiments, optionally, step S120 of forming a semiconductor epitaxial layer on one side of the substrate includes:

[0103] S1210 , forming a first semiconductor epitaxial sublayer of a first conductivity type on one side of the substrate, and implanting ions into the first semiconductor epitaxial sublayer to form a super junction structure.

[0104] Specifically, refer to Figure 8 The substrate 10 and the first semiconductor epitaxial sublayer 201 can be formed in different processes. The substrate 10 and the first semiconductor epitaxial sublayer 201 can also be formed in the same preparation process, that is, the substrate 10 and the first semiconductor epitaxial sublayer 201 can be a whole SiC film layer structure formed in the same preparation process; after the whole SiC film layer structure is processed on the front side, the back side of the SiC film layer structure is thinned, and the back side of the SiC film layer structure is heavily doped with ions to form the substrate 10.

[0105] refer to Fig. 9 , ion implantation is performed on the surface of the first semiconductor epitaxial sublayer 201 away from the substrate 10 to form a super junction structure 40. In the process of forming the super junction structure 40, the position and pattern of the super junction structure 40 can be defined by a mask, and the second conductivity type doping ions can be implanted to form a second conductivity type doping region; then the position and pattern of the first conductivity type super junction 41 can be defined by a mask, and the first conductivity type doping ions can be implanted in the second conductivity type doping region to form the first conductivity type super junction 41; the area in the second conductivity type doping region where the first conductivity type doping ions are not implanted forms the second conductivity type super junction 42.

[0106] S1220, forming a second semiconductor epitaxial sublayer of the first conductivity type on a side of the first semiconductor epitaxial sublayer away from the substrate, and performing ion implantation in the second semiconductor epitaxial sublayer to form a body region and a first conductivity type contact region.

[0107] Specifically, refer to Fig.10 , continue to grow the second semiconductor epitaxial sublayer 202 ; the material of the second semiconductor epitaxial sublayer 202 can be the same as that of the first semiconductor epitaxial sublayer 201 .

[0108] refer to Fig.11 ,for Figure 3 and Figure 4 In the semiconductor power device shown, second conductivity type ions and first conductivity type ions are implanted from the second semiconductor epitaxial sublayer 202 at a side away from the substrate 10 , thereby forming a body region 22 and a first conductivity type contact region 23 , respectively.

[0109] refer to Fig.12 ,for Figure 5 and Figure 6The semiconductor power device shown in the figure further includes: implanting first conductive type ions to form a current diffusion layer 25 between the body region 22 and the drift region 21 before ion implantation is performed in the second semiconductor epitaxial sublayer 202 to form the body region 22 and the first conductive type contact region 23 .

[0110] S1230. Perform ion implantation again at both ends of the first conductive type contact region to form a second conductive type contact region; wherein the contact region includes a first conductive type contact region and a second conductive type contact region; and a distance from a bottom surface of the second conductive type contact region to the substrate is greater than a distance from a bottom surface of the gate trench to the substrate.

[0111] Specifically, the position and pattern of the second conductive type contact region 24 are defined by a mask, and the second conductive type ions are implanted to form the second conductive type contact region 24. Figure 3 and Figure 5 When the semiconductor power device shown in FIG. 1 is formed, the depth of the second conductive type ion implantation in this step is relatively shallow; Figure 4 and Figure 6 In the semiconductor power device shown in FIG. 1 , the depth of the second conductive type ion implantation in this step is relatively deep. Fig.13 , exemplarily showing the formation Figure 6 The depth of the second conductivity type ion implantation during the structure shown.

[0112] Based on the above embodiments, optionally, the gate trench includes a first-level sub-trench 01 and a second-level sub-trench 02 located at the bottom of the first-level sub-trench 01, and the width of the second-level sub-trench 02 is smaller than the width of the first-level sub-trench 01. Step S130 forms a gate trench on the surface of the semiconductor epitaxial layer away from the substrate, including:

[0113] S1310, etching the contact region, the body region, the drift region in sequence from the surface of the semiconductor epitaxial layer away from the substrate to the top of the super junction structure to form a first-level sub-trench.

[0114] Specifically, refer to Fig.14 , a first-level sub-groove 01 can be formed on the side of the semiconductor epitaxial layer 20 away from the substrate 10 by a photolithography process. The specific steps may include: depositing SiO on the surface of the semiconductor epitaxial layer 20 away from the substrate 10 by a deposition process such as CVD. 2As the first mask layer, a photoresist PR is spin-coated on the surface of the first mask layer, and a photoresist PR of a desired pattern is formed by exposure and development, and then the first mask layer is etched based on the patterned photoresist PR to pattern the first mask layer. The patterned first mask layer exposes the preset position of the gate trench. Based on the patterned first mask layer, the semiconductor epitaxial layer 20 is etched until the top of the super junction structure 40 to form a first-level sub-trench 01. Among them, the etching process can adopt a plasma dry etching process, such as RIE or ICP etching process.

[0115] S1320, etching a first conductive type super junction at a portion of the thickness at the bottom of the first-level sub-trench to form a second-level sub-trench.

[0116] Specifically, refer to Fig.15 SiO is deposited on the bottom and sidewalls of the first-level sub-trench 01. 2 as a second mask layer; patterning the second mask layer to form an opening that only exposes the first conductive type super junction 41; etching the first conductive type super junction 41 at the bottom of the first-level sub-trench 01 to form a second-level sub-trench 02; removing the first mask layer and the second mask layer.

[0117] On the basis of the above embodiments, optionally, step S140 of forming a gate structure 30 in the gate trench includes:

[0118] S1410, forming a gate insulation on the sidewall and bottom of the gate trench.

[0119] S1420, forming a polysilicon gate in a cavity surrounded by a gate insulating layer; wherein the gate structure includes a gate insulating layer and a polysilicon gate.

[0120] Specifically, refer to Fig.16 The material of the gate insulating layer 32 may include SiO 2 and Al 2 O 3 The gate insulating layer 32 may be prepared by at least one of ALD (Atomic Layer Deposition), thermal oxidation, and wet method. A polysilicon material is filled in the gate trench to form a polysilicon gate 31. The gate structure 30 includes a polysilicon gate 31 and a gate insulating layer 32 wrapping the polysilicon gate 31.

[0121] Optionally, the method for preparing a semiconductor power device further includes:

[0122] An interlayer insulating layer ILD is formed on the upper surface of the gate structure 30 ; the interlayer insulating layer ILD is used to isolate the second electrode 60 from the gate structure 30 ;

[0123] A second electrode 60 is formed on a surface of the semiconductor epitaxial layer 20 away from the substrate 10 , and the second electrode 60 contacts the first conductive type contact region 23 and the second conductive type contact region 24 ;

[0124] A passivation layer 70 and a protective layer 80 are sequentially formed on a side of the second electrode 60 away from the substrate; the material of the passivation layer 70 may include silicon nitride (SiN), and the material of the protective layer 80 may include polyimide;

[0125] A first electrode 50 is formed on a surface of the substrate 10 away from the semiconductor epitaxial layer 20 .

[0126] The embodiment of the present invention further provides a power module, comprising a substrate and at least one semiconductor power device according to any embodiment of the present invention, wherein the substrate is used to carry the semiconductor power device. The same technical effects are achieved and will not be described in detail here.

[0127] The embodiment of the present invention further provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor power device as described in any embodiment of the present invention, and the semiconductor power device is electrically connected to the circuit board. It has the same technical effect and is not described here.

[0128] The embodiment of the present invention further provides a vehicle, comprising a load and a power conversion circuit as described in any embodiment of the present invention, the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power, and then input it into the load. The same technical effects are achieved, which will not be described in detail here.

[0129] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A semiconductor power device, characterized in that: include: substrate; A semiconductor epitaxial layer is located on one side of the substrate; the semiconductor epitaxial layer comprises a drift region, a body region and a contact region which are sequentially away from the substrate; A gate trench and a gate structure, wherein the gate trench is located on a surface of the semiconductor epitaxial layer away from the substrate; and the gate structure is located in the gate trench; A super junction structure is located in the drift region and on the side of the gate structure close to the substrate; wherein the super junction structure includes a first conductivity type super junction and a second conductivity type super junction located on opposite sides of the first conductivity type super junction in a direction parallel to the substrate; the second conductivity type super junction is opposite to the conductivity type of the drift region, and the second conductivity type super junction covers the corner between the surface and the side wall of the gate structure close to the substrate.

2. The semiconductor power device according to claim 1, characterized in that: The contact region includes a first conductive type contact region and a second conductive type contact region; the second conductive type contact region is located at opposite sides of the gate trench; the first conductive type contact region is located between the gate trench and the second conductive type contact region, and is located on a side of the body region away from the substrate; Wherein, the distance from the second conductive type contact area to the substrate is greater than the distance from the super junction structure to the substrate.

3. The semiconductor power device according to claim 1, characterized in that: The gate trench comprises at least two sub-trenches, the at least two sub-trenches are arranged in sequence in the direction from the semiconductor epitaxial layer to the substrate, and the width of the sub-trench close to the substrate of two adjacent sub-trenches is smaller than the width of the sub-trench far from the substrate; the two adjacent sub-trenches are connected to each other; The first conductive type super junction is provided at least at the bottom of the sub-trench closest to the substrate, and the second conductive type super junction extends along the sidewall of the sub-trench closest to the substrate at least to the step surface between two adjacent sub-trenches closest to the substrate.

4. The semiconductor power device according to claim 3, characterized in that: The gate trench comprises two sub-trench, namely a first-level sub-trench and a second-level sub-trench located at the bottom of the first-level sub-trench; The first conductive type super junction is located at the bottom of the second-level sub-trench; the second conductive type super junction is located at two opposite sides of the first conductive type super junction and extends toward the first-level sub-trench along the sidewall of the second-level sub-trench.

5. The semiconductor power device according to claim 2, characterized in that: The second conductive type contact region is located at a side of the body region away from the substrate; the thickness of the second conductive type contact region is less than the total thickness of the first conductive type contact region and the body region; Alternatively, the second conductive type contact region is located on a side of the first conductive type contact region away from the gate trench and on a side of the body region away from the gate trench; a thickness of the second conductive type contact region is greater than or equal to a total thickness of the first conductive type contact region and the body region.

6. The semiconductor power device according to claim 5, characterized in that: The semiconductor epitaxial layer also includes a current diffusion layer; In the case where the second conductive type contact region is located on a side of the body region away from the substrate and the thickness of the second conductive type contact region is less than the total thickness of the first conductive type contact region and the body region, the current diffusion layer is located between the body region and the drift region; When the second conductive type contact region is located on the first conductive type contact region and a side of the body region away from the gate trench, and the thickness of the second conductive type contact region is greater than or equal to the total thickness of the first conductive type contact region and the body region, the current diffusion layer is located between the body region and the drift region, and between the second conductive type contact region and the drift region.

7. A method for preparing a semiconductor power device, characterized in that: Used for preparing the semiconductor power device according to any one of claims 1 to 6; include, providing a substrate; A semiconductor epitaxial layer is formed on one side of a substrate; the semiconductor epitaxial layer comprises a drift region, a body region and a contact region which are sequentially away from the substrate, and a super junction structure located in the drift region; wherein the super junction structure comprises a first conductive type super junction and a second conductive type super junction located on opposite sides of the first conductive type super junction in a direction parallel to the substrate, and the second conductive type super junction is opposite to the conductive type of the drift region; forming a gate trench on a surface of the semiconductor epitaxial layer away from the substrate; A gate structure is formed in the gate trench; wherein the super junction structure is located on a side of the gate structure close to the substrate; and the second conductive type super junction covers a corner between a surface surface and a side wall of the gate structure close to the substrate.

8. The method for preparing a semiconductor power device according to claim 7, characterized in that: A semiconductor epitaxial layer is formed on one side of the substrate, comprising: forming a first semiconductor epitaxial sublayer of a first conductivity type on one side of the substrate, and performing ion implantation in the first semiconductor epitaxial sublayer to form the super junction structure; forming a second semiconductor epitaxial sublayer of the first conductivity type on a side of the first semiconductor epitaxial sublayer away from the substrate, and performing ion implantation in the second semiconductor epitaxial sublayer to form a body region and a first conductivity type contact region; Ion implantation is performed again at both ends of the first conductive type contact area to form a second conductive type contact area; wherein the contact area includes a first conductive type contact area and a second conductive type contact area; and the distance from the bottom surface of the second conductive type contact area to the substrate is greater than the distance from the bottom surface of the gate trench to the substrate.

9. The method for preparing a semiconductor power device according to claim 8, characterized in that: Before performing ion implantation in the second semiconductor epitaxial sublayer to form a body region and a first conductive type contact region, the method further includes: A current diffusion layer is formed between the body region and the drift region.

10. The method for preparing a semiconductor power device according to claim 7, characterized in that: The gate trench comprises a first-level sub-trench and a second-level sub-trench located at the bottom of the first-level sub-trench; Forming a gate trench on a surface of the semiconductor epitaxial layer away from the substrate comprises: From the surface of the semiconductor epitaxial layer away from the substrate, sequentially etching the contact region, the body region, the drift region to the top of the super junction structure to form a first-level sub-trench; A first conductive type super junction at a portion of the thickness of the bottom of the first-level sub-trench is etched to form a second-level sub-trench; the width of the second-level sub-trench is smaller than the width of the first-level sub-trench.

11. The method for preparing a semiconductor power device according to claim 7, characterized in that: A gate structure is formed in the gate trench, comprising: forming a gate insulating layer on the sidewalls and bottom of the gate trench; A polysilicon gate is formed in a cavity surrounded by the gate insulating layer; wherein the gate structure includes the gate insulating layer and the polysilicon gate.

12. A power module, characterized in that: It comprises a substrate and at least one semiconductor power device according to any one of claims 1 to 6, wherein the substrate is used to carry the semiconductor power device.

13. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor power device according to any one of claims 1 to 6, wherein the semiconductor power device is electrically connected to the circuit board.

14. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 13, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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